Master circuit mos controlled bypass delay protection circuit and method for battery management system bms

Abstract

This invention relates to the field of power loop control and protection technology for battery management systems (BMS), specifically a controlled bypass delay protection circuit for the main circuit MOS of a BMS. The circuit includes a main circuit power control unit, comprising a main charging switch unit, a main discharging switch unit, and a current sampling unit; an auxiliary charging control unit connected across the first and second terminals of the main charging switch unit, used to form a bypass buffer path during the transient period of the main charging switch unit's on or off; and an auxiliary discharging control unit connected between the first and second terminals of the main discharging switch unit. This controlled bypass delay protection circuit and method for the main circuit MOS of a BMS achieves controlled bypass buffering across the two ends of the main MOS, providing a bypass path through the delay MOS (QG1 / QG2) during the main MOS switching transient, significantly reducing inrush current and turn-off overvoltage spikes.

Description

Technical Field

[0001] This invention relates to the field of power loop control and protection technology for battery management systems (BMS), specifically to a controlled bypass delay protection circuit and method for the main circuit MOS of a battery management system (BMS). Background Technology

[0002] In two-wheeled electric vehicles and lightweight energy storage systems, the Battery Management System (BMS) typically uses power MOSFETs as the main circuit switches to control the charging and discharging paths. External chargers or motor controller inputs usually have large capacitors, and wiring harnesses and connectors contain parasitic inductance. Under transient conditions such as power-on insertion / removal, fault protection, and rapid shutdown, the main circuit MOSFETs are prone to experiencing significant di / dt and dv / dt surges, leading to:

[0003] 1. Large inrush current during turn-on causes the main MOSFET to enter the linear region at the moment of turn-off, resulting in overheating or breakdown.

[0004] 2. High overvoltage spikes during turn-off, parasitic inductance flyback leading to MOS avalanche risk;

[0005] 3. High dv / dt can cause false turn-on (Miller effect), resulting in switch bounce or abnormal current.

[0006] 4. The charging and discharging directions are inconsistent, and a single soft-start parameter is difficult to take into account both charging and discharging paths.

[0007] Existing solutions often reduce switching stress through gate resistors, simple RC soft-start, or unidirectional delay control. However, these solutions are still prone to problems such as insufficient protection, sensitivity to parameter drift, and poor compatibility under different operating conditions in low-cost BMS. Therefore, a circuit structure that can provide "bypass buffering" during the main circuit switching transient is needed, and that can independently optimize the charging and discharging directions. Summary of the Invention

[0008] To address the shortcomings of existing technologies, this invention provides a controlled bypass delay protection circuit and method for the main circuit MOS of a battery management system (BMS). By setting a bypass delay branch consisting of a delay MOS and RC / unidirectional conduction devices at both ends of the main MOS, a controlled buffer path is provided during the main MOS's turn-on / turn-off transients to reduce the risk of surge current, turn-off spikes, and high dv / dt mis-turn-on, thereby protecting the main circuit power MOS devices and improving system reliability.

[0009] To achieve the above objectives, the present invention provides the following technical solution: a main circuit MOS-controlled bypass delay protection circuit for a battery management system (BMS), comprising:

[0010] The main circuit power control unit includes a main charging switch unit, a main discharging switch unit, and a current sampling unit;

[0011] An auxiliary charging control unit is connected across the first and second terminals of the main charging switch unit. It is used to form a bypass buffer path during the transient period when the main charging switch unit is turned on or off, and exit the bypass state after a preset time.

[0012] An auxiliary discharge control unit is connected between the first and second terminals of the main discharge switch unit. It is used to form a bypass buffer path during the transient period when the main discharge switch unit is turned on or off, and exits the bypass state after a preset time.

[0013] Furthermore, the main charging switch unit includes a main charging power switch QF1 and its charging drive branch. The main charging power switch QF1 is used to control the charging current path between the battery pack and the charger.

[0014] Furthermore, the charging drive branch includes:

[0015] The charging interlock drive upper transistor QH1 and the charging interlock drive lower transistor QL2 together form an interlock circuit, which is used to quickly pull down the gate of the charging main power switch transistor QF1 according to the charging control signal, so as to realize the rapid turn-off of the charging main power switch transistor QF1.

[0016] The charging gate drive resistor R66 is used to limit the gate drive current, adjust the gate charging speed, and suppress switching oscillations.

[0017] The charging gate discharge resistor Rm67 is used to form the discharge path of the gate of the charging main power switch QF1.

[0018] The signal input resistor RF2 is used to introduce the external charging control signal into the driving branch of the main charging power switch QF1.

[0019] The anti-reverse-feedback diode D34 is used to unidirectionally introduce the charging control signal into the drive network, while preventing the voltage of the drive stage from flowing back to the front-end control terminal.

[0020] And the charging clamping diode D8 is used to provide a bypass path under specific operating conditions, limit the potential difference between local nodes to prevent the driving voltage from being too high, which could damage the charging main power switch QF1.

[0021] Furthermore, the main discharge switch unit includes a discharge main power switch transistor QF12 and its discharge drive branch. The discharge main power switch transistor QF12 is used to control the discharge current path between the battery pack and the load terminal.

[0022] Furthermore, the discharge drive branch includes:

[0023] Discharge interlock drive upper tube QH3, discharge interlock drive lower tube QL1;

[0024] The discharge gate drive resistor Rm15 is used to limit the gate charging and discharging current of the discharge main power switch QF12 and suppress gate oscillation during the switching process.

[0025] The discharge bias resistor Rm3 and the discharge bleed resistor Rm26 are used to bias, bleed and stabilize the drive input to prevent the main power switch QF12 from being mis-turned when the control signal is floating.

[0026] Clamping current-limiting resistor R36 prevents accidental contact and accelerates the release of residual charge;

[0027] The isolation diode Dm6 is used to unidirectionally introduce the discharge control signal into the drive network, while preventing the voltage of the drive stage from flowing back to the front-end control terminal;

[0028] The discharge clamping diode Dm7 is used to provide a bypass path under specific operating conditions, limit the potential difference between local nodes to prevent excessive drive voltage, which could damage the discharge main power switch QF12.

[0029] Furthermore, the current sampling unit includes sampling resistor RN8 and sampling resistor RN14. The sampling resistor RN8 and sampling resistor RN14 are connected between the node current + and the node current -, and are used to sample and detect the charging and discharging current in the main circuit.

[0030] Furthermore, it also includes a buffer absorption unit, which includes a charging absorption capacitor Cm1, a charging absorption resistor Rm2, a discharging absorption resistor Rm25, and a discharging absorption capacitor Cm2. The charging absorption capacitor Cm1 and the charging absorption resistor Rm2 are used to absorb peak energy, reduce dv / dt, and reduce high-frequency ringing when the charging main power switch QF1 switches. The discharging absorption capacitor Cm2 and the discharging absorption resistor Rm25 are used to filter and buffer the voltage fluctuations in the branch where the discharging main power switch QF12 is located.

[0031] Furthermore, the auxiliary charging control unit includes:

[0032] The auxiliary charging switch QG2 is used to form a bypass buffer when the main charging power switch QF1 is in a transient state of being turned on or off, so that the voltage change across the main charging power switch QF1 is smoother.

[0033] The first RC delay network includes a first delay resistor RT2 and a first delay capacitor Cm3, which is used to delay the charging control signal so that the operation of the auxiliary charging switch QG2 has a delay characteristic.

[0034] The first unidirectional conducting device Dm10 is used to provide a unidirectional conducting path, making the delay directional;

[0035] The first controller QH4 is used as a controlled device to gradually change the gate drive potential of the auxiliary charging switch QG2 under the action of the delay network, so as to realize the gradual turn-on or controlled turn-off of the auxiliary charging switch QG2.

[0036] The first gate slope network includes a first gate slope resistor RB23 and a first gate filter C42, which are used to provide slope control and filtering for the gate of the auxiliary charging switch QG2 to suppress false turn-on caused by dv / dt.

[0037] And discharge resistor RG1, used to provide a discharge path.

[0038] Furthermore, the auxiliary discharge control unit includes:

[0039] The auxiliary discharge switch QG1 is used to provide a bypass buffer by being turned on for a short time during the switching transient of the main power switch QF12, thereby reducing turn-off spikes and turn-on impacts.

[0040] The second RC delay network includes a second delay resistor RT1 and a second delay capacitor Cm53, which are used to enable the discharge auxiliary branch to have delayed conduction or delayed turn-off characteristics.

[0041] The second unidirectional conduction device Dm8 is used to provide a unidirectional conduction path, so that the turn-off or turn-on process has a directional delay;

[0042] The second control device QH2 constitutes the front-end driver device of the auxiliary discharge switch QG1 and is used to control the rapid turn-off of the auxiliary discharge switch QG1. Under the action of the delay network, the second control device QH2 gradually changes the gate drive of the auxiliary discharge switch QG1 to form controlled turn-on or controlled turn-off.

[0043] The second gate slope network, which includes a second gate slope resistor RB24 and a second gate filter C52, is used to provide slope control and filtering for the gate of the auxiliary discharge switch QG1 to reduce the risk of false turn-on.

[0044] And discharge resistor RG2, used to provide a gate discharge path.

[0045] A method for a MOS-controlled bypass delay protection circuit in the main circuit of a battery management system (BMS) includes the following steps:

[0046] During charging, the control unit sends a charging enable signal to drive the main charging power switch QF1 to prepare for conduction;

[0047] During the transient phase of the main power switch QF1 conducting, the auxiliary charging control unit briefly turns on the auxiliary charging switch QG2 to form a buffer bypass across the main power switch QF1, limiting the rate of voltage change across QF1 and suppressing surges.

[0048] When the delay time is reached or a stable condition is detected, the auxiliary charging switch QG2 exits the bypass state, and the main charging power switch QF1 is stably turned on to bear the main current.

[0049] When charging is turned off or protection is triggered, the main charging power switch QF1 is turned off, and the auxiliary charging switch QG2 can be controlled to turn on / off for a short time to buffer the turn-off spike.

[0050] During discharge, the control unit sends a discharge permission signal to drive the main power switch QF12 to prepare for conduction;

[0051] During the transient phase of the discharge main power switch QF12 conduction process, the auxiliary discharge control unit briefly turns on the auxiliary discharge switch QG1 to form a buffer bypass across the discharge main power switch QF12, limiting the rate of change of current / voltage.

[0052] After the delay ends, the auxiliary discharge switch QG1 is deactivated, and the main discharge power switch QF12 is stably turned on to bear the main current.

[0053] When the discharge is turned off or the protection is triggered, the main discharge power switch QF12 is turned off, and the auxiliary discharge switch QG1 is controlled to turn on / off to reduce the risk of turn-off spikes and false turn-on.

[0054] Compared with the prior art, the technical solution of this application has the following beneficial effects:

[0055] 1. The main circuit MOS controlled bypass delay protection circuit and method of the battery management system (BMS) realizes controlled bypass buffering across the two ends of the main MOS. By providing a bypass path through the delay MOS (QG1 / QG2) during the switching transient of the main MOS, the surge current and turn-off overvoltage spike are significantly reduced.

[0056] 2. The main circuit MOS controlled bypass delay protection circuit and method of the battery management system (BMS) realizes independent optimization of charging and discharging. The charging delay and discharging delay parameters can be set separately to adapt to the different transient characteristics of the charger end and the load end.

[0057] 3. The main circuit MOS controlled bypass delay protection circuit and method of the battery management system (BMS) is used to suppress false turn-on and ringing. The gate slope network and clamp / filter network reduce the Miller false turn-on caused by dv / dt, thereby improving system stability.

[0058] 4. The main circuit MOS controlled bypass delay protection circuit and method of the battery management system (BMS) achieves low cost and easy mass production. It is implemented using discrete components and does not rely on expensive driver chips, making it suitable for two-wheeled vehicle BMS.

[0059] 5. The controlled bypass delay protection circuit and method for the main circuit MOS of the battery management system (BMS) improves the lifespan of the main circuit power MOS, reduces linear region losses and avalanche stress, and enhances long-term reliability. Attached Figure Description

[0060] Figure 1 This is a schematic diagram of the structure of the present invention;

[0061] Figure 2 This is a circuit diagram of the present invention. Detailed Implementation

[0062] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0063] Please see Figure 1-2 The main circuit MOS controlled bypass delay protection circuit of the battery management system (BMS) in this embodiment includes a main circuit power control unit, an auxiliary charging control unit, and an auxiliary discharging control unit. It realizes controlled bypass buffering across the two ends of the main MOS and provides a bypass path during the transient period of the main MOS switching through a delay switch, which significantly reduces surge current and turn-off overvoltage spikes.

[0064] In this embodiment, the main circuit power control unit includes a main charging switch unit, a main discharging switch unit, and a current sampling unit.

[0065] The main charging switch unit includes a main charging power switch transistor QF1 and its charging drive branch.

[0066] Specifically, the main current path of the charging main power switch QF1 is connected between node C- and node P-. As the main switch of the charging path, QF1 is connected to node C- at one end and node P- at the other end, thus forming the main charging path between the negative terminal of the battery and the negative terminal of the external port. QF1 is used to control the charging current path between the battery pack and the charger. The gate of QF1 is connected to the left charging drive branch, and the charging drive branch controls its gate potential to determine the on and off states of QF1.

[0067] In a preferred embodiment, the charging drive branch includes a charging interlock drive upper transistor QH1, a charging interlock drive lower transistor QL2, a charging gate drive resistor R66, a charging gate discharge resistor Rm67, a signal input resistor RF2, an anti-reverse current diode D34, and a charging clamping diode D8.

[0068] Specifically, the charging gate drive resistor R66 and the charging gate discharge resistor Rm67 are connected in the gate drive path of the charging main power switch QF1. One end of the charging gate drive resistor R66 is connected to the drive control node, and the other end is connected to the drive branch related to the gate of the charging main power switch QF1, used to limit the gate drive current, adjust the gate charging speed, and suppress switching oscillation. One end of the charging gate discharge resistor Rm67 is connected to the transistor drive network, and the other end is connected to the gate node of the charging main power switch QF1, used to form the discharge path of the gate of the charging main power switch QF1.

[0069] One end of the signal input resistor RF2 is connected to the "charging control" signal input terminal, and the other end is connected to the pre-stage drive network of the charging main power switch QF1. It is used to introduce the external charging control signal into the drive branch of the charging main power switch QF1, and at the same time to limit the gate charging and discharging current and suppress ringing.

[0070] The charging interlock driver upper transistor QH1 and the charging interlock driver lower transistor QL2 constitute a drive unit that controls the gate of the charging main power switch transistor QF1. The control terminals of QH1 and QL2 are connected to relevant charging control nodes, and their output terminals are connected to the gate drive network of QF1. QH1 and QL2 can form an interlock circuit to rapidly pull down the gate of QF1 according to the charging control signal, thereby achieving rapid turn-off of QF1.

[0071] One end of the anti-reverse-feeding diode D34 is connected to the "charging MOS" control input terminal, and the other end is connected to the front-stage node of the drive network composed of the charging interlock drive upper transistor QH1 and the charging clamping diode D8. It is used to unidirectionally introduce the charging control signal into the drive network, while preventing the voltage of the drive stage from flowing back to the front-stage control terminal.

[0072] The charging clamp diode D8 is connected between the top main circuit node and the C- node to provide a bypass path under specific operating conditions, limit the potential difference between local nodes to prevent excessive drive voltage, which could damage the charging main power switch QF1. The charging clamp diode D8 and the anti-reverse-current diode D34 form a clamping protection structure, which can clamp the gate voltage or critical nodes due to overvoltage.

[0073] Understandably, through the above structure, the charging main power switch QF1 has controllable switching capability and anti-peak capability.

[0074] Meanwhile, the main discharge switch unit includes the main discharge power switch transistor QF12 and its discharge drive branch.

[0075] The main current path of the discharge main power switch QF12 is connected between node P- and node current +. QF12 acts as the main switch for the discharge path, with one end connected to node P- and the other end connected to node current +, thus forming the main discharge path between the negative terminal of the external port and the sampling branch. QF12 controls the discharge current path between the battery pack and the load. The gate of QF12 is connected to the left-side discharge drive branch, which controls its on / off state.

[0076] In a preferred embodiment, the discharge drive branch includes a discharge interlock drive upper transistor QH3, a discharge interlock drive lower transistor QL1, a discharge gate drive resistor Rm15, a discharge bias resistor Rm3, a clamping current limiting resistor R36, a discharge discharge resistor Rm26, an isolation diode Dm6, and a discharge clamping diode Dm7.

[0077] Specifically, one end of the discharge gate drive resistor Rm15 is connected to the gate of the discharge main power switch QF12, and the other end is connected to the discharge drive node. It is used to limit the charging and discharging current of the gate of the discharge main power switch QF12 and suppress gate oscillation during the switching process.

[0078] The discharge bias resistor Rm3 and the discharge bleed resistor Rm26 are connected between the pre-discharge drive network and the reference node, respectively, to bias, bleed, and stabilize the drive input, and to prevent the discharge main power switch QF12 from being falsely turned on when the control signal is floating.

[0079] One end of the isolation diode Dm6 is connected to the "discharge MOS" control input terminal, and the other end is connected to the front-stage node of the drive network composed of the upper discharge interlock drive transistor QH3 and the lower discharge interlock drive transistor QL1. It is used to unidirectionally introduce the discharge control signal into the drive network, while preventing the voltage of the drive stage from flowing back to the front-stage control terminal.

[0080] The discharge clamping diode Dm7 is connected in the gate drive branch of the discharge main power switch QF12. It is used to provide a bypass path under specific operating conditions, limit the potential difference between local nodes, and prevent the drive voltage from being too high, which could damage the discharge main power switch QF12.

[0081] The discharge interlock drive upper transistor QH3 and the discharge interlock drive lower transistor QL1 form an interlock circuit, providing a fast turn-off loop.

[0082] The clamping current-limiting resistor R36 can be used to prevent accidental touches and accelerate the release of residual charge.

[0083] Understandably, through the above structure, the discharge main power switch QF12 has controllable switching and overvoltage resistance capabilities.

[0084] Furthermore, the current sampling unit includes sampling resistor RN8 and sampling resistor RN14. Sampling resistor RN8 and sampling resistor RN14 are connected between the node current + and node current -, and are used to sample and detect the charging and discharging current in the main circuit. Sampling resistor RN8 and sampling resistor RN14 can be connected in parallel to reduce the power consumption of a single sampling resistor and improve the sampling capability.

[0085] It should be noted that when the corresponding MOSFET is turned on, the current flows from the C- node through the charging main power switch QF1 to the P- node, then through the discharging main power switch QF12 to the current+ node, and finally through the sampling resistor RN8 and the sampling resistor RN14 to the current- node.

[0086] By controlling the conduction states of the main charging power switch QF1 and the main discharging power switch QF12 respectively, independent control of the main charging circuit and the main discharging circuit can be achieved.

[0087] To suppress voltage spikes and oscillations generated during the instantaneous switching of the main circuit, this embodiment includes a buffer absorption unit in the main circuit. The buffer absorption unit includes a charging absorption capacitor Cm1, a charging absorption resistor Rm2, a discharging absorption resistor Rm25, and a discharging absorption capacitor Cm2.

[0088] The charging absorption capacitor Cm1 and the charging absorption resistor Rm2 are connected in parallel. One end of the parallel branch is connected to the high-level node near C- and the upper end of the charging main power switch QF1, and the other end is connected to the middle longitudinal bus node. This parallel branch forms an RC absorption network, which is used to absorb peak energy, reduce dv / dt, and reduce high-frequency ringing when the charging main power switch QF1 switches.

[0089] The discharge absorption capacitor Cm2 and the discharge absorption resistor Rm25 are connected between the middle longitudinal bus and the node near the current +, and are used to filter and buffer the voltage fluctuations in the branch where the discharge main power switch QF12 is located.

[0090] In this embodiment, the auxiliary charging control unit is connected between the first and second terminals of the main charging power switch QF1, which is equivalent to connecting both ends of the main charging power switch QF1. Specifically, it includes: an auxiliary charging switch QG2, a first RC delay network, a first unidirectional conducting device Dm10, a first control device QH4, a first gate slope network, and a discharge resistor RG1. The auxiliary charging control unit is used to controllably conduct the auxiliary charging switch QG2 to form a bypass buffer path during the transient period when the main charging power switch QF1 is turned on or off, and exits the bypass state after a preset time.

[0091] It is understandable that when the main charging power switch QF1 experiences a transient turn-on or turn-off, the auxiliary charging switch QG2 will turn on for a short time to form a bypass buffer, making the voltage change across the main charging power switch QF1 smoother. After the delay ends, the auxiliary charging switch QG2 will turn off, and the main circuit will be normally turned on by the main charging power switch QF1.

[0092] The first RC delay network includes a first delay resistor RT2 and a first delay capacitor Cm3, and the first gate slope network includes a first gate slope resistor RB23 and a first gate filter C42.

[0093] Specifically, one end of the main current channel of the auxiliary charging switch QG2 is connected to the C- node, and the other end is connected to the output node of the right auxiliary branch. Its gate is connected to the emitter of the first controller QH4 through the first gate slope resistor RB23. The gate of the auxiliary charging switch QG2 is driven by the "charging control" signal through the delay network.

[0094] The output terminal of the first controller QH4 is connected to the C- node, its emitter is connected to the first gate slope resistor RB23, and its base is connected to the first delay resistor RT2. As a controlled device, the first controller QH4 gradually changes the gate drive potential of the auxiliary charging switch QG2 under the action of the delay network, thereby realizing the gradual turn-on or controlled de-energization of the auxiliary charging switch QG2.

[0095] The first delay resistor RT2 is connected at one end to the "charging control" input node and at the other end to the control node of the first controller QH4, and is used to limit the input control current.

[0096] The first unidirectional conducting device Dm10 is connected in the auxiliary charging drive branch to provide a unidirectional conducting path, making the delay directional.

[0097] The first delay capacitor Cm3 is connected across the first unidirectional conducting device Dm10. The first delay resistor RT2 and the first delay capacitor Cm3 form a charging delay timing network, which is used to delay the charging control signal so that the action of the auxiliary charging switch QG2 has a delay characteristic.

[0098] The first gate filter C42 is connected to the output terminal of the first controller QH4. The first gate slope resistor RB23 and the first gate filter C42 provide slope control and filtering for the gate of the auxiliary charging switch QG2, suppressing false turn-on caused by dv / dt.

[0099] The discharge resistor RG1 is connected in the auxiliary charging control branch to provide a discharge path.

[0100] In this embodiment, the auxiliary discharge control unit includes an auxiliary discharge switch QG1, a second RC delay network, a second unidirectional conduction device Dm8, a second control device QH2, a second gate slope network, and a discharge discharge resistor RG2.

[0101] The second RC delay network includes a second delay resistor RT1 and a second delay capacitor Cm53, and the second gate slope network includes a second gate slope resistor RB24 and a second gate filter C52.

[0102] Understandably, during the switching transient of the main power discharge switch QF12, the auxiliary discharge switch QG1 is delayed in conduction to provide a bypass buffer, thereby reducing turn-off spikes and conduction impacts. After the delay ends, the auxiliary discharge switch QG1 is deactivated, and the main circuit is normally conducted by the main power discharge switch QF12.

[0103] Specifically, one end of the main current channel of the auxiliary discharge switch QG1 is connected to the right auxiliary branch node, and the other end is connected to the current+ node. Its gate is connected to the emitter of the second controller QH2 through the second gate slope resistor RB24. The second gate slope resistor RB24 is used to control the gate charging and discharging current of the auxiliary discharge switch QG1. The gate of the auxiliary discharge switch QG1 is driven by the "discharge MOS control" signal through a delay network.

[0104] The second controller QH2 constitutes the pre-stage driver for the auxiliary discharge switch QG1. One end of QH2 is connected to the current + node, the control terminal is connected to the auxiliary discharge control branch, and the emitter is connected to the second gate slope resistor RB24. To control the rapid turn-off of the auxiliary discharge switch QG1, the second controller QH2, under the action of the delay network, gradually changes the gate drive of the auxiliary discharge switch QG1, resulting in controlled turn-on or controlled de-energization.

[0105] The second delay resistor RT1 is connected at one end to the "discharge MOS" control signal input terminal and at the other end to the control node of the second controller QH2, and is used to limit the current of the input signal.

[0106] The second unidirectional conducting device Dm8 is connected in the auxiliary discharge drive branch to form a unidirectional channel. The second unidirectional conducting device Dm8 provides a unidirectional conducting path, so that the turn-off / turn-on process has a directional delay.

[0107] The second delay capacitor Cm53 is connected between the auxiliary discharge control node and the reference node. It is used together with the second delay resistor RT1 to form an RC delay network, so that the discharge auxiliary branch has the characteristics of delayed conduction or delayed turn-off.

[0108] The second gate filter C52 is connected near the output of the second controller QH2 to stabilize the drive waveform of the auxiliary discharge switch QG1. The second gate slope resistor RB24 and the second gate filter C52 provide slope control and filtering for the gate of the auxiliary discharge switch QG1, reducing the risk of false turn-on.

[0109] The discharge resistor RG2 is connected to the gate-related branch of the auxiliary discharge switch QG1 to provide a gate discharge path.

[0110] It should be noted that the auxiliary charging control unit and the auxiliary discharging control unit are independent of each other, and their delay parameters can be set separately to adapt to the different transient characteristics of the charger end and the load end.

[0111] A method for a MOS-controlled bypass delay protection circuit in the main circuit of a battery management system (BMS) includes the following steps:

[0112] Charging direction (involving QF1, QG2, and RG1);

[0113] The control unit sends a charging enable signal to drive the main charging power switch QF1 to prepare for conduction;

[0114] During the transient phase of the main power switch QF1 conducting, the auxiliary charging control unit briefly turns on the auxiliary charging switch QG2 to form a buffer bypass across the main power switch QF1, limiting the rate of voltage change across QF1 and suppressing surges.

[0115] When the delay time is reached or a stable condition is detected, the auxiliary charging switch QG2 exits the bypass state, and the main charging power switch QF1 is stably turned on to bear the main current.

[0116] When charging is turned off or protection is triggered, the main charging power switch QF1 is turned off, and the auxiliary charging switch QG2 can be controlled to turn on / off for a short time to buffer the turn-off spike.

[0117] The discharge resistor RG1 in the auxiliary charging control branch is used to provide a charge discharge path, ensuring that the drive node quickly resets after being turned off and consumes residual energy.

[0118] Discharge direction (involving QF12, QG1, and RG2);

[0119] The control unit sends a discharge permission signal to drive the main power switch QF12 to prepare for conduction.

[0120] During the transient phase of the discharge main power switch QF12 conduction process, the auxiliary discharge control unit briefly turns on the auxiliary discharge switch QG1 to form a buffer bypass across the discharge main power switch QF12, limiting the rate of change of current / voltage.

[0121] After the delay ends, the auxiliary discharge switch QG1 is deactivated, and the main discharge power switch QF12 is stably turned on to bear the main current.

[0122] When the discharge is turned off or the protection is triggered, the main discharge power switch QF12 is turned off, and the auxiliary discharge switch QG1 is controlled to turn on / off in order to reduce the risk of turn-off spikes and false turn-on.

[0123] The discharge resistor RG2 is connected to the gate-related branch of the auxiliary discharge switch QG1 to provide a gate discharge path, ensuring that the gate charge is quickly discharged after turn-off and preventing false turn-on.

[0124] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0125] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A main loop MOS controlled bypass delay protection circuit for a battery management system (BMS), characterized in that, include: The main circuit power control unit includes a main charging switch unit, a main discharging switch unit, and a current sampling unit; An auxiliary charging control unit is connected across the first and second terminals of the main charging switch unit. It is used to form a bypass buffer path during the transient period when the main charging switch unit is turned on or off, and exit the bypass state after a preset time. An auxiliary discharge control unit is connected between the first and second terminals of the main discharge switch unit. It is used to form a bypass buffer path during the transient period when the main discharge switch unit is turned on or off, and exits the bypass state after a preset time.

2. A master circuit MOS controlled bypass delay protection circuit for a battery management system (BMS) according to claim 1, characterized in that: The main charging switch unit includes a main charging power switch transistor QF1 and its charging drive branch. The main charging power switch transistor QF1 is used to control the charging current path between the battery pack and the charger.

3. A master circuit MOS controlled bypass delay protection circuit for a battery management system (BMS) according to claim 2, characterized in that: The charging drive branch includes: The charging interlock drive upper transistor QH1 and the charging interlock drive lower transistor QL2 together form an interlock circuit, which is used to quickly pull down the gate of the charging main power switch transistor QF1 according to the charging control signal, so as to realize the rapid turn-off of the charging main power switch transistor QF1. The charging gate drive resistor R66 is used to limit the gate drive current, adjust the gate charging speed, and suppress switching oscillations. The charging gate discharge resistor Rm67 is used to form the discharge path of the gate of the charging main power switch QF1. The signal input resistor RF2 is used to introduce the external charging control signal into the driving branch of the main charging power switch QF1. The anti-reverse-feedback diode D34 is used to unidirectionally introduce the charging control signal into the drive network, while preventing the voltage of the drive stage from flowing back to the front-end control terminal. And the charging clamping diode D8 is used to provide a bypass path under specific operating conditions, limit the potential difference between local nodes to prevent the driving voltage from being too high, which could damage the charging main power switch QF1.

4. A master circuit MOS controlled bypass delay protection circuit for battery management system (BMS) according to claim 1, characterized in that: The main discharge switch unit includes a discharge main power switch transistor QF12 and its discharge drive branch. The discharge main power switch transistor QF12 is used to control the discharge current path between the battery pack and the load.

5. A master circuit MOS controlled bypass time delay protection circuit for a battery management system (BMS) according to claim 4, characterized in that: The discharge drive branch includes: Discharge interlock drive upper tube QH3, discharge interlock drive lower tube QL1; The discharge gate drive resistor Rm15 is used to limit the gate charging and discharging current of the discharge main power switch QF12 and suppress gate oscillation during the switching process. The discharge bias resistor Rm3 and the discharge bleed resistor Rm26 are used to bias, bleed and stabilize the drive input to prevent the main power switch QF12 from being mis-turned when the control signal is floating. Clamping current-limiting resistor R36 prevents accidental contact and accelerates the release of residual charge; The isolation diode Dm6 is used to unidirectionally introduce the discharge control signal into the drive network, while preventing the voltage of the drive stage from flowing back to the front-end control terminal; The discharge clamping diode Dm7 is used to provide a bypass path under specific operating conditions, limit the potential difference between local nodes to prevent excessive drive voltage, which could damage the discharge main power switch QF12.

6. A master circuit MOS controlled bypass time delay protection circuit for battery management system (BMS) according to claim 1, characterized in that: The current sampling unit includes sampling resistor RN8 and sampling resistor RN14. The sampling resistor RN8 and sampling resistor RN14 are connected between node current + and node current -, and are used to sample and detect the charging and discharging current in the main circuit.

7. The main circuit MOS controlled bypass delay protection circuit for a battery management system (BMS) according to claim 5, characterized in that: It also includes a buffer absorption unit, which includes a charging absorption capacitor Cm1, a charging absorption resistor Rm2, a discharging absorption resistor Rm25, and a discharging absorption capacitor Cm2. The charging absorption capacitor Cm1 and the charging absorption resistor Rm2 are used to absorb peak energy, reduce dv / dt, and reduce high-frequency ringing when the main charging power switch QF1 switches. The discharging absorption capacitor Cm2 and the discharging absorption resistor Rm25 are used to filter and buffer the voltage fluctuations in the branch where the main discharging power switch QF12 is located.

8. The main circuit MOS controlled bypass delay protection circuit for a battery management system (BMS) according to claim 1, characterized in that: The auxiliary charging control unit includes: The auxiliary charging switch QG2 is used to form a bypass buffer when the main charging power switch QF1 is in a transient state of being turned on or off, so that the voltage change across the main charging power switch QF1 is smoother. The first RC delay network includes a first delay resistor RT2 and a first delay capacitor Cm3, which is used to delay the charging control signal so that the operation of the auxiliary charging switch QG2 has a delay characteristic. The first unidirectional conducting device Dm10 is used to provide a unidirectional conducting path, making the delay directional; The first controller QH4 is used as a controlled device to gradually change the gate drive potential of the auxiliary charging switch QG2 under the action of the delay network, so as to realize the gradual turn-on or controlled turn-off of the auxiliary charging switch QG2. The first gate slope network includes a first gate slope resistor RB23 and a first gate filter C42, which are used to provide slope control and filtering for the gate of the auxiliary charging switch QG2 to suppress false turn-on caused by dv / dt. And discharge resistor RG1, used to provide a discharge path.

9. The main circuit MOS controlled bypass delay protection circuit for a battery management system (BMS) according to claim 1, characterized in that: The auxiliary discharge control unit includes: The auxiliary discharge switch QG1 is used to provide a bypass buffer by being turned on for a short time during the switching transient of the main power switch QF12, thereby reducing turn-off spikes and turn-on impacts. The second RC delay network includes a second delay resistor RT1 and a second delay capacitor Cm53, which are used to enable the discharge auxiliary branch to have delayed conduction or delayed turn-off characteristics. The second unidirectional conduction device Dm8 is used to provide a unidirectional conduction path, so that the turn-off or turn-on process has a directional delay; The second control device QH2 constitutes the front-end driver device of the auxiliary discharge switch QG1 and is used to control the rapid turn-off of the auxiliary discharge switch QG1. Under the action of the delay network, the second control device QH2 gradually changes the gate drive of the auxiliary discharge switch QG1 to form controlled turn-on or controlled turn-off. The second gate slope network, which includes a second gate slope resistor RB24 and a second gate filter C52, is used to provide slope control and filtering for the gate of the auxiliary discharge switch QG1 to reduce the risk of false turn-on. And discharge resistor RG2, used to provide a gate discharge path.

10. A method for a controlled bypass delay protection circuit for the main circuit MOS of a battery management system (BMS), characterized in that, Includes the following steps: During charging, the control unit sends a charging enable signal to drive the main charging power switch QF1 to prepare for conduction; During the transient phase of the main power switch QF1 conducting, the auxiliary charging control unit briefly turns on the auxiliary charging switch QG2 to form a buffer bypass across the main power switch QF1, limiting the rate of voltage change across QF1 and suppressing surges. When the delay time is reached or a stable condition is detected, the auxiliary charging switch QG2 exits the bypass state, and the main charging power switch QF1 is stably turned on to bear the main current. When charging is turned off or protection is triggered, the main charging power switch QF1 is turned off, and the auxiliary charging switch QG2 can be controlled to turn on / off for a short time to buffer the turn-off spike. During discharge, the control unit sends a discharge permission signal to drive the main power switch QF12 to prepare for conduction; During the transient phase of the discharge main power switch QF12 conduction process, the auxiliary discharge control unit briefly turns on the auxiliary discharge switch QG1 to form a buffer bypass across the discharge main power switch QF12, limiting the rate of change of current / voltage. After the delay ends, the auxiliary discharge switch QG1 is deactivated, and the main discharge power switch QF12 is stably turned on to bear the main current. When the discharge is turned off or the protection is triggered, the main discharge power switch QF12 is turned off, and the auxiliary discharge switch QG1 is controlled to turn on / off to reduce the risk of turn-off spikes and false turn-on.

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