Design method of software radio intelligent voice noise reduction system
By using a software radio system based on Xilinx Zynq7020 and AD9361 chips, combined with FPGA hardware parallel acceleration and reconfigurable design, the problem of real-time voice noise reduction in complex noise environments of traditional platforms is solved, realizing efficient, flexible, and low-power intelligent voice communication.
Patent Information
- Application Number
- CN202511267528.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-05
- Publication Date
- 2025-12-12
AI Technical Summary
Traditional software radio platforms based on CPUs or DSPs struggle to meet the demands of high throughput and parallel computing when processing complex intelligent speech denoising algorithms, leading to increased processing latency and difficulty in achieving real-time voice interaction, especially in broadband or multi-channel scenarios where performance is limited.
The software-defined radio intelligent speech noise reduction system, which uses Xilinx Zynq7020 and AD9361 chips, combines the hardware parallel acceleration and reconfigurability of FPGA. Through DCNN hardware accelerator and spectrum monitoring unit, it realizes anti-aliasing filtering, speech framing, convolution, activation, pooling and DQPSK modulation and demodulation, and supports frequency band switching to adapt to complex noise environments.
It achieves intelligent voice communication with high real-time performance, high flexibility and high performance, improves voice clarity and signal-to-noise ratio, has frequency band adaptability and low power consumption characteristics, and is suitable for portable or embedded application scenarios.
Smart Images
Figure CN121122297A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of communication technology, in particular to a software radio intelligent voice noise reduction system design method. BACKGROUND
[0002] It is a key challenge for current wireless communication to realize high-quality and low-delay real-time voice communication under complex electromagnetic environment and strong noise interference. Although the traditional software radio platform based on general-purpose processor (CPU) or digital signal processor (DSP) has the advantage of flexibility, it faces significant bottlenecks in processing increasingly complex intelligent voice noise reduction algorithms (such as deep neural networks): its serial processing architecture is difficult to efficiently meet the high throughput and parallel computing requirements inherent in voice signal processing, resulting in increased processing delay and difficulty in meeting the millisecond-level response requirements required for real-time voice interaction, especially in wideband or multi-channel scenarios.
[0003] Therefore, there is an urgent need for a software radio intelligent voice noise reduction system design method based on field programmable gate array (FPGA) to realize high real-time, high flexibility and high performance intelligent voice communication in complex noise environment. SUMMARY
[0004] The purpose of the present application is to overcome the shortcomings of the prior art and provide a software radio intelligent voice noise reduction system design method that can meet the high real-time, high flexibility and high performance intelligent voice noise reduction requirements in complex noise environment.
[0005] To achieve the above-mentioned application purposes, the technical solutions adopted by the present application are as follows:
[0006] The present application provides a software radio intelligent voice noise reduction system design method, comprising an SDR board card and a xilinx zynq7020 chip and a digital-to-analog conversion / analog-to-digital conversion module arranged on the SDR board card, the xilinx zynq7020 chip running a pre-processing module, a DCNN hardware accelerator, a DQPSK modulation and demodulation module, and a spectrum monitoring unit, the xilinx zynq7020 chip comprising a PS end and a PL end, wherein the PS end runs the spectrum monitoring unit, and the PL end runs the pre-processing module, the DCNN hardware accelerator and the DQPSK modulation and demodulation module;
[0007] The design method comprises the following steps:
[0008] Step one: the PS end runs an embedded operating system, the analog-to-digital conversion / digital-to-analog conversion module collects voice radio frequency signals, and after down-conversion and digitization, the I / Q data is directly sent to the PL end through a high-speed interface, the data first passes through the pre-processing module for anti-aliasing filtering and voice framing processing, and then is input to the deep optimized DCNN hardware accelerator;
[0009] Step two: the DCNN hardware accelerator convolves, activates and pools the input data, and inputs it into a DQPSK modulation and demodulation module for differential encoding, pulse shaping filtering and quadrature carrier modulation, to generate a baseband signal to be transmitted, and returns to an analog-to-digital conversion / digital-to-analog conversion module for up-conversion and radio frequency transmission, forming a full hardware accelerated closed loop processing pipeline;
[0010] Step three: the PS end continuously monitors the received signal quality through a spectrum monitoring unit, and when it detects that the current working frequency band has strong interference leading to a decrease in communication quality, it automatically generates a control instruction according to a preset strategy, driving the analog-to-digital conversion / digital-to-analog conversion module to quickly switch to a backup clean communication frequency band, thereby ensuring the robustness of the communication link.
[0011] Preferably, the PS end is the processing part in the xilinx zynq7020 chip, which is an arm architecture-based processor subsystem responsible for global system control, communication protocol management and dynamic parameter configuration of the radio frequency front end of the analog-to-digital conversion / digital-to-analog conversion module; the dynamic parameter settings include frequency band, gain and bandwidth adjustment.
[0012] Preferably, the analog-to-digital conversion / digital-to-analog conversion module uses an AD9361 chip.
[0013] Preferably, the signal quality includes signal-to-noise ratio and bit error rate.
[0014] Preferably, the DQPSK modulation and demodulation module modulates and demodulates the data, and if the bit error rate of the demodulated data exceeds a preset threshold, it indicates that channel interference has affected data transmission, i.e. the communication quality has decreased.
[0015] Preferably, when the spectrum monitoring unit detects that the signal-to-noise ratio of the received signal is lower than a preset threshold, it indicates that the noise or interference power significantly exceeds the useful signal, i.e. the communication quality has decreased.
[0016] Preferably, the spectrum monitoring unit monitors the amplitude and phase of the spectrum by converting the time domain signal into a frequency domain signal using the Fourier transform calculation formula; the Fourier transform calculation formula is as follows:
[0017]
[0018] where F(jω) is the spectral density function of the signal f(t), t is time, ω is the angular frequency, j is the imaginary unit, e -jωt is a complex exponential function.
[0019] Preferably, the preset strategy is: when the SNR of 100 consecutive periods is lower than a preset threshold, the frequency band switching is triggered; each period is 5 ms, and the SNR is represented as:
[0020] SNR: 10*log10(Ps / Pn)
[0021] wherein Ps represents the average power of the signal, and Pn represents the average power of the noise.
[0022] Preferably, the convolution operation is completed by sliding a filter to perform element multiplication and summation on the input data; the formula is as follows:
[0023]
[0024] wherein the input feature map is the convolution kernel is the output feature map is (i,j) is the position on the output feature map, c in is the input channel index, C out is the output channel index, is the bias term corresponding to the output channel, k h and k w respectively represent the height and width of the convolution kernel, which define the size of the local receptive field used in the convolution operation; H and W respectively represent the height and width of the input feature map, which describe the spatial dimensions of the input data, and m and n are position indexes for traversing within the convolution kernel; H' and W' respectively represent the height and width of the output feature map.
[0025] The activation operation uses RELU as the activation function, and for any input number x, the calculation formula of the ReLU activation function is as follows:
[0026] f(x) = max(0, x),
[0027] for the input feature map the output feature map after ReLU activation is:
[0028]
[0029] wherein c represents the channel index of the input feature map X, c in is the input channel index, and c is an index variable for traversing all channels of the input feature map, c in -1; Y(i,j,c) represents the value of the output feature map at position (i,j) and channel c. X(i,j,c) represents the value of the input feature map at the same position and channel;
[0030] The pooling operation: average pooling is adopted, the average value in each pooling window is selected as the output by setting the pooling window size and step, the pooling operation is completed, and the formula is as follows:
[0031]
[0032] Wherein, the size of the pooling window is p h ×p w The step of the pooling window sliding on the input feature map is s h ×s w P h Indicates the height of the pooling window, defines the size of the area in the vertical direction for the pooling operation, p w Indicates the width of the pooling window, defines the size of the area in the horizontal direction for the pooling operation, s h Indicates the step of the pooling operation in the vertical direction, representing the number of pixels in the vertical direction when the pooling window moves each time; s w Indicates the step of the pooling operation in the horizontal direction, representing the number of pixels in the horizontal direction when the pooling window moves each time.
[0033] Advantages
[0034] Compared with the prior art, the beneficial effects obtained by the present application are:
[0035] The software radio intelligent voice noise reduction system of the application is designed as a software radio intelligent voice noise reduction system adopting Xilinx Zynq7020 chip and AD9361 chip, and through the innovative heterogeneous computing architecture, excellent performance improvement is realized. The ARM processor and FPGA integrated in the Xilinx Zynq7020 chip closely cooperate, fully exert the hardware parallel acceleration advantage, so that the complex DCNN intelligent noise reduction model can run efficiently, and the voice clarity and signal-to-noise ratio are significantly improved. At the same time, the flexibility, the core feature of software radio, is fully embodied in the system: the AD9361 radio frequency front end supports wide frequency band adjustment, so that the system can seamlessly adapt to various wireless communication frequency bands and standards; and the reconfigurable ability based on FPGA further supports the remote dynamic update and optimization of the DCNN noise reduction algorithm without interrupting the service, and endows the system with strong environmental adaptability and continuous evolution ability.
[0036] This invention not only boasts excellent intelligent noise reduction performance but also excels in communication reliability and overall energy efficiency. The adoption of DQPSK modulation technology effectively enhances the anti-interference capability and transmission robustness of the baseband signal under complex channel conditions, ensuring the quality of the voice communication link. The heterogeneous architecture of the Xilinx Zynq7020 chip, through reasonable hardware and software task partitioning and collaborative optimization, achieves high-efficiency operation of the entire system, significantly reducing power consumption and making it highly suitable for portable or embedded applications with long battery life requirements. Ultimately, this end-to-end solution, integrating high-performance intelligent noise reduction, full-band software radio flexibility, robust anti-interference communication, and low-power design, provides strong technical support for achieving clear, reliable, and real-time voice communication in harsh noisy environments. Attached Figure Description
[0037] Figure 1 This is a flowchart illustrating the design method of the software-defined radio intelligent voice noise reduction system of the present invention.
[0038] Figure 2 The diagram shows the DCNN intelligent noise reduction model of the software radio intelligent speech noise reduction system design method of the present invention. Detailed Implementation
[0039] To make the objectives, technical solutions, and advantages of the present invention clearer and more complete, the present invention will be further described in detail below with reference to the embodiments. Obviously, the embodiments described below are some embodiments of the present invention, but the scope of protection claimed by the present invention is not limited to the specific embodiments below.
[0040] like Figure 1 As shown, a software-defined radio intelligent voice noise reduction system design method includes an SDR board and a Xilinx Zynq7020 chip and a digital-to-analog converter / analog-to-digital converter module mounted on the SDR board. The analog-to-digital converter / digital-to-analog converter module uses the AD9361 chip. The AD9361 chip is a high-performance, highly integrated RF transceiver that integrates the RF front-end and a flexible mixed-signal baseband section. It integrates a frequency synthesizer and has two independent direct-conversion receivers. Each receiver subsystem has independent automatic gain control, DC offset correction, quadrature correction, and digital filtering functions. At the same time, the transmitter of the AD9361 chip adopts a direct-conversion architecture, which can achieve high modulation accuracy and ultra-low noise.
[0041] The xilinx zynq7020 chip runs the preprocessing module, the DCNN hardware accelerator, the DQPSK modulation and demodulation module and the spectrum monitoring unit, the xilinx zynq7020 chip includes a PS end and a PL end, wherein the PS end runs the spectrum monitoring unit, the PL end runs the preprocessing module, the DCNN hardware accelerator and the DQPSK modulation and demodulation module; the PS end (Processing System (PS) end, the PS end is the processing system part in the Xilinx ZYNQ7020 chip, which is an arm architecture-based processor subsystem), responsible for global system control, communication protocol management and dynamic parameter configuration of the AD9361 chip radio frequency front end, such as frequency band, gain and bandwidth adjustment. The PL end (Programmable Logic (PL) end, the PL end is the programmable logic part in the Zynq chip, which is based on FPGA architecture, allows users to realize custom hardware logic according to requirements, realizes key high-speed data processing through customized hardware logic design, and this architecture ensures seamless high-speed flow of radio frequency signals to baseband processing, laying the foundation for low delay. The design method of the application makes full use of the hardware parallel processing capability of FPGA to accelerate the computationally intensive intelligent noise reduction algorithm, and realizes extremely low delay; at the same time, combining the high reconfigurability of FPGA, it can flexibly adapt to different wireless communication waveforms and frequency bands (inheriting the flexibility of software radio), and can also optimize hardware level for specific noise reduction algorithms.
[0042] As shown in Figure 1 The design method comprises the following steps:
[0043] Step one, the PS end runs an embedded operating system, the analog / digital conversion module collects voice radio frequency signals, and after down-conversion and digitization, the I / Q data is directly sent to the PL end through a high-speed interface, the data is first subjected to anti-aliasing filtering and voice framing by the preprocessing module (i.e. anti-aliasing filtering is performed by a digital FIR low-pass filter to filter out high-frequency noise interference, followed by noise reduction sampling, and then voice framing is performed, i.e. a Hamming window sliding window is used to divide continuous voice into fixed length frames such as 256 points.), and then input into the deeply optimized DCNN hardware accelerator.
[0044] Step two: after the DCNN hardware accelerator performs convolution, activation and pooling operations on the input data, the data is input into the DQPSK modulation and demodulation module to perform differential encoding, pulse shaping filtering and quadrature carrier modulation, to generate a baseband signal to be transmitted, and the baseband signal is fed back to the analog / digital conversion module for up-conversion and radio frequency transmission, forming a full hardware accelerated closed loop processing pipeline;
[0045] Specifically, the convolution process is that: the convolution layer processes the input data by applying a filter, which element-wise multiplies and sums with the local region of the input data to generate a feature map; that is, it is completed by sliding a filter on the input data to perform element multiplication and summation; the formula is as follows:
[0046]
[0047] wherein: the input feature map is the convolution kernel is the output feature map is (i, j) is the position on the output feature map, c in is the input channel index, C out is the output channel index, is the bias term corresponding to the output channel, k h and k w respectively represent the height and width of the convolution kernel, which define the size of the local receptive field used in the convolution operation; H and W represent the height and width of the input feature map respectively, which describe the spatial dimensions of the input data, and m and n are position indexes for traversing within the convolution kernel; H' and W' represent the height and width of the output feature map respectively.
[0048] The activation operation uses RELU as the activation function, and for any input number x, the calculation formula of the ReLU activation function is as follows:
[0049] f(x) = max(0, x),
[0050] for the input feature map the output feature map after ReLU activation is:
[0051]
[0052] wherein c represents the channel index of the input feature map X, c in is the input channel index, c is an index variable for traversing all channels of the input feature map, and c takes a value range of 0 to c in -1; Y(i, j, c) represents the value of the output feature map at position (i, j) and channel c. X(i, j, c) represents the value of the input feature map at the same position and channel;
[0053] The pooling operation adopts average pooling, and by setting the pooling window size and step, the average value in each pooling window is selected as the output to complete the pooling operation, and the formula is as follows:
[0054]
[0055] wherein the pooling window size is p h x pw The pooling window slides on the input feature map with a stride of s. h ×s w p h p represents the height of the pooling window, defining the size of the region where pooling operations are performed vertically. w This represents the width of the pooling window, defining the size of the region where pooling operations are performed horizontally. h This represents the step size of the pooling operation in the vertical direction, indicating the number of pixels the pooling window advances vertically with each movement; s w This represents the step size of the pooling operation in the horizontal direction, which is the number of pixels the pooling window moves forward in the horizontal direction each time it moves.
[0056] like Figure 2 As shown, the DCNN (Deep Convolutional Neural Network) hardware accelerator uses a DCNN intelligent noise reduction model. This model is specifically trained for filtering external environmental noise. An example of the DCNN intelligent noise reduction model's workflow is as follows:
[0057] The input feature map, with a data shape of [129, 8, 1], contains data information in terms of frequency, time, and number of channels. The input data is zero-padding in a ZeroPadding2D layer to ensure the output size of subsequent convolutional operations matches expectations. Then, it enters a repeated convolutional module for convolution operations, using ReLU activation and BatchNormalization to introduce non-linearity, accelerate training, and improve model stability. Skip connections are designed between the second and eleventh, and fifth and eighth convolutional modules. These skip connections add the output of earlier layers to the output of the current layer before continuing with subsequent convolutions, activations, and normalization operations, mitigating the vanishing gradient problem and enabling the network to learn more complex feature representations. After the output of the last convolutional module, it enters a SpatialDropout2D layer, randomly zeroing out a portion of the entire feature map to reduce overfitting and improve the model's generalization ability. The final convolutional layer transforms the feature map into the final output data with a shape of [129, 1, 1].
[0058] Step 3: To cope with the complex and ever-changing electromagnetic environment, this invention designs an intelligent spectrum management mechanism. The PS end continuously monitors the quality of the received signal (such as signal-to-noise ratio and bit error rate) through a spectrum monitoring unit. When the spectrum monitoring unit detects strong interference in the current operating frequency band that causes a decline in communication quality (i.e., when the spectrum monitoring unit detects that the signal-to-noise ratio of the received signal is lower than a preset threshold, indicating that the noise or interference power significantly exceeds the useful signal, or the bit error rate after DQPSK modulation and demodulation exceeds a preset range, indicating that channel interference has affected the reliability of data transmission), it automatically generates control commands according to a preset strategy to drive the AD9361 to quickly switch to a backup clean communication frequency band, effectively avoiding interference sources and ensuring the robustness of the communication link.
[0059] Specifically, the spectrum monitoring unit uses the Fourier transform formula to convert the time-domain signal into a frequency-domain signal to monitor the amplitude and phase of the spectrum. The Fourier transform formula is as follows;
[0060]
[0061] Where F(jω) is the spectral density function of the signal f(t), t is time, ω is the angular frequency, j is the imaginary unit, and e is the frequency. -jωt It is a complex exponential function.
[0062] The preset strategy is as follows: when the signal-to-noise ratio (SNR) is lower than a preset threshold for 100 consecutive cycles (5ms per cycle), a frequency band switch is triggered; the SNR is expressed as:
[0063] SNR: 10*log10(Ps / Pn)
[0064] Where Ps represents the average power of the signal, and Pn represents the average power of the noise.
[0065] This invention presents a software-defined radio (SDR) intelligent voice noise reduction system design method. Utilizing a SDR intelligent voice noise reduction system based on the Xilinx Zynq7020 and AD9361 chips, it achieves significant performance improvements through an innovative heterogeneous computing architecture. The Zynq7020 chip's integrated ARM processor and FPGA work closely together, fully leveraging the advantages of hardware parallel acceleration. This enables the complex DCNN intelligent noise reduction model to run efficiently, significantly improving voice clarity and signal-to-noise ratio. Simultaneously, the core characteristic of SDR—flexibility—is fully reflected in this system: the AD9361 chip's RF front-end supports wide-band adjustable frequency, allowing the system to seamlessly adapt to various wireless communication frequency bands and standards; while the FPGA's reconfigurability supports remote dynamic updates and optimizations of the DCNN noise reduction algorithm without service interruption, endowing the system with strong environmental adaptability and continuous evolution capabilities. This design, combining SDR spectrum flexibility with heterogeneous computing hardware acceleration, enables the system to continuously provide clear, reliable, and real-time voice communication capabilities in various high-noise and strong-interference real-world application scenarios, with all core processing efficiently completed within a single-chip system.
[0066] This invention not only boasts excellent intelligent noise reduction performance but also excels in communication reliability and overall energy efficiency. The adoption of DQPSK modulation technology effectively enhances the anti-interference capability and transmission robustness of the baseband signal under complex channel conditions, ensuring the quality of the voice communication link. The heterogeneous architecture of the Xilinx Zynq7020 chip, through reasonable hardware and software task partitioning and collaborative optimization, achieves high-efficiency operation of the entire system, significantly reducing power consumption and making it highly suitable for portable or embedded applications with long battery life requirements. Ultimately, this end-to-end solution, integrating high-performance intelligent noise reduction, full-band software radio flexibility, robust anti-interference communication, and low-power design, provides strong technical support for achieving clear, reliable, and real-time voice communication in harsh noisy environments.
[0067] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Based on the disclosure and teachings of the above specification, those skilled in the art can also make changes and modifications to the above embodiments. Therefore, this invention is not limited to the specific embodiments disclosed and described above, and some modifications and changes to the invention should also fall within the scope of protection of the claims of this invention. Furthermore, although some specific terms are used in this specification, these terms are only for convenience of explanation and do not constitute any limitation on this invention.
Claims
1. A design method for a software-defined radio intelligent voice noise reduction system, characterized in that, The device includes an SDR board and a Xilinx Zynq7020 chip and a digital-to-analog converter / analog-to-digital converter module mounted on the SDR board. The Xilinx Zynq7020 chip runs a preprocessing module, a DCNN hardware accelerator, a DQPSK modulation and demodulation module, and a spectrum monitoring unit. The Xilinx Zynq7020 chip includes a PS end and a PL end, wherein the PS end runs the spectrum monitoring unit, and the PL end runs the preprocessing module, the DCNN hardware accelerator, and the DQPSK modulation and demodulation module. This design method includes the following steps: Step 1: The PS terminal runs an embedded operating system. The analog-to-digital converter / digital-to-analog converter module collects the voice radio frequency signal, performs down-conversion and digitization, and its I / Q data is directly sent to the PL terminal through a high-speed interface. The data first passes through the preprocessing module for anti-aliasing filtering and voice frame processing, and then is input to the depth-optimized DCNN hardware accelerator. Step 2: After the DCNN hardware accelerator performs convolution, activation, and pooling operations on the input data, it inputs the data into the DQPSK modulation and demodulation module for differential coding, pulse shaping filtering, and quadrature carrier modulation to generate the baseband signal to be transmitted. The signal is then sent back to the analog-to-digital converter / digital-to-analog converter module for up-conversion and radio frequency transmission, forming a fully hardware-accelerated closed-loop processing pipeline. Step 3: The PS terminal continuously monitors the quality of the received signal through the spectrum monitoring unit. When strong interference is detected in the current working frequency band, causing a decrease in communication quality, the PS terminal automatically generates control commands according to the preset strategy to drive the analog-to-digital converter / digital-to-analog converter module to quickly switch to the backup clean communication frequency band, ensuring the robustness of the communication link.
2. The design method of a software-defined radio intelligent voice noise reduction system according to claim 1, characterized in that: The PS terminal is the processing part of the Xilinx Zynq7020 chip, which is an ARM-based processor subsystem responsible for global system control, communication protocol management, and dynamic parameter configuration of the RF front-end of the analog-to-digital converter / digital-to-analog converter module; the dynamic parameter settings include frequency band, gain, and bandwidth adjustment.
3. The design method for a software-defined radio intelligent voice noise reduction system according to claim 2, characterized in that: The analog-to-digital converter / digital-to-analog converter module uses the AD9361 chip.
4. The design method of a software-defined radio intelligent voice noise reduction system according to claim 1, characterized in that: The signal quality includes the signal-to-noise ratio and the bit error rate.
5. The design method of a software-defined radio intelligent voice noise reduction system according to claim 4, characterized in that: The DQPSK modulation and demodulation module performs modulation and demodulation processing on the data. If the bit error rate of the demodulated data exceeds the preset threshold, it indicates that channel interference has affected data transmission, i.e., the communication quality has deteriorated.
6. The design method of a software-defined radio intelligent voice noise reduction system according to claim 5, characterized in that: When the spectrum monitoring unit detects that the signal-to-noise ratio of the received signal is lower than a preset threshold, it indicates that the noise or interference power significantly exceeds the useful signal, i.e., the communication quality deteriorates.
7. The design method of a software-defined radio intelligent voice noise reduction system according to claim 6, characterized in that: The spectrum monitoring unit uses the Fourier transform formula to convert the time-domain signal into a frequency-domain signal to monitor the amplitude and phase of the spectrum. The Fourier transform formula is as follows: Where F(jω) is the spectral density function of the signal f(t), t is time, ω is the angular frequency, j is the imaginary unit, and e is the frequency. -jωt It is a complex exponential function.
8. The design method of a software-defined radio intelligent voice noise reduction system according to claim 7, characterized in that: The preset strategy is as follows: when the signal-to-noise ratio (SNR) is lower than a preset threshold for 100 consecutive cycles, a frequency band switch will be triggered; each cycle is 5ms, and the SNR is expressed as: SNR: 10*log10(Ps / Pn), Where Ps represents the average power of the signal, and Pn represents the average power of the noise.
9. The design method of a software-defined radio intelligent voice noise reduction system according to claim 1, characterized in that: The convolution operation is performed by sliding a filter, performing element-wise multiplication on the input data, and then summing the results; the formula is as follows: Where: the input feature map is Convolution kernel is Output feature map (i, j) is the position on the output feature, c in It is the input channel index, C out It is the output channel index. This is the bias term corresponding to the output channel, k h and k w H and W represent the height and width of the convolution kernel, respectively, defining the size of the local receptive field used in the convolution operation; H and W represent the height and width of the input feature map, respectively, describing the spatial size of the input data; m and n are the position indices used to traverse the convolution kernel; H′ and W′ represent the height and width of the output feature map, respectively. The activation operation uses ReLU as the activation function. For any input number x, the ReLU activation function is calculated as follows: f(x) = max(0,x), For the input feature map The output feature map after ReLU activation is: Where c represents the channel index of the input feature map X, c in Here, 'c' is the input channel index, and 'c' is an index variable used to iterate through all channels of the input feature map. The value of 'c' ranges from 0 to c. in -1; Y(i,j,c) represents the value of the output feature map at position (i,j) and channel c; X(i,j,c) represents the value of the input feature map at the same position and channel; The pooling operation employs average pooling. By setting the pooling window size and stride, the average value within each pooling window is selected as the output to complete the pooling operation. The formula is as follows: Where the pooling window size is p h ×p w The pooling window slides on the input feature map with a stride of s. h ×s w p h p represents the height of the pooling window, defining the size of the region where pooling operations are performed vertically. w This represents the width of the pooling window, defining the size of the region where pooling operations are performed horizontally. h This represents the step size of the pooling operation in the vertical direction, indicating the number of pixels the pooling window advances vertically with each movement; s w This represents the step size of the pooling operation in the horizontal direction, which is the number of pixels the pooling window advances horizontally each time it moves.