A protection circuit for preventing overvoltage during power-up

Abstract

The application discloses a protection circuit for preventing overvoltage during power-on, and relates to a chip circuit. The present scheme is proposed in view of the problem that the overvoltage protection means in the prior art is imperfect. The protection circuit comprises a pulse control signal generation module and a low-resistance switch. The pulse control signal generation module acquires a power-on signal of a working circuit to be protected, and outputs a single pulse control signal to an enable end of the low-resistance switch. The low-resistance switch pulls an overvoltage node of the working circuit to be protected to a safe level under the action of the control signal. The advantage is that the overvoltage node during power-on is protected by using a digital circuit with rapid response and a complementary switch at all times, and the protection no longer depends on real-time monitoring of the node. The low-resistance switch can continuously keep closed after completing the power-on protection, and does not interfere with the subsequent normal operation of the working circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to chip circuit, especially to a protection circuit for preventing overvoltage during power-up. BACKGROUND

[0002] With the continuous progress of semiconductor manufacturing process, the feature size of integrated circuits is continuously reduced, and the supply voltage of core devices is also reduced to balance power consumption, speed and reliability. However, in many application scenarios, the chip still needs to communicate with external devices or systems with higher voltage (such as memory interface, display driver, etc.); or internal modules still need to mix high and low voltage domains to maintain the high performance and large signal processing capability of the module (such as ADC, DAC, SerDes, etc.).

[0003] Therefore, in modern system-on-chip, there are generally mixed voltage domain circuits that integrate high-voltage-resistant MOS tubes and standard MOS tubes with thin gate oxides. Generally, when the gate-source, source-drain, and source-body voltages exceed 1.1 or 1.2 times the standard voltage, it is overvoltage. In mixed voltage domains, circuits that mix high-voltage-resistant MOS tubes and standard MOS tubes, power-up transients can cause MOS tubes to be overvoltage. For example, the power-up establishment process of a negative feedback loop; standard MOS tubes with thin gate oxides are driven by modules in a high power voltage domain, which can cause voltage overshoot at circuit nodes. Overvoltage can reduce the life of MOS tubes, and long-term and large-scale overvoltage can even break down MOS tubes, causing chip failure.

[0004] A common overvoltage protection circuit is to continuously detect the key nodes of the circuit when the circuit is working normally and trigger the protection circuit when overvoltage is detected. However, due to the unstable state of the circuit nodes during power-up and the fact that each analog circuit is not in a normal working state, the common overvoltage protection circuit does not work. SUMMARY

[0005] The present application aims to provide a protection circuit for preventing overvoltage during power-up to solve the problems existing in the prior art.

[0006] The protection circuit for preventing overvoltage during power-up in the present application comprises a pulse control signal generation module and a low-resistance switch.

[0007] The pulse control signal generation module obtains the power-up signal of the working circuit to be protected and outputs a single pulse control signal to the enable end of the low-resistance switch.

[0008] The low-resistance switch pulls the overvoltage node of the working circuit to be protected to a safe level under the action of the control signal.

[0009] The structure of the low-resistance switch is as follows:

[0010] The source of the first PMOS is connected to the third node, the drain of the first PMOS is connected to the power-on overvoltage node of the working circuit to be protected, and the gate of the first PMOS is connected to the inverted enable signal.

[0011] The source of the first NMOS is connected to the third node, the drain of the first NMOS is connected to the power-on overvoltage node of the working circuit to be protected, and the gate of the first NMOS is connected to the enable signal.

[0012] The source of the second PMOS is connected to the power supply AVDD, the drain of the second PMOS is connected to one end of the first resistor, and the gate of the second PMOS is connected to the inverted enable signal.

[0013] The other end of the first resistor is connected to the third node.

[0014] One end of the second resistor is connected to the third node, and the other end is grounded.

[0015] The safe level is generated by the voltage division of the first resistor and the second resistor.

[0016] The inverted enable signal is generated by the enable signal passing through the third NAND gate.

[0017] The pulse control signal generation module structure is:

[0018] The input end of the first NAND gate is connected to the power-on signal, and the output end of the first NAND gate is connected to the second node.

[0019] The input end of the second NAND gate is connected to the second node, and the output end of the second NAND gate is connected to the gate of the third PMOS and the gate of the second NMOS, respectively.

[0020] The source of the third PMOS is connected to the power supply AVDD, and the drain of the third PMOS is connected to the first node.

[0021] The source of the second NMOS is grounded, and the drain of the second NMOS is connected to the first node after passing through the third resistor.

[0022] The upper plate of the first capacitor is connected to the first node, and the lower plate of the first capacitor is grounded.

[0023] The first input end of the XOR gate is connected to the first node, the second input end of the XOR gate is connected to the second node, and the output end of the XOR gate is connected to the enable end of the low-resistance switch as the output end of the pulse control signal generation module.

[0024] The source of the fourth PMOS is connected to the power supply AVDD, the drain of the fourth PMOS is connected to the output end of the XOR gate, and the gate of the fourth PMOS is connected to the power-on signal.

[0025] The protection circuit for preventing overvoltage during power-up has the advantages that the digital circuit with rapid response and the complementary switch are used to protect the overvoltage node during power-up at all times, and the real-time monitoring of the node is no longer relied on. The low-resistance switch can be kept closed after completing the protection of power-up, and does not interfere with the subsequent normal operation of the working circuit. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 is a structural schematic diagram of the protection circuit.

[0027] Figure 2 is a structural schematic diagram of the low-resistance switch.

[0028] Figure 3 is a schematic diagram of the on-resistance of the first PMOS transistor and the first NMOS transistor in the low-resistance switch.

[0029] Figure 4 is a structural schematic diagram of the pulse control signal generation module.

[0030] Figure 5 is a voltage timing diagram of the pulse control signal generation module.

[0031] Figure 6 is an application example schematic diagram of the protection circuit, and the working circuit is a bias circuit.

[0032] Figure 7 is Figure 6 is a voltage timing diagram when the fifth PMOS transistor shown in the fifth PMOS transistor is not connected to the protection circuit.

[0033] Figure 8 is Figure 6 is a voltage timing diagram after the fifth PMOS transistor shown in the fifth PMOS transistor is connected to the protection circuit.

[0034] Reference signs:

[0035] PM1-first PMOS transistor, PM2-second PMOS transistor, PM3-third PMOS transistor, PM4-fourth PMOS transistor, PM5-fifth PMOS transistor;

[0036] NM1-first NMOS transistor, NM2-second NMOS transistor;

[0037] R1-first resistance, R2-second resistance, R3-third resistance, R on,P on-resistance of the first PMOS transistor, R on,N on-resistance of the first NMOS transistor, R on,eq equivalent on-resistance of the first PMOS transistor and the first NMOS transistor;

[0038] C1 - First capacitor;

[0039] INV1 - First NOT gate, INV2 - Second NOT gate, INV3 - Third NOT gate;

[0040] XOR gate;

[0041] net1 - First node, net2 - Second node, net3 - Third node;

[0042] PWR - Power-on signal, EN - Enable signal, ENN - Inverting enable signal. Detailed Implementation

[0043] like Figure 1 As shown, the protection circuit for preventing power-on overvoltage in this invention includes a pulse control signal generation module and a low-impedance switch. The pulse control signal generation module acquires the power-on signal of the circuit to be protected and outputs a single-pulse control signal to the enable terminal of the low-impedance switch. Under the action of the control signal, the low-impedance switch pulls the power-on overvoltage node of the circuit to be protected to a safe level.

[0044] like Figure 2 As shown, the low-resistance switch structure is as follows:

[0045] The source of the first PMOS transistor PM1 is connected to the third node net3, the drain of the first PMOS transistor PM1 is connected to the overvoltage node of the circuit to be protected, and the gate of the first PMOS transistor PM1 is connected to the inverted enable signal.

[0046] The source of the first NMOS transistor NM1 is connected to the third node net3, the drain of the first NMOS transistor NM1 is connected to the overvoltage node of the circuit to be protected, and the gate of the first NMOS transistor NM1 is connected to the enable signal.

[0047] The source of the second PMOS transistor PM2 is connected to the power supply AVDD, the drain of the second PMOS transistor PM2 is connected to one end of the first resistor R1, and the gate of the second PMOS transistor PM2 is connected to the inverting enable signal.

[0048] The other end of the first resistor R1 is connected to the third node net3.

[0049] The second resistor R2 is connected at one end to the third node net3, and the other end is grounded.

[0050] The safe voltage level is generated by voltage division by the first resistor R1 and the second resistor R2.

[0051] The inverted enable signal is generated by passing the enable signal through the third NOT gate INV3.

[0052] The on-resistance of the complementary switch composed of the first PMOS PM1 and the first NMOS NM1 is as shown in Figure 3 Compared with the single-pipe switch, the complementary switch can maintain a lower on-resistance in a larger input range, so that the overvoltage node can be more quickly and accurately controlled at the potential of the first node net1.

[0053] The working principle of the low-resistance switch is as follows:

[0054] When EN is 1, ENN is 0, and the low-resistance switch works. All the three MOS tubes are turned on. Since the first resistor R1 and the second resistor R2 are voltage-divided, the voltage of the first node net1 is AVDD*R2 / (R1+R2), and the overvoltage node can be controlled near the voltage of the first node net1.

[0055] When EN is 0, ENN is 1, and the low-resistance switch is turned off. All the three MOS tubes are turned off, eliminating the static power consumption of the first resistor R1 and the second resistor R2 branch and not affecting the normal operation of the IN node.

[0056] As shown in Figure 4 The structure of the pulse control signal generation module is as follows:

[0057] The input end of the first NOT gate INV1 is connected to the power-on signal, and the output end of the first NOT gate INV1 is connected to the second node net2.

[0058] The input end of the second NOT gate INV2 is connected to the second node net2, and the output end of the second NOT gate INV2 is connected to the gate of the third PMOS PM3 and the gate of the second NMOS NM2.

[0059] The source of the third PMOS PM3 is connected to the power supply AVDD, and the drain of the third PMOS PM3 is connected to the first node net1.

[0060] The source of the second NMOS NM2 is grounded, and the drain of the second NMOS NM2 is connected to the first node net1 through the third resistor R3.

[0061] The upper plate of the first capacitor C1 is connected to the first node net1, and the lower plate of the first capacitor C1 is grounded.

[0062] The first input end of the XOR gate XOR is connected to the first node net1, the second input end of the XOR gate XOR is connected to the second node net2, and the output end of the XOR gate XOR is connected to the enable end of the low-resistance switch as the output end of the pulse control signal generation module.

[0063] The source of the fourth PMOS PM4 is connected to the power supply AVDD, the drain of the fourth PMOS PM4 is connected to the output end of the XOR gate XOR, and the gate of the fourth PMOS PM4 is connected to the power-on signal.

[0064] The working principle of the pulse control signal generation module is as follows:

[0065] S1. The pulse control signal generation module needs to be reset before the power-on of the working circuit to be protected, and waits for the power-on signal PWR to be pulled high, so PWR also serves as the reset signal of the pulse control signal generation module.

[0066] Specifically, when PWR is 0, the pulse control signal generation module is in a reset state, and OUT needs to be 1, because at this time, it is in a state that the power supply has been powered on but the working circuit has not started, and the circuit nodes are all in a high resistance state. Since there is a parasitic capacitor on the node or the node is connected to the power supply through a capacitor, during the power-on process of the power supply ramp, the charge will accumulate to cause overvoltage, and the low resistance switch also needs to be opened to discharge the charge. Since PWR is 0 at this time, the output of the first NOT gate INV1 is 1, so the second node net2 is 1; the output of the second NOT gate INV2 is 0, the second NMOS tube NM2 closes the third PMOS tube PM3 to turn on, so the first node net1 is 1; therefore, the output logic of the XOR gate is 0, but since the fourth PMOS tube PM4 is also in the on state, OUT outputs 1.

[0067] S2. After PWR is pulled high, the working circuit enters the power-on process, the pulse control signal generation module is out of the reset state and works normally, generates a high level with a duration of T as the enable signal EN of the low resistance switch, so that the low resistance switch is opened to pull the overvoltage node to a safe level. After the duration T, EN is pulled low to close the low resistance switch. At the same time, the working circuit to be protected is powered on and works normally.

[0068] Specifically, when PWR changes from 0 to 1, the fourth PMOS tube PM4 is turned off, the second node net2 quickly changes from 1 to 0 under the action of the first NOT gate INV1; the output of the second NOT gate INV2 quickly changes from 0 to 1, so that the second NMOS tube NM2 is turned on and the third PMOS tube PM3 is closed, and the first node net1 is discharged to 0 through the RC network and the second NMOS tube NM2 slowly, with a time constant of RC; therefore, when PWR changes from 0 to 1, the two input ports of the XOR gate are first 1 and 0, and after a period of time, both become 0, so OUT will maintain a high level for a period of time to open the low resistance switch, and then become a low level to turn off the low resistance switch.

[0069] Adjusting the value of RC can control the high level pulse width of OUT, and the specific voltage timing of the pulse control signal generation module is as follows: Figure 5As shown, from top to bottom are voltage waveforms of PWR, second node net2, first node net1 and OUT. First, PWR is 0, the circuit is in reset state, and the output keeps high level, then PWR flips to 1, one input of the XOR gate quickly becomes 0, and the other input slowly discharges to 0 due to the effect of RC, and about 7.4us later, the output OUT flips to 0, and the pulse width is about 7.4us.

[0070] S3. If the working circuit is normally working, and the working circuit is artificially powered off and then powered on again, that is, PWR is pulled low and then pulled high, the process of steps S1 and S2 will be repeated.

[0071] The protection circuit described in the application can be applied to various working circuits requiring power-on overvoltage protection, and can be applied to one or more nodes with power-on overvoltage risk in a working circuit. The working circuit can be a bias circuit, a memory interface, a display driving circuit, etc. In an embodiment, taking one to-be-protected node of a bias circuit as an example, as shown in the figure. The bias circuit in this embodiment is composed of three MOS transistors in series, and each MOS transistor gate is connected to an amplifier output end one by one, and is supplied with high and low voltage domains at the same time, and high-voltage-resistant and standard MOS transistors are mixedly used and there is negative feedback, so overvoltage nodes will appear during power-on process. The fifth PMOS transistor PM5 serves as the third level MOS transistor, and the gate of the fifth PMOS transistor PM5 serves as the to-be-protected node, and the corresponding gate voltage is Bias. Figure 6

[0072] Under normal working, all MOS transistors will not be overvoltage, but at the initial stage of power-on, due to the uncertainty of the output of the amplifier corresponding to the fifth PMOS transistor PM5, if the gate voltage Bias output by the amplifier is relatively high, the source voltage of the fifth PMOS transistor PM5 will also be too high, and the voltage between the source and the drain will be too large, which is greater than 1.1 times of the standard voltage. As a comparative example, disconnect the low-resistance switch shown in the figure from the fifth PMOS transistor PM5, that is, as a prior art, the protection circuit described in the application is not introduced, and the voltage condition is as shown in the figure. Figure 6 Figure 7 The working circuit is powered on with 1.8V and 0.9V power supply, and then the power-on signal PWR is enabled, and the voltage conditions of the gate, source and drain of the fifth PMOS transistor PM5 are observed, as shown in the figure. Figure 7 The gate voltage VG of the fifth PMOS transistor PM5 is very high, reaching 871mV, and the transistor keeps a certain current flowing through, and the source voltage VS reaches 1.32V at most, and the voltage difference between the source and the drain reaches 1.127V during the establishment process, and the overvoltage is about 25% and lasts for a period of time. Then it is restored to a stable value after about 6us, and the source voltage VS stabilizes to 0.9V.

[0073] ​​Then, the IN pin of the low-resistance switch described in this invention is connected to the gate of the fifth PMOS transistor PM5, and a power-on operation is performed again. The voltage condition is as follows. Figure 8 As shown. When the pulse signal EN is 1, compared to Figure 7 The continuous rise of the gate voltage VG was interrupted, and it was directly pulled to 314mV by the low-resistance switch, thus avoiding the situation described above. Figure 7 When the voltage rises directly to 871mV, the source voltage is reduced, keeping the source-drain voltage difference within 0.9V. After 7.4us, the low-resistance switch is turned off, and the source voltage VS quickly returns to its steady-state value, remaining at 0.9V.

[0074] In summary, the comparison shows that the protection circuit described in this invention can prevent overvoltage of the node during power-on and does not rely on real-time monitoring of the node, thus avoiding situations such as misjudgment of disk leakage or monitoring failure.

[0075] For those skilled in the art, various other corresponding changes and modifications can be made based on the technical solutions and concepts described above, and all such changes and modifications should fall within the protection scope of the claims of this invention.

Claims

1. A protection circuit for preventing overvoltage upon power-on, characterized in that, Includes a pulse control signal generation module and a low-impedance switch; The pulse control signal generation module acquires the power-on signal of the circuit to be protected and outputs a single pulse control signal to the enable terminal of the low-impedance switch. The low-resistance switch pulls the overvoltage node of the circuit to be protected to a safe level under the action of the control signal; The low-resistance switch structure is as follows: The source of the first PMOS transistor (PM1) is connected to the third node (net3), the drain of the first PMOS transistor (PM1) is connected to the overvoltage node of the circuit to be protected, and the gate of the first PMOS transistor (PM1) is connected to the inverted enable signal. The source of the first NMOS transistor (NM1) is connected to the third node (net3), the drain of the first NMOS transistor (NM1) is connected to the overvoltage node of the circuit to be protected, and the gate of the first NMOS transistor (NM1) is connected to the enable signal. The source of the second PMOS transistor (PM2) is connected to the power supply AVDD, the drain of the second PMOS transistor (PM2) is connected to one end of the first resistor (R1), and the gate of the second PMOS transistor (PM2) is connected to the inverting enable signal. The other end of the first resistor (R1) is connected to the third node (net3); One end of the second resistor (R2) is connected to the third node (net3), and the other end is grounded; The safe voltage level is generated by voltage division using the first resistor (R1) and the second resistor (R2); The structure of the pulse control signal generation module is as follows: The input of the first NOT gate (INV1) is connected to the power-on signal, and the output of the first NOT gate (INV1) is connected to the second node (net2). The input of the second NOT gate (INV2) is connected to the second node (net2), and the output of the second NOT gate (INV2) is connected to the gate of the third PMOS transistor (PM3) and the gate of the second NMOS transistor (NM2), respectively. The source of the third PMOS transistor (PM3) is connected to the power supply AVDD, and the drain of the third PMOS transistor (PM3) is connected to the first node (net1). The source of the second NMOS transistor (NM2) is grounded, and the drain of the second NMOS transistor (NM2) is connected to the first node (net1) through the third resistor (R3). The upper plate of the first capacitor (C1) is connected to the first node (net1), and the lower plate of the first capacitor (C1) is grounded. The first input of the XOR gate is connected to the first node (net1), the second input of the XOR gate is connected to the second node (net2), and the output of the XOR gate is connected to the enable terminal of the low-impedance switch as the output of the pulse control signal generation module. The source of the fourth PMOS transistor (PM4) is connected to the power supply AVDD, the drain of the fourth PMOS transistor (PM4) is connected to the XOR gate output, and the gate of the fourth PMOS transistor (PM4) is connected to the power-on signal.

2. The protection circuit for preventing overvoltage upon power-on according to claim 1, characterized in that, The inverted enable signal is generated by passing the enable signal through the third NOT gate (INV3).

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