Communication encryption method based on enhanced shock burst protocol

Abstract

This invention relates to the field of communication encryption technology, and more particularly to a communication encryption method based on the EnhancedShockBurst protocol. The method includes the following steps: reading plaintext data to be sent and obtaining the current value of the internally stored packet counter; padding the plaintext data to obtain a plaintext data block; calculating and generating a session key using a preset root key and the current packet counter value as input parameters; performing round key expansion processing on the session key to obtain a round key sequence; generating a key stream with the same length as the plaintext data block using the round key as input; performing an XOR operation between the key stream and the plaintext data block to obtain an encrypted ciphertext data block; and extracting the packet counter value as a key identifier, appending it to the ciphertext data block to form an encrypted payload. This invention achieves real-time security protection of communication data through dynamic round key generation and byte-by-byte XOR encryption.

Description

Technical Field

[0001] This invention relates to the field of communication encryption technology, and in particular to a communication encryption method based on the EnhancedShockBurst protocol. Background Technology

[0002] EnhancedShockBurst (ESB) is a short-range wireless communication protocol widely adopted due to its efficient packet structure, low-power transmission, and support for automatic acknowledgment mechanisms. However, existing technologies still have certain shortcomings in security encryption. Traditional encryption methods typically use fixed keys or static session keys, which can easily lead to ciphertext pattern repetition when facing data replay attacks or multiple transmissions of the same plaintext, thus reducing communication security. Since ESB is applied to low-power, low-bandwidth wireless devices, conventional symmetric encryption algorithms face pressure in terms of real-time performance and resource consumption, failing to fully balance security and computational efficiency. Existing methods often do not fully utilize the protocol's own packet counter and frame index information in conjunction with the key generation process, resulting in a lack of dynamic key updates, making it easy for attackers to predict key change patterns through data analysis. Summary of the Invention

[0003] Therefore, it is necessary to provide a communication encryption method based on the EnhancedShockBurst protocol to solve at least one of the above-mentioned technical problems.

[0004] To achieve the above objectives, a communication encryption method based on the EnhancedShockBurst protocol includes the following steps:

[0005] Step S1: Read the plaintext data to be sent, obtain the current value of the internally stored packet counter, and perform length padding on the plaintext data to obtain a plaintext data block;

[0006] Step S2: Using the preset root key and the current packet counter value as input parameters, calculate and generate the session key; perform round key expansion processing on the session key to obtain the round key sequence;

[0007] Step S3: Using the round key as input, generate a key stream with the same length as the plaintext data block in sequence. Perform an XOR operation between the key stream and the plaintext data block to obtain the encrypted ciphertext data block. Extract the packet counter value as the key identifier and append it to the ciphertext data block to form the encrypted payload.

[0008] Step S4: Write the encrypted payload into the payload field of the EnhancedShockBurst protocol frame, complete frame assembly according to the protocol specification, and start wireless transmission; after transmission is completed, increment the internal packet counter value and update the storage.

[0009] The beneficial effects of this invention are as follows: by tightly coupling padding with the packet counter, the encryption context of each data block is made unique, thereby preventing pattern repetition attacks caused by traditional fixed-length padding. It can simultaneously achieve a balance between encryption diversity and processing efficiency in low-power wireless devices with limited hardware.

[0010] Introducing round constants and bit operations into each round of key generation not only enhances the nonlinear characteristics of the key space but also ensures that the key stream is completely different even if the same plaintext is sent at different times through dynamic updates to the packet counter. This strategy, combining round key expansion and packet counters, provides natural resistance to replay attacks and statistical analysis attacks targeting low-rate, short-frame wireless channels.

[0011] It achieves lightweight data encryption and forms an independent identifier by embedding the lower 8 bits of the packet counter in the ciphertext header, enabling the receiver to quickly locate the round key state corresponding to the data frame and achieve efficient decryption. At the same time, it avoids the need to store all historical keys on a large scale, which is an optimization that is rarely considered in embedded wireless devices. Attached Figure Description

[0012] Figure 1 This is a flowchart illustrating the steps of a communication encryption method based on the EnhancedShockBurst protocol.

[0013] Figure 2 This is a schematic diagram of the key grouping process;

[0014] Figure 3 This is a schematic diagram of the communication XOR operation process;

[0015] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0016] The technical method of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0017] Furthermore, the accompanying drawings are merely illustrative of the invention and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor methods and / or microcontroller methods.

[0018] It should be understood that although the terms "first," "second," etc., may be used herein to describe various units, these units should not be limited by these terms. These terms are used merely to distinguish one unit from another. For example, without departing from the scope of the exemplary embodiments, a first unit may be referred to as a second unit, and similarly, a second unit may be referred to as a first unit. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0019] To achieve the above objectives, please refer to Figures 1 to 3 A communication encryption method based on the EnhancedShockBurst protocol includes the following steps:

[0020] Step S1: Read the plaintext data to be sent, obtain the current value of the internally stored packet counter, and perform length padding on the plaintext data to obtain a plaintext data block;

[0021] Step S2: Using the preset root key and the current packet counter value as input parameters, calculate and generate the session key; perform round key expansion processing on the session key to obtain the round key sequence;

[0022] Step S3: Using the round key as input, generate a key stream with the same length as the plaintext data block in sequence. Perform an XOR operation between the key stream and the plaintext data block to obtain the encrypted ciphertext data block. Extract the packet counter value as the key identifier and append it to the ciphertext data block to form the encrypted payload.

[0023] Step S4: Write the encrypted payload into the payload field of the Enhanced ShockBurst protocol frame, complete frame assembly according to the protocol specification, and start wireless transmission; after transmission is completed, increment the internal packet counter value and update the storage.

[0024] In one embodiment, during runtime, the data reading module within the communication control unit opens the data buffer to be sent and sequentially reads a complete frame of plaintext data from the buffer. This plaintext data is typically the payload encapsulated at the application layer, with a length between 20 and 32 bytes. To ensure data alignment for subsequent encryption algorithms, it is determined whether the length of the plaintext data is a multiple of 4; if not, a byte padding operation is automatically performed, using 0x00 or 0xFF as padding values ​​to fill to the nearest 4-byte boundary, forming a standardized plaintext data block. Simultaneously, the current value of the internal packet counter is read from the storage control unit. The packet counter is typically a 32-bit incrementing register, and its initial value is written by the device firmware during the power-on initialization phase. After reading, this value is cached in a registered variable and participates in key derivation and identifier generation in subsequent steps.

[0025] Next, within the security key management module, the key derivation function is called, using the preset root key and the current packet counter value as input parameters for calculation. The root key is typically a fixed value of 16 bytes, stored in the secure storage area of ​​the encryption chip and cannot be read by the user; the packet counter value is converted to 4 bytes in little-endian byte order. The derivation function performs a hash calculation (such as a truncated form of SHA-256), extracting the first 16 bytes of its output as the session key. Subsequently, the round key expansion process is called, expanding the session key into 4-byte groups to generate several round keys. In each round, the 0th key group is circularly shifted right by 7 bits, then XORed byte-wise with the round constant expanded by the current round index, updating it to a new working base set. Then, it is modulo binary addition and XORed with the corresponding group, finally outputting the round key for this round. Generally, 10 rounds of expansion are performed, generating 10 round keys, which are then stored sequentially in the key sequence buffer.

[0026] After the round key sequence is generated, the encryption control module is activated to generate a key stream from the key sequence round by round, according to the length of the plaintext data block. The key stream generated in each round is the same length as the data block. The data encryption unit synchronously inputs the plaintext block and the key stream, performs a byte-by-byte XOR operation, and writes the result to the output buffer immediately to form the ciphertext data block. All XOR calculations are performed by the hardware logic operation unit without CPU interruption.

[0027] After the ciphertext data block is generated, the packet counter register is accessed again, and the lower 8 bits of its current value are extracted as the key identifier. This identifier is then appended to the header of the ciphertext data block in the data output module. At this point, the entire encrypted payload consists of a 1-byte identifier and n bytes of ciphertext data, with a complete data structure and fixed length.

[0028] The communication protocol encapsulation module writes the encrypted payload into the payload area of ​​the EnhancedShockBurst (ESB) protocol frame, filling in the frame header, address field, payload, and CRC check field sequentially according to the protocol specifications. After frame encapsulation is complete, the RF transceiver module initiates the wireless transmission process, transmitting the assembled frame through the 2.4GHz RF channel. Upon receiving a successful transmission signal, the module automatically performs a packet counter update operation, incrementing the counter value and writing it back to the non-volatile memory area to prepare for the next frame transmission.

[0029] Of particular importance, step S1 includes:

[0030] Read the plaintext data to be sent and extract the complete data frame from the buffer in byte order;

[0031] The real-time value of the current packet counter is obtained by combining the internal storage module, and the count value is written to the temporary storage register as a synchronization identifier.

[0032] The extracted plaintext data is padded according to the preset encrypted block length;

[0033] If the data length is insufficient, zero values ​​are appended or randomly padded to the standard length. After alignment, the data is organized into continuous data blocks, forming standardized plaintext data blocks.

[0034] In one embodiment, after receiving a transmission task trigger signal, the encryption control unit sequentially reads the plaintext data frames to be transmitted from the data buffer, extracting the complete data byte by byte. Then, it reads the current counter value from the internal packet counter register and writes this value into a temporary register as a synchronization identifier for this encryption. For the read plaintext data, padding is performed in units of a preset encryption block length (e.g., 32 bytes). When the data frame length is less than 32 bytes, zero values ​​are appended for padding; in another operating mode, pseudo-randomly generated bytes can also be appended to increase data unpredictability. After padding, consecutive bytes are organized into standardized data blocks, forming plaintext data blocks of uniform length for use in subsequent round key encryption.

[0035] In another embodiment, when the encryption task starts, the encryption unit reads the data frames to be sent sequentially from the data buffer, ensuring the data order is complete and without loss. The current value of the internal packet counter register is transmitted to the encryption unit through the bus interface and written to the synchronization register, marking the counter value corresponding to the current encrypted data. Subsequently, the plaintext data is padded to a block length of 64 bytes. If the data length is less than 64 bytes, zero values ​​are first added for alignment, and then bytes generated by the internal pseudo-random number generator are selectively added according to the configuration to prevent information leakage due to repeated data block patterns. After processing, a series of standardized plaintext data blocks are formed, each data block synchronized with the counter value, for use in subsequent round key generation and encryption operations.

[0036] Preferably, step S2 includes:

[0037] The preset root key and the current packet counter value are concatenated in a predetermined byte order to form the key derivation input. A truncated hash calculation is then performed to obtain a fixed-length session key.

[0038] The session key is divided into multiple key blocks, and the key block numbered 0 is set as the working base group. Round key expansion processing is performed on the key blocks to obtain the round key for this round.

[0039] Store the round key of this round into the round key sequence, and proceed to the generation of the round key for the next round;

[0040] Once the number of round key generation attempts reaches the preset value, the loop stops, and a complete round key sequence is obtained.

[0041] In one embodiment, the root key can be preset as a 16-byte binary array, and the packet counter uses a 4-byte incrementing counting format. When the device starts the encryption task, it first concatenates the 4-byte value of the current packet counter into the root key in high-order order to obtain a continuous key-derived input sequence. Subsequently, the processing unit calls the on-chip lightweight hash module (e.g., a truncated SHA-1 or CRC32 improved algorithm) to perform a hash operation on the concatenated input and truncates the first 12 bytes as the session key. After obtaining the session key, the control logic divides it into 3 key groups of 4 bytes each, with the group numbered 0 serving as the working base group. At this time, each group is loaded into the register sequentially, and the round key expansion operation is performed. The expansion operation includes: cyclically shifting the working base group data 7 bits to the left, performing an XOR operation with the remaining group data sequentially, and appending a 1-byte round number constant incrementing by the round number. After each operation is completed, the new round key result is written to the round key sequence cache. This process is repeated until the number of round key generation reaches the set number of rounds (e.g., 20 times), at which point the loop terminates, ultimately yielding a round key sequence of length 80 bytes, which provides continuous round key input for subsequent encryption steps.

[0042] In another embodiment, the root key uses an 8-byte structure and participates in derivation in conjunction with a dynamic counter. The concatenation order of the derivation inputs adopts a least significant byte-first arrangement, that is, the least significant byte of the counter is located at the beginning of the input, thereby simplifying address operations on resource-constrained chips. During the derivation stage, the control unit directly uses a hardware random perturbation value as the hash initial vector, performs an improved FNV-1a hybrid hash on the concatenated input, and outputs an 8-byte result as the session key. This session key is divided into two groups of 4-byte key blocks, with group 0 designated as the base group. During each round of expansion, the base group is cyclically shifted right by 3 bits and then XORed with the other group. At the same time, the round number is multiplied by a constant 3 and added to the least significant byte of the group to enhance the non-repetition of each round. After each round of expansion is completed, the result data is written to the round key sequence buffer. The number of rounds is counted, and the generation process automatically ends when the number of expansions equals the preset number of rounds (e.g., the number of key bytes divided by 4 and then added by 4). The resulting round key sequence is stored sequentially in the on-chip Flash area to provide a fixed-length round key set for subsequent key stream generation.

[0043] Preferably, the preset root key and the current packet counter value are concatenated in a predetermined byte order to form the key derivation input, and a truncated hash calculation is performed to obtain a fixed-length session key, including:

[0044] The function uses the preset root key and the current packet counter value to read the root key and the packet counter value sequentially as a binary byte stream.

[0045] The binary byte stream is concatenated according to a preset byte order to form a continuous key derivation input sequence;

[0046] The hash calculation is performed using the key-derived input sequence as the input parameter.

[0047] Extract the first fixed-length bytes from the hash output according to the preset truncation length to obtain the fixed-length session key.

[0048] In one embodiment, the root key is pre-stored in the device's non-volatile memory area, with a length of 16 bytes. The packet counter is incremented by the sending end after each packet transmission, occupying 4 bytes. When performing encryption operations, the control unit first reads the 16-byte root key data from the memory area via the memory bus, and then reads the current packet counter value from the register. After reading, the program writes these two sets of data into the buffer sequentially, in high-byte-first, low-byte-last order, forming a continuous 20-byte sequence. Subsequently, the processing unit calls the lightweight hash module to perform a truncated hash operation on the byte sequence. The algorithm used here is an improved SHA-1, which internally performs only one round of compression to reduce computation. The hash output is 160 bits (20 bytes), and the first 12 bytes are taken as the current session key. The generated session key is immediately written into a temporary buffer in RAM, and the lower 2 bytes of the current packet counter are appended to the end of the buffer for subsequent identification of the packet sequence number corresponding to the session key. The buffer is automatically cleared after this round of encryption to prevent subsequent tasks from reading old key data.

[0049] In another embodiment, the root key is set to an 8-byte structure and stored in the microcontroller's secure register, while the packet counter is a 2-byte incrementing counter. The control logic first writes the root key and packet counter into a temporary register in low-byte priority order, forming a continuous 10-byte input sequence. To reduce the computational burden on the chip, this embodiment does not use a standard hash library, but instead employs a custom truncated hash process based on the FNV-1a algorithm. Specifically, each byte of the input sequence is XORed sequentially with the constant 0x811C9DC5 and then multiplied by the prime number 0x01000193; the result is retained after each iteration, keeping the lower 32 bits. After the entire sequence is processed, two more rounds are performed, shifting the result 8 bits to the right and XORing it with the original value to increase the diffusion. The first 6 bytes of the final output are used as the session key. To avoid duplicate collisions caused by truncation, the least significant bit of the packet counter is appended to the end of the key as a random perturbation. The generated session key is stored in the encryption module's register in little-endian format for use in subsequent rounds of key expansion.

[0050] like Figure 2 The diagram shown illustrates the key grouping process, specifically:

[0051] Preferably, the session key is subjected to round key expansion processing to obtain the round key for this round, which includes:

[0052] The session key is divided into multiple key blocks in units of 4 bytes, numbered sequentially as group 0, group 1, group 2 and group 3, and the key block numbered group 0 is set as the working base set;

[0053] Set the number of round key generation to a fixed value. In each round of generation, use the current cycle number as the round sequence index to select the working base set and the corresponding key group as the operation object.

[0054] In each round of generation, a cyclic right shift operation of seven bits is performed on the working base set to obtain the right shift result grouping;

[0055] The right shift result group is XORed with the round constant formed by the round order index after expansion processing to generate the updated working base set;

[0056] Perform a circular left shift operation of four bits on the key block, and then perform an addition operation between the left shift result and the updated working radix to obtain the intermediate result block;

[0057] The intermediate results are grouped and XORed with the round constant to obtain the round key for this round.

[0058] In one embodiment, the control unit divides the 12-byte session key into three groups of 4 bytes each, numbered 0, 1, and 2 respectively, with the key group numbered 0 designated as the working base group. The round key generation control module sets the number of rounds to 20, and in each loop, it sequentially selects the current round number as the round sequence index. In each round, the program first performs a circular right shift operation of 7 bits on the working base group, storing the shifted byte sequence in a temporary register as the right shift result group. Subsequently, the control unit looks up the corresponding value in a preset round constant table according to the round sequence index, and performs a byte-by-byte XOR operation between the right shift result group and the round constant to obtain the updated working base group. Next, it performs a circular left shift operation of 4 bits on the key group of the current operation, and performs a byte-by-byte modulo operation between the left shift result and the updated working base group. Addition operations are performed to obtain intermediate result blocks. Finally, the intermediate result blocks are XORed byte by byte with the round constant to obtain the round key for this round. After each round key is generated, it is written to the round key sequence cache, and the round sequence index is incremented to enter the next round loop, until 20 rounds of expansion are completed, resulting in a complete round key sequence for subsequent encryption steps.

[0059] In another embodiment, the session key is 8 bytes long and divided into two key groups of 4 bytes each, numbered 0 and 1. Group 0 serves as the working base set. The number of round key generation rounds is set to 16. During each round of expansion, the control module first performs a circular right shift operation of 7 bits on the working base set and stores the result in a register. Then, the round sequence index is multiplied by 3 as the round constant generation parameter. The right shift result is combined with the generated round constant through an XOR operation to obtain the updated working base set. Subsequently, a circular left shift operation of 4 bits is performed on the key group numbered 1. The result is added byte by byte to the updated working base set (modulo 32-bit) to obtain the intermediate result group. Finally, the intermediate result group is XORed byte by byte with the round constant to output the round key for the current round. After the round key generation is completed, each round key is sequentially stored in the on-chip RAM buffer. The round number increment controller checks whether the number of rounds has reached 16. If not, the next round of expansion continues, ultimately forming a complete round key sequence of 32 bytes in length.

[0060] Preferably, the process of performing an XOR operation between the right-shift result group and the round constant formed by the expanded round sequence index to generate the updated working base set includes:

[0061] The right shift results are grouped and input together with the corresponding round order index into the round constant generation unit;

[0062] Within the generation unit, an expansion process is performed based on the range of values ​​for the round order index, resulting in a round constant that is consistent with the length of the right-shifted result group bytes.

[0063] The right shift result is grouped and XORed with the round constant bitwise to obtain the updated working base set.

[0064] In one embodiment, the round key generation module performs a cyclic right shift operation of 7 bits on the working base set of the current round, obtaining a right-shifted result group. Subsequently, the control logic sends the right-shifted result group and the current round sequence index together to the round constant generation unit. Inside the generation unit, an expansion algorithm is selected based on the round sequence index value: when the index is less than 10, the round sequence index value is repeatedly padded to the same byte length (4 bytes) as the right-shifted result group; when the index is greater than or equal to 10, the round sequence index is left-shifted by 1 bit and then repeatedly padded to 4 bytes, forming the round constant byte sequence. After obtaining the round constant, the processing unit performs an XOR operation on the right-shifted result group and the round constant bytes one by one to obtain the updated working base set, and writes it to a temporary register for use in the next operation.

[0065] In another embodiment, the right-shift result group and the round sequence index are simultaneously fed into the round constant generation unit. Inside the generation unit, the round sequence index is modulo 4 to obtain an expansion factor. Then, the round sequence index value is cyclically copied to a length equal to the byte length of the right-shift result group, forming a round constant byte sequence. Subsequently, a bitwise XOR operation is performed on the right-shift result group and the round constant byte sequence, and the result is output to the working register, overwriting the original working base set, serving as the updated working base set for subsequent round key generation operations.

[0066] Preferably, a circular left shift operation of four bits is performed on the key group, and the left shift result is added to the updated working radix to obtain intermediate result groups, including:

[0067] Perform a circular left shift operation of four bits on the key block and use the shifted byte sequence as the result.

[0068] Using the left shift result as the operand and the updated working base as the addition operand, perform the operation byte by byte according to modulo binary addition;

[0069] The addition results are organized into a standard byte sequence to obtain intermediate result groups.

[0070] In one embodiment, the control unit performs a cyclic left shift operation of the key group for the current round of operation by 4 bits, in units of 4 bytes, to obtain the left-shifted result group. Subsequently, the processor aligns the left-shifted result group byte-by-byte with the previously generated updated working base group, and performs modulo-256 addition byte-by-byte, retaining the lower 8 bits of the calculation result for each byte and discarding any overflow. After completing the byte-by-byte addition, the processor writes the results to a temporary buffer in the original order, forming a standard byte sequence, which serves as an intermediate result group for subsequent XOR operations. Throughout this process, data movement between registers and addition are all completed internally by the microcontroller, requiring no external memory access.

[0071] In another embodiment, after the key group is circularly shifted left by 4 bits in the register, the shift result is directly written to the operation register of the round key generation module. Subsequently, the control logic adds the shift result byte-by-byte to the updated working base set using modulo 2^32 addition, calculating in groups of 4 bytes, discarding any overflowing high-order bits. After the calculation, each group of results is written back to the round key buffer, forming a continuous byte sequence to obtain an intermediate result group. This intermediate result group will be directly used as the input for the next step XOR operation with the round constant, without further processing.

[0072] Preferably, storing the round key of the current round into a round key sequence, and generating the round key for the next round includes:

[0073] Write the current round key into the round key sequence buffer, and record the sequence index of the current round key after writing is complete;

[0074] The round key generation control module increments the round sequence index and checks whether the current round number has reached the preset round number limit.

[0075] If the preset maximum number of rounds is not reached, a control signal for generating the round key for the next round is triggered, and the predetermined cyclic operation to generate the round key for the next round begins.

[0076] In one embodiment, the round key generated in the current round is written to a preset round key sequence buffer in 4-byte units. The buffer manages the storage location of the round keys through index pointers. After writing, the starting index value of the round key in the sequence buffer is recorded for subsequent round key reading and encryption. Subsequently, in the round key generation control module, the round sequence index value is incremented by 1 and compared with a preset round number upper limit. If the current round sequence index is less than the round number upper limit, the generation control module outputs a round key generation trigger signal to the round key expansion unit. The round key expansion unit reselects the corresponding key group and working base group according to the new round sequence index and performs a predetermined cyclic operation to generate the round key for the next round. In this embodiment, the size of the round key sequence buffer is set to 20 groups, each group being 4 bytes, and the initial value of the round sequence index is 0. Sequential writing and triggering of the next round generation are achieved through cyclic counting, ensuring that the entire round key sequence is complete and continuous.

[0077] In another embodiment, the round key for the current round is written to a separate round key sequence storage unit via a DMA interface. After writing, the sequence management register records the storage address and round number of the round key. The round key generation control logic reads the information from the sequence management register, increments the round number, and determines whether a preset round limit has been reached. If the limit has not been reached, the control logic outputs a "next round start" signal to the round key generation unit. This unit reads the corresponding session key group and the current working base group, and generates the round key for the next round according to predefined cyclic right shift, XOR, and addition operations. After generation, it is still written to the round key sequence storage unit, and the round sequence index register is updated. In this embodiment, the round key sequence storage unit adopts a double buffering mechanism, writing the current round key while preparing the generation parameters for the next round, ensuring efficient connection between round key generation and sequence storage. The round number is used cyclically from 0 to 19 to form a complete round key sequence.

[0078] Please see Figure 3 This is a schematic diagram of the communication XOR operation process in this invention;

[0079] Preferably, step S3 includes:

[0080] In the encryption control unit, the current round key is read sequentially from the round key sequence;

[0081] In each round of encryption, the corresponding plaintext data block is read, encrypted with the current round key, the intermediate ciphertext block is output, and the blocks are concatenated in sequence to generate a key stream.

[0082] The generated key stream is XORed byte by byte with the complete plaintext data block, and the result is output to the ciphertext buffer to form the ciphertext data block.

[0083] The current counter value is read from the packet counter register, the lower 8 bits of which are extracted as the key identifier and appended to the header of the ciphertext data block to form the encrypted payload.

[0084] In one embodiment, in the encryption control unit, the round key corresponding to the current round sequence index is read from the round key sequence buffer. The length of the round key for this round is 4 bytes. Subsequently, the corresponding plaintext data blocks are read synchronously according to the byte group structure (each group consists of 4 bytes). During each round of encryption, each pair of plaintext blocks is XORed with the round key, and then subjected to encryption transformations such as cyclic left shift and right shift as specified by the round key expansion to generate intermediate ciphertext blocks. After encrypting all blocks in the current round, the intermediate ciphertext blocks are sequentially concatenated to form a key stream corresponding to the round key length. Within the entire plaintext data block, plaintext bytes are read sequentially, and XORed bit by bit with the corresponding bytes in the key stream. The XOR result is written to the ciphertext buffer in the original order to form a complete ciphertext data block. Finally, the current counter value is read from the packet counter register unit, the lower 8 bits are written as the key identifier to the beginning of the output buffer, and then the ciphertext data block body is written afterward to complete the construction of the encryption payload.

[0085] In another embodiment, the encryption control module sequentially reads the current round key (4 bytes) from the round key sequence storage unit via a DMA interface and sends it to the round key processing unit. Plaintext data blocks are input to the encryption unit in 4-byte groups. Each group of plaintext data is first XORed with the current round key, and then round-by-round encryption transformations (including cyclic shift, addition, and XOR mixed operations) are performed according to the round key expansion rules to generate intermediate ciphertext blocks. After all rounds are completed, the intermediate ciphertext blocks are sequentially combined into a complete key stream in the encryption output buffer, and then XORed bit-by-bit with the plaintext data blocks, finally written to the ciphertext data buffer. After generating the ciphertext data blocks, the complete count value is read from the packet counter register, and the lowest 8 bits are obtained as a single-byte key identifier through bit truncation. This identifier is first written to a temporary buffer, and then the ciphertext data blocks are written to the subsequent positions in the buffer to form the final encryption payload. This embodiment employs a segmented buffering and pipelined processing mechanism to achieve efficient connection between key stream generation, plaintext encryption, and key identifier appending.

[0086] It should be added that after the encryption control unit starts working, it is initialized, setting the internal parameters to n=1 and m=0, where n points to the current plaintext data packet to be processed, and m is the current encryption round counter. Then it enters the core encryption loop: in each round, the unit sequentially reads the corresponding m-th round key from the round key sequence, and simultaneously reads the n-th plaintext packet and the previous packet data (i.e., the (n-1)-th packet) as feedback. These three are subjected to the specified encryption transformation, outputting an intermediate ciphertext packet. After completing one transformation, the round counter m is incremented by 1, and it is checked whether its value is less than the preset total number of rounds. If it is less, the current n-th packet is used for the next round of encryption transformation. If the total number of rounds has been reached or exceeded, it indicates that the encryption processing of the current plaintext packet is complete. At this time, the packet sequence number n is incremented by 1, and the round counter... m is reset to 0, and it is determined whether all groups have been processed (i.e., whether n is less than or equal to 7). If not, it returns to the beginning of the loop and continues processing the next group with the new group and the intermediate ciphertext generated in the previous round as input. If all groups have been processed, it exits the loop. After the loop ends, all the sequentially generated intermediate ciphertext groups are concatenated in order to form the final key stream. After that, the encryption unit performs a byte-by-byte XOR operation on the generated complete key stream and the original complete plaintext data block. The result is output to the ciphertext buffer to form a complete ciphertext data block. To complete the data encapsulation, the unit reads the current count value from the packet counter register, extracts its lower 8 bits as the key identifier used for this encryption, and appends the identifier to the beginning of the ciphertext data block to form the final encrypted payload that can be transmitted or stored.

[0087] Preferably, the generated keystream is XORed byte-by-byte with the complete plaintext data block, and the result is output to the ciphertext buffer to form the ciphertext data block, including:

[0088] In the data encryption unit, the generated key stream is divided into several byte sequences according to the data block length;

[0089] Starting with the first byte of the plaintext data block, the first byte of the key stream sequence is read synchronously, and a bitwise XOR calculation is performed to obtain the encryption result of the first byte.

[0090] The byte index is incremented sequentially, and the bytes of the plaintext data block are XORed bit by bit with the corresponding bytes in the key stream until all bytes of the entire data block have been processed.

[0091] The XOR results of each byte are written to the output buffer in the original byte order to form a complete ciphertext data block.

[0092] In one embodiment, within the data encryption unit, the previously generated keystream is divided into several byte sequences according to the length of the plaintext data block, for example, each processing unit consists of 4 bytes. Starting with the first byte of the plaintext data block, the first byte of the keystream sequence is read simultaneously, and a bitwise XOR operation is performed on both to obtain the encryption result of the first byte. Subsequently, the byte index is incremented sequentially, and each byte of the plaintext data block is XORed with the corresponding byte in the keystream until all bytes of the entire data block have been processed. During processing, after each byte's XOR operation is completed, the result is immediately written to the corresponding position in the ciphertext buffer. After completing the byte-by-byte XOR operation of the entire plaintext data block, a complete ciphertext data block is formed in the output buffer, with the same order as the original plaintext data block, providing the foundation for the subsequent construction of the encrypted payload.

[0093] In another embodiment, the encryption control module segments the keystream into temporary buffers according to the data block length, with each segment's length matching the block length corresponding to the plaintext data block. During encryption, bytes are read synchronously from the plaintext data block buffer and the keystream buffer. The first byte of plaintext is XORed bitwise with the corresponding byte in the keystream to generate the first byte of ciphertext. Subsequent bytes are then processed in a loop: the next byte of the plaintext data block is read, XORed bitwise with the corresponding byte in the keystream buffer, and the result is directly written to the ciphertext output buffer. This process continues until the last byte of the plaintext data block is processed. Through this segmented buffering and byte-by-byte writing method, the output buffer ultimately stores the complete ciphertext data block, maintaining byte order correspondence with the plaintext data block, providing a complete data foundation for generating the encrypted payload.

[0094] Preferably, the current counter value is read from the packet counter register, its lower 8 bits are extracted as a key identifier, and the identifier is appended to the header of the ciphertext data block to form the encrypted payload, which includes:

[0095] At the moment the encryption task is triggered, the complete value of the current counter is read from the packet counter register.

[0096] Perform a bit truncation operation on the counter value, retaining its lowest 8 significant bits, and generate a key identifier of a single byte length;

[0097] Write the key identifier to the temporary buffer and associate it with the index number of the current ciphertext data block;

[0098] During the data output phase, the key identifier is written first and placed at the beginning of the ciphertext data block;

[0099] After the key identifier is written, the main data of the ciphertext data blocks are written sequentially to form a complete encrypted payload.

[0100] In one embodiment, when the encryption control unit receives an encryption task trigger signal, it reads the complete 32-bit value of the current counter from the packet counter register. A bit truncation operation is performed on this counter value, retaining only the lowest 8 bits. This 8-bit binary data is written as a single-byte key identifier into a temporary buffer, and the index number of the current ciphertext data block in the buffer is recorded for association. During the data output stage, the key identifier is read from the temporary buffer and written to the first byte position of the ciphertext output buffer. Subsequently, the complete ciphertext data block body is written sequentially to the remaining positions in the buffer, forming a structurally complete encryption payload in the output buffer, with the first byte being the key identifier and subsequent bytes being the ciphertext data.

[0101] In another embodiment, after the encryption task is initiated, the packet counter register unit sends the complete 64-bit value of the current counter to the encryption unit. The encryption unit performs a masking operation on the received counter value, retaining only the lowest 8 bits of data, generating a single-byte key identifier, and establishing an index mapping with the corresponding ciphertext data block in the buffer. During the payload generation phase, the key identifier is first retrieved from the buffer and written to the beginning of the output buffer; then, the ciphertext data blocks are written byte by byte sequentially to the subsequent positions in the output buffer. In this way, the output buffer forms a complete encryption payload, and each transmitted ciphertext data begins with the key identifier to ensure that the receiving end can recognize the corresponding round key.

[0102] Of particular importance, step S4 includes:

[0103] Write the encrypted payload, after encryption processing, into the payload field of the EnhancedShockBurst protocol frame.

[0104] According to the protocol frame structure specification, frame control information, address information and check fields are added sequentially to generate a complete data frame that conforms to the transmission standard.

[0105] After frame assembly is completed, the wireless transmission module is activated to perform the data transmission task and the transmission completion signal is monitored.

[0106] When the confirmation of completion is reached, the current value of the internal packet counter is incremented by one, and the updated count value is written to the storage unit to maintain counting continuity.

[0107] In one embodiment, after encrypting the plaintext data and attaching the key identifier, the encryption unit writes the generated encrypted payload into the payload field of the EnhancedShockBurst protocol frame. Subsequently, according to the protocol, it sequentially fills in the frame control fields (such as frame type and acknowledgment request flag), sender and receiver address information, and the Cyclic Redundancy Check (CRC) field to form a complete transmission data frame. After frame assembly, the wireless transmission module is triggered to start via the SPI interface and begin transmitting data in the 2.4GHz band. The transmission module continuously monitors the status register; when it detects that the "transmission complete" flag is set, the encryption control unit increments the internal packet counter and writes the new count value into the non-volatile storage unit to ensure the continuity of the counting for the next frame encryption operation.

[0108] In another embodiment, the encrypted data payload is first written to the corresponding payload field in the protocol frame buffer. Subsequently, the protocol frame assembly logic sequentially adds frame header information (including frame length, frame type, and frame sequence number), source / destination address fields, and a 2-byte CRC checksum to ensure the frame conforms to the EnhancedShockBurst protocol specification. After frame assembly, the transmission process is initiated via an embedded RF module. During transmission, the module continuously polls the transmission status register until data transmission is confirmed to be complete. The encryption control unit then reads the internal packet counter, increments its current value by 1, and writes it back to the register and EEPROM storage area to maintain the continuity of the counter and ensure the uniqueness and synchronization of subsequently transmitted data.

[0109] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features of the invention herein.

Claims

1. A communication encryption method based on the EnhancedShockBurst protocol, characterized in that, Includes the following steps: Step S1: Read the plaintext data to be sent, obtain the current value of the internally stored packet counter, and perform length padding on the plaintext data to obtain a plaintext data block; Step S2: Calculate and generate the session key using the preset root key and the current packet counter value as input parameters; Perform round key expansion processing on the session key to obtain the round key sequence; wherein, step S2 includes: The preset root key and the current packet counter value are concatenated in a predetermined byte order to form the key derivation input. A truncated hash calculation is then performed to obtain a fixed-length session key. The session key is divided into multiple key blocks, and the key block numbered 0 is set as the working base set. Round key expansion is performed on the key blocks to obtain the round key for this round. The round key expansion process includes: performing round key expansion on the session key to obtain the round key for this round. The session key is divided into multiple key blocks in units of 4 bytes, numbered sequentially as group 0, group 1, group 2 and group 3, and the key block numbered group 0 is set as the working base set; Set the number of round key generation to a fixed value. In each round of generation, use the current cycle number as the round sequence index to select the working base set and the corresponding key group as the operation object. In each round of generation, a cyclic right shift operation of seven bits is performed on the working base set to obtain the right shift result grouping; The right shift result group is XORed with the round constant formed by the round order index after expansion processing to generate the updated working base set; Perform a circular left shift operation of four bits on the key block, and then perform an addition operation between the left shift result and the updated working radix to obtain the intermediate result block; The intermediate results are grouped and XORed with the round constant to obtain the round key for this round; Store the round key of this round into the round key sequence, and proceed to the generation of the round key for the next round; Once the number of round key generation attempts reaches the preset value, the loop stops, and a complete round key sequence is obtained. Step S3: Using the round key as input, generate a key stream with the same length as the plaintext data block in sequence. Perform an XOR operation between the key stream and the plaintext data block to obtain the encrypted ciphertext data block. Extract the packet counter value as the key identifier and append it to the ciphertext data block to form the encrypted payload. Step S4: Write the encrypted payload into the payload field of the EnhancedShockBurst protocol frame, complete frame assembly according to the protocol specification, and start wireless transmission; after transmission is completed, increment the internal packet counter value and update the storage.

2. The communication encryption method based on the EnhancedShockBurst protocol according to claim 1, characterized in that, The preset root key and the current packet counter value are concatenated in a predetermined byte order to form the key derivation input. A truncated hash calculation is then performed to obtain a fixed-length session key, which includes: The function uses the preset root key and the current packet counter value to read the root key and the packet counter value sequentially as a binary byte stream. The binary byte stream is concatenated according to a preset byte order to form a continuous key derivation input sequence; The hash calculation is performed using the key-derived input sequence as the input parameter. Extract the first fixed-length bytes from the hash output according to the preset truncation length to obtain the fixed-length session key.

3. The communication encryption method based on the EnhancedShockBurst protocol according to claim 1, characterized in that, The right-shifted result group is XORed with the round constant formed by the expanded round order index to generate the updated working base set, which includes: The right shift results are grouped and input together with the corresponding round order index into the round constant generation unit; Within the generation unit, an expansion process is performed based on the range of values ​​for the round order index, resulting in a round constant that is consistent with the length of the right-shifted result group bytes. The right shift result is grouped and XORed with the round constant bitwise to obtain the updated working base set.

4. The communication encryption method based on the EnhancedShockBurst protocol according to claim 1, characterized in that, Perform a circular left shift operation of four bits on the key block, and then add the shifted result to the updated working radix. The resulting intermediate result blocks include: Perform a circular left shift operation of four bits on the key block and use the shifted byte sequence as the result. Using the left shift result as the operand and the updated working base as the addition operand, perform the operation byte by byte according to modulo binary addition; The addition results are organized into a standard byte sequence to obtain intermediate result groups.

5. The communication encryption method based on the EnhancedShockBurst protocol according to claim 1, characterized in that, The round key for this round is stored in the round key sequence. The generation of the round key for the next round includes: Write the current round key into the round key sequence buffer, and record the sequence index of the current round key after writing is complete; The round key generation control module increments the round sequence index and checks whether the current round number has reached the preset round number limit. If the preset maximum number of rounds is not reached, a control signal for generating the round key for the next round is triggered, and the predetermined cyclic operation to generate the round key for the next round begins.

6. The communication encryption method based on the EnhancedShockBurst protocol according to claim 1, characterized in that, Step S3 includes: In the encryption control unit, the current round key is read sequentially from the round key sequence; In each round of encryption, the corresponding plaintext data block is read, encrypted with the current round key, the intermediate ciphertext block is output, and the blocks are concatenated in sequence to generate a key stream. The generated key stream is XORed byte by byte with the complete plaintext data block, and the result is output to the ciphertext buffer to form the ciphertext data block. The current counter value is read from the packet counter register, the lower 8 bits of which are extracted as the key identifier and appended to the header of the ciphertext data block to form the encrypted payload.

7. The communication encryption method based on the EnhancedShockBurst protocol according to claim 6, characterized in that, The generated keystream is XORed byte-by-byte with the complete plaintext data block, and the result is output to the ciphertext buffer to form the ciphertext data block, which includes: In the data encryption unit, the generated key stream is divided into several byte sequences according to the data block length; Starting with the first byte of the plaintext data block, the first byte of the key stream sequence is read synchronously, and a bitwise XOR calculation is performed to obtain the encryption result of the first byte. The byte index is incremented sequentially, and the bytes of the plaintext data block are XORed bit by bit with the corresponding bytes in the key stream until all bytes of the entire data block have been processed. The XOR results of each byte are written to the output buffer in the original byte order to form a complete ciphertext data block.

8. The communication encryption method based on the EnhancedShockBurst protocol according to claim 6, characterized in that, The current counter value is read from the packet counter register, its lower 8 bits are extracted as the key identifier, and the identifier is appended to the header of the ciphertext data block to form the encrypted payload, which includes: At the moment the encryption task is triggered, the complete value of the current counter is read from the packet counter register. Perform a bit truncation operation on the counter value, retaining its lowest 8 significant bits, and generate a key identifier of a single byte length; Write the key identifier to the temporary buffer and associate it with the index number of the current ciphertext data block; During the data output phase, the key identifier is written first and placed at the beginning of the ciphertext data block; After the key identifier is written, the main data of the ciphertext data blocks are written sequentially to form a complete encrypted payload.

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