Three-dimensional vertical structure phase change memory and preparation method thereof
By using a three-dimensional vertical structure design, technical problems that are difficult to solve in existing technologies have been solved, and efficient three-dimensional vertical structure phase change memory has been fabricated. The problems of storage density and thermal crosstalk have been solved, making it suitable for fields such as artificial intelligence and cloud computing.
Patent Information
- Application Number
- CN202511170398.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-20
- Publication Date
- 2025-12-12
AI Technical Summary
Existing three-dimensional phase change memory cell sizes are limited by photolithography precision, interlayer interconnects occupy a large area, storage density improvement is limited, and there are problems such as thermal crosstalk and high reset current.
A three-dimensional vertical structure design is adopted. By forming a symmetrical recessed structure in the word line structure and a through-hole structure in the insulating medium, the material distribution is optimized by using anisotropic etching and self-aligned etching processes to form a selection layer, insertion layer and phase change layer, thereby reducing thermal conductivity and optimizing the arrangement of memory cells.
It increases storage density, reduces thermal crosstalk, reduces reset current, and improves data storage reliability and efficiency, making it suitable for high-density non-volatile storage needs.
Smart Images
Figure CN121126792A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of memory technology, in particular to a three-dimensional vertical structure phase change memory and a preparation method thereof. BACKGROUND
[0002] The existing three-dimensional structure phase change memory mostly adopts horizontal wiring + vertical via structure, the cell size is limited by the lithography precision, the interlayer interconnection occupies a large area, and the storage density is limited. Moreover, the adjacent storage layers share the heating electrode or the heat diffusion path, and the heat crosstalk is significant. In addition, the contact area of the ring-shaped heating electrode and the phase change material is too large, the heat is seriously lost, and the reset current is high.
[0003] In view of this, the present application is proposed. SUMMARY
[0004] The present application aims to provide a three-dimensional vertical structure phase change memory and a preparation method thereof, which can solve the problems in the background art.
[0005] In a first aspect of the present application, a preparation method of a three-dimensional vertical structure phase change memory is provided, comprising the following steps:
[0006] S1, forming a word line structure in a stack structure on a substrate;
[0007] S2, forming a symmetrical recess structure in an electrode layer of the word line structure;
[0008] S3, forming a gating layer in the recess structure;
[0009] S4, filling an insulating medium, and forming a via structure in the insulating medium on both sides of the word line structure;
[0010] S5, sequentially forming an insertion layer and a phase change layer outside the gating layer;
[0011] S6, forming a top electrode layer in the via structure.
[0012] Preferably, step S1 comprises:
[0013] S11, depositing a stack structure on a substrate; the substrate comprises a circuit sheet, and the circuit sheet is provided with a metal interconnection via; the stack structure comprises a plurality of insulating medium layers and a plurality of electrode layers which are alternately stacked;
[0014] S12, etching the stack structure to form a word line structure.
[0015] Preferably, step S2 comprises: isotropically etching the electrode layer of the word line structure to form a symmetrical recess structure.
[0016] Preferably, step S3 comprises:
[0017] S31. Deposit gated materials using atomic layer deposition, physical vapor deposition, or chemical vapor deposition methods;
[0018] S32. Optimize the etching process by using anisotropic and isotropic etching of the channel material, retaining part of the channel material along the word line direction in the recessed structure to form a channel layer.
[0019] Preferably, step S4 includes:
[0020] S41. Fill with insulating medium and flatten;
[0021] S42. Along the word line direction, through-hole structures are formed on the insulating medium on both sides of the word line structure using photolithography and self-aligned etching processes.
[0022] Preferably, step S5 includes:
[0023] S51. Deposit the insertion layer material using physical vapor deposition, chemical vapor deposition or atomic layer deposition methods;
[0024] S52. Using self-aligned etching of the insertion layer material, a portion of the insertion layer material along the word line direction within the recessed structure is retained to form an insertion layer.
[0025] S53. Deposit phase change layer materials using physical vapor deposition, chemical vapor deposition or atomic layer deposition methods;
[0026] S54. Using anisotropic etching of the phase change layer material, a portion of the phase change layer material along the word line direction in the recessed structure and the through-hole structure is retained to form a phase change layer.
[0027] Preferably, step S6 includes:
[0028] S61. Self-aligned etching of the insulating layer material in the substrate exposes the metal interconnect vias of the circuit chip;
[0029] S62, Fill the electrode material and completely fill the through-hole structure;
[0030] S63. The top electrode material is removed by chemical mechanical planarization or etching process, making it flush with the top insulating medium to form a top electrode layer.
[0031] Preferably, the following steps are also included:
[0032] S7. Etch a stepped structure at the edge of the word line structure to expose each layer of word lines and some circuit chips;
[0033] S8. Fill the dielectric and planarize it to form a dielectric layer;
[0034] S9. Through photolithography etching, contact holes are formed on word lines of each layer and on memory cells that are not connected to metal interconnect vias of the circuit chip. Contact holes are filled and planarized to form metal interconnect vias.
[0035] A second aspect of the present invention provides a three-dimensional vertical structure phase change memory, which is fabricated using the method for fabricating the three-dimensional vertical structure phase change memory, comprising: a stacked structure disposed on a substrate;
[0036] The stacked structure includes a word line structure;
[0037] The electrode layer of the word line structure has a symmetrical recessed structure.
[0038] The recessed structure is provided with a gated layer, an insertion layer and a phase change layer in sequence.
[0039] Through-hole structures are provided in the insulating medium on both sides of the word line structure;
[0040] A top electrode layer is provided inside the through-hole structure.
[0041] Preferably, in the top electrode layer, a portion of the top electrode layer is connected to a metal interconnect via at the bottom, and another portion of the top electrode layer is connected to a metal interconnect via at the top.
[0042] The present invention has at least the following beneficial effects:
[0043] (1) In view of the bottleneck of the stacked hole etching process, the present invention proposes a scheme to process through holes only in a single insulating medium to form a through hole array. By utilizing the material uniformity to optimize the etching accuracy and yield, the etching difficulty can be greatly reduced, which is more suitable for the fabrication of three-dimensional stacked structure memory.
[0044] (2) The insulating medium used in this invention can form a thermal isolation groove around the storage unit. By blocking the thermal diffusion path through the insulating medium with low thermal conductivity, it helps to reduce thermal crosstalk between adjacent units and improve the reliability of data storage.
[0045] (3) By optimizing the position of bit line circuits and the efficient arrangement of multi-layer memory cells, the present invention doubles the storage density compared to the traditional structure.
[0046] (4) The high-density phase-change memory based on a three-dimensional vertical structure provided by the present invention has achieved a performance breakthrough through innovative structural design and process optimization, providing an efficient solution for the high-density non-volatile storage needs in fields such as artificial intelligence and cloud computing. Attached Figure Description
[0047] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0048] Figure 1 This is a schematic diagram of the structure after the stacked structure is deposited on the substrate according to the present invention;
[0049] Figure 2 This invention provides a schematic diagram of the structure after forming the character line structure. Figure 1 ;
[0050] Figure 3 This invention provides a schematic diagram of the structure after forming the character line structure. Figure 2 ;
[0051] Figure 4 This invention provides a schematic diagram of the structure after forming the recessed structure. Figure 1 ;
[0052] Figure 5 This invention provides a schematic diagram of the structure after forming the recessed structure. Figure 2 ;
[0053] Figure 6 Schematic diagram of the structure after deposition of the gated material provided by the present invention Figure 1 ;
[0054] Figure 7 Schematic diagram of the structure after deposition of the gated material provided by the present invention Figure 2 ;
[0055] Figure 8 This invention provides a schematic diagram of the structure after etching to form the gated layer. Figure 1 ;
[0056] Figure 9 This invention provides a schematic diagram of the structure after etching to form the gated layer. Figure 2 ;
[0057] Figure 10 Schematic diagram of the structure after filling with insulating medium and planarizing provided by the present invention Figure 1 ;
[0058] Figure 11 Schematic diagram of the structure after filling with insulating medium and planarizing provided by the present invention Figure 2 ;
[0059] Figure 12 This is a schematic diagram of the structure after etching to form a through-hole structure, as provided by the present invention.Figure 1 ;
[0060] Figure 13 This is a schematic diagram of the structure after etching to form a through-hole structure, as provided by the present invention. Figure 2 ;
[0061] Figure 14 This is a schematic diagram of the structure after the deposition of the insertion layer material provided by the present invention;
[0062] Figure 15 This is a schematic diagram of the structure after etching to form the insertion layer, as provided by the present invention.
[0063] Figure 16 This is a schematic diagram of the structure of the phase change layer material provided by the present invention after deposition;
[0064] Figure 17 This is a schematic diagram of the structure after etching to form a phase change layer, as provided by the present invention.
[0065] Figure 18 This is a schematic diagram of the structure after the metal interconnect vias of the exposed circuit chip provided by the present invention.
[0066] Figure 19 A schematic diagram of the structure provided by the present invention after filling the electrode material and completely filling the through-hole structure;
[0067] Figure 20 This is a schematic diagram of the structure after the top electrode layer is formed, as provided by the present invention.
[0068] Figure 21 This is a schematic diagram of the structure after the step structure is formed, provided by the present invention.
[0069] Figure 22 This is a schematic diagram of the structure after the formation of the dielectric layer provided by the present invention;
[0070] Figure 23 Schematic diagram of the structure after forming metal interconnect vias provided by the present invention Figure 1 ;
[0071] Figure 24 Schematic diagram of the structure after forming metal interconnect vias provided by the present invention Figure 2 .
[0072] Explanation of reference numerals in the attached figures: 1. Substrate; 1-1. Circuit chip; 1-2. Metal interconnect via of the circuit chip; 2. Stacked structure; 2-1. Insulating dielectric layer; 2-2. Electrode layer; 3. Word line structure; 4. Recessed structure; 5. Gating material; 6. Insulating dielectric; 7. Through-hole structure; 8. Insertion layer material; 9. Phase change layer material; 10. Electrode material; 11. Step structure; 12. Dielectric layer; 13. Metal interconnect via. Detailed Implementation
[0073] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.
[0074] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form includes the plural form unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.
[0075] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0076] This embodiment provides a method for fabricating a three-dimensional vertical structure phase-change memory, including the following steps:
[0077] S1. A word line structure is formed in the stacked structure on the substrate.
[0078] In this embodiment, step S1 includes:
[0079] S11. Deposit a stacked structure on a substrate; the substrate includes circuit chips and circuit sheets, the circuit chips being provided with metal interconnect vias; the stacked structure includes several layers of insulating dielectric layers and several layers of electrode layers alternately stacked.
[0080] S12, Etching and stacking structure to form word line structure.
[0081] S2. A symmetrical recessed structure is formed in the electrode layer of the word line structure.
[0082] In this embodiment, step S2 includes: using isotropic etching of the electrode layer of the word line structure to form a symmetrical recessed structure.
[0083] S3. A selection layer is formed within the recessed structure.
[0084] In this embodiment, step S3 includes:
[0085] S31. Deposit gated materials using atomic layer deposition, physical vapor deposition, or chemical vapor deposition methods;
[0086] S32. Optimize the etching process by using anisotropic and isotropic etching of the channel material, retaining part of the channel material along the word line direction in the recessed structure to form a channel layer.
[0087] S4. Fill with insulating medium to form a through-hole structure in the insulating medium on both sides of the word line structure.
[0088] In this embodiment, step S4 includes:
[0089] S41. Fill with insulating medium and flatten;
[0090] S42. Along the word line direction, through-hole structures are formed on the insulating medium on both sides of the word line structure using photolithography and self-aligned etching processes.
[0091] S5. An insertion layer and a phase change layer are formed sequentially outside the gated layer.
[0092] In this embodiment, step S5 includes:
[0093] S51. Deposit the insertion layer material using physical vapor deposition, chemical vapor deposition or atomic layer deposition methods;
[0094] S52. Using self-aligned etching of the insertion layer material, a portion of the insertion layer material along the word line direction within the recessed structure is retained to form an insertion layer.
[0095] S53. Deposit phase change layer materials using physical vapor deposition, chemical vapor deposition or atomic layer deposition methods;
[0096] S54. Using anisotropic etching of the phase change layer material, a portion of the phase change layer material along the word line direction in the recessed structure and the through-hole structure is retained to form a phase change layer.
[0097] S6. A top electrode layer is formed within the through-hole structure.
[0098] In this embodiment, step S6 includes:
[0099] S61. Self-aligned etching of the insulating layer material in the substrate exposes the metal interconnect vias of the circuit chip;
[0100] S62, Fill the electrode material and completely fill the through-hole structure;
[0101] S63. The top electrode material is removed by chemical mechanical planarization or etching process, making it flush with the top insulating medium to form a top electrode layer.
[0102] S7. Etch a stepped structure at the edge of the word line structure to expose each layer of word lines and some circuit chips.
[0103] S8. Fill the medium and planarize it to form a medium layer.
[0104] S9. Through photolithography etching, contact holes are formed on word lines of each layer and on memory cells that are not connected to metal interconnect vias of the circuit chip. Contact holes are filled and planarized to form metal interconnect vias.
[0105] The preparation method of this embodiment will be described in more detail below with reference to the accompanying drawings:
[0106] For step S11, as follows Figure 1 As shown, a stacked structure 2 is deposited on a substrate 1. The form of the substrate 1 is not limited. In this embodiment, the substrate 1 includes an existing circuit chip 1-1 and metal interconnect vias 1-2 of the circuit chip.
[0107] Specifically, the stacked structure 2 includes m layers of insulating dielectric layers 2-1 and n layers of electrode layers 2-2, which are alternately stacked, where m and n are integers. In actual operation, the number of electrode layers 2-2 can be selected according to the actual situation to meet the user's bit density requirements for the three-dimensional phase-change memory array. This embodiment uses three layers of insulating dielectric layers 2-1 and two layers of electrode layers 2-2 as an example.
[0108] Among them, the electrode layer 2-2 material can be metals such as TiN, TaN, W and their compounds, and the insulating layer material can be silicon oxide, silicon nitride and amorphous carbon.
[0109] For step S12, as Figures 2-3 As shown, the stacked structure 2 is etched to form the word line structure 3.
[0110] For step S2, as Figures 4-5 As shown, the electrode layer 2-2 of the word line structure 3 is etched isotropically to form a recessed structure 4 symmetrically arranged on both sides of the main structure.
[0111] For step S31, as follows Figures 6-7 As shown, the gate material 5 is deposited using atomic layer deposition, physical vapor deposition, or chemical vapor deposition. The gate material 5 can be any suitable material well known to those skilled in the art, and can include at least one element selected from O (oxygen), S (sulfur), Se (selenium), Te (tellurium), Ge (germanium), Sb (antimony), Si (silicon), or As (arsenic), for example, including chalcogenide materials, which can be Ge-Se-based materials, Ge-Te-based materials, etc.
[0112] For step S32, as Figures 8-9 As shown, the etching process is optimized by using anisotropic and isotropic etching of the gate material 5, retaining part of the gate material 5 along the word line direction in the recessed structure 4 to form a gate layer. That is, the gate layer covers the sidewall of the electrode layer 2-2 of the word line structure 3. At this time, the recessed structure 4 is not completely filled.
[0113] For step S41, as Figures 10-11 As shown, insulating medium 6 is filled and planarized. The insulating medium 6 can be made of silicon oxide.
[0114] For step S42, as Figures 12-13 As shown, via structures 7 are formed on the insulating medium 6 on both sides of the word line structure 3 using photolithography and self-aligned etching processes along the word line direction. Self-aligned etching of the via structures 7 is performed only on a single insulating medium 6 to form a via array. Utilizing material uniformity optimizes etching accuracy and yield, significantly reducing etching difficulty and providing more space for the process window, making it more suitable for the fabrication of three-dimensional stacked memory structures. Furthermore, the insulating medium 6 can form thermal isolation trenches around the memory cells, blocking heat diffusion paths through the low thermal conductivity of the insulating medium, helping to reduce thermal crosstalk between adjacent cells and improve data storage reliability. The number of via structures 7 needs to be determined based on specific circumstances; this embodiment uses four via structures 7 as an example.
[0115] For step S51, as follows Figure 14 As shown, the intercalation layer material 8 is deposited using physical vapor deposition, chemical vapor deposition, or atomic layer deposition. The intercalation layer material 8 can be amorphous carbon, tungsten, titanium nitride, etc. When the intercalation layer material is tungsten or titanium nitride, it mainly serves an adhesive function. When the intercalation layer material is amorphous carbon, it not only serves an adhesive function for the gated layer and phase change layer, but also prevents the segregation of elements in the phase change layer from causing performance failure, and effectively prevents heat dissipation, facilitating thermal management.
[0116] For step S52, as Figure 15 As shown, by using self-aligned etching of the insertion layer material 8, a portion of the insertion layer material 8 along the word line direction is retained in the recessed structure 4 to form an insertion layer, that is, the insertion layer covers the sidewall of the gate layer. At this time, the recessed structure 4 is not completely filled.
[0117] For step S53, as Figure 16 As shown, a phase change layer material 9 is deposited using physical vapor deposition, chemical vapor deposition, or atomic layer deposition methods. The phase change layer material 9 can be GST or a material doped with metals, non-metals, or compounds.
[0118] For step S54, as Figure 17 As shown, the phase change layer material 9 is etched anisotropically to retain part of the phase change layer material 9 along the word line direction in the recessed structure 4 and the through-hole structure 7, forming a phase change layer. That is, the phase change layer covers the sidewall of the through-hole structure 7, and the recessed structure 4 is completely filled at this time.
[0119] For step S61, as Figure 18 As shown, the insulating layer material in the self-aligned etched substrate 1 is used to expose the metal interconnect vias 1-2 of the circuit chip.
[0120] For step S62, as Figure 19 As shown, the electrode material 10 is filled and the through-hole structure 7 is completely filled.
[0121] For step S63, as Figure 20 As shown, the top electrode material 10 is removed by chemical mechanical planarization or etching process, making it flush with the top insulating medium 6 to form a top electrode layer, which is then connected by wires to form a bit line (BL).
[0122] For step S7, as Figure 21 As shown, a stepped structure 11 is formed by etching at the edge of the word line structure 3, exposing the metal word lines and some circuit chips of each layer.
[0123] For step S8, as Figure 22 As shown, a dielectric layer 12 is formed by filling the dielectric with a dielectric material and planarizing the dielectric.
[0124] For step S9, as Figures 23-24 As shown, contact holes are formed on each word line and on the memory cells that are not connected to the metal interconnect vias 1-2 of the circuit chip through one or more photolithography etching processes. Then, the contact holes are filled and planarized to form metal interconnect vias 13, so that each phase change memory cell can work independently and will not interfere with each other.
[0125] Specifically, the insertion layer, phase change layer, electrode layer, and top electrode layer form a phase change memory cell. In this invention, the top electrode layer in each via structure 7 can be shared by two memory cells, meaning that the storage density is doubled compared to the traditional structure through optimization of the bit line circuit position.
[0126] This embodiment also provides a three-dimensional vertical structure phase change memory, which is fabricated using the method of this embodiment, including: a stacked structure 2 disposed on a substrate 1; a word line structure 3 disposed in the stacked structure 2; a symmetrical recessed structure 4 disposed in the electrode layer of the word line structure 3; a gate layer, an insertion layer and a phase change layer disposed sequentially in the recessed structure 4; a through-hole structure 7 disposed in the insulating medium on both sides of the word line structure 4; and a top electrode layer disposed in the through-hole structure 7.
[0127] In this embodiment, in the top electrode layer, a portion of the top electrode layer is connected to the metal interconnect vias 1-2 of the circuit chip at the bottom, and another portion of the top electrode layer is connected to the metal interconnect via 13 at the top. During subsequent bit line interconnection, these two top electrode layers will not be connected in series in the same memory cell simultaneously, ensuring storage density.
[0128] In summary, the high-density phase-change memory with a three-dimensional vertical structure provided by this invention achieves a performance breakthrough through innovative structural design and process optimization, providing an efficient solution for the high-density non-volatile storage needs in fields such as artificial intelligence and cloud computing.
[0129] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.
[0130] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for fabricating a three-dimensional vertical structure phase-change memory, characterized in that, Includes the following steps: S1. Forming word line structures in a stacked structure on a substrate; S2. A symmetrical recessed structure is formed in the electrode layer of the word line structure; S3. A gated layer is formed within the recessed structure; S4. Fill with insulating medium to form a through-hole structure in the insulating medium on both sides of the word line structure; S5. An insertion layer and a phase change layer are formed sequentially on the outside of the gating layer; S6. A top electrode layer is formed within the through-hole structure.
2. The method for fabricating a three-dimensional vertical structure phase-change memory according to claim 1, characterized in that, Step S1 includes: S11. Deposit a stacked structure on a substrate; the substrate includes a circuit chip, the circuit chip being provided with metal interconnect vias; the stacked structure includes several layers of insulating dielectric layers and several layers of electrode layers alternately stacked. S12, Etching and stacking structure to form word line structure.
3. The method for fabricating a three-dimensional vertical structure phase-change memory according to claim 1, characterized in that, Step S2 includes: using isotropic etching of the electrode layer of the word line structure to form a symmetrical recessed structure.
4. The method for fabricating a three-dimensional vertical structure phase-change memory according to claim 1, characterized in that, Step S3 includes: S31. Deposit gated materials using atomic layer deposition, physical vapor deposition, or chemical vapor deposition methods; S32. Using anisotropic and isotropic etching of the gate material, a portion of the gate material along the word line direction within the recessed structure is retained to form a gate layer.
5. The method for fabricating a three-dimensional vertical structure phase-change memory according to claim 1, characterized in that, Step S4 includes: S41. Fill with insulating medium and flatten; S42. Along the word line direction, through-hole structures are formed on the insulating medium on both sides of the word line structure using photolithography and self-aligned etching processes.
6. The method for fabricating a three-dimensional vertical structure phase-change memory according to claim 1, characterized in that, Step S5 includes: S51. Deposit the insertion layer material using physical vapor deposition, chemical vapor deposition or atomic layer deposition methods; S52. Using self-aligned etching of the insertion layer material, a portion of the insertion layer material along the word line direction within the recessed structure is retained to form an insertion layer. S53. Deposit phase change layer materials using physical vapor deposition, chemical vapor deposition or atomic layer deposition methods; S54. Using anisotropic etching of the phase change layer material, a portion of the phase change layer material along the word line direction in the recessed structure and the through-hole structure is retained to form a phase change layer.
7. The method for fabricating a three-dimensional vertical structure phase-change memory according to claim 1, characterized in that, Step S6 includes: S61. Self-aligned etching of the insulating layer material in the substrate exposes the metal interconnect vias of the circuit chip; S62, Fill the electrode material and completely fill the through-hole structure; S63. The top electrode material is removed by chemical mechanical planarization or etching process, making it flush with the top insulating medium to form a top electrode layer.
8. The method for fabricating a three-dimensional vertical structure phase-change memory according to claim 1, characterized in that, It also includes the following steps: S7. Etch a stepped structure at the edge of the word line structure to expose each layer of word lines and some circuit chips; S8. Fill the dielectric and planarize it to form a dielectric layer; S9. Through photolithography etching, contact holes are formed on word lines of each layer and on memory cells that are not connected to metal interconnect vias of the circuit chip. Contact holes are filled and planarized to form metal interconnect vias.
9. A three-dimensional vertical structure phase-change memory, characterized in that, The preparation method according to any one of claims 1-8 is used to prepare the following: a stacked structure disposed on a substrate; The stacked structure includes a word line structure; The electrode layer of the word line structure has a symmetrical recessed structure. The recessed structure is provided with a gated layer, an insertion layer and a phase change layer in sequence. Through-hole structures are provided in the insulating medium on both sides of the word line structure; A top electrode layer is provided inside the through-hole structure.
10. The three-dimensional vertical structure phase-change memory according to claim 9, characterized in that, In the top electrode layer, a portion of the top electrode layer is connected to a metal interconnect via at the bottom, and another portion of the top electrode layer is connected to a metal interconnect via at the top.