Display module and display device

Abstract

A display module and a display device, the display module comprising: a display substrate (10), the display substrate (10) comprising a display area and a non-display area; a scanning line and a data line are arranged in the display area; the driving chip group (30 g) comprises a plurality of source electrode driving chips (30), and the source electrode driving chips (30) are configured to provide data signals for the data lines; at least two of the plurality of source driving chips (30) are target driving chips (30a); a timing control chip (60) configured to provide a first initial driving signal to each target driving chip (30a); the time sequence control chip (60) provides different first initial driving signals for different target driving chips (30a) in the same driving chip set (30 g); the target driving chip (30a) is further configured to perform level conversion on the first initial driving signal to obtain a target driving signal; and the gate driving circuit (20) is electrically connected with each target driving chip (30a) in the driving chip group (30g) and is configured to provide a scanning signal for the scanning line according to the target driving signal provided by each source driving chip (30).

Description

Display module and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display module and a display device. Background Art

[0002] In the display module, a source driver chip and a gate driver circuit are provided in the peripheral area of ​​the display substrate. The source driver chip is configured to provide a data signal to the display area of ​​the display substrate; the gate driver circuit is configured to provide a scanning signal to the display area under the drive of multiple target drive signals.

[0003] In some products, the gate drive circuit is electrically connected to a source drive chip. The source drive chip electrically connected to the gate drive circuit is also configured to perform level conversion on multiple initial drive signals provided by the timing control chip to obtain multiple target drive signals to provide to the corresponding gate drive circuits.

[0004] Summary of the Invention

[0005] In a first aspect, the present disclosure provides a display module, comprising:

[0006] A display substrate, the display substrate comprising a display area and a non-display area located around the display area; the display area is provided with scan lines and data lines;

[0007] a driver chipset, the driver chipset comprising a plurality of source driver chips, the source driver chips being configured to provide data signals to the data lines; at least two of the plurality of source driver chips being target driver chips;

[0008] a timing control chip, the timing control chip being electrically connected to the target driver chip and configured to provide a first initial driving signal to each target driver chip; wherein the timing control chip provides different first initial driving signals to different target driver chips in the same driver chip group; and the target driver chip is further configured to perform level conversion on the first initial driving signal to obtain a target driving signal;

[0009] A gate driving circuit is electrically connected to each of the target driving chips in the driving chipset and is configured to provide a scanning signal for the scanning line according to the first target driving signal provided by each of the source driving chips.

[0010] In some embodiments, the display module further comprises: a plurality of driving lines, the target driving chip being electrically connected to the gate driving circuit via the plurality of driving lines;

[0011] Wherein, at least part of the driving lines, the source driver chip and the gate driver circuit are all arranged in the non-display area of ​​the display substrate.

[0012] In some embodiments, the gate driving circuit is located on one side of the display area along a first direction, and the plurality of source driving chips in the driving chipset are located on one side of the display area along a second direction and are arranged along the first direction; the first direction is perpendicular to the second direction;

[0013] Each of the driver chipsets corresponds to one of the gate driver circuits, the plurality of target driver chips in the driver chipset comprising: a first target driver chip and a second target driver chip, the second target driver chip being located on a side of the first target driver chip away from the corresponding gate driver circuit; the plurality of driver lines comprising: a first driver line and a second driver line; the first target driver chip being electrically connected to the corresponding gate driver circuit via the first driver line, and the second target driver chip being electrically connected to the corresponding gate driver circuit via the second driver line;

[0014] The second driving line includes a first transmission portion, and the first transmission portion and the first driving line are arranged in the non-display area of ​​the display substrate; wherein, in the first driving line and the second driving line connected to the same driving chipset, the first transmission portion of the second driving line is located on a side of the first driving line away from the display area.

[0015] In some embodiments, the display substrate further includes: a substrate; the scan line and the data line are both arranged on the substrate; the first transmission part includes a plurality of first sub-layers stacked and electrically connected in a direction away from the substrate, and the first driving line includes a plurality of second sub-layers stacked and electrically connected in a direction away from the substrate, and the first sub-layers and the second sub-layers are arranged in the same layer in a one-to-one correspondence.

[0016] In some embodiments, the display substrate further includes a storage capacitor located in the display area, the storage capacitor including a first plate and a second plate, the first plate being disposed on the same layer as at least one of the scan lines, the second plate being located on a side of the first plate away from the substrate, and the data line being located on a side of the layer where the second plate is located away from the substrate;

[0017] The plurality of first sub-layers are respectively arranged on the same layer as the first electrode plate, the second electrode plate, and the data line.

[0018] In some embodiments, the display module further includes: a flexible circuit board and a driving circuit board, one end of the flexible circuit board is electrically connected to the display substrate, and the other end is electrically connected to the driving circuit board, and the timing control chip is disposed on the driving circuit board;

[0019] The second driving line also includes: a second transmission part, a third transmission part, a fourth transmission part and a fifth transmission part, the second transmission part is connected between the first transmission part and the third transmission part, the fourth transmission part is connected between the third transmission part and the fifth transmission part, and the fifth transmission part is arranged in the non-display area and is electrically connected to the second target driving chip; the second transmission part and the fourth transmission part are arranged on the flexible circuit board, and the third transmission part is arranged on the driving circuit board.

[0020] In some embodiments, the display substrate further includes a fan-out line provided on the substrate, and the source driver chip is electrically connected to the data line through the fan-out line;

[0021] The orthographic projections of the fifth transmission portion, the first transmission portion, and the first transmission line on the substrate do not overlap with the orthographic projection of the fan-out line on the substrate.

[0022] In some embodiments, the first transmission portion is arranged on the substrate of the display substrate and includes a plurality of first sublayers stacked and electrically connected in a direction away from the substrate; the fifth transmission portion includes a plurality of third sublayers stacked and electrically connected in a direction away from the substrate, and the third sublayers are arranged in the same layer in a one-to-one correspondence with the first sublayers.

[0023] In some embodiments, the display module further includes a plurality of signal input lines, the source driver chip is electrically connected to the timing control chip via the signal input lines, and the signal input lines include a first input portion provided on the driver circuit board;

[0024] The display module includes a plurality of the driver chipsets, and the first input parts connected to the first target driver chips in different driver chipsets are arranged on the same layer; the first input parts connected to the second target driver chips in different driver chipsets are arranged on the same layer.

[0025] In some embodiments, the display substrate further includes a substrate and a first pad arranged on the substrate, and the flexible circuit board is electrically connected to the first pad; the signal input line further includes a second input portion arranged on the substrate, the second input portion is connected between the first pad and the source driver chip, and the second input portion is arranged on the same layer as the first pad.

[0026] In some embodiments, the second input portion and the first pad are both provided on the same layer as the data line.

[0027] In some embodiments, the timing control signal is specifically configured to provide a multi-channel first initial driving signal to each target driver chip, and the difference in the number of channels of the first initial driving signal provided to any two target driver chips is less than or equal to 4.

[0028] In some embodiments, the timing control chip is further configured to provide a second initial driving signal to the source driver chip; each of the source driver chips is specifically configured to perform level conversion on the second initial driving signal to obtain the data signal.

[0029] In some embodiments, each of the source driver chips serves as the target driver chip.

[0030] In some embodiments, the gate driving circuit is provided on opposite sides of the display area along the first direction; the gate driving circuits located on both sides of the display area are electrically connected to two driving chip sets, respectively, and the two driving chip sets are respectively located on both sides of the first center line of the display substrate; the first center passes through the center of the display substrate and extends perpendicular to the first direction.

[0031] The present disclosure also provides a display device, which includes the above-mentioned display module. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following detailed description, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings:

[0033] FIG1 is a schematic diagram of a display module provided in some embodiments.

[0034] FIG2 is a schematic diagram of a signal flow of a display module provided in some embodiments of the present disclosure.

[0035] FIG3 is a schematic diagram of a signal flow of a display module provided in some other embodiments of the present disclosure.

[0036] FIG4 is a schematic diagram of wiring distribution of a display module provided in some embodiments of the present disclosure.

[0037] FIG5 is a schematic diagram of film layers of a display module provided in some embodiments of the present disclosure.

[0038] FIG6 is a schematic diagram illustrating the configuration of fan-out lines provided in some embodiments of the present disclosure.

[0039] FIG7 is a schematic diagram showing how the first fan-out line and the second fan-out line are connected to the data line, respectively, in some embodiments of the present disclosure.

[0040] FIG8 is a schematic diagram showing the connection between the flexible circuit board and the display substrate provided in some embodiments of the present disclosure.

[0041] FIG9 is a structural block diagram of a target driver chip provided in some embodiments of the present disclosure. DETAILED DESCRIPTION

[0042] The following describes the specific embodiments of the present disclosure in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present disclosure and are not intended to limit the present disclosure.

[0043] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0044] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the usual meanings understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0045] As used herein, "parallel" and "perpendicular" include the conditions described and conditions similar to the conditions described, and the range of the similar conditions is within an acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range for approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range for approximate perpendicularity can also be, for example, a deviation within 5°.

[0046] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0047] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0048] FIG1 is a schematic diagram of a display module provided in some embodiments. As shown in FIG1 , the display module includes a display substrate 10 , a plurality of source driver chips 30 , a timing control chip 60 , and a gate driver circuit 20 .

[0049] The display substrate 10 has a display area AA and a non-display area NA located around the display area AA. The display area AA is a region for displaying images. The display substrate 10 includes a substrate and a plurality of scan lines and a plurality of data lines disposed on the substrate.

[0050] A gate driver circuit 20 is provided on one side of the display area AA, or on both opposite sides of the display area AA. On the same side of the display area AA, the gate driver circuit 20 is electrically connected to the nearest source driver chip 30.

[0051] The timing control chip 60 is disposed on a driver circuit board 61 and is configured to provide multiple first initial drive signals to the source driver chip 30 connected to the gate driver circuit 20 and to provide a second initial drive signal to each source driver chip 30. Upon receiving the multiple first initial drive signals, the source driver chip 30 is configured to perform level conversion on the multiple first initial drive signals to obtain multiple target drive signals. Upon receiving the second initial drive signal (as indicated by the dotted arrows in FIG. 1 ), the source driver chip 30 is configured to perform level conversion on the second initial drive signal to obtain a data signal, which is then provided to the data line. Driven by the multiple target drive signals, the gate driver circuit 20 provides a scan signal to the display area AA.

[0052] In one example, the display module is a liquid crystal display module, the multiple scan lines in the display area AA include multiple gate lines, and the gate drive circuit 20 provides a first scan signal to the multiple gate lines; the multi-channel target drive signal includes a multi-channel signal that enables the gate drive circuit 20 to work normally, thereby providing the first scan signal to the multiple gate lines row by row; for example, the multi-channel target drive signal may include: a frame start signal, a first clock signal, a second clock signal, and the like.

[0053] In another example, the display module is an OLED display module, and the multiple scan lines in the display area AA include multiple gate lines and multiple light-emitting control lines. The gate drive circuit 20 may include: a first drive sub-circuit for providing a first scan signal to the multiple gate lines row by row, and a second drive sub-circuit for providing a second scan signal to the multiple light-emitting control lines row by row. The multiple target drive signals may include multiple drive signals that enable the first drive sub-circuit and the second drive sub-circuit to operate normally. For example, the multiple target drive signals may include: a first frame start signal, a second frame start signal, a first clock signal, a second clock signal, and the like.

[0054] In the display modules of some high-end gaming laptops and other products, there is an increasing demand for ultra-high frequency drive (e.g., 240Hz, 300Hz, or even above 360Hz). In this situation, the gate driver circuit 20 requires more channels (i.e., more channels) of target drive signals. For the display module shown in Figure 1, when the number of channels required by the gate driver circuit 20 increases, the processing capacity of the source driver chip 30 needs to be increased to enable it to handle target drive signals with more channels, which increases development costs.

[0055] Figure 2 is a signal flow schematic diagram of the display module provided in some embodiments of the present disclosure, Figure 3 is a signal flow schematic diagram of the display module provided in other embodiments of the present disclosure, Figure 4 is a wiring distribution schematic diagram of the display module provided in some embodiments of the present disclosure, and Figure 5 is a film layer schematic diagram of the display module provided in some embodiments of the present disclosure. As shown in Figures 2 to 4, the display module includes: a display substrate 10, a driving chipset 30g, a timing control chip 60 and a gate driving circuit 20.

[0056] The display substrate 10 has a display area AA and a non-display area NA located around the display area AA. The display area AA is used to display images. As shown in Figure 5, the display substrate 10 includes a substrate 11 and a plurality of scan lines and a plurality of data lines DL disposed on the substrate 11. The substrate 11 can be a rigid substrate made of glass or a flexible substrate made of an organic material such as polyimide (PI). The scan lines extend along a first direction, and the data lines DL extend along a second direction. The first direction intersects the second direction, for example, the first direction is perpendicular to the second direction.

[0057] The driver chipset 30g is disposed on the substrate 11 and includes a plurality of source driver chips 30, each of which is configured to provide a data signal to the data line DL, wherein at least two of the plurality of source driver chips 30 serve as target driver chips 30a.

[0058] The timing control chip 60 is electrically connected to each target driver chip 30a and is configured to provide a first initial drive signal to each target driver chip 30a. The timing control chip 60 provides different first initial drive signals to different target driver chips 30a within the same driver chipset 30g. The target driver chip 30a is further configured to perform level conversion on the first initial drive signal to obtain a target drive signal.

[0059] The gate driver circuit 20 is electrically connected to each target driver chip 30a in the driver chipset 30g and is configured to provide a scan signal to the scan line based on the first target drive signal provided by each source driver chip 30. The number of gate driver circuits 20 and the number of driver chipsets 30g can both be one or more. When both the number of gate driver circuits 20 and the number of driver chipsets 30g are more than one, each gate driver circuit 20 can be connected to a target driver chip 30a in the driver chipset 30g.

[0060] In the disclosed embodiment, the driver chipset 30g connected to the gate driver circuit 20 includes at least two target driver chips 30a. These target driver chips 30a collectively provide the gate driver circuit 20 with the required multiple target drive signals. Therefore, a single target driver chip 30a need not process a large number of signal channels, yet can still meet the gate driver circuit 20's multi-channel drive signal requirements. This also eliminates the need for additional level conversion chips, thereby reducing development and production costs. Furthermore, the multiple target drive signals are collectively provided by multiple target driver chips 30a, thereby alleviating the problem of excessive temperature rise caused by a single chip processing too many signals.

[0061] In some embodiments, within the same driver chipset 30g, the target driver chips 30a output target drive signals with the same or similar number of channels, thereby ensuring that the power consumption of each target driver chip 30a is approximately the same, preventing excessive power consumption of a particular target driver chip 30a from causing a localized excessive temperature rise. For example, the timing control chip 60 provides a multi-channel first initial drive signal to each target driver chip 30a, and the difference in the number of channels of the first initial drive signal provided to any two target driver chips 30a does not exceed 1, 2, 3, or 4, thereby ensuring that the difference in the number of channels of the target drive signals output by any two target driver chips 30a does not exceed 1, 2, 3, or 4.

[0062] For example, each gate driving circuit 20 requires a target driving signal with 32 channels. The driving chipset 30 g connected to each gate driving circuit 20 includes two target driving chips 30 a , and each target driving chip 30 a provides a target driving signal with 16 channels.

[0063] In some embodiments, as shown in FIG3 , each driver chipset 30 g includes M (M is an integer greater than 2) source driver chips 30 , of which N (N is an integer greater than 1 and less than M) source driver chips 30 serve as target driver chips 30 a . In other embodiments, as shown in FIG2 , each driver chipset 30 g includes at least two source driver chips 30 , each of which serves as a target driver chip 30 a , that is, each source driver chip 30 receives multiple target drive signals from the gate driver circuit 20 . In this case, the number of signal channels processed by a single target driver chip 30 a is reduced, thereby reducing the power consumption of the target driver chip 30 a.

[0064] In some embodiments, the display module further includes: a plurality of drive lines (such as the first drive line 71 and the second drive line 72 in FIG. 4 ), each target drive signal is electrically connected to a corresponding gate drive circuit 20 through the plurality of drive lines, thereby transmitting the multiple target drive signals to the gate drive circuit 20. At least a portion of the drive lines, the source driver chip 30, and the gate driver circuit 20 are all disposed in the non-display area NA of the display substrate 10.

[0065] As shown in Figures 2 to 4, the gate driver circuit 20 is located on one side of the display area AA along a first direction. The multiple source driver chips 30 in the driver chipset 30g are located on one side of the display area AA along a second direction and are arranged along the first direction. The first direction is perpendicular to the second direction. Each driver chipset 30g corresponds to a gate driver circuit 20. The multiple target driver chips 30a in the driver chipset 30g include: a first target driver chip 31 and a second target driver chip 32. The second target driver chip 32 is located on a side of the first target driver chip 31 away from the corresponding gate driver circuit 20. The multiple drive lines include: a plurality of first drive lines 71 and a plurality of second drive lines 72. The first target driver chip 31 is electrically connected to the corresponding gate driver circuit 20 via the plurality of first drive lines 71, and the second target driver chip 32 is electrically connected to the corresponding gate driver circuit 20 via the plurality of second drive lines 72.

[0066] The second drive line 72 includes a first transmission portion 721, which is electrically connected to the gate drive circuit 20. The first transmission portion 721 and the first drive line 71 are arranged in the non-display area NA of the display substrate 10. Among the first drive lines 71 and the second drive lines 72 connected to the same drive chipset 30g, the first transmission portion 721 of the second drive line 72 is located on a side of the first drive line 71 away from the display area AA. In this case, the orthographic projections of the first transmission portion 721 and the first drive line 71 on the substrate 11 do not overlap, thereby preventing parasitic capacitance generated by the overlap from interfering with the target drive signal.

[0067] As shown in FIG5 , in some embodiments, the first transmission portion 721 may include a plurality of first sub-layers 7211 stacked and electrically connected in a direction away from the substrate 11, and the first driving line 71 may include a plurality of second sub-layers 711 stacked and electrically connected in a direction away from the substrate 11. In the same first transmission portion 721, each two adjacent first sub-layers 7211 may be connected via a plurality of vias. Alternatively, as shown in FIG5 , the first transmission portion 721 includes three layers of first sub-layers 7211, wherein the top first sub-layer 7211 passes through the middle first sub-layer 7211 to be electrically connected to the bottom first sub-layer 7211. When the top first sub-layer 7211 passes through the middle first sub-layer 7211, the two first sub-layers 7211 are also in contact, thereby achieving parallel connection between the plurality of first sub-layers 7211 and reducing the resistance of the first transmission portion 7211. Similarly, in the same first driving line 71, each adjacent two second sub-layers 711 are connected through multiple vias; or, as shown in Figure 5, the first driving line 71 includes three layers of second sub-layers 711, and the top second sub-layer 711 passes through the second sub-layer 711 of the middle layer to be electrically connected to the bottom second sub-layer 711, and when the top second sub-layer 711 passes through the second sub-layer 711 of the middle layer, the two second sub-layers 711 are also in contact, thereby realizing parallel connection between multiple second sub-layers 711 and reducing the resistance of the first driving line 71.

[0068] In some embodiments, the first sub-layer 7211 and the second sub-layer 711 are disposed in the same layer in a one-to-one correspondence, thereby simplifying the manufacturing process. It should be noted that "disposed in the same layer" in the embodiments of the present disclosure means that the two structures are formed from the same material layer through a patterning process, so the two are in the same layer in terms of stacking relationship; however, this does not mean that the distance between the two and the substrate 11 must be the same.

[0069] As shown in Figure 5, the display substrate includes multiple pixel circuits and multiple light-emitting devices located on a substrate 11. Each light-emitting device is connected to a pixel circuit, which is used to provide a driving current to the light-emitting device to drive the light-emitting device to emit light. The pixel circuit includes multiple thin-film transistors and a storage capacitor. The storage capacitor Cs includes a first plate Cs1 and a second plate Cs2 that are arranged opposite each other. The second plate Cs2 is located on the side of the first plate Cs1 that is away from the substrate 11.

[0070] As shown in Figure 5, the thin film transistor 12 includes a gate 121, an active layer 122, a source 123 and a drain 124. Taking the thin film transistor 12 as an example of a top-gate thin film transistor, the active layer 122 is located between the gate 121 and the substrate 11. The material of the active layer 122 may include, for example, an inorganic semiconductor material (for example, polycrystalline silicon, amorphous silicon, etc.), an organic semiconductor material, or an oxide semiconductor material. The active layer 122 includes a channel portion and a source connection portion and a drain connection portion located on both sides of the channel portion. The source connection portion is connected to the source 123 of the thin film transistor 12, and the drain connection portion is connected to the drain 124 of the thin film transistor 12. Both the source connection portion and the drain connection portion may be doped with impurities (for example, N-type impurities or P-type impurities) with a higher impurity concentration than that of the channel portion. The channel portion is opposite to the gate electrode 121 of the thin film transistor 12 . When the voltage signal applied to the gate electrode 121 reaches a certain value, a carrier path is formed in the channel portion, so that the source electrode 123 and the drain electrode 124 of the thin film transistor 12 are turned on.

[0071] The buffer layer BFL is disposed between the thin film transistor 12 and the substrate 11 to prevent or reduce diffusion of metal atoms and / or impurities from the substrate 11 into the active layer 122 of the transistor. The buffer layer BFL may include an inorganic material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may be formed as a multilayer or single layer.

[0072] The first gate insulating layer GI1 is disposed on a side of the active layer 122 away from the substrate 11. The material of the first gate insulating layer GI1 may include a silicon compound or a metal oxide. For example, the material of the first gate insulating layer GI1 includes silicon oxynitride, silicon oxide, silicon nitride, silicon oxycarbide, silicon carbide nitride, aluminum oxide, aluminum nitride, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. Furthermore, the first gate insulating layer GI1 may be a single layer or multiple layers.

[0073] The first gate metal layer is disposed on a side of the first gate insulating layer GI1 away from the substrate 11. The first gate metal layer includes the gate electrodes 121 of each thin film transistor, the first electrode plate of the storage capacitor, and the gate line. The material of the gate electrode layer may include, for example, a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. For example, the gate electrode layer may include gold, a gold alloy, silver, a silver alloy, aluminum, an aluminum alloy, aluminum nitride, tungsten, tungsten nitride, copper, a copper alloy, nickel, chromium, chromium nitride, molybdenum, a molybdenum alloy, titanium, titanium nitride, platinum, tantalum, tantalum nitride, neodymium, scandium, strontium ruthenium oxide, zinc oxide, tin oxide, indium oxide, gallium oxide, indium tin oxide, indium zinc oxide, or the like. The first gate metal layer may have a single layer or multiple layers.

[0074] The second gate insulating layer GI2 is disposed on a side of the gate electrode layer away from the substrate 11 . The material of the second gate insulating layer GI2 may be selected from the above description of the first gate insulating layer GI1 .

[0075] The second gate metal layer is arranged on the side of the second gate insulation layer GI2 away from the substrate 11 and includes a second plate (not shown) of the storage capacitor. The material of the second gate metal layer can be the same as that of the first gate metal layer. For details, please refer to the conductive materials listed above.

[0076] All scan lines may be located in the first gate metal layer, or a portion of the scan lines may be located in the first gate metal layer and another portion may be located in the second gate metal layer. For example, the gate lines may be located in the first gate metal layer and the light emission control lines may be located in the second gate metal layer.

[0077] The interlayer insulating layer ILD is disposed on the side of the second plate of the capacitor away from the substrate 11. The material of the interlayer insulating layer ILD may include, for example, silicon compounds, metal oxides, etc. Specifically, the silicon compounds and metal oxides listed above may be selected and will not be described in detail here.

[0078] The first source-drain conductive layer is disposed on a side of the interlayer insulating layer ILD away from the substrate 11. The first source-drain conductive layer may include a source 123 and a drain 124 of each transistor and a plurality of data lines DL. The source 123 is electrically connected to the source connection portion, and the drain 124 is electrically connected to the drain connection portion. The first source-drain conductive layer may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. For example, the first source-drain conductive layer may be a single layer or multiple layers of metal, such as Mo / Al / Mo or Ti / Al / Ti.

[0079] The first planarization layer PLN1 is arranged on the side of the first source-drain conductive layer away from the substrate 11. The first planarization layer PLN1 can be made of organic insulating materials. For example, the organic insulating material includes polyimide, epoxy resin, acrylic, polyester, photoresist, polyacrylate, polyamide, silicone and other resin materials.

[0080] The second source-drain conductive layer is disposed on a side of the first planarization layer PLN1 away from the substrate 11. The second source-drain conductive layer may include a transfer electrode TE, which is electrically connected to the drain electrode 124 of the thin film transistor 12 through a via. The material of the second source-drain conductive layer may be selected from the materials listed above for the first source-drain conductive layer.

[0081] The second planarization layer PLN2 is disposed on a side of the second source-drain conductive layer away from the substrate 11 , and the material of the second planarization layer PLN2 may be the same as that of the first planarization layer PLN1 .

[0082] The pixel definition layer (PDL) is located on the side of the second planarization layer PLN2 facing away from the substrate 11. The pixel definition layer (PDL) has multiple pixel openings, with the light-emitting devices 13 corresponding one to each pixel opening. The light-emitting devices 13 include a first electrode 131, a second electrode 132, and a light-emitting functional layer 133 located between the first and second electrodes 131, 132. For example, the first electrode 131 is an anode, and the second electrode 132 is a cathode. The first electrode 131 is connected to the transfer electrode TE via a via, and thus electrically connected to the drain electrode 124 of the thin-film transistor 12 through the transfer electrode TE. Optionally, the first electrode 131 is a reflective electrode made of a metal material, and the second electrode 132 is a transparent electrode made of a transparent conductive material (e.g., indium tin oxide). The light-emitting functional layer 133 may include a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer stacked in sequence. The first electrode 131 is located between the pixel definition layer (PDL) and the planarization layer PLN, with a portion of the first electrode 131 exposed by the pixel openings. The second electrodes 132 of the plurality of light emitting devices 13 may be formed into an integral structure.

[0083] Optionally, the light emitting device 13 is an OLED device, in which case the light emitting layer uses an organic light emitting material; or, the light emitting device 13 is a QLED (Quantum Dot Light Emitting Diodes) device, in which case the light emitting layer uses a quantum dot light emitting material.

[0084] In some embodiments, as shown in FIG4 , the source driver chip 30 is electrically connected to a plurality of data lines DL via a plurality of fan-out lines FL, each fan-out line FL being connected to a data line DL. In one example, the plurality of fan-out lines FL are arranged in at least two layers. FIG6 is a schematic diagram of the arrangement of the fan-out lines provided in some embodiments of the present disclosure, and FIG7 is a schematic diagram of the first fan-out line and the second fan-out line provided in some embodiments of the present disclosure being respectively connected to the data lines. As shown in FIG6 and FIG7 , the plurality of fan-out lines FL include a plurality of first fan-out lines FL1 and a plurality of second fan-out lines FL2, the first fan-out line FL1 being arranged in the first gate metal layer, and the second fan-out line FL2 being located in the second gate metal layer. For example, the two fan-out lines FL connected to two adjacent data lines DL are the first fan-out line FL1 and the second fan-out line FL2, respectively. This arrangement can increase the spacing between two adjacent fan-out lines FL in the same layer, thereby preventing short circuits.

[0085] In some embodiments of the present disclosure, the multiple first sub-layers 7211 of the first transmission part 721 are respectively arranged on the same layer as the gate line, the second electrode plate and the data line DL, and the multiple second sub-layers 711 of the first driving line 71 are respectively arranged on the same layer as the gate line, the second electrode plate and the data line DL, thereby eliminating the need to use additional processes to produce the first transmission part 721 and the first driving line 71.

[0086] As shown in Figures 2 to 4 , the display module further includes a flexible circuit board 50 and a driver circuit board 61. One end of the flexible circuit board 50 is electrically connected to the display substrate 10, and the other end is electrically connected to the driver circuit board 61. Specifically, the display substrate 10 also includes a first solder pad provided on the substrate 11, and the driver circuit board 61 includes a second solder pad. One end of the flexible circuit board 50 is bonded to the first solder pad, and the other end is bonded to the second solder pad.

[0087] The timing control chip 60 is disposed on the driver circuit board 61. As shown in Figure 4, the second drive line 72 also includes a second transmission portion 722, a third transmission portion 723, a fourth transmission portion 724, and a fifth transmission portion 725. The second transmission portion 722 is connected between the first transmission portion 721 and the third transmission portion 723, the fourth transmission portion 724 is connected between the third transmission portion 723 and the fifth transmission portion 725, and the fifth transmission portion 725 is disposed in the non-display area NA and electrically connected to the first pad and the second target driver chip 32. The second transmission portion 722 and the fourth transmission portion 724 are disposed on the flexible circuit board 50, while the third transmission portion 723 is disposed on the driver circuit board 61. In other words, the second drive line 72 passes through the flexible circuit board 50, the driver circuit board 61, and then passes through the flexible circuit board 50 again before returning to the display substrate 10. This arrangement can reduce or even prevent overlap between the second drive line 72 and the fan-out line FL, thereby reducing or even preventing signal interference caused by parasitic capacitance between the two.

[0088] In an example, the orthographic projections of the fifth transmission portion 725 , the first transmission portion 721 and the first transmission line on the substrate 11 do not overlap with the orthographic projection of the fan-out line FL on the substrate 11 , so as to prevent the second driving line 72 from overlapping with the fan-out line FL.

[0089] In some embodiments, as shown in FIG5 , the fifth transmission portion 725 includes a plurality of third sublayers 7251 stacked and electrically connected in a direction away from the substrate 11. Each two adjacent third sublayers 7251 in the same fifth transmission portion 725 can be electrically connected via multiple vias, thereby enabling parallel connection of the plurality of third sublayers 7251 and reducing the resistance of the fifth transmission portion 725. The third sublayers 7251 are disposed in a one-to-one correspondence with the first sublayer 7211 of the first transmission portion 721, thereby simplifying the fabrication process. For example, the plurality of third sublayers 7251 are disposed in the same layer as the gate line, the second plate Cs2 of the storage capacitor Cs, and the data line DL, respectively.

[0090] Figure 8 is a schematic diagram of the connection between the flexible circuit board and the display substrate provided in some embodiments of the present disclosure. As shown in Figure 8, the flexible circuit board 50 has a third pad PAD3, and the second driving line 72 is arranged on the flexible circuit board 50 and can be arranged on the same layer as the third pad PAD3 and connected. The third pad PAD3 is bound and connected to the first pad PAD1, and one of the first sublayers 7211 of the first transmission part 721 is directly connected to the first pad PAD1, thereby achieving electrical connection between the first transmission part 721 and the second transmission part 722 with the help of the first pad PAD1 and the third pad PAD3.

[0091] In some embodiments, as shown in FIG4 , the display module further includes a plurality of first signal input lines 81. The target driver chip 30a is electrically connected to the timing control chip 60 via the first signal input lines 81. The target driver chip 30a receives the first initial driving signal via the first signal input lines 81. The first signal input lines 81 include a first input portion 811, a second input portion 812, and a third input portion 813. The first input portion 811 is disposed on the driver circuit board 61 and is electrically connected to the timing control chip 60. The second input portion 812 is disposed on the substrate 11 of the display substrate 10 and is connected between the first pad PAD1 and the target driver chip 30a. The third input portion 813 is connected between the first input portion 811 and the second input portion 812.

[0092] The display module includes multiple driver chipsets 30g. The first input portions 811 connected to the first target driver chips 31 in different driver chipsets 30g are arranged on the same layer. The first input portions 811 connected to the second target driver chips 32 in different driver chipsets 30g are arranged on the same layer. It should be noted that the first input portion 811 can be entirely located in a single conductive layer or in multiple conductive layers. As long as the two first input portions 811 utilize the same film structure, they can be considered to be arranged on the same layer. For example, the first input portion 811 connected to each first target driver chip 31 includes a first portion and a second portion. The first portion is electrically connected to the timing control chip 60, and the second portion is connected between the first portion and the third input portion 813. The first portion is located in the first conductive layer of the driver circuit board 61, and the second portion is located in the second conductive layer of the driver circuit board 61. In other words, the first input portions 811 connected to different first target driver chips 31 are arranged on the same layer.

[0093] In actual applications, the first input part 811 and the second input part 812 can be set according to the actual wiring conditions on the driver circuit board 61, as long as the first input part 811 and the second input part 812 are insulated and spaced apart, and the two are insulated and spaced apart from other wiring on the driver circuit board 61.

[0094] In some embodiments, the second input portion 812 is provided on the same layer as the first pad, allowing the first pad and the second input portion 812 to be fabricated simultaneously using the same patterning process, simplifying the manufacturing process. For example, the first pad, the second input portion 812, and the data line DL are provided on the same layer. The first pad is relatively close to the target driver chip 30a, so the second input portion 812 is relatively short. Even if the second input portion 812 is designed as a single-layer structure, the resistance of the second input portion 812 will not be excessively high.

[0095] In some embodiments, the timing control chip 60 is further configured to provide a second initial drive signal to the source driver chip 30 (the dotted arrows in Figures 2 and 3 represent the second initial drive signal). The source driver chip 30 includes: a first level conversion circuit, which is configured to perform level conversion on the second initial drive signal to obtain a data signal. Figure 9 is a block diagram of the structure of the target driver chip provided in some embodiments of the present disclosure. As shown in Figure 9, in addition to including the first level circuit LS1, the target driver chip 30a also includes: a second level conversion circuit LS2, which is configured to perform level conversion on the first initial drive signal to obtain a target drive signal.

[0096] Among them, when the total number of source driver chips 30 is greater than the total number of target driver chips 30a, the source driver chip 30 that is not the target driver chip 30a can only include the first level conversion circuit LS1, but not the second level conversion circuit LS2; of course, it can also include the first level conversion circuit LS1 and the second level conversion circuit LS2 at the same time, so that all source driver chips 30 adopt the same structure, reducing development and production costs.

[0097] The display module further includes a plurality of second signal input lines (not shown). Each source driver chip 30 is electrically connected to the timing control chip 60 via the second signal input lines to receive the second initial drive signal via the second signal input lines. The second signal input lines include a portion located on the display substrate 10, a portion located on the flexible circuit board 50, and a portion located on the driver circuit board 61.

[0098] In some embodiments, as shown in Figures 2 and 3 , gate driver circuits 20 are disposed on opposite sides of the display area AA along a first direction. The gate driver circuits 20 located on either side of the display area AA are electrically connected to two driver chipsets 30g, respectively. The two driver chipsets 30g are located on either side of a first centerline L1 of the display substrate 10. The first centerline L1 passes through the center of the display substrate 10 and extends perpendicular to the first direction. The two driver chipsets 30g can be symmetrically disposed.

[0099] It should be noted that, in the above embodiment, the driving chipset 30g is described as including the first target driving chip 31 and the second target driving chip 32. Of course, the driving chipset 30g can also include more target driving chips 30a, such as the third target driving chip and the fourth target driving chip, all of which fall within the scope of protection of the present disclosure.

[0100] It should also be noted that in Figures 2 to 4, in order to illustrate the connection relationship of the wiring, the driving circuit board 61, the flexible circuit board 50 and the display substrate 10 are illustrated on the same plane. In actual applications, the flexible circuit board 50 can be set to a bent state so that the driving circuit board 61 is located on the backlight side of the display substrate 10.

[0101] An embodiment of the present disclosure further provides a display device, comprising the display module in the above embodiment.

[0102] The display device may include any device or product having a display function. For example, the display device may be a smart phone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (such as a head-mounted device, electronic clothing, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, etc.

[0103] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A display module, wherein, Comprising: A display substrate, the display substrate including a display area and a non-display area located around the display area; Scan lines and data lines are provided in the display area; A driving chipset, the driving chipset including a plurality of source driving chips, the source driving chips being configured to provide data signals to the data lines; at least two of the plurality of source driving chips being target driving chips; A timing control chip, the timing control chip being electrically connected to the target driving chips and being configured to provide a first initial driving signal to each of the target driving chips; wherein, the first initial driving signals provided by the timing control chip for different target driving chips in the same driving chipset are different; the target driving chips are further configured to perform level conversion on the first initial driving signal to obtain a target driving signal; A gate driving circuit, the gate driving circuit being electrically connected to each of the target driving chips in the driving chipset and being configured to provide a scan signal to the scan lines according to the first target driving signals provided by the respective source driving chips.

2. The display module according to claim 1, wherein The display module further includes: a plurality of driving lines, the target driving chips being electrically connected to the gate driving circuit through the plurality of driving lines; Wherein, at least a part of the driving lines, the source driving chips and the gate driving circuit are all provided in the non-display area of the display substrate.

3. The display module according to claim 2, wherein, The gate driving circuit is located on one side of the display area along a first direction, and a plurality of source driving chips in the driving chipset are located on one side of the display area along a second direction and are arranged along the first direction; The first direction is perpendicular to the second direction; Each driving chipset corresponds to one gate driving circuit, the plurality of target driving chips in the driving chipset including: a first target driving chip and a second target driving chip, the second target driving chip being located on a side of the first target driving chip away from the corresponding gate driving circuit; the plurality of driving lines including: a first driving line and a second driving line; the first target driving chip is electrically connected to the corresponding gate driving circuit through the first driving line, and the second target driving chip is electrically connected to the corresponding gate driving circuit through the second driving line; The second driving line includes a first transmission portion, the first transmission portion and the first driving line being provided in the non-display area of the display substrate; wherein, in the first driving line and the second driving line connected by the same driving chipset, the first transmission portion of the second driving line is located on a side of the first driving line away from the display area.

4. The display module according to claim 3, wherein, The display substrate further includes: a substrate; the scan lines and the data lines are both provided on the substrate; the first transmission portion includes a plurality of first sub-layers stacked and electrically connected in a direction away from the substrate, the first driving line includes a plurality of second sub-layers stacked and electrically connected in a direction away from the substrate, and the first sub-layers and the second sub-layers are provided in the same layer in one-to-one correspondence.

5. The display module according to claim 4, wherein, The display substrate further includes a storage capacitor located in the display area. The storage capacitor includes a first electrode plate and a second electrode plate. The first electrode plate is arranged in the same layer as at least one of the scanning lines. The second electrode plate is located on a side of the first electrode plate away from the substrate. The data line is located on a side of the layer where the second electrode plate is located away from the substrate. Wherein, the multiple first sub-layers are respectively arranged in the same layer as the first electrode plate, the second electrode plate, and the data line.

6. The display module according to claim 3, wherein, The display module further includes a flexible circuit board and a driving circuit board. One end of the flexible circuit board is electrically connected to the display substrate, and the other end is electrically connected to the driving circuit board. The timing control chip is arranged on the driving circuit board. The second driving line further includes a second transmission portion, a third transmission portion, a fourth transmission portion, and a fifth transmission portion. The second transmission portion is connected between the first transmission portion and the third transmission portion. The fourth transmission portion is connected between the third transmission portion and the fifth transmission portion. The fifth transmission portion is arranged in the non-display area and is electrically connected to the second target driving chip. The second transmission portion and the fourth transmission portion are arranged on the flexible circuit board, and the third transmission portion is arranged on the driving circuit board.

7. The display module according to claim 6, wherein, The display substrate further includes fan-out lines arranged on the substrate. The source driving chip is electrically connected to the data lines through the fan-out lines. Orthogonal projections of the fifth transmission portion, the first transmission portion, and the first transmission line on the substrate do not overlap with the orthogonal projection of the fan-out line on the substrate.

8. The display module according to claim 6, wherein, The first transmission portion is arranged on the substrate of the display substrate and includes multiple first sub-layers stacked and electrically connected in a direction away from the substrate. The fifth transmission portion includes multiple third sub-layers stacked and electrically connected in a direction away from the substrate. The third sub-layers are arranged in the same layer as the first sub-layers in a one-to-one correspondence.

9. The display module according to claim 6, wherein, The display module further includes multiple signal input lines. The source driving chip is electrically connected to the timing control chip through the signal input lines. The signal input lines include a first input portion arranged on the driving circuit board. Wherein, the display module includes multiple of the driving chip groups. The first input portions connected to the first target driving chips in different driving chip groups are arranged in the same layer. The first input portions connected to the second target driving chips in different driving chip groups are arranged in the same layer.

10. The display module according to claim 9, wherein, The display substrate further includes a substrate and a first pad arranged on the substrate. The flexible circuit board is electrically connected to the first pad. The signal input lines further include a second input portion arranged on the substrate. The second input portion is connected between the first pad and the source driving chip. The second input portion is arranged in the same layer as the first pad.

11. The display module according to claim 10, wherein, The second input portion and the first pad are both arranged in the same layer as the data lines.

12. The display module according to any one of claims 1 to 11, wherein, The timing control signal is specifically configured to provide multi-channel first initial driving signals to each of the target driving chips, and the difference in the number of channels of the first initial driving signals provided to any two of the target driving chips is less than or equal to 4.

13. The display module according to any one of claims 1 to 11, wherein, The timing control chip is further configured to provide a second initial driving signal to the source driving chip; each of the source driving chips is specifically configured to perform level conversion on the second initial driving signal to obtain the data signal.

14. The display module according to any one of claims 1 to 11, wherein, Each of the source driving chips serves as the target driving chip.

15. The display module according to any one of claims 1 to 11, wherein, The gate driving circuits are disposed on opposite sides of the display area along the first direction; the gate driving circuits on both sides of the display area are electrically connected to two driving chip groups respectively, and the two driving chip groups are respectively located on both sides of the first center line of the display substrate; the first center passes through the center of the display substrate and extends perpendicular to the first direction.

16. A display device, wherein, It includes the display module according to any one of claims 1 to 15.

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