Light detection device

Abstract

The present invention reduces the current of a load transistor in a non-read period while suppressing a decline in image quality. The light detection device includes: a first signal line connected to a first active pixel; a first current source connected to the first signal line; a first switch disposed between the first effective pixel and the first current source; a second signal line connected to the second active pixel; a second current source connected to the second signal line; a second switch disposed between the second effective pixel and the second current source; a horizontal connection signal line for connecting the first signal line and the second signal line; a dummy signal line connected to the dummy pixel; a third current source connected to the dummy signal line; and a control unit for controlling a potential of the horizontal connection signal line based on a potential of the dummy signal line.

Description

Technical Field

[0001] This technology relates to a light detection device. In particular, this technology relates to a light detection device capable of forming a source layer between a pixel and a load transistor via a vertical signal line. Background Technology

[0002] To achieve low power consumption in imaging devices, there is a method for separating the vertical signal line from the load transistor during non-readout periods. For example, a solid-state imaging device has been proposed that stops the current supply to the load MOS circuit after the comparator of the A / D converter inverts, in order to reduce power consumption (see, for example, Patent Document 1). Citation List Patent documents

[0003] Patent Document 1: Japanese Patent Application Publication No. 2020-88785 Summary of the Invention The problem to be solved by the present invention

[0004] However, if the current to the load transistor is stopped during the non-readout period, the potential of the vertical signal line during the non-readout period will separate from the potential of the vertical signal line during the readout period, and image quality may be degraded due to capacitive coupling.

[0005] This technology was developed in view of this situation, and its purpose is to reduce the current of the load transistor during non-readout periods while suppressing image quality degradation. Solution to the problem

[0006] This technology aims to solve the aforementioned problems, and its first aspect is a light detection device comprising: a first signal line connected to a first effective pixel; a first current source connected to the first signal line; a first switch disposed between the first effective pixel and the first current source; a second signal line connected to a second effective pixel; a second current source connected to the second signal line; a second switch disposed between the second effective pixel and the second current source; a horizontal connecting signal line connecting the first signal line and the second signal line; a virtual signal line connected to a virtual pixel; a third current source connected to the virtual signal line; and a control unit that controls the potential of the horizontal connecting signal line based on the potential of the virtual signal line. This achieves the effect of stopping the current of the load transistor during non-readout periods while suppressing the difference between the potential of the vertical signal line during non-readout periods and the potential of the vertical signal line during readout periods.

[0007] Furthermore, in the first aspect, the control unit can control the virtual signal line and the horizontal connection signal line to have the same potential. This results in stopping the current of the load transistor during non-readout periods while matching the potential of the vertical signal line during non-readout periods with the potential of the vertical signal line during readout periods.

[0008] Furthermore, in the first aspect, the control unit may include an operational amplifier, a first input of which is connected to the dummy signal line, and a second input of which is connected to the horizontal connection signal line. This allows for the comparison of the potential of the dummy signal line with the potential of the horizontal connection signal line.

[0009] Furthermore, in the first aspect, the control unit may include a transistor that drives the horizontal connection signal line based on the output of the operational amplifier. This results in the effect of controlling the potential of the horizontal connection signal line based on a comparison between the potential of the virtual signal line and the potential of the horizontal connection signal line.

[0010] Furthermore, in the first aspect, the control unit may include a mode setting unit that sets the current flowing through the transistor during the readout period. This results in the effect of controlling the current flowing through the transistor during the readout period.

[0011] Furthermore, in the first aspect, the virtual pixel may include an optical blackbody (OPB) pixel. This provides the effect of matching the potential of the vertical signal line during the non-readout period with the potential of the vertical signal line during the readout period, while addressing manufacturing deviations in the characteristics of the light detection device.

[0012] Furthermore, in the first aspect, the light detection device may further include: a third switch disposed between the first signal line and the horizontal connection signal line; and a fourth switch disposed between the second signal line and the horizontal connection signal line. This provides the effect of disconnecting the first and second signal lines from the horizontal connection signal line during the readout period.

[0013] Furthermore, in the first aspect, the first and second switches can be turned off during the vertical blanking period, and the third and fourth switches can be turned on during the vertical blanking period. This results in the effect of stopping the current to the load transistor during the vertical blanking period while matching the potential of the vertical signal line during the vertical blanking period with the potential of the vertical signal line during the readout period.

[0014] Furthermore, in the first aspect, the first and second switches can be opened during the horizontal blanking period, and the third and fourth switches can be closed during the horizontal blanking period. This results in the effect of stopping the current to the load transistor during the horizontal blanking period while matching the potential of the vertical signal line during the horizontal blanking period with the potential of the vertical signal line during the readout period.

[0015] Additionally, in the first aspect, the light detection device may further include a fifth switch disposed between the virtual pixel and the third current source. This provides the effect of disconnecting the virtual pixel from the third current source during the readout period.

[0016] Furthermore, in the first aspect, the fifth switch can be closed during the vertical blanking period and opened during the readout period. This results in the effect of allowing current to flow through the dummy signal line during the vertical blanking period and stopping the current flowing through the dummy signal line during the readout period.

[0017] Furthermore, in the first aspect, the fifth switch can be closed during the horizontal blanking period and opened during the readout period. This results in the effect of allowing current to flow through the dummy signal line during the horizontal blanking period and stopping the current flowing through the dummy signal line during the readout period.

[0018] Furthermore, in the first aspect, the light detection device may further include: a first column in which the first effective pixels are arranged along a column direction; a second column in which the second effective pixels are arranged along the column direction; and a virtual column in which virtual pixels are arranged along the column direction. This results in the following effect: in a pixel array unit formed by arranging effective pixels in a matrix along the row and column directions, the current of the load transistor is stopped during the non-readout period, while the difference between the potential of the vertical signal line during the non-readout period and the potential of the vertical signal line during the readout period is suppressed.

[0019] Furthermore, in the first aspect, the first column may include the first effective pixel and the first OPB pixel, the second column may include the second effective pixel and the second OPB pixel, and the virtual column may include virtual effective pixels and virtual OPB pixels. This results in the following effect: in a pixel array unit where effective pixels are arranged in a matrix along the row and column directions, the potential of the vertical signal line during the non-readout period is matched with the potential of the vertical signal line during the readout period, while addressing manufacturing differences in the characteristics of the light detection device. Furthermore, in the first aspect, multiple virtual columns can be configured. This improves the output accuracy of the virtual columns. Attached Figure Description

[0020] Figure 1This is a block diagram illustrating an example of the construction of an imaging apparatus according to the first embodiment. Figure 2 This is a block diagram illustrating a construction example of a solid-state imaging device according to the first embodiment. Figure 3 This is a diagram illustrating an example of the circuit construction of pixels disposed in a solid-state imaging device according to the first embodiment. Figure 4 This is a diagram illustrating an example of the construction of a column readout circuit provided in a solid-state imaging device according to the first embodiment. Figure 5 This is a timing diagram illustrating an example of the readout period and non-readout period of the solid-state imaging device according to the first embodiment. Figure 6 This is a timing diagram showing an example of the waveform of the vertical signal line during the horizontal blanking period and the AD conversion period of the solid-state imaging device according to the first embodiment. Figure 7 This is a graph showing the relationship between the load current and the control current in each mode of the solid-state imaging device according to the first embodiment. Figure 8 This is a graph showing the relationship between frame rate and current consumption in each mode of the solid-state imaging device according to the first embodiment. Figure 9 This is a diagram illustrating an example of the construction of a column readout circuit provided in a solid-state imaging device according to the second embodiment. Figure 10 This is a block diagram illustrating a construction example of a solid-state imaging device according to a third embodiment. Figure 11 This is a diagram illustrating an example of the circuit construction of pixels disposed in a solid-state imaging device according to the fourth embodiment. Figure 12 This is a transmission diagram showing an example of a stacked solid-state imaging device according to the fifth embodiment. Specific Implementation

[0021] Embodiments of this technology (hereinafter referred to as embodiments) will be described below. They will be described in the following order. 1. First Embodiment (An example of controlling the potential of a horizontal connection signal line used to connect a vertical signal line to a valid pixel based on the potential of a virtual signal line connected to a virtual pixel set in a virtual column) 2. Second embodiment (example of setting up multiple virtual columns with virtual pixels connected to virtual signal lines arranged along the column direction) 3. Third embodiment (an example of setting a virtual column of n (n is a positive integer less than m) in a portion of an invalid pixel column of m (m is a positive integer) columns arranged around the effective pixel array) 4. Fourth Embodiment (Example of Pixels Using Hall Sensors) 5. Fifth Embodiment (Example of a semiconductor chip on which a solid-state imaging device is formed by stacking)

[0022] <1. First Embodiment> Figure 1 This is a diagram illustrating an example of the construction of an imaging apparatus including a light detection device according to the first embodiment. Note that a solid-state imaging device is used as an example of a light detection device in the following description.

[0023] In the accompanying drawings, the imaging device 100 includes an optical system 101, a solid-state imaging device 102, an imaging control unit 103, an image processing unit 104, a storage unit 105, a display unit 106, and an operation unit 107. The imaging control unit 103, image processing unit 104, storage unit 105, display unit 106, and operation unit 107 are interconnected via a bus 108. Note that the imaging device 100 can be used independently or integrated into a mobile terminal such as a smartphone, an authentication device or a monitoring device, or a vehicle or drone.

[0024] The optical system 101 allows light from the subject to enter the solid-state imaging device 102, forming an optical image on the light-receiving surface of the solid-state imaging device 102. The optical system 101 may include, for example, a focusing lens, a zoom lens, and an aperture. The optical system 101 may also include multiple lenses such as a wide-angle lens, a standard lens, and a telephoto lens.

[0025] For each pixel, the solid-state imaging device 102 converts the optical image formed on the light-receiving surface into an electrical signal, digitizes it, and outputs it. The solid-state imaging device 102 is, for example, a complementary metal-oxide-semiconductor (CMOS) image sensor. The CMOS image sensor can be a back-illuminated image sensor or a front-illuminated image sensor. Note that the light detection device is not limited to the solid-state imaging device 102 and can be applied to time-of-flight (ToF) sensors or event-based vision sensors, etc.

[0026] The imaging control unit 103 controls the imaging of the solid-state imaging device 102 according to commands from the operation unit 107. At this time, the imaging control unit 103 can control the exposure time, exposure amount, and imaging sequence of the solid-state imaging device 102.

[0027] The image processing unit 104 performs image processing based on the output of the solid-state imaging device 102. Image processing may include, for example, gamma correction, white balance processing, sharpness processing, or grayscale conversion processing. The image processing unit 104 may include a processor that performs processing based on software.

[0028] The storage unit 105 is used to store images captured by the solid-state imaging device 102, and to store imaging parameters of the solid-state imaging device 102. In addition, the storage unit 105 may also store programs for enabling the imaging device 100 to operate based on software. The storage unit 105 may include a read-only memory (ROM), a random access memory (RAM), and a memory card.

[0029] The display unit 106 is used to display captured images and various information to support imaging operations. The display unit 106 may be a liquid crystal display or an organic electroluminescent (EL) display.

[0030] The operation unit 107 provides a user interface for operating the imaging device 100. The operation unit 107 may include, for example, buttons, dials, and switches provided in the imaging device 100. The operation unit 107 may be implemented as a touch panel together with the display unit 106.

[0031] Note that, depending on the form of the imaging device 100, some of the above-mentioned functions may be omitted, or conversely, undisclosed functions may be further included.

[0032] Figure 2 This is a block diagram illustrating a construction example of a solid-state imaging device according to the first embodiment.

[0033] exist Figure 2 In the solid-state imaging device 102, there are pixel array units 111, vertical scanning circuit 112, column readout circuit 113, column signal processing unit 114, horizontal scanning circuit 115 and control circuit 116.

[0034] Pixel array unit 111 includes virtual pixels (DIX) and multiple pixel pixels (PIX). The pixel array unit 111 may be configured with virtual columns (DCA); the virtual pixels (DIX) are arranged in the virtual columns (DCA) along the column direction. The pixel pixels (PIX) are arranged in a matrix along the row direction (also called the horizontal direction) and the column direction (also called the vertical direction). Each virtual pixel (DIX) and each pixel pixel (PIX) may include an effective pixel capable of receiving incident light and a masked OPB pixel. Each virtual pixel (DIX) and each pixel pixel (PIX) may be sensitive to visible light, near-infrared light (NIR), short-wavelength infrared light (SWIR), or ultraviolet light or X-rays. Note that when each pixel pixel (PIX) is sensitive to visible light, each pixel pixel (PIX) may form a Bayer array or a quad Bayer array. When each virtual pixel (DIX) and each pixel pixel (PIX) is sensitive to infrared light, each virtual pixel (DIX) and each pixel pixel (PIX) may be formed by a Hall sensor to improve conversion efficiency. In a Hall sensor, the generation efficiency of holes is higher than that of electrons during photoelectric conversion.

[0035] During signal readout, each virtual pixel DIX and each pixel PIX can form a source follower together with the column readout circuit 113. For each row, the virtual pixel DIX and each pixel PIX are connected to the horizontal drive line HSL. Furthermore, for each column, the virtual pixel DIX is connected to the virtual signal line DSL, and for each column, the pixel PIX is connected to the vertical signal line VSL. When reading signals from each virtual pixel DIX and each pixel PIX, the horizontal drive line HSL drives each virtual pixel DIX and each pixel PIX in each row. For each column, the vertical signal line VSL transmits the signal read from the pixel PIX to the column signal processing unit 114. The virtual signal line DSL connects each virtual pixel DIX to a current source.

[0036] The vertical scanning circuit 112 scans the pixels to be read along the column direction. The vertical scanning circuit 112 may include a vertical register. Here, while reading signals from each pixel, the vertical scanning circuit 112 can drive each pixel in each row via the horizontal drive line HSL.

[0037] When reading signals from each pixel PIX, the column readout circuit 113 can form a source follower together with each pixel PIX. At this time, the column readout circuit 113 can change the potential of the vertical signal line VSL based on the charge held in the pixel PIX.

[0038] Furthermore, the column readout circuit 113 can interconnect the vertical signal lines VSL of the corresponding columns during non-readout periods. Then, the column readout circuit 113 can control the potential of the vertical signal lines VSL of the corresponding columns based on the potential of the virtual signal line DSL. At this time, the column readout circuit 113 can control the virtual signal line DSL and the vertical signal lines VSL of each column to have the same potential. This control can be performed during either the vertical blanking period or the horizontal blanking period.

[0039] The column signal processing unit 114 processes the signal transmitted from each pixel PIX in the column direction. For example, the column signal processing unit 114 may perform correlated double sampling (CDS) processing based on the signal transmitted from each pixel PIX in the column direction. In addition, the column signal processing unit 114 may perform analog-to-digital (AD) conversion processing based on the signal transmitted from each pixel PIX in the column direction and output the imaging signal Gout.

[0040] The column signal processing unit 114 includes a column ADC unit 114A. The column ADC unit 114A can perform AD conversion processing in parallel for each column. At this time, the column ADC unit 114A can perform AD conversion for each column based on the comparison result between the pixel signal read from the pixel PIX and a reference signal. Note that the column readout circuit 113 and the column signal processing unit 114 can be disposed on corresponding sides of the pixel array unit 111 along the column direction.

[0041] The horizontal scanning circuit 115 scans the pixels to be read along the row direction. The horizontal scanning circuit 115 may include a horizontal register.

[0042] The control circuit 116 controls the vertical scanning circuit 112, the column readout circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115. For example, the control circuit 116 can control the scanning timing in the column direction, the scanning timing in the row direction, the operation timing of the column readout circuit 113, and the processing timing of the column signal processing unit 114.

[0043] Furthermore, the control circuit 116 can be configured to set the timing of the potential of each vertical signal line VSL based on the potential of the virtual signal line DSL. The control circuit 116 can set this timing to a vertical blanking period or a horizontal blanking period.

[0044] The control circuit 116 includes a mode setting unit 116A. The mode setting unit 116A can set a mode for controlling the potential of each vertical signal line VSL based on the potential of the virtual signal line DSL. In this mode, the current consumption during the readout period can be switched. At this time, the mode setting unit 116A can set a normal mode, a low-power mode, and a standby mode. Note that the control circuit 116 is an example of the control unit described in the claims.

[0045] Figure 3 This is a block diagram illustrating an example of the circuit construction of pixels disposed in a solid-state imaging device according to the first embodiment.

[0046] exist Figure 3 In this design, the pixel PIX includes a photodiode 121, a transmission transistor 122, a reset transistor 123, an amplification transistor 124, a selection transistor 125, and a floating diffuser FD. Metal-oxide-semiconductor (MOS) transistors can be used as the transmission transistor 122, the reset transistor 123, the amplification transistor 124, and the selection transistor 125.

[0047] Amplifying transistor 124 and selecting transistor 125 are connected in series. The cathode of photodiode 121 is connected to the floating diffuser FD via transfer transistor 122. Furthermore, the floating diffuser FD is connected to the power supply VDD via reset transistor 123. Additionally, the power supply VDD is connected to the vertical signal line VSL via a series circuit of amplifying transistor 124 and selecting transistor 125. The gate of amplifying transistor 124 is connected to the floating diffuser FD.

[0048] The transmission signal TGL is supplied to the gate of the transmission transistor 122. The reset signal RST is supplied to the gate of the reset transistor 123. The select signal SEL is supplied to the gate of the select transistor 125. The transmission signal TGL, the reset signal RST, and the select signal SEL can be transmitted through... Figure 2 The horizontal drive line (HSL) is transmitted to each pixel (PIX).

[0049] When the transmission transistor 122 is turned on, the charge accumulated in the photodiode 121 is transferred to the floating diffuser FD. Subsequently, when the selection transistor 125 is turned on, the source potential of the amplification transistor 124 changes according to the potential of the floating diffuser FD. Then, the source potential of the amplification transistor 124 is applied to the vertical signal line VSL through the selection transistor 125 and transmitted through the vertical signal line VSL. Furthermore, when the reset transistor 123 is turned on, the charge accumulated in the floating diffuser FD is released.

[0050] Figure 4 This is a diagram illustrating an example of the construction of a column readout circuit provided in a solid-state imaging device according to the first embodiment.

[0051] exist Figure 4 In the pixel array unit 111, there is an effective pixel area 131 and an OPB pixel area 231. Virtual effective pixels DVX and effective pixels PVX1 to PVX3… are arranged in the effective pixel area 131. Virtual OPB pixels DBX and OPB pixels PBX1 to PBX3… are arranged in the OPB pixel area 231. The virtual effective pixels DVX and virtual OPB pixels DBX are arranged in a virtual column DCA.

[0052] The virtual effective pixel DVX includes pixel circuit 132-0, amplifying transistor 124-0, and selection transistor 125-0. The virtual OPB pixel DBX includes pixel circuit 232-0, amplifying transistor 224-0, and selection transistor 225-0. Effective pixels PVX1 to PVX3... each include pixel circuits 132-1 to 132-3..., amplifying transistors 124-1 to 124-3..., and selection transistors 125-1 to 125-3... respectively. OPB pixels PBX1 to PBX3... each include pixel circuits 232-1 to 232-3..., amplifying transistors 224-1 to 224-3..., and selection transistors 225-1 to 225-3... respectively. Each pixel circuit 132-0 to 132-3 and 232-0 to 232-3 may include a photodiode 121, a transmission transistor 122, a reset transistor 123, and a floating diffuser FD.

[0053] The virtual effective pixel DVX and the virtual OPB pixel DBX are connected to the virtual signal line DSL. The effective pixels PVX1 to PVX3... and the OPB pixels PBX1 to PBX3... are respectively connected to the vertical signal lines VSL1 to VSL3... The selection transistor 225-0 of the virtual OPB pixel DBX can be turned on / off in a manner independent of the selection transistor 125-0 of the virtual effective pixel DVX, the selection transistors 125-1 to 125-3... of the effective pixels PVX1 to PVX3... respectively, and the selection transistors 225-1 to 225-3... of the OPB pixels PBX1 to PBX3... respectively.

[0054] The virtual signal line DSL is connected to the current source 160 via switch 180. Additionally, the virtual signal line DSL is connected to the inverting input terminal of operational amplifier 191 via switch 170.

[0055] Vertical signal lines VSL1 to VSL3... are connected to current sources 161 to 163... via switches 181 to 183... respectively. Furthermore, vertical signal lines VSL1 to VSL3... are connected to the horizontal connection signal line HCL via switches 171 to 173... respectively. Switches 170 to 173... and 180 to 183... can both be field-effect transistors.

[0056] The non-inverting input terminal of operational amplifier 191 and the drain of driving transistor 192 are connected to the horizontal connection signal line HCL. The output terminal of operational amplifier 191 is connected to the gate of driving transistor 192. At this time, operational amplifier 191 compares the potential of the virtual signal line DSL with the potential of the horizontal connection signal line HCL, and can drive driving transistor 192 so that the virtual signal line DSL and the horizontal connection signal line HCL have the same potential. Driving transistor 192 can be a field-effect transistor.

[0057] Comparators 151 to 153... are connected to vertical signal lines VSL1 to VSL3, respectively. The potentials of vertical signal lines VSL1 to VSL3... are then applied to the inverting input terminals of comparators 151 to 153... A reference signal DAC is input to the non-inverting input terminal of each comparator 151 to 153... The reference signal DAC is, for example, a ramp signal. Comparators 151 to 153... then compare the potentials of vertical signal lines VSL1 to VSL3 with the reference signal DAC, and can output the comparison results VO1 to VO3 respectively.

[0058] Control circuit 116 can disconnect switches 181 to 183... and close switches 170 to 173... and 180 during the vertical blanking and horizontal blanking periods. Furthermore, vertical scan circuit 112 turns on the selection transistor 225-0 of the virtual OPB pixel DBX and turns off the selection transistor 125-0 of the virtual active pixel DVX, the selection transistors 125-1 to 125-3... of the active pixels PVX1 to PVX3..., and the selection transistors 225-1 to 225-3... of the OPB pixels PBX1 to PBX3..., respectively. At this time, column readout circuit 113 can be controlled to ensure that the virtual signal line DSL and the vertical signal line VSL of each column have the same potential.

[0059] Furthermore, the control circuit 116 can close switches 181 to 183... and open switches 170 to 173... and 180 during the readout period. Additionally, the vertical scan circuit 112 turns off the selection transistor 225-0 of the virtual OPB pixel DBX and the selection transistor 125-0 of the virtual effective pixel DVX, and turns on the selection transistors 125-1 to 125-3... of the effective pixels PVX1 to PVX3... and the selection transistors 225-1 to 225-3... of the OPB pixels PBX1 to PBX3... respectively. At this time, the column ADC unit 114A can perform AD conversion on the pixel signals read from each pixel PVX1 to PVX3 based on the comparison results VO1 to VO3 output from comparators 151 to 153... respectively.

[0060] Furthermore, the control circuit 116 can independently control the opening / closing of switch 180 and switches 181 to 183... For example, when switches 181 to 183... are closed, the control circuit 116 can close or open switch 180. Here, by opening switch 180 when switches 181 to 183... are closed, the current flowing through the virtual signal line DSL during the readout period can be cut off, and low power consumption can be achieved.

[0061] Additionally, the control circuit 116 inputs a mode setting signal MOD to the operational amplifier 191. The mode setting signal MOD can set the normal mode, low power mode, and standby mode.

[0062] Figure 5 This is a timing diagram illustrating an example of the readout period and non-readout period of the solid-state imaging device according to the first embodiment.

[0063] exist Figure 5 In this process, a vertical time period H6 is set for one frame based on the vertical synchronization signal XVS. A standby time period H1 can be set before the vertical time period H6. A vertical readout time period H2 and a vertical blanking time period H3 are set within each vertical time period H6. In addition, a non-exposure time period H4 and an exposure time period H5 are set within each vertical time period H6.

[0064] When transitioning to the vertical readout period H2, a readout operation PREAD is performed for each pixel in each row. When transitioning to the exposure period H5, a shutter operation RSH is performed for each pixel in each row. Here, during the vertical blanking period H3, it is assumed that switches 181 to 183... are open, and the vertical signal lines VSL1 to VSL3... are disconnected from current sources 161 to 163... respectively. At this time, the potential VL1 of each vertical signal line VSL1 to VSL3... rises based on the turn-off leakage current of the selection transistor 125, and horizontal stripes appear due to the coupling CUP between the vertical signal lines VSL1 to VSL3... and the pixels.

[0065] Simultaneously, when switches 181 to 183... are open during the vertical blanking period H3, switches 170 to 173... and 180 are closed. At this time, vertical signal lines VSL1 to VSL3... are connected to the horizontal connection signal line HCL via switches 171 to 173... respectively. Furthermore, the dummy signal line DSL is connected to the current source 160. Then, operational amplifier 191 drives drive transistor 192 such that the dummy signal line DSL and the horizontal connection signal line HCL have the same potential. Therefore, during the vertical blanking period H3, the rise of the potential VL2 of each vertical signal line VSL1 to VSL3... is suppressed, and the appearance of lateral stripes caused by the coupling capacitance CUP between each vertical signal line VSL1 to VSL3... and the pixel is suppressed.

[0066] Figure 6 This is a timing diagram illustrating an example of the waveform of the vertical signal line during the horizontal blanking period and the AD conversion period of the solid-state imaging device according to the first embodiment. Note that in Figure 6 In the diagram, the potentials VL1 and VL2 of the vertical signal lines are shown in a polarity-reversed manner.

[0067] exist Figure 6In this process, the horizontal blanking period H11 and the horizontal readout period H12 are set based on the horizontal enable signal H11. Within each horizontal readout period H12, the P-phase AD conversion period PAD and the D-phase AD conversion period DAD are set.

[0068] Here, it is assumed that during the horizontal blanking period H11, switches 181 to 183... are open, and vertical signal lines VSL1 to VSL3... are disconnected from current sources 161 to 163... respectively. At this time, the potential VL1 of each vertical signal line VSL1 to VSL3 rises due to the turn-off leakage of the selection transistor 125.

[0069] Simultaneously, when switches 181 to 183... are open during the horizontal blanking period H11, switches 170 to 173... and 180 are closed. At this time, vertical signal lines VSL1 to VSL3... are connected to the horizontal connection signal line HCL via switches 171 to 173... respectively. Furthermore, the dummy signal line DSL is connected to the current source 160. Then, operational amplifier 191 drives drive transistor 192, causing the dummy signal line DSL and the horizontal connection signal line HCL to have the same potential. Therefore, during the horizontal blanking period H11, the rise of the potential VL2 of each vertical signal line VSL1 to VSL3... is suppressed. At this time, the potential VL2 of each vertical signal line VSL1 to VSL3... can be set to an arbitrary level, thereby shortening the setup time. Therefore, the proportion (duty cycle) of the horizontal blanking period H11 within a horizontal period can be increased, thereby achieving low power consumption during the horizontal blanking period H11.

[0070] Figure 7 The relationship between the load current and the control current of the solid-state imaging device according to the first embodiment is shown in each mode. Note that... Figure 7 Part a shows the current flowing through the vertical signal lines VSL1 to VSL3... in constant current mode (when switches 181 to 183... are closed during the vertical blanking period). Figure 7 Part b shows the current flowing through the vertical signal lines VSL1 to VSL3... in normal mode when switches 181 to 183... are open during the vertical blanking period. Figure 7 Part c shows the current flowing through the vertical signal lines VSL1 to VSL3... in standby mode when switches 181 to 183... are open during the vertical blanking period. Figure 7 Part d shows the current flowing through the vertical signal lines VSL1 to VSL3... when switches 181 to 183... are open during the vertical blanking period in low-power mode.

[0071] exist Figure 7In part a, under constant current mode, the current consumed during the readout period and the vertical blanking period is IPAmA.

[0072] exist Figure 7 In part b, under normal mode, the current consumption during the readout period is IPBmA, and the current consumption during the vertical blanking period is IPCmA. IPB = IPA + IPC. In normal mode, although the current consumption during the readout period increases compared to constant current mode, the current consumption during the vertical blanking period decreases. Here, the number of vertical signal lines (VSLs) is greater than the number of virtual signal lines (DSLs). Therefore, although the increase in current consumption during the readout period is small, the decrease in current consumption during the vertical blanking period is significant. Thus, in normal mode, power consumption can be reduced compared to constant current mode.

[0073] exist Figure 7 In part c, during standby mode, the current consumption during the readout period is IPAmA, and the current consumption during the vertical blanking period is IPCmA. Although the current consumption during the readout period in standby mode is the same as that in constant current mode, the current consumption during the vertical blanking period is lower compared to constant current mode. Therefore, the power consumption in standby mode can be reduced compared to normal mode.

[0074] exist Figure 7 In part d, in low-power mode, the current consumption during the readout period is IPAmA+α, and the current consumption during the vertical blanking period is IPCmA. In low-power mode, the current consumption is slightly higher than in constant-current mode, but the current consumption during the vertical blanking period is lower. Therefore, in low-power mode, power consumption can be reduced compared to constant-current mode.

[0075] Figure 8 This is a graph illustrating the relationship between frame rate and current consumption in each mode of the solid-state imaging device according to the first embodiment. Note that L1 represents constant current mode, L2 represents normal mode, L3 represents low power mode, and L4 represents standby mode.

[0076] exist Figure 8 In this study, compared to constant current mode L1, normal mode L2, low power mode L3, and standby mode L4 exhibit significant power reduction at low frame rates (e.g., long exposures). However, in normal mode L2, power consumption may increase at high frame rates compared to constant current mode L1. Therefore, at high frame rates with a fixed frame rate, operation can be performed in constant current mode L1. Alternatively, during the readout period, operation can be performed in low power mode L3 or standby mode L4.

[0077] As described above, in the first embodiment, the potential of the horizontal connection signal line HCL, which connects the vertical signal lines VSL1 to VSL3..., is controlled based on the potential of the virtual signal line DSL connected to the virtual pixels disposed in the virtual column DCA. Therefore, when the vertical signal lines VSL1 to VSL3... are disconnected from the current sources 161 to 163... respectively, the virtual signal line DSL and the horizontal connection signal line HCL can be set to the same potential. Thus, power consumption can be reduced while suppressing lateral stripes caused by coupling between each vertical signal line VSL1 to VSL3... and the pixel.

[0078] <2. Second Embodiment> In the first embodiment described above, the potential of the horizontal connection signal line HCL is controlled based on the potential of the virtual signal line DSL connected to the virtual pixels disposed in the virtual column DCA. In the second embodiment, multiple virtual columns are provided, in which virtual pixels connected to the virtual signal lines are arranged along the column direction.

[0079] Figure 9 This is a diagram illustrating an example of the construction of a light detection device according to the second embodiment.

[0080] exist Figure 9 In this embodiment, the imaging device includes virtual columns DCA1 and DCA2, replacing the virtual column DCA of the first embodiment described above. The other structures of the imaging device in the second embodiment are similar to those of the imaging device in the first embodiment described above.

[0081] The construction of each virtual column DCA1 and DCA2 is similar to that of virtual column DCA. In this case, virtual effective pixels DVX1 and virtual OPB pixels DBX1 are arranged in virtual column DCA1. Virtual effective pixels DVX2 and virtual OPB pixels DBX2 are arranged in virtual column DCA2.

[0082] The virtual effective pixel DVX1 includes pixel circuit 132-01, amplification transistor 124-01, and selection transistor 125-01. The virtual OPB pixel DBX1 includes pixel circuit 232-01, amplification transistor 224-01, and selection transistor 225-01.

[0083] Virtual effective pixel DVX1 and virtual OPB pixel DBX1 are connected to virtual signal line DSL1. Virtual signal line DSL1 is connected to current source 160-1 via switch 180-1. Additionally, virtual signal line DSL1 is connected to the inverting input terminal of operational amplifier 191 via switch 170.

[0084] The virtual effective pixel DVX2 includes pixel circuit 132-02, amplification transistor 124-02, and selection transistor 125-02. The virtual OPB pixel DBX2 includes pixel circuit 232-02, amplification transistor 224-02, and selection transistor 225-02.

[0085] Virtual effective pixel DVX2 and virtual OPB pixel DBX2 are connected to virtual signal line DSL2. Virtual signal line DSL2 is connected to current source 160-2 via switch 180-2. Additionally, virtual signal line DSL2 is connected to the inverting input terminal of operational amplifier 191 via switch 170.

[0086] Each pixel circuit 132-01, 132-02, 232-01 and 232-02 may include a photodiode 121, a transmission transistor 122, a reset transistor 123 and a floating diffuser FD.

[0087] Here, the potentials of multiple virtual signal lines DSL1 and DSL2 are averaged and input to the non-inverting input of operational amplifier 191. Operational amplifier 191 then compares the average potential of virtual signal lines DSL1 and DSL2 with the potential of the horizontal connection signal line HCL. Then, operational amplifier 191 drives drive transistor 192 so that the average potential of virtual signal lines DSL1 and DSL2 has the same potential as the horizontal connection signal line HCL.

[0088] As described above, in the second embodiment, multiple virtual columns DCA1 and DCA2 are provided, in which virtual pixels connected to virtual signal lines DSL1 and DSL2 are arranged along the column direction. Therefore, the in-phase input of operational amplifier 191 can be set based on the average potential of multiple virtual signal lines DSL1 and DSL2. Therefore, when the vertical signal lines VSL1 to VSL3 are disconnected from current sources 161 to 163 respectively, the driving accuracy of operational amplifier 191 in setting the virtual signal lines DSL and the horizontal connection signal line HCL to the same potential can be improved.

[0089] Note that in the second embodiment described above, an example of setting two virtual columns DCA1 and DCA2 was given, but it is also possible to set more than three virtual columns.

[0090] <3. Third Embodiment> In the first embodiment described above, the potential of the horizontal connection signal line HCL is controlled based on the potential of the virtual signal line DSL connected to the virtual pixels disposed in the virtual column DCA. In the third embodiment, n virtual columns are disposed in a portion of the m columns of invalid pixels surrounding the effective pixel array.

[0091] Figure 10This is a block diagram illustrating a construction example of a solid-state imaging device according to a third embodiment.

[0092] exist Figure 10 In this embodiment, the solid-state imaging device 302 includes a pixel array unit 311, replacing the pixel array unit 111 of the first embodiment described above. The other structures of the solid-state imaging device 302 in the third embodiment are similar to those of the solid-state imaging device 102 in the first embodiment described above.

[0093] The pixel array unit 311 includes an effective pixel array 312, invalid pixel rows 313, and invalid pixel columns 314. The invalid pixel rows 313 can be arranged on both sides of the effective pixel array 312 in the column direction. The invalid pixel columns 314 can be arranged on both sides of the effective pixel array 312 in the row direction.

[0094] In the effective pixel array 312, effective pixels are arranged in a matrix along the row and column directions. In the invalid pixel row 313, invalid pixels are arranged along the row direction. In the invalid pixel column 314, invalid pixels are arranged along the column direction. An m-column invalid pixel column 314 can be set. In this case, an n-column virtual column 315 can be set within the invalid pixel column 314. In the virtual column 315, virtual pixels are arranged along the column direction. Virtual effective pixels and virtual OPB pixels can be set within the virtual pixels. The virtual column 315 is connected to the virtual signal line DSL. The construction of a virtual column 315 can be similar to the construction of the virtual column DCA in the first embodiment described above.

[0095] As described above, in the third embodiment, a virtual column 315 is provided in a portion of the invalid pixel column 314 disposed around the effective pixel array 312. Therefore, n columns of virtual pixels can be arranged around the effective pixel array 312.

[0096] <4. Fourth Embodiment> In the first embodiment described above, pixels that accumulate electrons based on photoelectric conversion are applied to a solid-state imaging device. In the fourth embodiment, pixels that accumulate holes based on photoelectric conversion are applied to a solid-state imaging device.

[0097] Figure 11 This is a diagram illustrating an example of the circuit construction of pixels disposed in a solid-state imaging device according to the fourth embodiment.

[0098] exist Figure 11In this embodiment, the pixel PHX includes a photodiode 410, a transmission transistor 412, and a reset transistor 413, replacing the photodiode 121, transmission transistor 122, and reset transistor 123 in the pixel PIX of the first embodiment described above. Furthermore, in the pixel PHX, capacitors SN1 and SN2 and a discharge transistor 414 are added as in the pixel PIX of the first embodiment described above. An N-channel field-effect transistor can be used as an amplification transistor 124 and a selection transistor 125. A P-channel field-effect transistor can be used as a transmission transistor 412, a reset transistor 413, and a discharge transistor 414. Capacitors SN1 and SN2 can be metal-insulated metal (MIM) capacitors or junction capacitors formed on a semiconductor substrate.

[0099] Photodiode 410 generates holes based on photoelectric conversion. The material of photodiode 410 can be, for example, a compound semiconductor with an InGaP, InAlP, InGaAs, InAlAs, or chalcopyrite structure. In this case, photodiode 410 can be sensitive to infrared light (e.g., wavelength range of 900 nm to 1700 nm). A power supply voltage Vtop is applied to the anode of photodiode 410. The power supply voltage Vtop can be varied according to the reset voltage used to initialize the charge of photodiode 410.

[0100] Transmission transistor 412 transfers the charge accumulated in photodiode 410 to the floating diffuser FD. Reset transistor 413 resets the charge accumulated in the floating diffuser FD. Discharge transistor 414 discharges the charge accumulated in capacitor SN1.

[0101] Amplifying transistor 124 and selecting transistor 125 are connected in series. This series circuit of amplifying transistor 124 and selecting transistor 125 is connected between the power supply voltage VDD3 and the vertical signal line VSL. The cathode of photodiode 410 is connected to the floating diffuser FD via transfer transistor 412. Furthermore, the floating diffuser FD is connected to the power supply voltage VDD1 via reset transistor 123. Voltage VDD1 is lower than the power supply voltage Vtop.

[0102] Capacitor SN1 is connected to the anode of photodiode 410. Transmission transistor 412 and discharge transistor 414 are connected in series. This series circuit of transmission transistor 412 and discharge transistor 414 is connected between the power supply voltage VDD1 and the floating diffuser FD. Capacitor SN2 is connected to the floating diffuser FD.

[0103] The transmission signal TGL is applied to the gate of the transmission transistor 412. The reset signal PST is applied to the gate of the reset transistor 413. The discharge signal OFG is applied to the gate of the discharge transistor 414.

[0104] As described above, in the fourth embodiment, a pixel PHX that accumulates holes based on photoelectric conversion is applied to a solid-state imaging device. Therefore, it is possible to suppress the occurrence of lateral stripes caused by coupling between the vertical signal line VSL and the pixel PHX, while reducing power consumption and improving sensitivity to the infrared region.

[0105] <5. Fifth Embodiment> In the first embodiment described above, the potential of the horizontal connection signal line HCL, which connects the vertical signal lines VSL1 to VSL3..., is controlled based on the potential of the virtual signal line DSL connected to the virtual pixel connection line disposed in the virtual column DCA. In the fifth embodiment, a semiconductor chip having a solid-state imaging device is stacked, the solid-state imaging device having pixel array units in which pixels are arranged in a matrix.

[0106] Figure 12 This is a transmission diagram showing an example of a stacked solid-state imaging device according to the fifth embodiment.

[0107] exist Figure 12 In this design, the solid-state imaging device includes semiconductor chips 921 and 922. Semiconductor chip 922 is stacked on top of semiconductor chip 921.

[0108] Pixel array unit 923 is formed on semiconductor chip 922. Pixel array unit 923 includes pixels 931 arranged in a matrix along the row and column directions. Pixel 931 can be... Figure 3 Pixel PIX or Figure 11 The pixel PHX is formed in the image. Pad electrodes 932 and via electrodes 933 are formed around the pixel array unit 923. The via electrodes 933 penetrate the semiconductor chip 922 and can electrically connect the semiconductor chips 921 and 922 to each other.

[0109] Peripheral circuitry 924 is formed on semiconductor chip 921. Peripheral circuitry 924 includes column readout circuitry 925, column ADC 926, communication interface 927, and oscillation circuitry 928. Column readout circuitry 925 and column ADC 926 can be formed in a manner corresponding to the positions of the pixel array unit 923 on both sides in the column direction.

[0110] Semiconductor chips 921 and 922 can be directly bonded. Direct bonding of semiconductor chips 921 and 922 can also be achieved using hybrid bonding. In this case, semiconductor chips 921 and 922 can be electrically connected based on a Cu-Cu connection. The semiconductor substrate material used for semiconductor chips 921 and 922 can be Si, InGaAs, or InP.

[0111] As described above, in the fifth embodiment, a semiconductor chip 922 on which pixel array units 923 are formed is stacked on a semiconductor chip 921 on which peripheral circuitry 924 is formed. This can improve the sensitivity of the solid-state imaging device while simultaneously suppressing the increase in the mounting area of ​​the semiconductor chip on which the solid-state imaging device is formed.

[0112] Note that the above embodiments represent examples of implementing this technology, and there is a correspondence between the contents of the embodiments and the contents specifically described in the claims. Similarly, there is a correspondence between the contents specifically described in the claims and the contents with the same names in the embodiments of this technology. However, this technology is not limited to these embodiments, and can be implemented by making various modifications to the embodiments without departing from its scope. Furthermore, the effects described in this specification are merely illustrative and not limiting, and other effects may also occur.

[0113] Note that this technology can also have the following configurations. (1) A light detection device, comprising: A first signal line is connected to a first valid pixel; A first current source is connected to the first signal line; A first switch is disposed between the first effective pixel and the first current source; The second signal line is connected to the second valid pixel; A second current source is connected to the second signal line; A second switch is disposed between the second valid pixel and the second current source; A horizontally connected signal line connects the first signal line and the second signal line; Virtual signal lines, which are connected to virtual pixels; A third current source, which is connected to the virtual signal line; and The control unit controls the potential of the horizontally connected signal line based on the potential of the virtual signal line. (2) According to the optical detection device described in (1), wherein, The control unit controls the virtual signal line and the horizontal connection signal line to have the same potential. (3) The optical detection device according to (1) or (2), wherein, The control unit includes an operational amplifier, a first input of which is connected to the virtual signal line, and a second input of which is connected to the horizontal connection signal line. (4) The optical detection device according to (3), wherein, The control unit includes a transistor that drives the horizontal connection signal line based on the output of the operational amplifier. (5) The optical detection device according to (4), wherein, The control unit includes a mode setting unit, which sets the current flowing through the transistor during the readout period. (6) The light detection apparatus according to any one of (1) to (5), wherein, The virtual pixels include optical blackbody (OPB) pixels. (7) The light detection apparatus according to any one of (1) to (6), further comprising: A third switch is disposed between the first signal line and the horizontal connection signal line; and A fourth switch is disposed between the second signal line and the horizontal connection signal line. (8) The optical detection device according to (7), wherein, The first switch and the second switch are open during the vertical blanking period, and The third switch and the fourth switch are closed during the vertical blanking period. (9) The optical detection device according to (7) or (8), wherein, The first switch and the second switch are open during the horizontal blanking period, and The third switch and the fourth switch are closed during the horizontal blanking period. (10) The light detection device according to claim 1, further comprising: a fifth switch disposed between the virtual pixel and the third current source. (11) The light detection apparatus according to any one of (1) to (10), wherein, The fifth switch is closed during the vertical blanking period and opened during the readout period. (12) The optical detection device according to (11), wherein, The fifth switch is closed during the horizontal blanking period and opened during the readout period. (13) The light detection apparatus according to any one of (1) to (12), further comprising: In the first column, the first effective pixels are arranged along the column direction; The second column, in which the second effective pixels are arranged along the column direction; and A virtual column, in which virtual pixels are arranged along the column direction. (14) The optical detection device according to (13), wherein, The first column includes the first valid pixel and the first OPB pixel. The second column includes the second valid pixel and the second OPB pixel, and The virtual column includes virtual valid pixels and virtual OPB pixels. (15) The optical detection device according to (13) or (14), wherein, Multiple virtual columns are provided. List of reference numerals

[0114] 100 Imaging Device 101 Optical System 102 Solid-state imaging devices 103 Imaging Control Unit 104 Image Processing Units 105 storage units 106 display units 107 Operation Unit 108 bus 111 pixel array unit 112 Vertical Scanning Circuit 113-column readout circuit 114 signal processing units 115 Horizontal Scanning Circuit 116 Control Circuit 121 Photodiode 122 Transmission Transistor 123 Reset transistor 124 Amplifying Transistors 125 Select Transistor PIX pixels DIX Virtual Pixels HSL Horizontal Drive Line VSL Vertical Signal Line HCL horizontal connection signal line DSL virtual signal line DCA Virtual Column Pixel circuits from 132-0 to 132-3 and from 232-0 to 232-3 Comparators 151 to 153 Current sources 161 to 163 170 to 173, 180 to 183 switches 191 Operational Amplifier 192 driving transistors 131 effective pixel area 231 OPB pixel area DVX Virtual Effective Pixels DBX Virtual OPB Pixels PVX effective pixels PBX OPB pixels

Claims

1. A light detection device, comprising: A first signal line is connected to a first valid pixel; A first current source is connected to the first signal line; A first switch is disposed between the first effective pixel and the first current source; The second signal line is connected to the second valid pixel; A second current source is connected to the second signal line; A second switch is disposed between the second valid pixel and the second current source; A horizontally connected signal line connects the first signal line and the second signal line; Virtual signal lines, which are connected to virtual pixels; A third current source is connected to the virtual signal line; as well as The control unit controls the potential of the horizontally connected signal line based on the potential of the virtual signal line.

2. The optical detection device according to claim 1, wherein, The control unit controls the virtual signal line and the horizontal connection signal line to have the same potential.

3. The optical detection device according to claim 1, wherein, The control unit includes an operational amplifier, a first input of which is connected to the virtual signal line, and a second input of which is connected to the horizontal connection signal line.

4. The optical detection device according to claim 3, wherein, The control unit includes a transistor that drives the horizontal connection signal line based on the output of the operational amplifier.

5. The optical detection device according to claim 4, wherein, The control unit includes a mode setting unit, which sets the current flowing through the transistor during the readout period.

6. The optical detection device according to claim 1, wherein, The virtual pixels include optical blackbody (OPB) pixels.

7. The optical detection device according to claim 1, further comprising: A third switch is disposed between the first signal line and the horizontal connection signal line; as well as A fourth switch is disposed between the second signal line and the horizontal connection signal line.

8. The optical detection device according to claim 7, wherein, The first switch and the second switch are open during the vertical blanking period, and The third switch and the fourth switch are closed during the vertical blanking period.

9. The optical detection device according to claim 7, wherein, The first switch and the second switch are open during the horizontal blanking period, and The third switch and the fourth switch are closed during the horizontal blanking period.

10. The optical detection device according to claim 1, further comprising: A fifth switch is disposed between the virtual pixel and the third current source.

11. The optical detection device according to claim 10, wherein, The fifth switch is closed during the vertical blanking period and opened during the readout period.

12. The optical detection device according to claim 10, wherein, The fifth switch is closed during the horizontal blanking period and opened during the readout period.

13. The optical detection device according to claim 1, further comprising: In the first column, the first effective pixels are arranged along the column direction; In the second column, the second effective pixels are arranged along the column direction; as well as A virtual column, in which virtual pixels are arranged along the column direction.

14. The optical detection device according to claim 13, wherein, The first column includes the first valid pixel and the first OPB pixel. The second column includes the second valid pixel and the second OPB pixel, and The virtual column includes virtual valid pixels and virtual OPB pixels.

15. The optical detection device according to claim 13, wherein, Multiple virtual columns are provided.

Images