A signal processing apparatus, a phase memory device, and a method

Abstract

A signal processing apparatus, a phase memory device, and a method are disclosed. The processing apparatus generates a digital waveform signal based on a frequency control word and through phase accumulation. It includes a phase memory unit and a control module. The phase memory unit acquires an initial memory value and a frequency control word corresponding to the frequency to be memorized. Based on the initial memory value, it synchronizes the phase accumulation during digital waveform signal generation with the frequency control word of the memorized frequency as a step size to acquire an accumulated memory value. The control module outputs the initial memory value and the frequency control word corresponding to the memorized frequency to the phase memory unit. When the set frequency of the signal to be output by the signal processing apparatus is the frequency memorized in the phase memory unit, it uses the synchronized accumulated memory value as the initial value for phase accumulation during digital waveform signal generation. Because the accumulated memory value is stored using dynamic synchronous phase accumulation, phase memory functionality is achieved when the signal frequency is recovered.

Description

Technical Field

[0001] This application relates to the field of digital signal processing technology, specifically to a signal processing apparatus, a phase memory device, and a method. Background Technology

[0002] Currently, in multi-channel output signal control, the phase difference between output signals can be adjusted. However, when the frequency of the signal output from one channel changes and returns, the phase relationship between the returned channel and the signals output from other channels will be flipped or shifted. Please refer to [reference needed]. Figure 1 The diagram illustrates the output signal waveforms of a dual RF channel in one embodiment. In the first time period, the output signals of the first and second channels have the same frequency, and ΔΦ is the phase difference between the two signals of the same frequency. In the second time period, the output signal of the first channel remains unchanged, while the second channel switches its output signal frequency (frequency change). In the third time period, when the frequency of the second channel's output signal returns to the frequency value of the first time period, the phase difference ΔΦ between the output signal of the second channel at its original frequency and the unchanged output signal of the first channel will shift. If it is desired that the phase difference ΔΦ between the changed RF channel and the output RF signals of other RF channels remains unchanged after the changed RF channel returns to its original frequency, the RF channel needs to have a phase memory function. Please refer to... Figure 2 This is a waveform demonstration diagram of the phase memory function in one embodiment. The original signal waveform is a waveform diagram of the initial output signal of the RF channel on the time axis. The solid line waveform is the actual output waveform of the RF channel, and the dashed line waveform is the memory waveform for implementing the phase memory function. The output waveform is a waveform diagram of the recovery process after the frequency of the RF channel output signal changes. The first time period is the initial signal waveform, the second time period is the waveform after the signal frequency changes, and the third time period is the initial signal recovery waveform after restoring the original frequency. The phase memory function ensures that when the frequency of the RF signal output by the RF channel changes and returns to its original value, the phase information of the original frequency RF signal is not lost, thereby maintaining the continuity and consistency of RF channel signal processing. Summary of the Invention

[0003] The main technical problem solved by this invention is how to realize the phase memory function in the signal processing process.

[0004] According to a first aspect, one embodiment provides a phase memory device for a signal, comprising:

[0005] A frequency synthesis circuit is used to output a digital waveform signal with a set frequency by phase accumulation based on a frequency control word;

[0006] The phase memory unit is used to receive the initial memory value and frequency control word corresponding to the memory frequency, and to perform phase accumulation synchronously with the frequency synthesis circuit based on the initial memory value and the frequency control word corresponding to the memory frequency as the step size, and to obtain the accumulated memory value.

[0007] The control module is used to acquire a set frequency and output a frequency control word according to the set frequency, and output the frequency control word to the frequency synthesis circuit. The control module is also used to output the initial memory value corresponding to the memory frequency and the frequency control word to the phase memory unit based on the phase memory instruction, and when a new set frequency is acquired, to determine whether the frequency control word corresponding to the new set frequency is the same as the frequency control word corresponding to the memory frequency in the phase memory unit. If they are the same, the current accumulated memory value corresponding to the memory frequency is output to the frequency synthesis circuit as the initial value for the phase accumulation of the frequency synthesis circuit.

[0008] In one embodiment, the frequency synthesis circuit includes a phase accumulator, a phase-to-amplitude converter, and a signal output module. The phase accumulator is used to acquire a frequency control word and perform phase accumulation with the frequency control word as the step size according to a preset reference clock, and outputs a phase accumulation value. The phase-to-amplitude converter is used to output an amplitude control signal according to the phase accumulation value and a set waveform type. The signal output module is used to output an analog signal with a set frequency according to the amplitude control signal.

[0009] The phase memory unit is configured to include at least one memory sub-unit. Each memory sub-unit is connected to a phase accumulator and is used to receive an initial memory value and a frequency control word corresponding to the memory frequency from the phase accumulator. Based on the initial memory value, the phase is accumulated according to the clock beat with the frequency control word corresponding to the memory frequency as the step size to obtain the accumulated memory value.

[0010] The control module is used to output the frequency control word to the phase accumulator, configure a corresponding memory sub-unit for at least one memorized frequency in the phase memory unit based on the phase memory instruction, output the initial memory value and frequency control word corresponding to the memorized frequency to the corresponding memory sub-unit, update the frequency control word output to the phase accumulator based on the new set frequency, determine whether the new frequency control word is the same as the frequency control word corresponding to the memorized frequency, if so, output the current accumulated memory value corresponding to the memorized frequency to the phase accumulator as the initial value for phase accumulation by the phase accumulator.

[0011] In one embodiment, the frequency to be memorized is the current set frequency when the control module receives the phase memory command; the initial memory value is the phase accumulation value currently output by the phase accumulator when the control module receives the phase memory command, or the phase accumulation value currently output by the phase accumulator when the control module receives a new set frequency.

[0012] In one embodiment, the frequency to be memorized is the current set frequency and subsequent set frequencies when the control module receives the phase memory command; the initial memory value is the phase accumulation value of the previous set frequency currently output by the phase accumulator each time a new set frequency is received, or the initial memory value is the phase accumulation value corresponding to the new set frequency currently output by the phase accumulator each time a new set frequency is received.

[0013] In one embodiment, the memory subunit includes a memory phase accumulator and a control word memory;

[0014] The memory phase accumulator and the control word memory are respectively connected to the phase accumulator. The control word memory is used to acquire and store the frequency control word corresponding to the memory frequency. The memory phase accumulator is used to perform phase accumulation synchronously with the frequency synthesis circuit based on the initial memory value and with the frequency control word corresponding to the memory frequency as the step size, and obtain the accumulated memory value.

[0015] In one embodiment, the signal output module includes a digital-to-analog converter (DAC) and a phase-locked loop (PLL). The input terminal of the DAC is connected to the output terminal of the phase-to-amplitude converter (P / A converter) and is used to convert the digital amplitude control signal output by the P / A converter into an analog signal. The output terminal of the DAC is connected to the P / A converter, which is used to lock the lower frequency analog signal output by the DAC into a higher frequency output signal.

[0016] In one embodiment, the analog signal output by the signal output module is a radio frequency signal.

[0017] In one embodiment, the phase memory device further includes a human-computer interaction module, wherein the setting frequency and / or phase memory command is input by the user through the human-computer interaction module.

[0018] In one embodiment, the phase memory instruction is generated based on the user's triggering of the phase memory function key, or based on the user's setting operation of a new set frequency.

[0019] In one embodiment, the phase memory device further includes a clock setting unit for providing a clock signal to the frequency synthesis circuit and the phase memory unit.

[0020] According to a second aspect, one embodiment provides a signal processing apparatus for outputting a digital waveform signal, the digital waveform signal being generated based on a frequency control word and through phase accumulation, comprising:

[0021] A phase memory unit is used to acquire the initial memory value and frequency control word corresponding to the memory frequency, and synchronize the phase accumulation when generating the digital waveform signal with the frequency control word of the memory frequency as the step size based on the initial memory value, and obtain the accumulated memory value.

[0022] The control module is used to output the initial memory value and frequency control word corresponding to the memory frequency to the phase memory unit based on the phase memory instruction, and when the processing device pre-outputs the new digital waveform signal, it determines whether the set frequency of the new digital waveform signal is the same as the memory frequency in the phase memory unit. If so, the accumulated memory value in the phase memory unit is used as the initial value of phase accumulation when generating the digital waveform signal.

[0023] According to a third aspect, one embodiment provides a method for phase memory of a signal, comprising:

[0024] Obtain the user's settings for the required output waveform frequency and waveform type;

[0025] A frequency control word is generated based on a set frequency, so that the frequency synthesis circuit can output a waveform signal with the set frequency by phase accumulation based on the frequency control word;

[0026] Monitor the phase memory command input by the user; based on the phase memory command, output the initial memory value and frequency control word corresponding to the frequency to be memorized to the phase memory unit, and control the phase memory unit to perform phase accumulation synchronously with the frequency synthesis circuit based on the initial memory value and the frequency control word corresponding to the frequency to be memorized as the step size, and obtain the accumulated memory value;

[0027] Update the frequency control word based on the new set frequency;

[0028] The frequency control word corresponding to the new set frequency is matched with the frequency control word corresponding to the memorized frequency stored in the phase memory unit;

[0029] If the match is successful, the accumulated memory value corresponding to the memory frequency that matches the new set frequency will be used as the initial value for the frequency synthesis circuit to perform phase accumulation based on the frequency control word, so as to output a waveform that is in phase with the memory frequency.

[0030] If the matching fails, the updated frequency control word is output to the frequency synthesis circuit, so that the frequency synthesis circuit can output a waveform signal with a new set frequency by phase accumulation based on the updated frequency control word.

[0031] In one embodiment, the frequency to be memorized is the current set frequency when the control module receives the phase memory command; the initial memory value is the phase accumulation value currently output by the phase accumulator when the control module receives the phase memory command, or the phase accumulation value currently output by the phase accumulator when the control module receives a new set frequency.

[0032] In one embodiment, the frequency to be memorized is the current set frequency and subsequent set frequencies when the control module receives the phase memory command; the initial memory value is the phase accumulation value of the previous set frequency currently output by the phase accumulator each time a new set frequency is received, or the initial memory value is the phase accumulation value corresponding to the new set frequency currently output by the phase accumulator each time a new set frequency is received.

[0033] According to the fourth aspect, one embodiment provides a computer program product including a computer program and / or instructions that, when executed by a processor, implement the phase memory method as described in the third aspect.

[0034] According to a fifth aspect, one embodiment provides a computer-readable storage medium storing a computer program that can be executed by a processor to implement the phase memory method as described in the third aspect.

[0035] According to the processing device of the above embodiment, the accumulated memory value is stored by means of dynamic synchronous phase accumulation, so that when the signal processing device restores the frequency stored in the output phase memory unit, it can still maintain the phase state of the digital waveform signal consistent with that before the frequency change, thereby realizing the phase memory function. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of the output signal waveform of a dual RF channel in one embodiment;

[0037] Figure 2 This is a waveform demonstration diagram of the phase memory function in one embodiment;

[0038] Figure 3 This is a functional structural block diagram of a phase memory device in one embodiment;

[0039] Figure 4 This is a schematic diagram showing the functional module connections of a frequency synthesis circuit in one embodiment;

[0040] Figure 5This is a functional structure block diagram of a phase memory unit in one embodiment;

[0041] Figure 6 This is a structural block diagram of the processing device in one embodiment;

[0042] Figure 7 This is a flowchart illustrating a phase memory method for a signal in one embodiment;

[0043] Figure 8 This is a block diagram illustrating the functional implementation of the RF channel phase memory function in one embodiment.

[0044] Figure 9 This is a flowchart illustrating a phase memory method for an RF channel in one embodiment.

[0045] Figure 10 This is a flowchart illustrating the RF channel phase memory process in one embodiment. Detailed Implementation

[0046] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of this application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to this application are not shown or described in the specification. This is to avoid obscuring the core parts of this application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0047] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0048] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages).

[0049] The purpose of phase memory can be simply understood as how to acquire or save the phase information or phase parameters of the transmitted signal before the switch when the output frequency of one or more RF channels changes and then returns to the previous frequency, or when the transmitted signal switches between multiple RF channels. Methods to achieve phase memory include single-sided phase compensation and double-sided phase synchronization. Double-sided phase synchronization involves phase offsets on both the transmitter's DDS and the receiver's NCO. Single-sided phase compensation involves performing phase compensation on the returned channel signal when the RF channel returns to the previous frequency, so that the returned channel signal is consistent with the phase before the switch, thus achieving phase memory.

[0050] This application employs a single-sided phase compensation method for phase memory. The concept of this application is based on the principle and method of generating digital waveform signals by frequency control words. By using a dynamic synchronous memory phase accumulation method to store the accumulated memory value, the phase memory function can be realized when restoring the frequency of the original digital waveform signal. Example

[0051] Please refer to Figure 3 The diagram below illustrates the functional structure of a phase memory device in one embodiment. The phase memory device includes a control module 10, a phase memory unit 20, and a frequency synthesis circuit 30. The frequency synthesis circuit 30 outputs a digital waveform signal with a set frequency based on a frequency control word through phase accumulation. The phase memory unit 20 receives the initial memory value corresponding to the memorized frequency and the frequency control word, and performs phase accumulation synchronously with the frequency synthesis circuit 30 based on the initial memory value and the frequency control word corresponding to the memorized frequency as a step size, to obtain the accumulated memory value. The control module 10 acquires a set frequency and outputs a frequency control word according to the set frequency, sending the frequency control word to the frequency synthesis circuit 30. The control module 10 also outputs the initial memory value corresponding to the memorized frequency and the frequency control word to the phase memory unit 20 based on a phase memory instruction. When a new set frequency is acquired, the control module 10 determines whether the frequency control word corresponding to the new set frequency is the same as the frequency control word corresponding to the memorized frequency in the phase memory unit 20. If they are the same, the current accumulated memory value corresponding to the memorized frequency is output to the frequency synthesis circuit 30 as the initial value for phase accumulation by the frequency synthesis circuit 30.

[0052] Please refer to Figure 4This is a schematic diagram of the functional modules of a frequency synthesis circuit in one embodiment. In one embodiment, the frequency synthesis circuit 30 includes a phase accumulator 31, a phase-to-amplitude converter 32, and a signal output module 40. The phase accumulator 31 is used to acquire a frequency control word and accumulate the phase in steps of the frequency control word according to a preset reference clock, outputting the accumulated phase value. The phase-to-amplitude converter 32 is used to output an amplitude control signal based on the accumulated phase value and a set waveform type. For example, by looking up a table, the amplitude value is found in the phase-to-amplitude correspondence table corresponding to the set waveform type based on the accumulated phase value, and a digital amplitude control signal is output. The signal output module 40 is used to output an analog signal with a set frequency based on the amplitude control signal.

[0053] The phase memory unit 20 is configured to include at least one memory sub-unit 21. Each memory sub-unit 21 is connected to the phase accumulator 31 and is used to receive the initial memory value and frequency control word corresponding to the memory frequency from the phase accumulator 31. Based on the initial memory value, the phase is accumulated according to the beat of the reference clock with the frequency control word corresponding to the memory frequency as the step size to obtain the accumulated memory value.

[0054] The control module 10 outputs a frequency control word to the phase accumulator 31, configures a corresponding memory sub-unit 21 for at least one memorized frequency in the phase memory unit 20 based on the phase memory instruction, outputs the initial memory value and frequency control word corresponding to the memorized frequency to the corresponding memory sub-unit 21, updates the frequency control word output to the phase accumulator 31 based on the new set frequency, determines whether the new frequency control word is the same as the frequency control word corresponding to the memorized frequency, and if so, outputs the current accumulated memory value corresponding to the memorized frequency to the phase accumulator 31 as the initial value for phase accumulation. In one embodiment, the memorized frequency is the current set frequency when the control module 10 receives the phase memory instruction, and the initial memory value is the phase accumulation value currently output by the phase accumulator 31 when the control module 10 receives the phase memory instruction, or the phase accumulation value currently output by the phase accumulator 31 when the control module 10 receives the new set frequency. In one embodiment, the frequency to be memorized is the current set frequency and subsequent set frequencies when the control module 10 receives the phase memory command. The initial memory value is the phase accumulation value of the previous set frequency currently output by the phase accumulator 31 each time a new set frequency is received, or the initial memory value is any phase accumulation value corresponding to the new set frequency currently output by the phase accumulator 31 each time a new set frequency is received.

[0055] like Figure 4As shown, the memory subunit 21 includes a memory phase accumulator 211 and a control word memory 212. The memory phase accumulator 211 and the control word memory 212 are respectively connected to the phase accumulator 31. The control word memory 212 is used to acquire and store the frequency control word corresponding to the memory frequency. The memory phase accumulator 211 is used to perform phase accumulation synchronously with the frequency synthesis circuit 30 based on the initial memory value, using the frequency control word corresponding to the memory frequency as the step size, and obtain the accumulated memory value. In one embodiment, the signal output module 40 includes a digital-to-analog converter 41 and a phase-locked loop (PLL) 42. The input terminal of the digital-to-analog converter 41 is connected to the output terminal of the phase / amplitude converter 32, and is used to convert the digital amplitude control signal output by the phase / amplitude converter 32 into an analog signal. The output terminal of the digital-to-analog converter 41 is connected to the PLL 42, and the PLL 42 is used to phase-lock the lower frequency analog signal output by the digital-to-analog converter 41 to obtain a higher frequency output signal. In one embodiment, the analog signal output by the signal output module 40 is a radio frequency (RF) signal. When the output signal is a low-frequency signal, the signal output module 40 may include a digital-to-analog converter 41 but not a phase-locked loop 42. The digital-to-analog converter 41 converts the digital amplitude control signal output by the phase / amplitude converter 32 into an analog signal.

[0056] like Figure 3 As shown, in one embodiment, the phase memory device further includes a human-machine interface module 50 and a clock setting unit 60. The setting frequency and / or phase memory command are input by the user through the human-machine interface module 50. In one embodiment, the phase memory command is generated based on the user's triggering of the phase memory function key, or based on the user's setting operation of a new setting frequency. The clock setting unit 60 is used to provide clock signals to the frequency synthesis circuit 30 and the phase memory unit 20.

[0057] Please refer to Figure 5 The diagram below shows the functional structure of a phase memory unit in one embodiment. In one embodiment, the phase memory unit 20 includes n memory sub-units 21, where n is a natural number greater than 1. Each memory sub-unit 21 is used to record a memory frequency point fm, where m ∈ [1, n]. Each memory sub-unit 21 is connected to a phase accumulator 31. The memory phase accumulator 211 of each memory sub-unit 21 shares the same operating clock (reference clock) with the phase accumulator 31. When the phase memory unit needs to store multiple memory frequencies (f1, f2, f3, ..., fm, ..., fn), they can be stored independently by the n memory sub-units 21.

[0058] Please refer to Figure 6The diagram below shows a structural block diagram of a processing device in one embodiment. In another embodiment, a signal processing device is disclosed for outputting a digital waveform signal. The digital waveform signal is an amplitude control signal generated based on a frequency control word and through phase accumulation. The processing device includes a phase memory unit 20 and a control module 10. The phase memory unit 20 is used to acquire an initial memory value and a frequency control word corresponding to the memorized frequency, and synchronizes the phase accumulation during the generation of the digital waveform signal with the frequency control word of the memorized frequency as a step size, based on the initial memory value, to obtain an accumulated memory value. The control module 10 is used to output the initial memory value and the frequency control word corresponding to the memorized frequency to the phase memory unit based on a phase memory instruction. When the processing device pre-outputs a new digital waveform signal, it determines whether the set frequency of the new digital waveform signal is the same as the memorized frequency in the phase memory unit. If so, the accumulated memory value in the phase memory unit is used as the initial value for phase accumulation during the generation of the digital waveform signal.

[0059] Please refer to Figure 7 This is a flowchart illustrating a signal phase memory method in one embodiment. This application also discloses a signal phase memory method, comprising:

[0060] Step 101: Obtain waveform parameters.

[0061] Obtain the user's settings for the required output waveform frequency and waveform type.

[0062] Step 102: Generate the frequency control word.

[0063] A frequency control word is generated based on a set frequency, so that the frequency synthesis circuit can output a waveform signal with the set frequency by phase accumulation based on the frequency control word.

[0064] Step 103: Perform phase memory.

[0065] The system monitors the user-input phase memory command and, based on the command, outputs the initial memory value and frequency control word corresponding to the frequency to be memorized to the phase memory unit. It then controls the phase memory unit to synchronously accumulate phase values ​​with the frequency control word corresponding to the frequency to be memorized, based on the initial memory value, and obtains the accumulated memory value. In one embodiment, the frequency to be memorized is the current set frequency when the control module receives the phase memory command, and the initial memory value is the phase accumulation value currently output by the phase accumulator when the control module receives the command, or the phase accumulation value currently output by the phase accumulator when the control module receives a new set frequency. In another embodiment, the frequency to be memorized includes the current set frequency and subsequent set frequencies when the control module receives the phase memory command, and the initial memory value is the phase accumulation value of the previous set frequency currently output by the phase accumulator each time a new set frequency is received, or the initial memory value is the phase accumulation value corresponding to the new set frequency currently output by the phase accumulator each time a new set frequency is received.

[0066] Step 104: Change the frequency control word.

[0067] The frequency control word is updated based on the new set frequency.

[0068] Step 105: Match frequency values.

[0069] The frequency control word corresponding to the new set frequency is matched with the frequency control word corresponding to the memorized frequency that has been stored in the phase memory unit.

[0070] Step 106, output signal.

[0071] If the match is successful, the accumulated memory value corresponding to the memorized frequency that matches the new set frequency is used as the initial value for the frequency synthesis circuit to perform phase accumulation based on the frequency control word, so as to output a waveform with the same phase as the memorized frequency. If the match is unsuccessful, the updated frequency control word is output to the frequency synthesis circuit, so that the frequency synthesis circuit can output a waveform signal with the new set frequency by phase accumulation based on the updated frequency control word.

[0072] The phase memory device disclosed in this application embodiment can be applied in spectrum analyzers and signal generators as a signal source.

[0073] To facilitate understanding of how the signal processing apparatus disclosed in this application implements the phase memory function, the following example uses the implementation of the phase memory function of an RF channel, specifically including:

[0074] Please refer to Figure 8This is a block diagram illustrating the functional implementation of the RF channel phase memory function in one embodiment. In one embodiment of this application, the RF channel transmitter adopts a hybrid frequency synthesizer architecture, including a phase memory unit 20, a frequency synthesis circuit 30, a signal output module 40, and an antenna 200. The phase memory unit 20 is housed in the FPGA module 100. A reference clock is output by a clock setting unit. The signal output module 40 includes a digital-to-analog converter 41 and a phase-locked loop (PLL) 42. The frequency synthesis circuit 30 includes a phase accumulator 31 and a phase-to-amplitude converter 32. The phase accumulator 31 acquires a frequency control word and performs phase accumulation according to the reference clock with the frequency control word as the step size, outputting the accumulated phase value. The phase-to-amplitude converter 32 outputs an amplitude-controlled DDS-CTRL signal (amplitude control signal) based on the accumulated phase value and a set waveform type. The signal output module 40 outputs an analog signal (RF signal) with a set frequency based on the amplitude control signal (DDS-CTRL signal). Phase accumulator 31 accumulates a frequency control word once per operating clock cycle (the FPGA module's operating clock, i.e., the reference clock), outputting a linearly increasing phase value. Phase / amplitude converter 32 is typically a lookup table that maps the phase value output by phase accumulator 31 to an amplitude value (e.g., a sampled value of a sine wave), and outputs a DDS-CTRL signal (essentially a digital sequence). The formula for obtaining the frequency value of the DDS-CTRL signal is:

[0075] f out = (X / 2 N ) * f clk ;

[0076] Where N is the bit width of the phase accumulator, X is the frequency control word, and f clk This is the operating clock frequency (reference clock frequency) of the FPGA module. The output frequency f can be changed with extremely fine precision by altering the frequency control word X. out .

[0077] A digital-to-analog converter (DAC) 41 receives the DDS-CTRL signal and converts it into a stepped analog waveform signal (DDS signal). The sampling frequency of the DAC 41 is controlled by a preset frequency DAC sampling clock. Since the DDS signal output by the DAC contains a large number of high-frequency harmonic components, in one embodiment, a low-pass filter (LPF) is also needed to filter the DDS signal to remove high-frequency noise and obtain an analog sine wave of the target frequency. The low-pass filtered DDS signal is used as the reference input signal for a phase-locked loop (PLL). The PLL 42 up-converts the DDS signal to the required radio frequency while cleaning the spectrum. In one embodiment, the PLL 42 includes a phase detector, a loop filter, a voltage-controlled oscillator (VCO), and a frequency divider. The phase detector compares the phase difference between the DDS signal (used as a reference signal) and the VCO signal of the feedback loop and outputs an error voltage. The loop filter filters out high-frequency components in the error voltage, generating a smooth DC control voltage. The design of the filter determines the locking speed, bandwidth, and noise performance of the PLL. The oscillation frequency of the voltage-controlled oscillator (VCO) is determined by the DC control voltage and is used to generate an RF signal at the target frequency. This RF signal is ultimately transmitted through antenna 200. The frequency divider divides the high-frequency signal generated by the VCO by N and then sends it back to the phase detector for comparison with the reference signal. When the phase-locked loop is locked, the frequency of the DDS signal and the loop lock frequency are:

[0078] f vco / N = f ref ;

[0079] Where N is the number of division stages in the frequency divider, f vco For the loop-locked frequency, f ref The frequency of the DDS signal.

[0080] The final output frequency is:

[0081] f rf = f vco = N * f ref ;

[0082] Among them, f ref f is the frequency of the low-frequency DDS signal. rf This refers to the frequency of the RF signal.

[0083] By changing the N-division ratio, the output frequency can be varied over a wide range. The frequency control word of the DDS can be fine-tuned to change the f-value of the DDS signal. ref It allows for fine-tuning of the frequency within the frequency band corresponding to each N value.

[0084] In one embodiment, the phase memory unit 20 in the FPGA module 100 includes at least one memory sub-unit 21, each phase memory unit 20 being used to record a memory frequency point fm of an RF signal. The memory sub-unit 21 includes a memory phase accumulator 211 and a control word memory 212. The memory phase accumulator 211 is used to synchronize the phase accumulator 31 when performing the phase memory function. The synchronized phase accumulator 31 includes:

[0085] After the phase memory function is enabled, the memory phase accumulator 211 inherits the phase accumulation value of the phase accumulator 31 and accumulates the phase accumulation value in each working clock cycle (the working clock of the FPGA module). Each accumulated value is related to the frequency control word of the pre-memorized memory frequency point fm. The control word memory 212 is used to store the frequency control word FTW of the phase / amplitude converter 32 when the phase memory function is enabled. fm Among them, the phase / amplitude converter 32 is based on the frequency control word FTW fm Output the DDS-CTRL signal to control the frequency of the RF signal output from the RF channel, i.e., the frequency of the RF signal output by the phase-locked loop 42 and the frequency control word FTW. fm Related.

[0086] When the RF channel output needs to be switched back to the memory frequency point f m When the RF signal is received (i.e., when the phase recovery function is executed), the phase accumulator 31 synchronizes with the memory phase accumulator 211. The synchronized memory phase accumulator 211 includes:

[0087] Phase accumulator 31 inherits the phase accumulation value from memory phase accumulator 211 and accumulates the phase accumulation value in each working clock cycle (the working clock of the FPGA module), then outputs the accumulated phase accumulation value to phase / amplitude converter 32. Phase / amplitude converter 32 retrieves the frequency control word FTW from control word memory 212. fm and reset the frequency control word FTW of the phase / amplitude converter 32 to the frequency control word FTW. fm When the reset is successful, the DDS-CTRL signal is output. Since the phase accumulator 31 synchronizes with the memory phase accumulator 211 to be updated during the phase recovery function, the phase state of the RF signal will be consistent with that when the phase memory function is enabled, thus realizing the phase memory function.

[0088] Please refer to Figure 9 This is a flowchart illustrating a phase memory method for an RF channel in one embodiment, including:

[0089] Step 201: Configure the RF channel output signal.

[0090] The RF channel is enabled and operating normally, outputting a variable-frequency RF signal. The FPGA module generates a variable-frequency amplitude control signal (DDS-CTRL signal). The phase accumulator accumulates one frequency control word per clock cycle and outputs it to the phase-to-amplitude converter. The phase-to-amplitude converter obtains the DDS-CTRL signal based on the accumulated value from the phase accumulator. The DDS-CTRL signal controls the digital-to-analog converter to output a lower-frequency analog signal (DDS signal). This DDS signal is then input to a phase-locked loop (PLL) to obtain a higher-frequency RF signal. By changing the frequency control word and the N division ratio in the PLL, an RF signal of arbitrary frequency can be output.

[0091] Step 202: Monitor the phase memory command.

[0092] The system monitors the user-input phase memory command and, based on this command, outputs the initial memory value and frequency control word corresponding to the frequency to be memorized to the phase memory unit. It then controls the phase memory unit to synchronously accumulate phase values ​​with the frequency control word corresponding to the frequency to be memorized, based on the initial memory value, and obtains the accumulated memory value. When executing the phase memory function, it needs to be implemented at a specific memory frequency f1. First, it must ensure that the RF channel outputs an RF signal corresponding to the memory frequency f1. Then, in response to the phase memory execution command, it uses the current phase / amplitude converter's frequency control word FTW. fm Latched to the control word memory. The phase / amplitude converter operates according to the frequency control word FTW. fm Output the DDS-CTRL signal to control the frequency of the RF signal output from the RF channel, i.e., the frequency of the RF signal output by the phase-locked loop (PLL) and the frequency control word FTW. fm Related. Additionally, a synchronous memory phase accumulator and a phase accumulator will be established, so that the phase accumulation value of the phase accumulator is inherited by the memory phase accumulator, and the phase accumulation value will be accumulated in each working clock cycle. Each accumulated value is related to the frequency control word of the pre-memorized memory frequency point fm.

[0093] Step 203: Change the output RF signal.

[0094] The RF channel changes the frequency of the currently output RF signal according to the channel signal frequency change command.

[0095] Step 204: Determine the frequency control word.

[0096] When performing a frequency change on the RF channel, if the phase memory unit stores a memory frequency point fm, it retrieves the frequency control word of the RF signal to be changed and compares it one by one with all the memory frequency points fm stored in the phase memory unit. If the memory frequency point fm does not contain the frequency control word of the RF signal to be changed, step 205 is executed, and the frequency of the RF signal output by the RF channel is directly changed. If the frequency control word of the RF signal to be changed is stored in the phase memory unit, then step 206 is executed.

[0097] Step 205, direct frequency conversion output.

[0098] When the frequency change of the RF channel is performed for the first time, if the phase memory unit has not yet saved any memory frequency point fm, or has only recorded the memory frequency point f1 before the current change, the frequency of the RF signal output by the RF channel is changed directly. Specifically, the frequency of the output RF signal can be changed by changing the frequency control word or the N division ratio in the phase lock.

[0099] Step 206: Inherit the accumulated value.

[0100] If the frequency control word of the RF signal to be modified is stored in the phase memory unit, then the RF signal corresponding to the memory frequency point fm of the frequency control word needs to be restored, i.e., the phase recovery execution instruction is executed. The phase accumulator and the memory phase accumulator are synchronized to inherit the accumulated value of the frequency control word in the memory phase accumulator. After synchronization, the phase accumulation value is accumulated in each working clock cycle, and the accumulated phase accumulation value is output to the phase / amplitude converter. Additionally, in response to the phase recovery execution instruction, the frequency control word FTW latched in the control word memory is retrieved. fm .

[0101] Step 207: Output the memorized RF signal.

[0102] Reset the frequency control word FTW of the phase / amplitude converter to the frequency control word FTW. fm When the reset is successful, a digital waveform signal is output to restore the frequency of the RF signal output by the RF channel to the frequency corresponding to the memory frequency point fm. Since the memory phase accumulator in the memory sub-unit is constantly updated, the phase state of the RF signal will also be consistent with that before the frequency change, thus realizing the phase memory function of the RF channel transmitter. Because the channel phase accumulator is synchronized dynamically in the memory sub-unit, it is ensured that the recovered RF signal phase state is consistent with that before the frequency change.

[0103] In one embodiment, when performing the phase memory function, a phase memory start command and a phase memory end command are sequentially acquired and executed. When acquiring the phase memory start command, the phase memory unit saves the phase of each frequency change according to the order of frequency control word changes and / or the frequency value change pattern (magnitude pattern, equal frequency interval pattern, etc.). When acquiring the phase memory end command, the phase memory function is stopped, and no new phases are saved. Please refer to [reference needed]. Figure 10 This is a flowchart illustrating the RF channel phase memory process in one embodiment, specifically including:

[0104] Step 301: Monitor the phase memory start command.

[0105] When the phase memory start command is received, the memory function of the phase memory unit is activated.

[0106] Step 302: Activate automatic memory mode.

[0107] When the frequency to be memorized is the current set frequency when the control module receives the phase memory command, the initial memory value is the phase accumulation value currently output by the phase accumulator when the control module receives the phase memory command, or the phase accumulation value currently output by the phase accumulator when the control module receives a new set frequency. When the frequency to be memorized includes the current set frequency and subsequent set frequencies when the control module receives the phase memory command, the initial memory value is the phase accumulation value of the previous set frequency currently output by the phase accumulator each time a new set frequency is received, or the initial memory value is the phase accumulation value corresponding to the new set frequency currently output by the phase accumulator each time a new set frequency is received. That is, after obtaining the phase memory start command, the phase of each frequency change is saved according to the order of frequency control word changes and / or the frequency value change pattern. In one embodiment, during the time period between executing the phase memory start command and the phase memory end command, the phase memory unit only records the phase signal of the frequency change.

[0108] Step 303: Obtain the phase memory end command.

[0109] The phase memory unit's memory function is disabled, and the phase memory function is not executed when the output signal frequency of the RF channel changes.

[0110] Step 304, repetition frequency change process.

[0111] It acquires and responds to phase recovery commands, and sequentially recovers the frequency and phase transformation process of the channel output RF signal according to the order of phase storage in the phase memory unit and / or the frequency value change pattern during the execution of the phase memory start command and phase memory end command, thereby realizing the dynamic reproduction of the frequency change process of the channel output signal.

[0112] The signal processing apparatus disclosed in this application embodiment is used to generate digital waveform signals based on a frequency control word and through phase accumulation. It includes a phase memory unit and a control module. The phase memory unit is used to acquire an initial memory value and a frequency control word corresponding to the memorized frequency, and synchronizes the phase accumulation during digital waveform signal generation with the frequency control word of the memorized frequency as a step size based on the initial memory value to acquire an accumulated memory value. The control module is used to output the initial memory value and the frequency control word corresponding to the memorized frequency to the phase memory unit, and when the set frequency of the signal pre-output signal of the signal processing device is the memorized frequency in the phase memory unit, it uses the synchronized accumulated memory value as the initial value for phase accumulation during digital waveform signal generation. Because the accumulated memory value is stored using a dynamic synchronous phase accumulation method, the phase memory function can be realized when the signal frequency is recovered.

[0113] Those skilled in the art will understand that, in the above embodiments, some or all of the frequency synthesis circuit, phase memory unit, and control module can be integrated into one or more integrated circuit chips, or can be implemented in a discrete device manner, either partially or entirely.

[0114] Those skilled in the art will understand that all or part of the functions of the various methods in the above embodiments can be implemented by hardware or by computer programs. When all or part of the functions in the above embodiments are implemented by computer programs, the program can be stored in a computer-readable storage medium, which may include: read-only memory, random access memory, disk, optical disk, hard disk, etc., and the program is executed by a computer to achieve the above functions. For example, the program can be stored in the memory of a device, and when the program in the memory is executed by the processor, all or part of the above functions can be achieved. In addition, when all or part of the functions in the above embodiments are implemented by computer programs, the program can also be stored in a server, another computer, disk, optical disk, flash drive, or external hard drive, etc., and can be downloaded or copied to the memory of a local device, or the system of the local device can be updated. When the program in the memory is executed by the processor, all or part of the functions in the above embodiments can be achieved.

[0115] The above examples illustrate the present invention only to aid in understanding it and are not intended to limit the scope of the invention. Those skilled in the art can make various simple deductions, modifications, or substitutions based on the principles of this invention.

Claims

1. A phase memory device for a signal, characterized in that, include: A frequency synthesis circuit is used to output a digital waveform signal with a set frequency by phase accumulation based on a frequency control word; The phase memory unit is used to receive the initial memory value and frequency control word corresponding to the memory frequency, and to perform phase accumulation synchronously with the frequency synthesis circuit based on the initial memory value and the frequency control word corresponding to the memory frequency as the step size, and to obtain the accumulated memory value. The control module is used to acquire a set frequency and output a frequency control word according to the set frequency, and output the frequency control word to the frequency synthesis circuit; the control module is also used to output the initial memory value corresponding to the memory frequency and the frequency control word to the phase memory unit based on the phase memory instruction, and when a new set frequency is acquired, to determine whether the frequency control word corresponding to the new set frequency is the same as the frequency control word corresponding to the memory frequency in the phase memory unit. If they are the same, the current accumulated memory value corresponding to the memory frequency is output to the frequency synthesis circuit as the initial value for the phase accumulation of the frequency synthesis circuit; The frequency synthesis circuit includes a phase accumulator, a phase-to-amplitude converter, and a signal output module. The phase accumulator is used to acquire a frequency control word and perform phase accumulation with the frequency control word as the step size according to a preset reference clock, and outputs the phase accumulation value. The phase-to-amplitude converter is used to output an amplitude control signal according to the phase accumulation value and a set waveform type. The signal output module is used to output an analog signal with a set frequency according to the amplitude control signal. The phase memory unit is configured to include at least one memory sub-unit. Each memory sub-unit is connected to a phase accumulator and is used to receive an initial memory value and a frequency control word corresponding to the memory frequency from the phase accumulator. Based on the initial memory value, the phase is accumulated according to the clock beat with the frequency control word corresponding to the memory frequency as the step size to obtain the accumulated memory value. The control module is used to output the frequency control word to the phase accumulator, configure a corresponding memory sub-unit for at least one memorized frequency in the phase memory unit based on the phase memory instruction, output the initial memory value and frequency control word corresponding to the memorized frequency to the corresponding memory sub-unit, update the frequency control word output to the phase accumulator based on the new set frequency, determine whether the new frequency control word is the same as the frequency control word corresponding to the memorized frequency, if so, output the current accumulated memory value corresponding to the memorized frequency to the phase accumulator as the initial value for phase accumulation by the phase accumulator.

2. The phase memory device as described in claim 1, characterized in that, The frequency to be memorized is the current set frequency when the control module receives the phase memory command; the initial memory value is the phase accumulation value currently output by the phase accumulator when the control module receives the phase memory command, or the phase accumulation value currently output by the phase accumulator when the control module receives a new set frequency.

3. The phase memory device as described in claim 1, characterized in that, The frequency to be memorized is the current set frequency and subsequent set frequencies when the control module receives the phase memory command; the initial memory value is the phase accumulation value of the previous set frequency currently output by the phase accumulator each time a new set frequency is received, or the initial memory value is the phase accumulation value corresponding to the new set frequency currently output by the phase accumulator each time a new set frequency is received.

4. The phase memory device as described in claim 1, characterized in that, The memory subunit includes a memory phase accumulator and a control word memory; The memory phase accumulator and the control word memory are respectively connected to the phase accumulator. The control word memory is used to acquire and store the frequency control word corresponding to the memory frequency. The memory phase accumulator is used to perform phase accumulation synchronously with the frequency synthesis circuit based on the initial memory value and with the frequency control word corresponding to the memory frequency as the step size, and obtain the accumulated memory value.

5. The phase memory device as described in claim 1, characterized in that, The signal output module includes a digital-to-analog converter (DAC) and a phase-locked loop (PLL). The input terminal of the DAC is connected to the output terminal of the phase / amplitude converter (PAC) and is used to convert the digital amplitude control signal output by the PAC into an analog signal. The output terminal of the DAC is connected to the PLC, which is used to lock the lower frequency analog signal output by the DAC into a higher frequency output signal.

6. The phase memory device as described in claim 5, characterized in that, The analog signal output by the signal output module is a radio frequency signal.

7. The phase memory device as described in claim 1, characterized in that, It also includes a human-computer interaction module, through which the setting frequency and / or phase memory commands are input by the user.

8. The phase memory device as described in claim 7, characterized in that, The phase memory command is generated based on the user's triggering of the phase memory function key, or based on the user's setting operation of a new set frequency.

9. The phase memory device as described in claim 1, characterized in that, It also includes a clock setting unit, which provides clock signals to the frequency synthesis circuit and the phase memory unit.

10. A signal processing apparatus, characterized in that, Used to output digital waveform signals, which are generated based on a frequency control word and through phase accumulation, including: A phase memory unit is used to acquire the initial memory value and frequency control word corresponding to the memory frequency, and synchronize the phase accumulation when generating the digital waveform signal with the frequency control word of the memory frequency as the step size based on the initial memory value, and obtain the accumulated memory value. A frequency synthesis circuit includes a phase accumulator, a phase-to-amplitude converter, and a signal output module. The phase accumulator is used to acquire a frequency control word and perform phase accumulation with the frequency control word as the step size according to a preset reference clock, and outputs the phase accumulation value. The phase-to-amplitude converter is used to output an amplitude control signal according to the phase accumulation value and a set waveform type. The signal output module is used to output an analog signal with a set frequency according to the amplitude control signal. The phase memory unit is configured to include at least one memory sub-unit. Each memory sub-unit is connected to a phase accumulator and is used to receive an initial memory value and a frequency control word corresponding to the memory frequency from the phase accumulator. Based on the initial memory value, the phase is accumulated according to the clock beat with the frequency control word corresponding to the memory frequency as the step size to obtain the accumulated memory value. The control module is used to output the initial memory value and frequency control word corresponding to the memory frequency to the phase memory unit based on the phase memory instruction, and when the processing device pre-outputs the new digital waveform signal, it determines whether the set frequency of the new digital waveform signal is the same as the memory frequency in the phase memory unit. If so, the accumulated memory value in the phase memory unit is used as the initial value of phase accumulation when generating the digital waveform signal. The control module is used to output the frequency control word to the phase accumulator, configure a corresponding memory sub-unit for at least one memorized frequency in the phase memory unit based on the phase memory instruction, output the initial memory value and frequency control word corresponding to the memorized frequency to the corresponding memory sub-unit, update the frequency control word output to the phase accumulator based on the new set frequency, determine whether the new frequency control word is the same as the frequency control word corresponding to the memorized frequency, if so, output the current accumulated memory value corresponding to the memorized frequency to the phase accumulator as the initial value for phase accumulation by the phase accumulator.

11. A method for phase memory of a signal, characterized in that, include: Obtain the user's settings for the required output waveform frequency and waveform type; A frequency control word is generated based on a set frequency, and the frequency synthesis circuit outputs a waveform signal with a set frequency by phase accumulation based on the frequency control word. Monitor user-inputted phase memory commands; Based on the phase memory instruction, the initial memory value and frequency control word corresponding to the memory frequency are output to the phase memory unit, and the phase memory unit is controlled to perform phase accumulation synchronously with the frequency synthesis circuit based on the initial memory value and the frequency control word corresponding to the memory frequency as the step size, and the accumulated memory value is obtained. Update the frequency control word based on the new set frequency; The frequency control word corresponding to the new set frequency is matched with the frequency control word corresponding to the memorized frequency stored in the phase memory unit; If the match is successful, the accumulated memory value corresponding to the memory frequency that matches the new set frequency will be used as the initial value for the frequency synthesis circuit to perform phase accumulation based on the frequency control word. The frequency synthesis circuit will output a waveform that is in phase with the memory frequency. If the matching fails, the updated frequency control word is output to the frequency synthesis circuit. The frequency synthesis circuit outputs a waveform signal with a new set frequency based on the updated frequency control word by phase accumulation.

12. The method as described in claim 11, characterized in that, The frequency to be memorized is the current set frequency when the control module receives the phase memory command; the initial memorized value is the phase accumulation value currently output by the phase accumulator when the control module receives the phase memory command, or the phase accumulation value currently output by the phase accumulator when the control module receives a new set frequency.

13. The method as described in claim 11, characterized in that, The frequency to be memorized is the current set frequency and subsequent set frequencies when the control module receives the phase memory command; the initial memory value is the phase accumulation value of the previous set frequency currently output by the phase accumulator each time a new set frequency is received, or the initial memory value is the phase accumulation value of the phase accumulator currently output by the phase accumulator corresponding to the new set frequency each time a new set frequency is received.

14. A computer program product, characterized in that, It includes a computer program and / or instructions that, when executed by a processor, implement the phase memory method for the signal as described in any one of claims 11 to 13.

Images