Electromagnetic signal generation method, system, storage medium and product adapted to hardware

Abstract

This disclosure presents a method, system, storage medium, and product for generating electromagnetic signals adapted to hardware. The method includes: acquiring a signal event descriptor and synchronously invoking a hardware configuration file of the hardware implementation layer; based on the hardware configuration file, converting the signal parameters in the signal event descriptor, which are of floating-point data type and contain physical units, into a hardware control word in fixed-point integer format; encapsulating the hardware control word into a signal event descriptor frame according to a fixed length adapted by the hardware implementation layer; and invoking the hardware implementation layer to load the signal event descriptor frame to generate an electromagnetic signal. This method can significantly improve system portability and testability by decoupling signal generation logic from hardware control logic, facilitating adaptation to multiple hardware scenarios.

Description

Technical Field

[0001] This disclosure relates to the field of digital signal generation technology, and in particular to an electromagnetic signal generation method, system, storage medium, and product adapted to hardware. Background Technology

[0002] In the field of electromagnetic signal simulation and testing, signal generation systems are the core equipment for completing radar simulation, communication testing, and electromagnetic environment simulation. At present, most mainstream signal generation solutions adopt an architecture in which application software directly connects to hardware execution units. After generating signal parameters according to test requirements, the application software directly issues hardware driver instructions. The hardware module completes fixed-point conversion, timing control, and electromagnetic signal output according to the instructions. This mode relies on the direct hardware connection architecture to achieve rapid signal generation and has been widely used in conventional single hardware adaptation scenarios.

[0003] However, in traditional signal generation schemes, the application software and hardware are deeply bound and tightly coupled, making it impossible to separate the signal generation logic from the hardware control logic. When the system replaces hardware devices, the entire software code must be rebuilt, resulting in extremely poor portability. At the same time, the coupled architecture makes it difficult to separate module testing, making it difficult to troubleshoot single component failures, resulting in weak system testability and making it difficult to meet the flexible testing requirements of multiple scenarios and multiple hardware adaptations. Summary of the Invention

[0004] In view of this, the present disclosure provides an electromagnetic signal generation method, system, storage medium and product adapted to hardware, which can greatly improve system portability and testability by decoupling signal generation logic from hardware control logic, and facilitate adaptation to multiple hardware scenarios.

[0005] In a first aspect, embodiments of this disclosure provide an electromagnetic signal generation method adapted to hardware, employing the following technical solution: Obtain the signal event descriptor and synchronously call the hardware configuration file of the adapted hardware implementation layer; Based on the hardware configuration file, the signal parameters in the signal event descriptor, which use floating-point data type and have physical units, are converted into hardware control words in fixed-point integer format; The hardware control word is encapsulated into a signal event descriptor frame according to the fixed length adapted by the hardware implementation layer. The hardware implementation layer is invoked to load the signal event descriptor frame and generate an electromagnetic signal.

[0006] Optionally, the physical unit includes a time unit; the step of converting the signal parameters in the signal event descriptor, which are of floating-point data type and have physical units, into hardware control words of fixed-point integer format based on the hardware configuration file includes: When the signal event descriptor includes signal parameters with time units and using floating-point data types, the system clock frequency is extracted from the hardware configuration file. Based on the system clock frequency, the signal parameters are converted into hardware control words represented by clock ticks, wherein the clock ticks are the quantization units used when time-type signal parameters are represented in fixed-point integer format.

[0007] Optionally, the physical unit includes a frequency unit; the step of converting the signal parameters in the signal event descriptor, which are of floating-point data type and have physical units, into a hardware control word in fixed-point integer format based on the hardware configuration file includes: When the signal event descriptor includes signal parameters using floating-point data type and frequency unit, the system clock frequency and the bit width of the numerically controlled oscillator phase accumulator are extracted from the hardware configuration file. Based on the system clock frequency and the bit width of the phase accumulator of the numerically controlled oscillator, the signal parameters are converted into a hardware control word adapted to the numerically controlled oscillator, wherein the hardware control word adapted to the numerically controlled oscillator is a frequency control word in fixed-point integer format.

[0008] Optionally, the physical unit includes an amplitude unit; the step of converting the signal parameters in the signal event descriptor, which are of floating-point data type and have physical units, into a hardware control word in fixed-point integer format based on the hardware configuration file includes: When the signal event descriptor includes signal parameters using floating-point data type and amplitude unit, the full-scale dynamic range and bit width of the digital-to-analog converter are extracted from the hardware configuration file. Based on the full-scale dynamic range and bit width of the digital-to-analog converter (DAC), the signal parameters are converted into a hardware control word adapted to the DAC, wherein the hardware control word adapted to the DAC is a DAC code value in fixed-point integer format.

[0009] Optionally, encapsulating the hardware control word into a signal event descriptor frame according to the fixed length adapted by the hardware implementation layer includes: The discrete integer parameters without physical units in the signal event descriptor are encapsulated into a hardware control word; According to the fixed-length encapsulation, all hardware control words generated based on the signal event descriptor are encapsulated into a signal event descriptor frame.

[0010] Optionally, the signal event descriptor includes a group-level control descriptor and a service signal descriptor. The group-level control descriptor contains group-level control class signal parameters, and the service signal descriptor contains a set of service signal class signal parameters that are controlled and constrained by the group-level control class signal parameters. The fixed-point integer format hardware control word includes a group-level control class hardware control word and a service signal hardware control word. The signal event descriptor frame includes a group header frame and a member frame. Based on the hardware configuration file, the group-level control class signal parameters contained in the group-level control descriptor are converted into group-level control class hardware control words; The group-level control hardware control word is encapsulated into a group header frame according to the fixed length. Based on the hardware configuration file, the service signal class signal parameters contained in the service signal descriptor are converted into service signal class hardware control words; The service signal class hardware control word is encapsulated into a member frame according to the fixed length.

[0011] Optionally, the step of invoking the hardware implementation layer to load a signal event descriptor frame and generate an electromagnetic signal includes: The hardware implementation layer is invoked to parse the group-level management and control hardware control word from the group header frame, and to parse the service signal hardware control word from the member frame that has a management and control constraint relationship with the group header frame. Based on the group-level control hardware control word and the service signal hardware control word, corresponding electromagnetic signals are generated.

[0012] Secondly, this disclosure also provides an electromagnetic signal generation system adapted to hardware, the system including an application logic layer, a hardware abstraction layer and a hardware implementation layer; The application logic layer is used to obtain signal event descriptors and send the signal event descriptors to the hardware abstraction layer; The hardware abstraction layer is used to convert the signal parameters in the signal event descriptor, which are of floating-point data type and have physical units, into hardware control words in fixed-point integer format based on the adapted hardware configuration file. The hardware control word is encapsulated into a signal event descriptor frame according to the fixed length adapted by the hardware implementation layer. The hardware implementation layer is used to load signal event descriptor frames and generate electromagnetic signals based on the signal event descriptor frames.

[0013] Thirdly, this disclosure also provides a computer device, which adopts the following technical solution: The computer device includes: At least one processor; and, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, which, when executed, enable the at least one processor to perform the electromagnetic signal generation method for any of the above-described adaptive hardware.

[0014] Fourthly, embodiments of this disclosure also provide a computer-readable storage medium storing computer instructions for causing a computer to execute the electromagnetic signal generation method adapted to any of the above-described hardware.

[0015] Fifthly, embodiments of this disclosure also provide a computer program product, including a computer program / instructions that, when executed by a processor, implement the steps of any of the methods described above.

[0016] The electromagnetic signal generation method for hardware adaptation provided in this disclosure decouples signal generation logic from hardware control logic by introducing independent signal event descriptors and hardware configuration files adapted to the current hardware implementation layer. This fundamentally breaks the deep binding relationship between application software and hardware in traditional solutions. The signal event descriptors uniformly carry the upper-layer signal logic, while the hardware configuration files separately encapsulate the adaptation rules of the hardware implementation layer. Their collaborative operation eliminates the dependence on specific hardware interfaces for operations such as signal parameter parsing and format conversion. When the system replaces hardware devices, only the corresponding hardware configuration file needs to be updated to complete the adaptation, without refactoring the entire software code, significantly improving the system's portability and hardware adaptability.

[0017] This solution adopts a layered processing and standardized encapsulation design approach. First, floating-point signal parameters with physical units are standardized into hardware control words in fixed-point integer format. Then, according to hardware implementation requirements, they are encapsulated into signal event descriptor frames in a unified format, achieving clear separation and independent operation of functional modules. The logic of each stage is independent and has clear boundaries, facilitating rapid location of faulty components when a single part malfunctions, reducing troubleshooting difficulty, improving system testability, and flexibly meeting signal generation and testing needs across multiple scenarios and hardware platforms.

[0018] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A flowchart illustrating the electromagnetic signal generation method for the hardware adapted to the embodiments of this disclosure; Figure 2 A schematic diagram of the structure of an electromagnetic signal generation system for adapting hardware provided in an embodiment of this disclosure; Figure 3 A flowchart illustrating a method for converting signal parameters with time units into fixed-point integer format, provided in an embodiment of this disclosure; Figure 4 A flowchart illustrating a method for converting signal parameters with frequency units into fixed-point integer format, provided in an embodiment of this disclosure; Figure 5 A flowchart illustrating a method for converting signal parameters with amplitude units into fixed-point integer format, provided in an embodiment of this disclosure; Figure 6 This is a flowchart illustrating the signal event descriptor frame acquisition method provided in this embodiment of the disclosure; Figure 7 A flowchart illustrating the method for generating header frames and member frames provided in this embodiment of the disclosure; Figure 8 A schematic flowchart of the electromagnetic signal generation method provided in the embodiments of this disclosure; Figure 9 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present disclosure. Detailed Implementation

[0021] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0022] It should be understood that the following specific examples illustrate the implementation of this disclosure, and those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. This disclosure can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this disclosure. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0023] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this disclosure, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0024] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this disclosure. The drawings only show the components related to this disclosure and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0025] Furthermore, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the described aspects can be practiced without these specific details.

[0026] Reference Figure 1 This disclosure provides a method for generating electromagnetic signals adapted to hardware, comprising the following steps: S1: Obtain the signal event descriptor and synchronously call the hardware configuration file of the hardware implementation layer; S2: Based on the hardware configuration file, convert the signal parameters in the signal event descriptor, which use floating-point data types and have physical units, into hardware control words in fixed-point integer format; S3: Encapsulate the hardware control word into a signal event descriptor frame according to the fixed length adapted by the hardware implementation layer; S4: Call the hardware implementation layer to load the signal event descriptor frame and generate an electromagnetic signal.

[0027] The electromagnetic signal generation method for hardware adaptation disclosed herein decouples signal generation logic from hardware control logic by introducing independent signal event descriptors and hardware configuration files adapted to the current hardware implementation layer. This fundamentally breaks the deep binding relationship between application software and hardware in traditional solutions. The signal event descriptors uniformly carry the upper-layer signal logic, while the hardware configuration files separately encapsulate the adaptation rules of the hardware implementation layer. Their collaborative operation eliminates the dependence on specific hardware interfaces for operations such as signal parameter parsing and format conversion. When the system replaces hardware devices, only the corresponding hardware configuration file needs to be updated to complete the adaptation, without refactoring the entire software code, significantly improving the system's portability and hardware adaptability.

[0028] This solution adopts a layered processing and standardized encapsulation design approach. First, floating-point signal parameters with physical units are standardized into hardware control words in fixed-point integer format. Then, according to hardware implementation requirements, they are encapsulated into signal event descriptor frames in a unified format, achieving clear separation and independent operation of functional modules. The logic of each stage is independent and has clear boundaries, facilitating rapid location of faulty components when a single part malfunctions, reducing troubleshooting difficulty, improving system testability, and flexibly meeting signal generation and testing needs across multiple scenarios and hardware platforms.

[0029] In S1, refer to Figure 2 The schematic diagram of the electromagnetic signal generation system adapted to the hardware demonstrates the following: When users need to quickly generate conventional electromagnetic signals for easy control, they select the signal source mode. In this mode, the application logic layer extracts signal event descriptors from the parameterized description input by the user. When users need to recreate complex electromagnetic environments for high-fidelity scene simulation, they select the scene-driven mode. In this mode, the application logic layer standardizes the scene scenario description input by the user, generates a scene scenario file, and then extracts signal event descriptors from the scene scenario file. The signal event descriptor is a structured data unit that describes signal events using standard floating-point data types and discrete integer data. It includes floating-point parameters with physical units and discrete integer parameters without physical units, but does not contain any hardware-specific parameters. This descriptor serves as a unified output format for the upper-layer application software, representing the physical truth value of the signal and the application scenario, thus decoupling the signal description from the hardware implementation.

[0030] The application logic layer sends all acquired signal event descriptors to the hardware abstraction layer (HAL). Triggered by the signal generation task, the core conversion engine within the HAL calls the hardware profile adapted to the hardware implementation layer. The hardware profile is a configuration data structure containing all key implementation parameters of the target hardware platform, including at least the system clock frequency, the bit width of the numerically controlled oscillator (CO) phase accumulator, the full-scale dynamic range of the digital-to-analog converter (DAC), and the bit width of the DAC, etc., which are used for parameter quantization calculations. This file is customized for different hardware platforms, providing a unified basis for the conversion of floating-point signal parameters to fixed-point integer format hardware control words. In addition, the hardware profile can also include the number of phases for multi-phase parallel processing of the FPGA (Field Programmable Gate Array). This parameter is used for hardware-level parallel timing control, that is, controlling the parallel output timing of the multi-phase DAC and the numerically controlled oscillator.

[0031] In S2, fixed-point integer format is a digital representation method where the decimal point is fixed after the least significant bit and stored and operated on in integer form. Its value is a physical quantity with fixed dimensions and resolution. This format has high operation efficiency, low hardware resource consumption, stable timing convergence, and does not require complex floating-point arithmetic units, making it more suitable for real-time processing and high-speed implementation at the hardware implementation layer. However, existing application logic layers usually use floating-point format for signal description and operation, which requires the hardware implementation layer to perform real-time conversion from floating-point to fixed-point integer format, consuming a lot of hardware computing power and processing time. This solution, however, converts floating-point signal parameters into fixed-point integer format hardware control words in advance according to hardware adaptation requirements before the hardware implementation layer. This allows the hardware implementation layer to directly use the converted control words to perform signal generation, significantly reducing hardware operation overhead and improving real-time performance and processing efficiency.

[0032] Signal event descriptors use floating-point data types and carry signal parameters in physical units. These physical quantities are diverse, primarily including time, frequency, and amplitude. The core conversion engine of the hardware abstraction layer employs a corresponding fixed-point integer format conversion method for each physical quantity type. For signal parameters in time units, refer to... Figure 3 The flowchart illustrating the method for converting signal parameters with time units into fixed-point integer format, "based on hardware configuration files, converting signal parameters with floating-point data types and physical units in signal event descriptors into hardware control words in fixed-point integer format," includes the following steps: S21: When the signal event descriptor includes signal parameters with time units and using floating-point data types, extract the system clock frequency from the hardware configuration file. S22: Based on the system clock frequency, convert the signal parameters into hardware control words represented by clock ticks, where the clock ticks are the quantization units used when time-type signal parameters are represented in fixed-point integer format.

[0033] The formula for converting floating-point data type signal parameters with time units into hardware control words expressed in clock ticks is as follows: In the formula, Represents a hardware control word expressed in clock ticks; This indicates a signal parameter using floating-point data type and a time unit, typically a second, microsecond, etc. This indicates the system clock frequency, measured in Hertz (Hz). This represents the rounding function. Clock ticks are integer counts based on the system hardware clock's reference period, and are related to the system clock's frequency; essentially, they are integer counters. This formula maps continuous time, measured in seconds, to discrete ticks measured in hardware clock cycles, facilitating hardware timing according to clock cycles.

[0034] For signal parameters in frequency units, refer to Figure 4 The flowchart illustrating the method for converting signal parameters with frequency units into fixed-point integer format, "based on hardware configuration files, converting signal parameters with floating-point data types and physical units in signal event descriptors into hardware control words in fixed-point integer format," includes the following steps: S23: When the signal event descriptor includes signal parameters in floating-point data type with frequency units, extract the system clock frequency and the bit width of the numerically controlled oscillator phase accumulator from the hardware configuration file. S24: Based on the system clock frequency and the bit width of the phase accumulator of the numerically controlled oscillator, the signal parameters are converted into a hardware control word adapted to the numerically controlled oscillator, wherein the hardware control word adapted to the numerically controlled oscillator is a frequency control word in fixed-point integer format.

[0035] The formula for converting signal parameters using floating-point data type and frequency units into hardware control words adapted to the numerically controlled oscillator is as follows: In the formula, This refers to the hardware control word adapted to the numerically controlled oscillator, abbreviated as NCO's Frequency Tuning Word (FTW). This indicates a signal parameter using floating-point data type and a frequency unit, typically Hertz. This indicates the bit width (number of bits) of the phase accumulator of the numerically controlled oscillator (NCO). Frequency is the rate of change over time. In hardware, the NCO is used to oscillate a waveform at a specified frequency. This formula can convert the target frequency, which is in Hertz, into the NCO's frequency control word to meet the hardware's signal generation requirements.

[0036] For signal parameters in amplitude units, refer to Figure 5 The flowchart illustrating the method for converting signal parameters with amplitude units to fixed-point integer format, "based on hardware configuration files, converting signal parameters with floating-point data types and physical units in signal event descriptors into hardware control words in fixed-point integer format," includes the following steps: S25: When the signal event descriptor includes signal parameters with floating-point data type and amplitude unit, extract the full-scale dynamic range and bit width of the digital-to-analog converter from the hardware configuration file. S26: Based on the full-scale dynamic range and bit width of the digital-to-analog converter (DAC), the signal parameters are converted into hardware control words that adapt to the DAC, wherein the hardware control words that adapt to the DAC are DAC code values ​​in fixed-point integer format.

[0037] The formula for converting signal parameters using floating-point data type and amplitude units into the hardware control word of the compatible digital-to-analog converter is as follows: In the formula, This refers to the hardware control word that adapts to the digital-to-analog converter, and is simply called the DAC output codeword (dac_code). This indicates a signal parameter using floating-point data type and with an amplitude unit, typically in volts. Indicates the full-scale dynamic range of the digital-to-analog converter; This indicates the bit width of the digital-to-analog converter. The amplitude is the voltage magnitude. In hardware, the DAC converts digital code values ​​into analog voltages. This formula can normalize the signal amplitude, which is in volts, to the dynamic range of the DAC, and then map it to the DAC's output code value, so that the DAC outputs the corresponding voltage.

[0038] This method of converting floating-point data type signal parameters with physical units in signal event descriptors into fixed-point integer format hardware control words allows for hardware adaptation when the underlying hardware is replaced. Only the hardware configuration file needs to be updated and the conversion interface from floating-point parameters to fixed-point integer format in the hardware abstraction layer needs to be adapted. The definition and editing logic of floating-point signal parameters in all upper-layer application software do not need to be modified, thus achieving decoupling between the application logic layer and the hardware implementation layer.

[0039] In S3, refer to Figure 6 The flowchart illustrating the signal event descriptor frame acquisition method shows that "encapsulating the hardware control word into a signal event descriptor frame according to the fixed length adapted by the hardware implementation layer" includes the following steps: S31: Encapsulate discrete integer parameters without physical units in the signal event descriptor into a hardware control word; S32: Encapsulates all hardware control words generated based on the signal event descriptor into a signal event descriptor frame according to a fixed length.

[0040] In S31, the signal event descriptor contains not only signal parameters with physical units but also discrete integer parameters without physical units (i.e., integer format parameters, such as ID, version number, and count parameters). The bit width of the discrete integer parameters is adjusted for adaptation, either by padding with zeros (if the bit width is insufficient) or truncating the value (if the bit width exceeds the limit) according to the preset bit width requirements, before being encapsulated into a hardware control word. Additionally, the bit width of signal parameters with physical units is also adjusted before being encapsulated into a hardware control word to adapt to the hardware implementation layer.

[0041] In S32, based on a preset fixed length (128 bits or 256 bits, preferably 256 bits), the hardware control word converted from each signal event descriptor is encapsulated into a corresponding signal event descriptor frame. One signal event descriptor can generate one signal event descriptor frame. During the encapsulation process, natural boundary bit width alignment is performed on multi-word fields within the frame body. Multi-word fields refer to parameter fields that occupy more bits than a single word (8 bits) and span basic data units. During alignment, a preset natural boundary bit width of 32 bits / 64 bits is used, and trailing zeros are padded to make the actual bit width of the multi-word field as a multiple of the nearest 32 bits or 64 bits. This ensures that the field start address is aligned with the boundary bit width, avoids cross-boundary data splicing during hardware parsing, and improves parsing efficiency. Moreover, the alignment boundary is preferably 64 / 128 / 256 bits, which can match the target DMA bus width. The target DMA bus width is preferably ≥512 bits to allow DMA to fetch frames at once.

[0042] Optionally, when the user specifies forward compatibility or unknown frame error tolerance for the frame format, a first fixed-width (2B or 4B) prefix (length_prefix) can be configured at the beginning of the frame. The core function of this prefix is ​​to identify the total bit width / byte length of the frame, providing the hardware with a basis for frame boundary identification, format compatibility, and skipping unknown frames. When the underlying transmission link lacks a check function or the user cannot accept the current bit error rate, a second fixed-width (16b or 32b) CRC check bit is reserved at the end of the frame. Based on the original data of the frame body (including the prefix and aligned parameter fields), a unique CRC value is calculated using the standard CRC algorithm and written to the check bit. The CRC check bit is a physical storage unit used to store the CRC value, and the CRC value is the characteristic check code of the frame data. The two work together to realize bit error detection in data transmission. When the hardware parses the data, it recalculates the CRC value of the frame data and compares it with the value in the check bit to determine whether the frame data has been corrupted during transmission. The prefix, the aligned multi-word field, and the cumulative bit width of the CRC check bit are consistent with the preset fixed length.

[0043] The signal event descriptor includes group-level control descriptors and service signal descriptors. Group-level control descriptors contain group-level control-type signal parameters, while service signal descriptors contain a set of service signal parameters constrained by the group-level control-type signal parameters. Fixed-point integer format hardware control words include group-level control-type hardware control words and service signal-type hardware control words. Signal event descriptor frames include group header frames and member frames. Group-level control-type signal parameters are control parameters such as timing scheduling, resource allocation, and mode configuration, while service signal parameters are service parameters that actually carry information and characterize the physical features of the signal. These two types of parameters together constitute the complete parameter set of a signal event. This distinction between control and service classes not only facilitates the upper-level application logic layer in focusing on the design and editing of signal service scenarios but also allows the hardware implementation layer to focus on efficiently executing control instructions. This further decouples the application logic layer from the hardware implementation layer, improving the system's portability, maintainability, and scalability.

[0044] Reference Figure 7 The flowchart illustrating the method for generating group header frames and member frames shows that the method for obtaining group header frames and member frames based on group-level control descriptors and service signal descriptors includes the following steps: S33: Based on the hardware configuration file, convert the group-level control class signal parameters contained in the group-level control descriptor into group-level control class hardware control words; S34: Encapsulate the group-level control class hardware control word into a group header frame according to a fixed length; S35: Based on the hardware configuration file, convert the signal parameters of the service signal class contained in the service signal descriptor into the service signal class hardware control word; S36: Encapsulate the hardware control word of the service signal class into a member frame according to a fixed length.

[0045] The method principle of encapsulating hardware control words in steps S33-S36 is the same as that of steps S2 and S31-S32. The only difference here is that the hardware control words and signal event descriptor frames are distinguished based on the two types of control and service.

[0046] In S4, refer to Figure 8 The flowchart illustrating the electromagnetic signal generation method shows the steps involved in "calling the hardware implementation layer to load the signal event descriptor frame and generate the electromagnetic signal": S41: Call the hardware implementation layer to parse the group-level control class hardware control word from the group header frame, and parse the service signal class hardware control word from the member frame that has a control constraint relationship with the group header frame; S42: Generate corresponding electromagnetic signals based on group-level control hardware control words and service signal hardware control words.

[0047] Among them, the group-level control hardware control word includes at least one of the following: group unique identifier (group_id), group start absolute time (timestamp), number of members in the group (member_count), number of loop playbacks (loop_count), interval time of each loop (loop_interval), target transmission channel identifier (target_tx_channel_id), and target pipeline identifier (target_pipeline_id). The group's unique identifier is used to clarify the group's usage nature, distinguishing between one-time dynamic groups (temporary groups for one-time use) and named manageable groups (persistent groups for long-term use), adapting to different signal generation scenario requirements; the group's absolute start time is used for precise timing synchronization, ensuring that each signal event is accurately triggered and output collaboratively at the specified time point; the number of members in the group indicates the number of associated business signal type hardware control words; the number of loop playbacks is used to support finite or infinite loops; the interval between each loop is used to define the loop period; the hardware used to perform signal generation tasks within the hardware implementation layer is the signal generation hardware, which consists of components such as FPGA, DSP (Digital Signal Processor), and ASIC (Application-Specific Integrated Circuit). It includes multiple transmission channels for simulating the complete link model from signal generation and processing at the source to final radiation through the antenna. The target transmission channel identifier is used to specify on which physical transmission channel the group should output; the target pipeline identifier is used to specify which specific signal processing pipeline should perform the generation task within the specified target transmission channel.

[0048] The hardware control word for service signals includes basic parameters and signal generation type-specific parameters. The basic parameters belong to the base class and include at least one of the member relative offset (timestamp_offset) and signal generation type (signal_type). The signal generation type-specific parameters belong to the derived class and include service field parameters corresponding to the signal generation type, such as pulse modulation service fields, digital modulation service fields, analog modulation service fields, echo modulation service fields, arbitrary wave modulation service fields, etc. The member relative offset is used in group mode to multiplex the relative time offset relative to the start time of the group. There can be more than one signal generation type, used to instruct the hardware implementation layer how to interpret subsequent service fields. The signal generation type-specific parameters immediately follow the basic parameters. When signal_type is pulse modulation (PulseMod), it is followed by pulse service fields describing parameters such as pulse width and sweep bandwidth. When signal_type is digital modulation (DigitalMod), it is followed by digital modulation service fields describing parameters such as modulation type (QPSK, 64QAM, etc.) and code rate. Other signal types follow the same pattern. This design allows developers to define a new `signal_type` enumeration value and corresponding business field structure when a new signal type needs to be supported in the future, without modifying the core hardware parsing framework. The hardware parsing logic is generic: it first reads `SED_Base`, then calls the corresponding processing module to parse the subsequent business fields based on the `signal_type` value, thus achieving high scalability.

[0049] After the signal generation hardware parses the group-level control hardware control words and the business signal control words with control constraints, it first determines the group type and execution rules based on the group's unique identifier. If the group's unique identifier is 0, it is marked as a one-time dynamic group and included in the scheduling queue according to the frame arrival order. At the same time, the physical transmission channel is specified according to the target transmission channel identifier, and the signal processing pipeline within the channel is selected according to the target pipeline identifier, completing resource pre-configuration. If the group's unique identifier is not 0, it is marked as a named manageable group. The group header information is first registered in the hardware's internal "group directory," supporting subsequent referencing and playback using the same group's unique identifier (reusing members at the boundary without repeated distribution), in-situ updates (replacing group content seamlessly at loop boundaries to achieve continuous scene updates), and cross-channel route pre-configuration (using the routing field in the group header to directly complete pipeline / channel selection without packet splitting). The process involves several steps, including precisely selecting the transmission channel and processing pipeline via routing fields, identifying the signal type based on the signal generation type, interpreting subsequent parameters according to the corresponding parsing rules, and configuring the basic signal generation logic in the designated signal processing pipeline by combining general physical parameters such as frequency, duration, and amplitude. Finally, using the local synchronous clock as a reference, the hardware initiates the signal generation process of the corresponding physical transmission channel and processing pipeline at the calculated signal trigger time. It performs basic signal synthesis, modulation, and other processing according to preset signal parameters, and outputs the signal sequentially to the designated transmission channel, forming an electromagnetic signal that meets simulation requirements. One-time dynamic groups directly reclaim their group parameters after completing the last loop, while named and manageable groups retain their group header information in the "group directory," supporting subsequent referencing, updates, or routing adjustments as needed, enabling flexible adaptation and continuous updates for complex electromagnetic scenarios. The formula for calculating the signal trigger time is as follows: t_abs=timestamp+k×loop_interval+timestamp_offset; In the formula, t_abs is the signal trigger time, which is also the absolute time of the member; k is the current loop count, the initial value of k is 0, and k≤loop_count-1.

[0050] This solution, by introducing hardware-independent raw signal event descriptors, not only improves system portability and testability, supporting unit and regression testing independent of hardware, but also serves as a persistent archive of simulation truth values, forming the gold standard for cross-platform verification. Simultaneously, through a clear division of responsibilities, application developers can focus on signal modeling, while hardware developers can focus on hardware implementation. The two interact through a clear boundary—the hardware abstraction layer. Upper-layer software development and hardware selection and implementation can be carried out in complete parallel; changes to one do not affect the other. This achieves complete decoupling between the application logic layer and the hardware implementation layer, significantly improving development efficiency and system stability.

[0051] Reference Figure 2 This disclosure provides an electromagnetic signal generation system adapted to hardware, the system including an application logic layer 1, a hardware abstraction layer 2 and a hardware implementation layer 3; Application logic layer 1 is used to obtain signal event descriptors and send the signal event descriptors to hardware abstraction layer 2; Hardware Abstraction Layer 2 is used to convert signal parameters in signal event descriptors, which use floating-point data types and have physical units, into hardware control words in fixed-point integer format based on the adapted hardware configuration file. The hardware control word is encapsulated into a signal event descriptor frame according to the fixed length adapted by the hardware implementation layer. Hardware implementation layer 3 is used to load signal event descriptor frames and generate electromagnetic signals based on the signal event descriptor frames.

[0052] Furthermore, the hardware abstraction layer 2 includes a core conversion engine 21, and the hardware implementation layer 3 includes signal generation hardware 31; The core conversion engine 21 is used to synchronously call the hardware configuration file adapted to the hardware implementation layer 3; Based on the hardware configuration file, the signal parameters in the signal event descriptor, which use floating-point data types and have physical units, are converted into hardware control words in fixed-point integer format. According to the fixed length adapted by the hardware implementation layer, the hardware control word is encapsulated into a signal event descriptor frame, and the signal event descriptor frame is sent to the signal generation hardware 31. Signal generation hardware 31 is used to receive signal event descriptor frames and generate electromagnetic signals based on the signal event descriptor frames.

[0053] The various variations and specific examples of the electromagnetic signal generation method for the adapted hardware provided above are also applicable to the electromagnetic signal generation system for the adapted hardware provided in this disclosure. Through the foregoing detailed description of the electromagnetic signal generation method for the adapted hardware, those skilled in the art can clearly understand the implementation method of the electromagnetic signal generation system for the adapted hardware. For the sake of brevity, it will not be described in detail here.

[0054] A computer device according to embodiments of the present disclosure includes a memory and a processor. The memory is used to store non-transitory computer-readable instructions. Specifically, the memory may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may, for example, include random access memory (RAM) and / or cache memory. The non-volatile memory may, for example, include read-only memory (ROM), hard disk, flash memory, etc.

[0055] The processor may be a central processing unit (CPU) or other form of processing unit with data processing capabilities and / or instruction execution capabilities, and may control other components in the computer device to perform desired functions. In one embodiment of this disclosure, the processor is used to execute computer-readable instructions stored in the memory, causing the computer device to perform all or part of the steps of the electromagnetic signal generation method for the adapted hardware of the foregoing embodiments of this disclosure.

[0056] Those skilled in the art will understand that, in order to solve the technical problem of how to achieve a good user experience, this embodiment may also include well-known structures such as communication buses and interfaces, and these well-known structures should also be included within the protection scope of this disclosure.

[0057] like Figure 9 This is a schematic diagram of a computer device provided for an embodiment of the present disclosure. It illustrates a structural schematic diagram suitable for implementing the computer device in the embodiments of the present disclosure. Figure 9 The computer device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0058] like Figure 9 As shown, a computer device may include a processor (such as a central processing unit, graphics processing unit, etc.), which can perform various appropriate actions and processes based on programs stored in read-only memory (ROM) or programs loaded from storage devices into random access memory (RAM). The RAM also stores various programs and data required for the operation of the computer device. The processor, ROM, and RAM are interconnected via a bus. Input / output (I / O) interfaces are also connected to the bus.

[0059] Typically, the following devices can be connected to the I / O interface: input devices, such as sensors or visual information acquisition devices; output devices, such as displays; storage devices, such as magnetic tapes or hard drives; and communication devices. Communication devices allow the computer device to communicate wirelessly or wiredly with other devices (such as edge computing devices) to exchange data. Although Figure 9 A computer apparatus with various devices is shown, but it should be understood that it is not required to implement or have all of the devices shown. More or fewer devices may be implemented or included alternatively.

[0060] In particular, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from a storage device, or installed from a ROM. When the computer program is executed by a processor, all or part of the steps of the electromagnetic signal generation method adapted to the hardware of embodiments of this disclosure are performed.

[0061] For a detailed description of this embodiment, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0062] A computer-readable storage medium according to embodiments of the present disclosure stores non-transitory computer-readable instructions. When these non-transitory computer-readable instructions are executed by a processor, all or part of the steps of the electromagnetic signal generation method for the adapted hardware of the foregoing embodiments of the present disclosure are performed.

[0063] The aforementioned computer-readable storage media include, but are not limited to: optical storage media (e.g., CD-ROM and DVD), magneto-optical storage media (e.g., MO), magnetic storage media (e.g., magnetic tape or portable hard drive), media with built-in rewritable non-volatile memory (e.g., memory card), and media with built-in ROM (e.g., ROM cartridge).

[0064] For a detailed description of this embodiment, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0065] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0066] In this disclosure, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. The block diagrams of devices, apparatuses, devices, and systems involved in this disclosure are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as "comprising," "including," "having," etc., are open-ended terms meaning "including but not limited to," and are used interchangeably with them. The terms "or" and "and" as used herein refer to the terms "and / or," and are used interchangeably with them unless the context clearly indicates otherwise. The term "such as" as used herein refers to the phrase "such as but not limited to," and is used interchangeably with it.

[0067] Additionally, as used herein, the "or" used in a list of items beginning with "at least one" indicates a separate list, such that a list of, for example, "at least one of A, B, or C" means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). Furthermore, the word "exemplary" does not imply that the described example is preferred or better than other examples.

[0068] It should also be noted that in the systems and methods of this disclosure, the components or steps can be decomposed and / or recombined. These decompositions and / or recombinations should be considered as equivalent solutions to this disclosure.

[0069] Various changes, substitutions, and modifications can be made to the technology described herein without departing from the teachings defined by the appended claims. Furthermore, the scope of the claims of this disclosure is not limited to the specific aspects of the processes, machines, manufactures, events, means, methods, and actions described above. Currently existing or later-developed processes, machines, manufactures, events, means, methods, or actions that perform substantially the same function or achieve substantially the same result as the corresponding aspects described herein can be utilized. Therefore, the appended claims include such processes, machines, manufactures, events, means, methods, or actions within their scope.

[0070] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.

[0071] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations therein.

Claims

1. A method for generating electromagnetic signals adapted to hardware, characterized in that, include: Obtain the signal event descriptor and synchronously call the hardware configuration file of the adapted hardware implementation layer; Based on the hardware configuration file, the signal parameters in the signal event descriptor, which use floating-point data type and have physical units, are converted into hardware control words in fixed-point integer format; The hardware control word is encapsulated into a signal event descriptor frame according to the fixed length adapted by the hardware implementation layer. The hardware implementation layer is invoked to load the signal event descriptor frame and generate an electromagnetic signal.

2. The electromagnetic signal generation method for adapting hardware according to claim 1, characterized in that, The physical unit includes a time unit; the step of converting the signal parameters in the signal event descriptor, which are of floating-point data type and have physical units, into a hardware control word in fixed-point integer format based on the hardware configuration file includes: When the signal event descriptor includes signal parameters with time units and using floating-point data types, the system clock frequency is extracted from the hardware configuration file. Based on the system clock frequency, the signal parameters are converted into hardware control words represented by clock ticks, wherein the clock ticks are the quantization units used when time-type signal parameters are represented in fixed-point integer format.

3. The electromagnetic signal generation method for adapting hardware according to claim 1, characterized in that, The physical unit includes a frequency unit; the step of converting the signal parameters in the signal event descriptor, which are of floating-point data type and have physical units, into a hardware control word in fixed-point integer format based on the hardware configuration file includes: When the signal event descriptor includes signal parameters using floating-point data type and frequency unit, the system clock frequency and the bit width of the numerically controlled oscillator phase accumulator are extracted from the hardware configuration file. Based on the system clock frequency and the bit width of the phase accumulator of the numerically controlled oscillator, the signal parameters are converted into a hardware control word adapted to the numerically controlled oscillator, wherein the hardware control word adapted to the numerically controlled oscillator is a frequency control word in fixed-point integer format.

4. The electromagnetic signal generation method for adapting hardware according to claim 1, characterized in that, The physical unit includes an amplitude unit; the step of converting the signal parameters in the signal event descriptor, which are of floating-point data type and have physical units, into a hardware control word in fixed-point integer format based on the hardware configuration file includes: When the signal event descriptor includes signal parameters using floating-point data type and amplitude unit, the full-scale dynamic range and bit width of the digital-to-analog converter are extracted from the hardware configuration file. Based on the full-scale dynamic range and bit width of the digital-to-analog converter (DAC), the signal parameters are converted into a hardware control word adapted to the DAC, wherein the hardware control word adapted to the DAC is a DAC code value in fixed-point integer format.

5. The electromagnetic signal generation method for adapting hardware according to claim 1, characterized in that, The step of encapsulating the hardware control word into a signal event descriptor frame according to the fixed length adapted by the hardware implementation layer includes: The discrete integer parameters without physical units in the signal event descriptor are encapsulated into a hardware control word; According to the fixed-length encapsulation, all hardware control words generated based on the signal event descriptor are encapsulated into a signal event descriptor frame.

6. The electromagnetic signal generation method for adapting hardware according to claim 5, characterized in that, The signal event descriptor includes a group-level control descriptor and a service signal descriptor. The group-level control descriptor contains group-level control class signal parameters, and the service signal descriptor contains a set of service signal class signal parameters that are controlled and constrained by the group-level control class signal parameters. The fixed-point integer format hardware control word includes a group-level control class hardware control word and a service signal hardware control word. The signal event descriptor frame includes a group header frame and a member frame. Based on the hardware configuration file, the group-level control class signal parameters contained in the group-level control descriptor are converted into group-level control class hardware control words; The group-level control hardware control word is encapsulated into a group header frame according to the fixed length. Based on the hardware configuration file, the service signal class signal parameters contained in the service signal descriptor are converted into service signal class hardware control words; The service signal class hardware control word is encapsulated into a member frame according to the fixed length.

7. The electromagnetic signal generation method for adapting hardware according to claim 6, characterized in that, The step of calling the hardware implementation layer to load the signal event descriptor frame and generate an electromagnetic signal includes: The hardware implementation layer is invoked to parse the group-level management and control hardware control word from the group header frame, and to parse the service signal hardware control word from the member frame that has a management and control constraint relationship with the group header frame. Based on the group-level control hardware control word and the service signal hardware control word, corresponding electromagnetic signals are generated.

8. An electromagnetic signal generation system adapted to hardware, characterized in that, The system includes an application logic layer, a hardware abstraction layer, and a hardware implementation layer; The application logic layer is used to obtain signal event descriptors and send the signal event descriptors to the hardware abstraction layer; The hardware abstraction layer is used to convert the signal parameters in the signal event descriptor, which are of floating-point data type and have physical units, into hardware control words in fixed-point integer format based on the adapted hardware configuration file. The hardware control word is encapsulated into a signal event descriptor frame according to the fixed length adapted by the hardware implementation layer. The hardware implementation layer is used to load signal event descriptor frames and generate electromagnetic signals based on the signal event descriptor frames.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing a computer to perform the electromagnetic signal generation method for the adapted hardware as described in any one of claims 1-7.

10. A computer program product comprising computer instructions, characterized in that, When executed by a processor, the computer instructions implement the steps of the electromagnetic signal generation method for the adapted hardware as described in any one of claims 1-7.

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