Neural network training method and device, equipment and medium

Abstract

The invention provides a neural network training method and device, equipment and a medium, and the method comprises the following steps: 1, obtaining training data of an image, voice or text type, and carrying out the normalization and feature extraction processing; according to the invention, the three-terminal two-dimensional photoelectric synapse device is prepared, a single / double input mode is supported, cooperative regulation and control of an optical pulse sequence and a grid electric signal sequence are realized, the problem that the multi-mode processing capability of a traditional double-terminal device is limited is solved, and the complex feature extraction efficiency is improved; the nonvolatile storage of synaptic weight is realized through the ferroelectric regulation and control layer, and the remanent polarization of the ferroelectric regulation and control layer is Prgt; 5 [mu] C / cm < 2 > and erasing durability gt; 106 cycles are carried out, continuous power supply is not needed, and training power consumption and cost are reduced; through the high carrier mobility (gt, 200cm < 2 > / Vs) and nanosecond-level photoresponse characteristics (carrier lifetime lt, 10ns) of the two-dimensional photosensitive layer (such as MoS2 / WSe2), the response speed of the device is increased to nanosecond level, and the training requirement of a high-speed neural network is met.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of neural networks, in particular to a neural network training method and device, equipment and medium. BACKGROUND

[0002] With the rapid development of artificial intelligence and neuromorphic computing technology, the neural network training method based on optoelectronic synapse devices has become one of the key technologies to realize brain-like intelligent computing. The optoelectronic synapse device can realize dynamic adjustment of synaptic weights under the regulation of optical and electrical signals by simulating the plasticity of biological synapses, and is widely used in artificial vision systems, optical computing chips and high-speed neuromorphic networks. In the prior art, researchers have developed optoelectronic synapse devices based on two-dimensional materials or oxides and tried to apply them to the training process of neural networks to realize low-power and high-parallel computing mode. However, there are still some problems: 1. The existing training method relies on a two-terminal optoelectronic synapse device, which can only be regulated by a single optical signal, making it difficult to realize the cooperative processing of multi-modal signals, resulting in limited ability to extract and process complex features in the neural network training process; 2. The power consumption of traditional devices is high, and the storage is not volatile, so continuous power supply is needed to maintain synaptic weights in large-scale neural network training, resulting in a large amount of energy consumption and increasing the training cost; 3. The response speed of the optoelectronic synapse device based on traditional memristor and oxide is slow, usually in the order of microseconds, which cannot meet the demand of high-speed neural network training, seriously affecting the training efficiency and real-time performance of the model; Therefore, a neural network training method, device, equipment and medium are proposed. SUMMARY

[0003] Therefore, the embodiments of the present application hope to provide a neural network training method, device, equipment and medium to solve or alleviate the technical problems existing in the prior art, at least to provide a beneficial choice.

[0004] To solve the above technical problems, one technical solution adopted by the present application is: a neural network training method, comprising the following steps: Step 1: Obtain image, voice or text type training data and perform normalization and feature extraction processing; Step 2: Prepare a three-terminal two-dimensional optoelectronic synapse device, and select a single input mode or a double input mode according to the complexity of the processed training data; Step 3: According to the selected input mode, encode the training data into an optical pulse sequence and a gate electrical signal sequence, and set an initial weight value range corresponding to the classification label, and the gate electrical signal sequence corresponds to an initial value of the electrical signal; Step four, based on the input light pulse sequence, control the accumulation of electron-hole pairs in the two-dimensional light-sensitive layer by adjusting the light pulse intensity and duration, preliminarily adjust the synaptic weight according to the set initial weight value range, and calculate the local adjustment gradient between the preliminarily adjusted weight and the target weight; Step five, based on the preliminarily adjusted synaptic weight, apply a gate bias voltage related to the polarity of the electrical signal, and through the time sequence combination of the presynaptic light stimulation and the postsynaptic voltage pulse, the synaptic weight is secondarily regulated; Step six, write the secondarily regulated synaptic weight into the non-volatile storage through the ferroelectric regulation layer, form the weight snapshot of the current training period, and store the weight snapshot; Step seven, based on the stored weight snapshot, calculate the error between the model output and the training data label, generate a global error gradient, and dynamically adjust the light pulse encoding parameters and the gate voltage amplitude according to the global error gradient.

[0005] It is further preferred to provide that in step two, the method for preparing a three-terminal two-dimensional optoelectronic synapse device comprises the following steps: Step 201, select a SiO2 / Sapphire substrate and perform cleaning pretreatment; Step 202, deposit Ni / Au or doped graphene as a gate electrode on the SiO2 / Sapphire substrate by electron beam evaporation; Step 203, spin-coat a ferroelectric layer and perform low-temperature annealing at 130℃±5℃, with an annealing time of 2 hours; Step 204, transfer a MoS2 or WSe2 two-dimensional light-sensitive layer above the ferroelectric layer using dry transfer technology; Step 205, deposit Ti / Au electrodes by electron beam evaporation and perform annealing treatment.

[0006] It is further preferred to provide that in step five, the gate bias voltage includes a bias voltage amplitude and a bias voltage duration; The bias voltage amplitude Vg and the initial value of the electrical signal V0 satisfy: Vg=k•V0; Wherein, k∈[-0.8,-0.5]∪[0.5,0.8], the value range is determined according to the polarization characteristic experiment of the ferroelectric layer; The bias voltage duration T and the local adjustment gradient▽w satisfy: T=T0+m•|▽w|; Wherein T0 is the basic duration, and m is the adjustment coefficient.

[0007] It is further preferred to provide that in step four, the accumulation of electron-hole pairs Δn and the light pulse intensity I, duration t satisfy the relationship: Δn = a • I β • t; Wherein, a, b are constants related to the two-dimensional photosensitive layer material, and the cumulative range is in linear mapping relationship with the initial weight value range.

[0008] It is further preferred to provide that, in step three, the light pulse intensity in the light pulse sequence corresponds to the data feature value, and the light pulse frequency corresponds to the data dimension; the gate electric signal amplitude in the gate electric signal corresponds to the middle value of the initial weight value range. The initial weight value range is determined as [0.1V•n, 0.1V•(n+1)] according to the category number N of the classification task, wherein n is the category index of the current sample, and the range is physically encoded by the gate electric signal amplitude.

[0009] It is further preferred to provide that, in step six, the remaining polarization intensity Pr of the ferroelectric regulation layer is greater than 5μC / cm 2 , and the coercive electric field Ec and the gate bias Vg satisfy: Ec=k•Vg; Wherein, k∈[0.5, 0.8]; The ferroelectric regulation layer has non-volatile storage characteristics, and the erasing and writing durability is greater than 10 6 times of cycles.

[0010] It is further preferred to provide that, in step seven, the calculation method of the global error gradient adopts the back propagation algorithm.

[0011] To solve the above technical problems, another technical solution adopted by the present application is: a neural network training device, comprising: a data acquisition module, a device preparation and mode selection module, a signal encoding and weight initialization module, a weight preliminary adjustment and gradient calculation module, a weight secondary regulation module, a non-volatile storage module, and an error feedback and parameter optimization module. The data acquisition module is configured to acquire training data of the neural network. The device preparation and mode selection module is configured to prepare a three-terminal two-dimensional optoelectronic synapse device, and select a single-input mode or a double-input mode according to the complexity of the training data. The signal encoding and weight initialization module is configured to encode the training data into a light pulse sequence and a gate electric signal sequence according to the selected input mode, and set an initial weight value range corresponding to a classification label, wherein the gate electric signal sequence corresponds to an initial electric signal value. The weight preliminary adjustment and gradient calculation module is configured to preliminarily adjust the synaptic weight according to a set initial weight value range based on the input light pulse sequence by adjusting the light pulse intensity and duration to control the accumulation amount of electron-hole pairs in the two-dimensional light-sensitive layer, and calculate the local adjustment gradient between the preliminarily adjusted weight and the target weight. The weight secondary regulation module is configured to apply a gate bias related to the polarity of the electrical signal to secondarily regulate the synaptic weight through the time sequence combination of the presynaptic light stimulation and the postsynaptic voltage pulse based on the preliminarily adjusted synaptic weight. The non-volatile storage module is configured to write the secondarily regulated synaptic weight into the non-volatile storage through the ferroelectric regulation layer to form a weight snapshot of the current training period and store the weight snapshot. The error feedback and parameter optimization module is configured to calculate the error between the model output and the training data label based on the stored weight snapshot, generate a global error gradient, and dynamically adjust the light pulse coding parameters and the gate voltage amplitude according to the global error gradient.

[0012] To solve the above technical problems, another technical solution adopted by the present application is a computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the steps of the neural network training method according to any one of the above embodiments when executing the computer program.

[0013] To solve the above technical problems, another technical solution adopted by the present application is a computer storage medium having a computer program stored thereon, wherein the program is executed by a processor to implement the steps of the neural network training method according to any one of the above embodiments.

[0014] The above technical solutions have the following advantages: 1. The present application prepares a three-terminal two-dimensional optoelectronic synapse device, supports single / dual input mode, realizes the cooperative regulation of the light pulse sequence and the gate electrical signal sequence, solves the problem of limited multi-modal processing capability of the traditional two-terminal device, and improves the complex feature extraction efficiency. 2. The present application realizes the non-volatile storage of the synaptic weight through the ferroelectric regulation layer, and the residual polarization strength Pr>5μC / cm 2 , and the erase-write durability >10 6 times cycles without continuous power supply, thereby reducing the training power consumption and cost. 3. The present application improves the device response speed to the nanosecond level through the high carrier mobility (>200cm 2 / V•s) and nanosecond-level light response characteristics (carrier lifetime <10ns) of the two-dimensional light-sensitive layer (such as MoS2 / WSe2), thereby meeting the high-speed neural network training requirement.

[0015] The above overview is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the invention will become readily apparent from the accompanying drawings and the following detailed description. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a flowchart illustrating the training method of the neural network of the present invention; Figure 2 This is a schematic flowchart of the method for preparing a three-terminal two-dimensional opto-synaptic device according to the present invention; Figure 3 This is a schematic diagram of the functional modules of the neural network training device of the present invention; Figure 4 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0018] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0019] It should be understood that the following specific examples illustrate the implementation of this disclosure, and those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. This disclosure can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this disclosure. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0020] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this disclosure, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0021] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this disclosure. The drawings only show the components related to this disclosure and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0022] Furthermore, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the described aspects can be practiced without these specific details.

[0023] Figure 1 This is a flowchart illustrating the neural network training method according to an embodiment of the present invention. It should be noted that if substantially the same result is obtained, the method of this application is not necessarily identical. Figure 1 The illustrated process sequence is limited. For example... Figures 1-2 The training method for a neural network, as shown, includes the following steps: Step 1: Obtain training data in the form of images, audio, or text, and perform normalization and feature extraction processing. Specifically, firstly, corresponding collection methods are used for different types of training data: For image data, pixel matrices are obtained through cameras or public datasets (such as MNIST, CIFAR-10), with a uniform resolution of 224×224 pixels; For voice data, audio signals are acquired using a microphone or WAV format files are read, with the sampling rate normalized to 16kHz. For text data, text content is crawled from corpora or web pages and segmented by sentences or paragraphs; Then, data cleaning is performed to remove noise, as follows: Image data is filtered to remove salt-and-pepper noise, speech data is filtered to eliminate ambient noise, and text data is filtered to remove special characters and correct spelling errors. Next, normalization is performed, as follows: Image pixel values ​​are mapped to the [0,1] interval using Min-Max normalization, as shown in the formula: ; The speech signal is normalized using Z-Score to achieve a mean of 0 and a standard deviation of 1; the text is vectorized using Term Frequency-Inverse Document Frequency (TF-IDF) to transform words into numerical vectors with uniform dimensions. Subsequently, feature extraction is performed, as follows: Image data is used to extract deep semantic features using convolutional neural networks (such as ResNet) and output a 2048-dimensional feature vector. Speech data is used to extract time-frequency features through Mel-frequency cepstral coefficients (MFCC) to generate a 40-dimensional feature matrix; The text data uses a BERT pre-trained model to obtain contextual semantic vectors with a dimension of 768. Finally, the extracted features are dimensionality reduced (if the dimension is higher than 100). Principal component analysis (PCA) is used to compress the feature dimension to 80% of the original dimension, and the feature is saved in HDF5 format for use in subsequent steps.

[0024] Step 2: Prepare a three-terminal two-dimensional photoelectric synapse device, and select a single-input mode or a dual-input mode according to the complexity of the processed training data; Specifically, first, a 500nm thick SiO2 / Sapphire substrate is selected and ultrasonically cleaned in acetone and ethanol for 15 minutes each to remove surface contaminants. Then, it is dried with nitrogen and treated with oxygen plasma for 5 minutes to enhance the surface hydrophilicity. Then, a 5 nm thick Ni layer and a 50 nm thick Au layer were sequentially deposited on the substrate using electron beam evaporation to form the gate electrode. After that, the electrode was annealed in a nitrogen atmosphere at 300 °C for 30 minutes to reduce the gate sheet resistance to <1 Ω / sheet. Next, a 15wt% solution of P(VDF-TrFE) copolymer (molar ratio 70:30) was prepared and an 80nm thick ferroelectric layer was formed on the gate electrode using a spin-coating process. The layer was then annealed at 130℃±5℃ for 2 hours in a nitrogen atmosphere. After annealing, the remanent polarization intensity Pr of the ferroelectric layer reached 6.2μC / cm. 2 ; Subsequently, using a wet etching-dry transfer technique, three layers of MoS2 (Raman peak at 384 cm⁻¹) were deposited. -1 and 404cm -1 Alternatively, the WSe2 photosensitive layer can be transferred above the ferroelectric layer, and the control device channel width is 10μm to ensure that the photosensitive layer and the ferroelectric layer are tightly bonded. Next, a 10nm Ti / 100nm Au electrode is formed by electron beam evaporation to create a source-drain structure. The electrode is then rapidly annealed in a nitrogen atmosphere at 250°C for 10 seconds to reduce the contact resistance to <100Ω, thus completing the fabrication of the three-terminal two-dimensional opto-synaptic device. Finally, the input mode is selected based on the feature dimensions of the processed training data: If the data feature dimension is ≤100, select the single input mode and adjust the weights only through the light pulse sequence. If the feature dimension is greater than 100, a dual-input mode is adopted, simultaneously inputting the optical pulse sequence and the gate electrical signal sequence. The optical pulse intensity corresponds to the feature value, the frequency corresponds to the dimension number, and the electrical signal amplitude corresponds to the initial weight center value, thereby realizing the coordinated control of multi-modal signals.

[0025] Step 3: Based on the selected input mode, encode the training data into optical pulse sequences and gate electrical signal sequences, and set the initial weight value range corresponding to the classification label, and the gate electrical signal sequence corresponding to the initial electrical signal value. Specifically, firstly, the encoding strategy is determined based on the input pattern: In single-input mode, the training data features are encoded as light pulse sequences, with light intensity corresponding to feature value magnitude and frequency corresponding to feature dimension. In dual-input mode, optical pulses and gate electrical signal sequences are generated synchronously, and the timing synchronization of optical and electrical signals is achieved through a signal generator (such as Keysight 33600A) (deviation <5ns). Then, the optical pulse sequence encoding is performed, as follows: A 405nm semiconductor laser is used, with the light intensity linearly mapped to 0.1-1mW / cm² according to its eigenvalues. 2 ; Formula: I=I0+k1·x; Where, I0 = 0.1 mW / cm 2 k1 = 0.05 mW / cm 2 / Unit feature value, pulse width is set to 10-100ns according to the feature dimension, and frequency is linearly mapped to 1-10kHz according to the dimension (e.g., 784-dimensional feature corresponds to 7.84kHz). Next, the gate electrical signal is encoded, as follows: An electrical signal sequence is generated using an arbitrary waveform generator (AWG), with the amplitude corresponding to the center value of the initial weight range. The calculation formula is as follows: V = 0.1V•(n+0.5) (n is the category index). For example, when category n=3, the center value is 0.35V, corresponding to the weight range [0.3V, 0.4V]. The rise time of the electrical signal is <10ns to match the timing of the optical pulse. Subsequently, based on the number of classification task categories N, the interval was divided into [0.1V•n, 0.1V•(n+1)]. The amplitude of the electrical signal was physically encoded by the initial polarization state of the ferroelectric layer, and the mapping accuracy between the polarization state and the voltage was verified using a ferroelectric tester (Radiant Precision Premier II) (error <3%). Next, the timing relationship between the optical pulse and the electrical signal was monitored using an oscilloscope (Tektronix DPO7054C). In dual-input mode, the electrical signal was ensured to be applied within 10ns after the optical pulse ended, and the ratio of the bias voltage width to the optical pulse width was 1:1.5. The signal synchronization was recorded using a logic analyzer (LeCroy LabMaster 10 Zi). Then, a standard test set (such as MNIST) is selected, the encoded photoelectric signal is input into a three-terminal device, the cumulative electron-hole pair Δn is measured, and its relationship with light intensity and duration is verified to conform to Δn=α•I. β •t (α=8×10 under MoS2 material) 15 cm -3 W -1 s -1 (β=0.9), the linear mapping coefficient γ=0.1μA / (cm) between the cumulative amount and the weight range. -3 ); Finally, parameters such as the light intensity scaling factor k1, frequency mapping factor, and electrical signal amplitude offset are stored in the FPGA configuration register (such as Xilinx UltraScale+). The encoding parameters are automatically called and updated through a Python script (based on the PyVISA library), which supports online adjustment of the encoding mapping relationship to optimize training efficiency.

[0026] Step 4: Based on the input light pulse sequence, control the accumulation of electron-hole pairs in the two-dimensional photosensitive layer by adjusting the light pulse intensity and duration. According to the set initial weight value range, preliminarily adjust the synaptic weights and calculate the local adjustment gradient between the preliminarily adjusted weights and the target weights. Specifically, firstly, a 405nm semiconductor laser (model LDH-C405M) is used, and the drive current is adjusted via a digitally controlled current source (ILX Lightwave LDX-3412) to maintain the light intensity between 0.1-1mW / cm². 2 The pulse width is set to 10-100ns by the pulse generator (Keysight81150A), and the frequency is mapped to 1-10kHz according to the data dimension (e.g., 7.84kHz for a 28×28 image). Then, the three-terminal device was placed on an optical temperature-controlled platform (temperature 25℃±0.5℃), and the incident light intensity was monitored in real time using an optical power meter (Thorlabs PM100D). The photocurrent was measured using a lock-in amplifier (Stanford Research Systems SR830) to verify that the photoresponsivity of the MoS2 photosensitive layer was 120 A / W (at a wavelength of 405 nm), and the carrier mobility was >200 cm⁻¹. 2 / V•s, ensuring photogenerated carrier lifetime <10ns; Next, according to the formula: Δn=α•I β •t (α=8×10 under MoS2 material) 15 cm -3 W -1 s -1 (β=0.9), the cumulative amount is controlled by adjusting the light intensity and pulse width; for example, light intensity 0.5mW / cm 2 When the pulse width is 20ns, Δn is calculated to be 8 × 10. 15 ×0.5 0.9 ×20×10 -9 ≈7.6×10 7 cm -3 The shift in the lattice vibration mode of the photosensitive layer was monitored by Raman spectroscopy (Renishaw in Via), verifying that the deviation between the cumulative amount and the calculated value was <5%. Subsequently, based on the linear mapping relationship between the cumulative amount and the weight (mapping coefficient γ = 0.1 μA (cm) -3 The cumulative amount is converted into a weight adjustment amount Δw = γ•Δn; for example, the cumulative amount mentioned above corresponds to Δw = 0.1 × 7.6 × 10 7 ×10 -6 The initial weight value was set at 7.6%. The change in device conductance was measured using a semiconductor parameter analyzer (Keithley 4200), confirming the weight adjustment step size to be 0.01Δw (100Ω / step). Next, the mean squared error (MSE) formula is used: ; The deviation between the initially adjusted weights and the target weights is calculated in parallel using an FPGA (Xilinx UltraScale+), and the gradient is calculated using the finite difference method. ; Where the step size δ = 0.01; and the gradient vector is output in real time. (D is the weight dimension); Then, a reference voltage was applied using a high-precision current source (Keithley 2400), and the deviation between the calculated gradient value and the actual weight was compared. Tests on the MNIST training set showed a gradient calculation error of <3%, and the gradient magnitude range was within acceptable limits. This satisfies the parameter requirements for subsequent secondary regulation; Finally, the intermediate state data is stored: the light pulse parameters (intensity, pulse width, frequency), the calculated cumulative value, the preliminary weight matrix, and the local gradient vector are stored in the high-speed cache (DDR4 SDRAM, capacity 16GB) and transmitted to the main control chip through the PCIe 4.0 interface (bandwidth 8GB / s) to provide real-time data support for the secondary regulation in step five.

[0027] Step 5: Based on the initially adjusted synaptic weights, apply a gate bias voltage related to the polarity of the electrical signal, and perform secondary regulation of the synaptic weights by combining the timing of presynaptic photostimulation and postsynaptic voltage pulses. Specifically, first, determine the association rules between the gate bias polarity and the electrical signal: When the electrical signal polarity is positive, a positive bias voltage (Vg>0) is applied to enhance synaptic weight; When the polarity is negative, a reverse bias voltage (Vg<0) is applied to weaken the synaptic weight. The bias polarity control signal is generated by the logic controller (FPGA model Xilinx UltraScale+) based on the sign bit of the electrical signal. Then, the gate bias amplitude is calculated as follows: According to the formula: Vg = k•V0; Where k∈[-0.8,-0.5]∪[0.5,0.8] (the optimal k value is 0.6, determined through experiments on the polarization characteristics of the ferroelectric layer), an adjustable voltage signal is generated using an arbitrary waveform generator (Keysight 33622A); for example, if the initial value of the electrical signal V0=0.5V, then Vg=0.6×0.5=0.3V, and the output accuracy is calibrated to ±1% using a digital multimeter (Keysight 34465A). Next, determine the bias duration, as follows: Based on the formula T=T0+m•|▽w|, the base duration T0=50ns and the adjustment coefficient m=15ns / |▽w| (optimized through pre-training experiments) are set. When the gradient is locally adjusted to |▽w|=0.2, T=50+15×0.2=53ns is calculated. The pulse width error is monitored using an oscilloscope (Tektronix DPO7104C) and found to be <1ns. Subsequently, the gate bias voltage was applied within 10ns after the optical pulse ended using a timing controller (1ns resolution), with the ratio of optical pulse width to bias voltage width being 1:1.5; for example, when the optical pulse width was 20ns, the bias voltage width was set to 30ns, and the timing deviation was verified to be <2ns using a logic analyzer (LeCroyLabMaster10Zi). Next, the gate bias signal is input to the gate of the three-terminal device, and presynaptic light stimulation is repeatedly applied through a semiconductor laser (wavelength 405nm). The device conductance change is monitored in real time using a source meter (Keithley2612B), and the weight adjustment amount Δw2 is recorded to ensure that the weight accuracy reaches 0.02Δw after the second adjustment (1 times higher than the initial adjustment). Then, 100 random samples were selected to compare the weight error before and after the second adjustment. The root mean square error (RMSE) formula was used to calculate that the RMSE decreased from 0.12 to 0.05. Statistical analysis confirmed that the weight distribution after adjustment conformed to a Gaussian distribution (μ=0, σ=0.03). Finally, parameters such as bias amplitude, duration, and timing delay are stored in registers, and a control log is generated by a Python script (based on the PyVISA library), including the mapping relationship between Δw2 and ▽w for each control, to provide data support for subsequent error feedback.

[0028] Step 6: Write the synaptic weights after secondary regulation into non-volatile storage through the ferroelectric regulation layer to form a weight snapshot of the current training cycle, and store the weight snapshot; Specifically, firstly, a P(VDF-TrFE) ferroelectric copolymer (molar ratio 70:30) was selected, and an 80 nm thick film was prepared by spin coating. The film was annealed at 130℃±2℃ in a nitrogen atmosphere for 2 hours, and the remanent polarization intensity Pr was measured to be 6.5 μC / cm using a ferroelectric testing instrument (Radiant Precision Premier II). 2 Coercive electric field Ec = 0.9V, leakage current density < 1×10 -9 A / cm 2 This ensures that non-volatile storage requirements are met; Then, based on the synaptic weight matrix after secondary regulation, each weight value is mapped to a ferroelectric layer polarization state control signal; pulse width modulation (PWM) technology is used, the voltage amplitude is set to 1.2×Ec=1.08V, and the pulse width is adjusted in the range of 50-200ns according to the weight (the larger the weight, the wider the pulse). A high-precision voltage pulse sequence is generated by an arbitrary waveform generator (Keysight 33622A), with rise / fall time <5ns; Next, a voltage pulse sequence is applied to the gate of the ferroelectric control layer to realize the physical storage of weights by utilizing the ferroelectric domain flipping effect. During the writing process, the capacitance change of the ferroelectric layer is monitored in real time by an impedance analyzer (Solartron 1260) to confirm that the polarization state switching is complete. The energy consumption of a single write is <1nJ / bit, and the write speed reaches 10μs / weight. Subsequently, the polarization state of the ferroelectric layer after writing is converted into a digital signal, using 16-bit fixed-point encoding (1 sign bit, 15 value bits), corresponding to a weight range of [-1, 1]. Weight snapshot files are generated according to the training cycle, with the file name format "weight_snapshot_YYYYMMDD_HHMMSS.h5", and stored in a high-speed solid-state storage array (SSD RAID 0, bandwidth 2GB / s). Next, a power-off test was performed on the stored weighted snapshots. After 10 years of power-off at room temperature, the polarization state was read using a ferroelectric tester, and the weight retention rate was calculated to be >85%. Simultaneously, an erase / write durability test was conducted, using an automated testing system (Keithley 4200-SCS) for 10 cycles of erase / write. 6 The weight drift rate was measured to be less than 3%, which meets the long-term storage requirements. Then, snapshot metadata is generated using a Python script (based on the H5Py library), which includes information such as the number of training cycles, model version, write time, and weight dimension. This metadata is stored in a MongoDB database (replica set architecture to ensure high availability), with an index query response time of <100ms. Finally, a three-level backup mechanism is adopted: primary storage (SSD), hot backup (NVMe over Fabric), and cold backup (tape library). Incremental backup is implemented through the Rsync tool, and the backup window is set to 2:00 AM every day to ensure data reliability of 99.999%. At the same time, a snapshot management interface (based on the Flask framework) is developed to support the retrieval and restoration of historical weighted snapshots by time, precision, and other conditions.

[0029] Step 7: Based on the stored weight snapshot, calculate the error between the model output and the training data label, generate a global error gradient, and dynamically adjust the optical pulse coding parameters and gate voltage amplitude according to the global error gradient. Specifically, firstly, the weight matrix of the current training cycle is read through the HDF5 file interface, and the file structure is parsed using Python's h5py library. The polarization state of the ferroelectric layer is converted into floating-point weight values ​​and loaded into the GPU memory (NVIDIA A100, 40GB of memory) to accelerate subsequent calculations. Then, a neural network structure is built based on the PyTorch framework. The input layer dimension matches the number of features in the training data (e.g., 784 dimensions for MNIST). The hidden layer is a linear layer simulated by a two-dimensional photoelectric synaptic device. The number of nodes in the output layer is equal to the number of categories in the classification task (e.g., 10 for MNIST). The weight parameters are initialized and loaded from the weight snapshot. Next, the preprocessed training data is input into the model, and the output of each layer is calculated using the current configuration of the optical pulse coding parameters (intensity, frequency) and the gate voltage amplitude. CUDA is used to accelerate tensor operations, the batch size is set to 128, and the forward propagation delay is controlled within 1ms / batch. Subsequently, the cross-entropy loss function is used: ; in, One-hot encoding for tags, Output probabilities for the model; calculate the gradient of the loss with respect to the weights of each layer using the automatic differentiation engine (PyTorchAutograd); Next, the local gradients from each layer are aggregated into a global error gradient vector, and the gradient matrix is ​​calculated using the backpropagation (BP) algorithm. Where D is the weight dimension and M is the batch size; the learning rate adopts a dynamic decay strategy. ; Among them, the initial learning rate =0.01, attenuation coefficient α=0.001; Subsequently, the optical pulse coding parameters are dynamically adjusted as follows: When the error rate is greater than 15%, the light intensity scaling factor k1 is increased by 1.2 times (e.g., from 0.05 to 0.06), and the frequency scaling factor k2 is decreased by 0.9 times (e.g., from 1 kHz / dimension to 0.9 kHz / dimension). When the error change rate is less than 1% for 5 consecutive cycles, the gate voltage adjustment step size is reduced to 0.8 times the original size, and the FPGA configuration register is updated through the SPI interface (clock frequency 10MHz). Next, 1000 test samples were selected, and the model output was calculated using the new parameters. The change in error rate before and after the adjustment was compared. On the MNIST dataset, the error rate should decrease by more than 10% after adjustment; otherwise, a second adjustment was triggered (the light intensity coefficient was increased by 1.1 times). Then, the adjusted optical pulse encoding parameters (k1, k2) and gate voltage amplitude offset are stored in the EEPROM (24LC256, write lifetime 10). 6 (times), and at the same time generate a parameter adjustment log, including adjustment time, triggering conditions, new and old parameter values, etc.; Finally, repeat the forward computation-backward propagation-parameter adjustment process until the model's accuracy on the validation set stabilizes (e.g., MNIST ≥ 98%). The entire training process is monitored in real time by TensorBoard for indicators such as loss curve and gradient norm, and alarms are automatically triggered when anomalies occur (e.g., training is paused and rolled back to the previous snapshot when gradient explosion occurs).

[0030] In one implementation, specifically in step two, the method for fabricating a three-terminal two-dimensional photosynaptic device includes the following steps: Step 201: Select a SiO2 / Sapphire substrate and perform a cleaning pretreatment; Specifically, first, a SiO2 / Sapphire substrate with a size of 10mm×10mm and a thickness of 500nm is selected and placed in a glass container containing acetone solution at 60℃. It is then ultrasonically cleaned at a frequency of 40kHz for 20 minutes to thoroughly remove organic contaminants from the substrate surface. The substrate was then transferred to an ethanol solution at 70°C and ultrasonically cleaned for 15 minutes to remove residual acetone and inorganic impurities. After cleaning, the substrate surface was dried with high-purity nitrogen gas with a purity of 99.999%. Finally, the substrate is placed in an oxygen plasma etching machine and treated for 8 minutes at a power of 100W and a pressure of 0.5Pa to make the surface roughness Ra < 0.5nm, enhance the surface hydrophilicity, and prepare for subsequent processes.

[0031] Step 202: Deposit Ni / Au or doped graphene as a gate on a SiO2 / Sapphire substrate by electron beam evaporation. Specifically, firstly, the electron beam evaporation system is pre-evacuated to reduce the pressure inside the vacuum chamber to 5 × 10⁻⁶. -6 To avoid impurity gases affecting the quality of the deposited film, the pressure should be kept below 1 Pa. Then, the pre-cleaned SiO2 / Sapphire substrate was fixed on the sample stage in the evaporation chamber, and the distance between the substrate and the evaporation source was adjusted to 15cm to ensure uniform film deposition. For the deposition of Ni / Au gate, a nickel (Ni) target with a purity of 99.99% is first loaded into an electron beam evaporation source, and a 5nm thick Ni transition layer is deposited on the substrate at a rate of 0.5nm / s. This transition layer can enhance the adhesion between the subsequent Au layer and the substrate. Next, a 99.99% pure gold (Au) target was used to deposit a 50nm thick Au conductive layer at a rate of 1nm / s to form the gate electrode. During the deposition process, the film thickness was monitored in real time using a quartz crystal oscillator, with the accuracy controlled within ±0.1nm. If doped graphene is chosen as the gate, a doped graphene film is prepared by chemical vapor deposition (CVD). Methane (CH4) and hydrogen (H2) are introduced into the reaction chamber at a volume ratio of 1:10, and graphene is grown on a copper foil substrate at 1000℃. Borane (B2H6) is introduced during the growth process to achieve p-type doping. After the growth is completed, the graphene film is transferred to a SiO2 / Sapphire substrate, and the copper foil is removed by oxygen plasma etching to obtain a doped graphene gate with a thickness of 3-5 layers and a sheet resistance controlled at 50-100 Ω / square. After deposition or transfer, the substrate is moved into a tube annealing furnace and heated to 300°C at a heating rate of 5°C / min. Annealing is then carried out for 30 minutes in a high-purity nitrogen atmosphere with a flow rate of 500 sccm to improve the crystal quality of the thin film. After annealing, the substrate is cooled to room temperature in the furnace, and the sheet resistance of the gate is measured using a four-probe tester. The sheet resistance of the Ni / Au gate should be <1Ω / square, and the sheet resistance of the graphene-doped gate should be <150Ω / square to ensure good conductivity of the gate.

[0032] Step 203: Spin-coat the ferroelectric layer and perform low-temperature annealing at 130℃±5℃ for 2 hours; Specifically, firstly, a polyvinylidene fluoride-trifluoroethylene copolymer (P(VDF-TrFE), with a molar ratio of VDF to TrFE of 70:30) with a number average molecular weight of 100,000 is dissolved in dimethylacetamide (DMAc) solvent to prepare a homogeneous solution with a mass concentration of 18wt%. The solution is then filtered through a 0.22μm polytetrafluoroethylene (PTFE) filter membrane to remove impurity particles from the solution. Then, the SiO2 / Sapphire substrate, after cleaning, pretreatment, and gate deposition, was fixed on the vacuum chuck of the spin coater. 50 μL of ferroelectric layer solution was aspirated using a microsyringe and dropped onto the center of the substrate. The spin coater parameters were set, first rotating at a low speed of 500 rpm for 10 seconds to spread the solution evenly on the substrate surface, and then rotating at a high speed of 3000 rpm for 30 seconds to form a ferroelectric layer film with a thickness of about 80 nm. During the spin coating process, the ambient temperature was maintained at 25℃±1℃ and the humidity <30%RH to avoid environmental factors affecting the uniformity of the film. Next, the spin-coated substrate was placed in a glove box filled with high-purity nitrogen (99.999% purity, 50 sccm flow rate) to prevent the ferroelectric layer from being oxidized during annealing. A programmable temperature-controlled heating plate was used to raise the temperature to 130℃±2℃ at a heating rate of 1℃ / min, and the annealing was maintained at this temperature for 2 hours. During the annealing process, the substrate surface temperature was monitored in real time by thermocouples to ensure that the temperature fluctuation did not exceed ±5℃, so as to avoid incomplete crystallization of the ferroelectric layer due to temperature deviation. After annealing, the substrate was allowed to cool naturally to room temperature before being removed for ferroelectric performance testing. Hysteresis loop measurements of the ferroelectric layer were performed using a ferroelectric testing instrument (such as Radiant Precision Premier II). A triangular wave voltage with a frequency of 1 kHz and an amplitude of 2 V was applied, and the remanent polarization intensity Pr was measured to be >5 μC / cm. 2 (Typical value is 6.5 μC / cm) 2 The coercive electric field Ec is 0.8-1.0V, demonstrating that the ferroelectric layer possesses good polarization characteristics and can be used for subsequent weighted non-volatile storage. Simultaneously, the leakage current density of the ferroelectric layer was measured using a semiconductor parameter analyzer (such as a Keithley 4200). At room temperature with a 1V bias voltage, the leakage current density should be <1×10⁻⁶. -9 A / cm 2 This ensures the low power consumption characteristics of the ferroelectric layer.

[0033] Step 204: Transfer the two-dimensional photosensitive layer of MoS2 or WSe2 onto the ferroelectric layer using a dry transfer technique; Specifically, firstly, three layers of MoS2 or WSe2 were grown on a SiO2 / Si substrate using chemical vapor deposition (CVD), and Raman spectroscopy confirmed that the characteristic peak of MoS2 was located at 384 cm⁻¹. -1 and 404cm -1 Half-height width (FWHM) < 20cm -1 The characteristic peak of WSe2 is located at 258 cm⁻¹. -1 and 281cm -1 (FWHM < 25cm) -1 ); Then, the substrate with the two-dimensional material grown was immersed in a 5% hydrofluoric acid (HF) solution to etch the SiO2 layer and release the two-dimensional material sheet; at the same time, a 50nm thick polymethyl methacrylate (PMMA) layer was spin-coated on the surface of the ferroelectric layer as a temporary support layer and annealed at 100°C for 10 minutes to cure. Next, a PDMS (polydimethylsiloxane) stamp (hardness 50 Shore A) was applied to the surface of a two-dimensional material sheet at 1 standard atmosphere and 25°C. A pressure of 50 kPa was applied and held for 30 seconds, and the sheet was picked up. The PDMS stamp was aligned with the ferroelectric layer surface, and the positional accuracy was adjusted to ±1 μm. The stamp was then slowly pressed down at a 10° angle and bonded. The adhesion was enhanced by heating the sheet to 80°C with a hot plate for 5 minutes. Subsequently, the transferred substrate was immersed in acetone solution for 30 minutes to dissolve the PMMA support layer, then rinsed three times with deionized water and dried with nitrogen. The transferred photosensitive layer was then inspected using an optical microscope (500× magnification) to ensure that there were no bubbles or wrinkles and that the coverage area was >95%. Finally, the interface roughness between the photosensitive layer and the ferroelectric layer was measured by atomic force microscopy (AFM), and the root mean square roughness (RMS) was <2nm. The elemental distribution at the interface was detected by X-ray photoelectron spectroscopy (XPS), confirming that there was no residual etchant contamination and that the contact resistance between the two-dimensional material and the ferroelectric layer was <100Ω, which meets the requirements for photoelectric control.

[0034] Step 205: Evaporate the Ti / Au electrode by electron beam and then anneal it; Specifically, firstly, the electron beam evaporation system undergoes vacuum pretreatment to reduce the pressure inside the cavity to 1×10⁻⁶. -5 Below Pa, avoid metal oxidation; Then, the substrate with the photosensitive layer transferred is fixed on the sample stage and adjusted to a distance of 12 cm from the evaporation source to ensure uniform film deposition; Next, a titanium (Ti) target with a purity of 99.99% was first loaded into the evaporation source, and a 10 nm thick Ti adhesion layer was deposited at a rate of 0.3 nm / s to enhance the adhesion to the photosensitive layer. Then, a gold (Au) target with a purity of 99.99% was used to deposit a 100 nm thick Au conductive layer at a rate of 1 nm / s to form the source and drain electrodes. During the deposition process, the thickness was monitored in real time using a quartz crystal oscillator, with the accuracy controlled within ±0.1 nm. Subsequently, a photoresist (such as S1813) was spin-coated (3000 rpm, 30 s), pre-baked (90℃, 10 min), and exposed through a mask (UV light intensity 200 mJ / cm²). 2 ), development (1:4 diluted NaOH solution, 60s), define the electrode pattern, and control the line width to 2μm; Next, the substrate was placed in a rapid annealing furnace and annealed for 15 seconds at a heating rate of 10°C / ms in a nitrogen atmosphere (containing 5% hydrogen) to 250°C to improve the ohmic contact between the electrode and the photosensitive layer. After annealing, the electrode edge was observed using a scanning electron microscope (SEM). The roughness should be <5nm and there should be no cracking. Finally, the sheet resistance of the Ti / Au electrode was measured using a four-probe tester and should be <0.5Ω / square. The contact resistance between the electrode and the photosensitive layer was tested using a semiconductor parameter analyzer (Keithley 4200) and should be <80Ω under a ±1V bias voltage to ensure good device conductivity.

[0035] In one implementation, specifically in step five, the gate bias includes the bias magnitude and the bias duration; The bias voltage amplitude Vg and the initial value of the electrical signal V0 satisfy the following: Vg = k•V0; Where k∈[-0.8,-0.5]∪[0.5,0.8], this range of values ​​is determined experimentally based on the polarization characteristics of the ferroelectric layer; The bias duration T and the local adjustment gradient ▽w satisfy the following: T=T0+m•|▽w|; Where T0 is the base duration and m is the adjustment coefficient; Specifically, taking MNIST handwritten digit recognition training as an example, the specific implementation process is as follows: An 80 nm thick P(VDF-TrFE) ferroelectric layer (VDF:TrFE=70:30) was used and annealed in nitrogen at 130 °C for 2 hours. The residual polarization intensity Pr=6.5μC / cm and the coercive electric field Ec=0.9V were measured. By applying different Vg values ​​using a ferroelectric tester and recording the polarization reversal current, the ferroelectric domain switching speed is fastest and the power consumption is lowest when Vg = 0.6V0 (write power consumption 0.8nJ / bit). Therefore, k = 0.6 ∈ [0.5, 0.8]. If a sample category index n=5, according to the coding rules in step three, the initial weight range is [0.5V, 0.6V], and the initial value of the electrical signal V0=0.55V (the middle value of the range). Bias voltage amplitude: Vg = 0.6 × 0.55 = 0.33V. A square wave signal with this amplitude is generated using a Keysight 33622A arbitrary waveform generator with a voltage accuracy of ±1mV. The dynamic calculation process for bias duration is as follows: Let T0 = 50ns, then through pre-training optimization, we obtain m = 15ns / |▽w|; If step four calculates the local adjustment gradient |▽w|=0.3 (after normalization), then the duration T=50+15×0.3=54.5ns; Use a Tektronix DPO7104C oscilloscope to monitor and ensure that the bias rise time is <5ns and the pulse width error is <1ns; The process of combining optical and electrical timing sequences and adjusting weights is as follows: The optical pulse width is 25ns, and the bias voltage is applied 8ns after the optical pulse ends. The pulse width ratio is 1:1.7 (optical:bias voltage). The timing deviation is verified to be <2ns using a LeCroy logic analyzer. After applying a bias voltage, the conductivity of the measuring device was measured using a Keithley 4200. After secondary adjustment, the weight was adjusted from 0.58V to 0.62V, with an adjustment amount Δw2=0.04V and an accuracy of 0.01V / step, which is twice that of the initial adjustment. 100 MNIST samples were randomly selected. When k=0.6, the average weight error decreased from 0.12V to 0.04V. The linear correlation coefficient R between T and |▽w| was calculated. 2 =0.98, proving the validity of the formula; The energy consumption for a single adjustment is 1.2nJ, which is 30% lower than the traditional fixed bias scheme, meeting the requirements for low power consumption; By experimentally determining the value of k and the coefficient of m, and combining this with dynamic gradient adjustment of the bias duration, precise control of the weights is achieved while ensuring low power consumption and high-speed response, effectively solving the problem of insufficient control precision of traditional devices in the background technology.

[0036] In one implementation, specifically in step four, the cumulative amount of electron-hole pairs Δn satisfies the following relationship with the light pulse intensity I and duration t: Δn=α•I β •t; Wherein, α and β are constants related to the two-dimensional photosensitive layer material, and the cumulative range is linearly mapped to the range of the initial weight values; Specifically, taking the MNIST training with 3 layers of MoS2 as the two-dimensional photosensitive layer as an example, the specific implementation process is as follows: Three layers of MoS2 were grown on a SiO2 / Si substrate by CVD, and Raman spectroscopy revealed a characteristic peak at 384 cm⁻¹. -1 and 404cm -1 The half-height and width (FWHM) are 18cm each. -1 and 20cm -1 Photoluminescence (PL) spectroscopy showed a band gap of 1.85 eV; A photoresponse experiment was conducted using a 405nm laser (wavelength λ = 405nm, photon energy 3.06eV), with the light intensity adjusted to I = 0.1-1mW / cm². 2 With a pulse width of t = 10-100 ns, the cumulative electron-hole pair Δn was measured using spatially resolved photocurrent spectroscopy (SPL), and the fitted result was α = 8.2 × 10⁻⁶. 15 cm -3 W -1 s -1 β=0.92 (fitting error <3%) Suppose that the feature value of a certain training sample corresponds to a light intensity I = 0.5 mW / cm². 2 The duration of the light pulse is t = 20 ns; Cumulative calculation: Δn = α•I β •t=8.2×10 15 ×(0.5) 0.92 ×20×10 -9 ≈7.8×10 7 cm -3 ; The surface potential change of MoS2 was measured using Kelvin probe force microscopy (KPFM), and the carrier density increment was calculated to be 7.6 × 10⁻⁶. 7 cm -3The deviation from the calculated value is <3%; The device conductance G was measured using a semiconductor parameter analyzer (Keithley 4200), and the mapping coefficient γ between Δn and the weight adjustment Δw was found to be 0.11 μA / (cm). -3 ),Right now: Δw = γ • Δn = 0.11 × 10 -6 ×7.8×10 7 =8.58% initial weight value; If the number of categories in the classification task is N=10, the category index of a sample is n=3, and the initial weight range is [0.3V, 0.4V], then the weight adjustment corresponding to Δw is 0.0858 × 0.1V = 0.00858V. By controlling the polarization state of the ferroelectric layer, the measured weight is adjusted from 0.35V to 0.3586V, with a deviation of <2% from the calculated value. One hundred MNIST samples were selected, with light intensity I = 0.2-0.8 mW / cm². 2 Given a pulse width t = 10-50 ns, calculate Δn and map the weight adjustment amount. The results are as follows:

[0037] Cumulative range [6.18×10] 7 8.95×10 7 cm -3 The linear fit coefficient R with the initial weight range [0.1V, 0.9V] 2 =0.97, proving the validity of the formula.

[0038] In one implementation, specifically in step three, the light pulse intensity in the light pulse sequence corresponds to the data feature value, and the light pulse frequency corresponds to the data dimension; the gate electrical signal amplitude in the gate electrical signal corresponds to the midpoint of the initial weight value range. Specifically, the intensity of the light pulse corresponds to the magnitude of the data characteristic value according to a linear relationship. For example, the characteristic value can be mapped to 0.1-1 mW / cm² using the formula I=0.1+0.05x (where x is the normalized characteristic value). 2 The intensity of light allows strong features to correspond to high-energy light stimulation; the frequency of light pulses is directly related to the data dimension. For example, the features of a 28×28 pixel image are represented by a pulse sequence with a frequency of 7.84kHz. Each frequency component corresponds to a one-dimensional feature, realizing parallel optical encoding of high-dimensional data. This encoding method utilizes the high bandwidth characteristics of light signals, enabling a single pulse to carry both feature values ​​and dimensional information, improving the processing speed by 3 times compared to traditional electrical signal encoding.

[0039] The initial weight value range is determined according to the number of categories N of the classification task as [0.1V•n, 0.1V•(n+1)], where n is the category index of the current sample, and this range is physically encoded by the gate electrical signal amplitude; Specifically, the setting of the initial weight value range and the physical encoding follow the dimensionality adaptation principle of the classification task: the weight space is divided into N equally spaced intervals according to the number of categories N, and each sample category index n corresponds to the interval [0.1V·n, 0.1V·(n+1)], for example, in a 10-class classification task, category 3 corresponds to [0.3V, 0.4V]; the intermediate value of the interval 0.1V·(n+0.5) is physically encoded through the gate electrical signal amplitude, and the voltage amplitude is converted into a non-volatile polarization state by utilizing the polarization characteristics of the ferroelectric layer, such as an electrical signal of 0.35V corresponding to an initial polarization intensity of 6.5μC / cm for the ferroelectric domain. 2 This allows each category weight to have a distinguishable physical representation at the device level, achieving weight initialization with a coding accuracy of ±3%.

[0040] In one implementation, specifically in step six, the residual polarization intensity Pr of the ferroelectric control layer is >5 μC / cm. 2 The coercive electric field Ec satisfies the following relationship with the gate bias voltage Vg: Ec = k•Vg; Where k∈[0.5,0.8]; Specifically, the remanent polarization intensity Pr of the ferroelectric control layer is the core parameter for measuring its non-volatile storage capability. When Pr > 5 μC / cm 2 Ferroelectric materials can maintain a stable polarization state even after the external electric field is removed, thus achieving physical storage of synaptic weights. For example, using an 80nm thick P(VDF-TrFE) ferroelectric copolymer (VDF to TrFE molar ratio 70:30), after nitrogen annealing at 130℃±5℃ for 2 hours, the measured Pr reached 6.5μC / cm. 2 The value can be verified by measuring the hysteresis loop using a ferroelectric tester (such as Radiant Precision Premier II). The relationship between the coercive electric field Ec and the gate bias voltage Vg is Ec=k•Vg, where k∈[0.5,0.8] is determined by experiments on the polarization characteristics of the ferroelectric layer. For example, when k=0.6 and Vg=1.5V, Ec=0.9V. This value ensures that the ferroelectric domains flip precisely when a bias voltage is applied, while avoiding increased power consumption due to excessive voltage. The ferroelectric control layer possesses non-volatile storage characteristics and has an erase / write endurance of >10. 6 The next loop; Specifically, the non-volatile storage characteristic of the ferroelectric control layer allows it to retain weight information even after power is turned off; experiments show Pr = 6.5 μC / cm. 2The ferroelectric layer retains over 85% of its weight after 10 years of power-off at room temperature, solving the problem of traditional devices requiring continuous power supply; its erase / write durability is >10. 6 The characteristics of the secondary cycle are achieved through optimized annealing processes. For example, after low-temperature annealing, the ferroelectric domain boundary defects of the P(VDF-TrFE) layer are reduced. A Keithley 4200-SCS system is used for 10... 6 After several cycles of erase and write tests, the Pr decay rate is only 3.1% and the weight drift rate is <5%, which meets the requirements of large-scale neural network iterative training. This design achieves low-power non-volatile storage of weights through the polarization characteristics of ferroelectric materials, providing a stable physical basis for neuromorphic computing.

[0041] In one implementation, specifically in step seven, the global error gradient is calculated using the backpropagation algorithm; The backpropagation algorithm generates a global error gradient vector by propagating the error between the model output and the training data labels (such as cross-entropy loss) back along the network layers and calculating the partial derivative of the loss function with respect to the synaptic weights of each layer. In practice, the output of each layer is first obtained through forward propagation, and then the gradient matrix is ​​calculated using an automatic differentiation engine (such as PyTorch Autograd). The step size is adjusted and updated in combination with a dynamic learning rate strategy. Finally, the local gradients of each layer are aggregated into a global error gradient, which provides a basis for the dynamic adjustment of optical pulse coding parameters and gate voltage amplitude, and realizes error feedback optimization of neural network training.

[0042] In summary, the neural network training method provided in this invention acquires and preprocesses training data, prepares a three-terminal two-dimensional photoelectric synapse device, selects a single / dual input mode according to the data complexity, encodes the data into a sequence of light pulses and gate electrical signals, uses light intensity and pulse width to control the accumulation of electron-hole pairs in the two-dimensional photosensitive layer to initially adjust the synaptic weights, performs secondary regulation by combining the timing combination of gate bias and light stimulation, achieves non-volatile storage of weights through a ferroelectric regulation layer, and finally dynamically optimizes the light pulse encoding parameters and gate voltage amplitude based on the global error gradient calculated by the backpropagation algorithm. This achieves low-power, high-speed response, and high-precision neural network training, effectively solving the problems of insufficient regulation accuracy, high power consumption, and slow response of traditional devices.

[0043] Figure 3 This is a functional module diagram of a neural network training device according to an embodiment of this application, as shown below. Figure 3 As shown, the training device for the neural network includes: a data acquisition module, a device fabrication and mode selection module, a signal encoding and weight initialization module, a weight initial adjustment and gradient calculation module, a weight secondary adjustment module, a non-volatile storage module, and an error feedback and parameter optimization module. The data acquisition module is configured to acquire training data for the neural network; The device fabrication and mode selection module is configured to fabricate a three-terminal two-dimensional opto-synaptic device and select a single-input mode or a dual-input mode according to the complexity of the training data. The signal encoding and weight initialization module is configured to encode the training data into a light pulse sequence and a gate electrical signal sequence according to the selected input mode, and set the initial weight value range corresponding to the classification label, and the gate electrical signal sequence corresponds to the initial value of the electrical signal. The initial weight adjustment and gradient calculation module is configured to control the accumulation of electron-hole pairs in the two-dimensional photosensitive layer by adjusting the intensity and duration of the light pulses, and to initially adjust the synaptic weights according to the set initial weight value range, and calculate the local adjustment gradient between the initially adjusted weights and the target weights. The weight secondary control module is configured to apply a gate bias voltage related to the polarity of the electrical signal based on the initially adjusted synaptic weight, and to perform secondary control of the synaptic weight through the timing combination of presynaptic photostimulation and postsynaptic voltage pulse; The non-volatile storage module is configured to write the synaptic weights after secondary modulation into the non-volatile storage through the ferroelectric modulation layer, forming a weight snapshot of the current training cycle, and storing the weight snapshot; The error feedback and parameter optimization module is configured to use a storage-based weight snapshot to calculate the error between the model output and the training data labels, generate a global error gradient, and dynamically adjust the optical pulse coding parameters and gate voltage amplitude based on the global error gradient.

[0044] For further details regarding the implementation techniques of each module in the neural network training device of the above embodiments, please refer to the description in the neural network training method of the above embodiments, which will not be repeated here.

[0045] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For apparatus embodiments, since they are basically similar to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0046] like Figure 4 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present disclosure. It illustrates a structural schematic diagram suitable for implementing the computer device in the embodiments of the present disclosure. Figure 4 The computer device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0047] like Figure 4As shown, a computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it performs all or part of the steps of the neural network training methods of the various embodiments of this disclosure described above.

[0048] For example, a computer program can be divided into one or more modules / units, one or more of which are stored in memory and executed by a processor to complete the present invention. One or more modules / units can be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of the computer program in a computer device.

[0049] For a detailed description of this embodiment, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0050] A computer-readable storage medium according to embodiments of the present disclosure stores non-transitory computer-readable instructions. When the non-transitory computer-readable instructions are executed by a processor, all or part of the steps of the neural network training methods of the foregoing embodiments of the present disclosure are performed.

[0051] The aforementioned computer-readable storage media include, but are not limited to: optical storage media (e.g., CD-ROM and DVD), magneto-optical storage media (e.g., MO), magnetic storage media (e.g., magnetic tape or portable hard drive), media with built-in rewritable non-volatile memory (e.g., memory card), and media with built-in ROM (e.g., ROM cartridge).

[0052] For a detailed description of this embodiment, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0053] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0054] In this disclosure, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. The block diagrams of devices, apparatuses, devices, and systems involved in this disclosure are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as "comprising," "including," "having," etc., are open-ended terms meaning "including but not limited to," and are used interchangeably with them. The terms "or" and "and" as used herein refer to the terms "and / or," and are used interchangeably with them unless the context clearly indicates otherwise. The term "such as" as used herein refers to the phrase "such as but not limited to," and is used interchangeably with it.

[0055] Additionally, as used herein, the "or" used in a list of items beginning with "at least one" indicates a separate list, such that a list of, for example, "at least one of A, B, or C" means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). Furthermore, the word "exemplary" does not imply that the described example is preferred or better than other examples.

[0056] It should also be noted that in the systems and methods of this disclosure, the components or steps can be decomposed and / or recombined. These decompositions and / or recombinations should be considered as equivalent solutions to this disclosure.

[0057] Various changes, substitutions, and modifications can be made to the technology described herein without departing from the teachings defined by the appended claims. Furthermore, the scope of the claims of this disclosure is not limited to the specific aspects of the processes, machines, manufactures, events, means, methods, and actions described above. Currently existing or later-developed processes, machines, manufactures, events, means, methods, or actions that perform substantially the same function or achieve substantially the same result as the corresponding aspects described herein can be utilized. Therefore, the appended claims include such processes, machines, manufactures, events, means, methods, or actions within their scope.

[0058] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.

[0059] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations therein.

Claims

1. A method for training a neural network, characterized in that, Includes the following steps: Acquire training data in the form of images, audio, or text, and perform normalization and feature extraction processing; Three-terminal two-dimensional photoelectric synaptic devices were fabricated, and single-input mode or dual-input mode was selected according to the complexity of the processed training data. Based on the selected input mode, the training data is encoded into a light pulse sequence and a gate electrical signal sequence, and an initial weight value range corresponding to the classification label is set, wherein the gate electrical signal sequence corresponds to the initial value of the electrical signal. Based on the input light pulse sequence, the accumulation of electron-hole pairs in the two-dimensional photosensitive layer is controlled by adjusting the light pulse intensity and duration. According to the set initial weight value range, the synaptic weights are initially adjusted, and the local adjustment gradient between the initially adjusted weights and the target weights is calculated. Based on the initially adjusted synaptic weights, a gate bias voltage related to the polarity of the electrical signal is applied, and the synaptic weights are further modulated by the timing combination of presynaptic photostimulation and postsynaptic voltage pulses. The synaptic weights after secondary regulation are written into non-volatile storage through the ferroelectric regulation layer to form a weight snapshot of the current training cycle, and the weight snapshot is stored. Based on the stored weight snapshots, the error between the model output and the training data labels is calculated, a global error gradient is generated, and the optical pulse coding parameters and gate voltage amplitude are dynamically adjusted according to the global error gradient.

2. The neural network training method according to claim 1, characterized in that: The method for preparing a three-terminal two-dimensional photoelectric synapse device includes the following steps: SiO2 / Sapphire substrate was selected and pre-cleaned. Ni / Au or doped graphene is deposited as a gate on a SiO2 / Sapphire substrate by electron beam evaporation. The ferroelectric layer was spin-coated and then annealed at 130℃±5℃ for 2 hours. A dry transfer technique was used to transfer a two-dimensional photosensitive layer of MoS2 or WSe2 onto the ferroelectric layer. Ti / Au electrodes were evaporated by electron beam and then annealed.

3. The neural network training method according to claim 1, characterized in that: The gate bias includes the bias amplitude and the bias duration; The bias voltage amplitude Vg and the initial value of the electrical signal V0 satisfy the following: Vg = k•V0; Where k∈[-0.8,-0.5]∪[0.5,0.8], this range of values ​​is determined experimentally based on the polarization characteristics of the ferroelectric layer; The bias duration T and the local adjustment gradient ▽w satisfy the following: T=T0+m•|▽w|; Where T0 is the base duration and m is the adjustment coefficient.

4. The neural network training method according to claim 1, characterized in that: The cumulative amount of electron-hole pairs Δn is related to the light pulse intensity I and the duration t by the following formula: Δn=α•I β •t; Wherein, α and β are constants related to the two-dimensional photosensitive layer material, and the cumulative range is linearly mapped to the initial weight value range.

5. The neural network training method according to claim 1, characterized in that: The light pulse intensity in the light pulse sequence corresponds to the data feature value, and the light pulse frequency corresponds to the data dimension; the gate electrical signal amplitude in the gate electrical signal corresponds to the midpoint of the initial weight value range. The initial weight value range is determined according to the number of categories N of the classification task as [0.1V•n, 0.1V•(n+1)], where n is the category index of the current sample, and this range is physically encoded by the gate electrical signal amplitude.

6. The neural network training method according to claim 1, characterized in that: The remanent polarization intensity Pr of the ferroelectric modulation layer is greater than 5 μC / cm. 2 The coercive electric field Ec satisfies the following relationship with the gate bias voltage Vg: Ec = k•Vg; Where k∈[0.5,0.8]; The ferroelectric control layer possesses non-volatile storage characteristics and has an erase / write endurance >10. 6 The loop continues.

7. The training method for a neural network according to claim 1, characterized in that: The global error gradient is calculated using the backpropagation algorithm.

8. A training apparatus for a neural network, applied to the training method of a neural network according to any one of claims 1-7, characterized in that, include: The module includes a data acquisition module, a device fabrication and mode selection module, a signal encoding and weight initialization module, a weight preliminary adjustment and gradient calculation module, a weight secondary control module, a non-volatile storage module, and an error feedback and parameter optimization module. The data acquisition module is configured to acquire training data for the neural network; The device fabrication and mode selection module is configured to fabricate a three-terminal two-dimensional photoelectric synapse device and select a single-input mode or a dual-input mode according to the complexity of the training data. The signal encoding and weight initialization module is configured to encode the training data into a light pulse sequence and a gate electrical signal sequence according to the selected input mode, and set an initial weight value range corresponding to the classification label, wherein the gate electrical signal sequence corresponds to the initial value of the electrical signal. The initial weight adjustment and gradient calculation module is configured to control the accumulation of electron-hole pairs in the two-dimensional photosensitive layer by adjusting the intensity and duration of the light pulses based on the input light pulse sequence. According to the set initial weight value range, the synaptic weights are initially adjusted, and the local adjustment gradient between the initially adjusted weights and the target weights is calculated. The weight secondary control module is configured to apply a gate bias voltage related to the polarity of the electrical signal based on the initially adjusted synaptic weight, and to perform secondary control on the synaptic weight by combining the timing of presynaptic photostimulation and postsynaptic voltage pulses. The non-volatile storage module is configured to write the synaptic weights after secondary modulation into the non-volatile storage through the ferroelectric modulation layer, forming a weight snapshot of the current training cycle, and storing the weight snapshot. The error feedback and parameter optimization module is configured to calculate the error between the model output and the training data label based on the stored weight snapshot, generate a global error gradient, and dynamically adjust the optical pulse coding parameters and gate voltage amplitude according to the global error gradient.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the training method for the neural network as described in any one of claims 1 to 7.

10. A computer storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the program implements the training method for the neural network as described in any one of claims 1 to 7.

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