Verification method, device and equipment for cross-level connection relation of integrated packaging chip

Abstract

The invention provides a method for verifying a cross-level connection relation of an integrated packaging chip, and relates to the technical field of computers, in particular to the field of chips. According to the specific implementation scheme, in design documents of all design layers of the integrated packaging chip, all design elements used for achieving cross-level connection are recognized; generating a cross-level normative name of each design element, and converting each design element into a unified coordinate space to obtain a global normalized mapping result; according to the definition of each design element in each design document and the normative name of each design element, generating a cross-hierarchy topology mapping table according to a cross-hierarchy connection relation graph; and according to a global normalization mapping result, performing connectivity verification on each signal transmission path in the cross-level topology mapping table to obtain a cross-level connection relation verification result of the integrated packaging chip. According to the scheme, the physical alignment deviation of each design element of the chip can be found in advance, the packaging reworking cost is reduced, and the purpose of preventing assembly failure is achieved.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and more particularly to the field of chips, specifically to a method for verifying cross-level interconnection relationships of an integrated packaged chip, a device for verifying cross-level interconnection relationships of an integrated packaged chip, electronic equipment, non-transitory computer-readable storage media, and computer program products. Background Technology

[0002] As Moore's Law approaches its physical limits, the sustained performance-to-power area (PPA) gains from upgraded process technologies are increasingly challenged, driving system designers to seek heterogeneous integration technologies. Solutions for implementing 3D Integrated Circuits (3DICs) and chiplets through heterogeneous integration offer additional opportunities for system-level functional integration and packaging cost optimization, and are beginning to be widely adopted in areas such as High Performance Computing (HPC), data centers, and high-end routers. Heterogeneous integration presents even greater technical challenges for verification engineers.

[0003] When verifying 3D integrated circuits, related technologies mainly use various design tools to verify a single design layer. This approach cannot effectively detect cross-layer connection conflicts. Alternatively, the entire 3D integrated circuit can be verified by manually comparing the netlist, but this approach is labor-intensive, time-consuming, and prone to errors. Summary of the Invention

[0004] This disclosure provides a method, apparatus, device, storage medium, and computer program product for verifying cross-level connectivity relationships of integrated packaged chips.

[0005] According to one aspect of the embodiments of this disclosure, a method for verifying cross-level interconnection relationships of an integrated packaged chip is provided, comprising:

[0006] In the design documents of each design layer of the integrated package chip, identify the design elements used to implement cross-layer connections;

[0007] Generate standardized names for each design element across different levels, and transform each design element into a unified coordinate space to obtain a globally normalized mapping result;

[0008] Based on the definitions of each design element in each design document and the standardized naming of each design element, a cross-level topology mapping table is generated according to at least one preset cross-level connection relationship diagram.

[0009] The cross-layer topology mapping table includes a plurality of signal transmission paths, and each signal transmission path includes design elements located at different design layers.

[0010] According to the global normalized mapping result, the connectivity of each signal transmission path in the cross-layer topology mapping table is verified, and a cross-layer connection relationship verification result of the integrated package chip is obtained.

[0011] According to another aspect of the embodiments of the present disclosure, a verification device for a cross-layer connection relationship of an integrated package chip is also provided, which includes:

[0012] A design element identification module is configured to identify design elements for realizing cross-layer connections in design documents of each design layer of the integrated package chip.

[0013] A design element specification conversion module is configured to generate a cross-layer specification naming of each design element, and convert each design element into a unified coordinate space respectively, to obtain a global normalized mapping result.

[0014] A topology mapping table generation module is configured to generate a cross-layer topology mapping table according to definitions of each design element in each design document and the specification naming of each design element, and according to a preset at least one cross-layer connection relationship graph.

[0015] The cross-layer topology mapping table includes a plurality of signal transmission paths, and each signal transmission path includes design elements located at different design layers.

[0016] A transmission path verification module is configured to verify the connectivity of each signal transmission path in the cross-layer topology mapping table according to the global normalized mapping result, and obtain a cross-layer connection relationship verification result of the integrated package chip.

[0017] According to another aspect of the embodiments of the present disclosure, an electronic device is also provided, which includes:

[0018] At least one processor; and

[0019] A memory connected in communication with the at least one processor; wherein

[0020] The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method for verifying a cross-layer connection relationship of an integrated package chip according to any one of the embodiments of the present disclosure.

[0021] According to another aspect of the embodiments of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is also provided, where the computer instructions are used to cause a computer to perform the verification method of the cross-level connection relationship of the integrated package chip according to any one of the embodiments of the present disclosure.

[0022] According to another aspect of the embodiments of the present disclosure, a computer program product is also provided, comprising a computer program which, when executed by a processor, implements the steps of the verification method of the cross-level connection relationship of the integrated package chip according to any one of the embodiments of the present disclosure.

[0023] It should be understood that the content described in this section is not intended to identify key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become apparent through the following description. BRIEF DESCRIPTION OF DRAWINGS

[0024] The accompanying drawings are used to better understand the present scheme, and do not limit the present disclosure. Among them:

[0025] Figure 1 is a schematic diagram of a verification method of a cross-level connection relationship of an integrated package chip according to an embodiment of the present disclosure;

[0026] Figure 2 is a schematic diagram of another verification method of a cross-level connection relationship of an integrated package chip according to an embodiment of the present disclosure;

[0027] Figure 3 is a structural diagram of a cross-level connection relationship diagram of an integrated package chip according to an embodiment of the present disclosure;

[0028] Figure 4 is a structural diagram of another cross-level connection relationship diagram of an integrated package chip according to an embodiment of the present disclosure;

[0029] Figure 5 is a structural diagram of a verification device of a cross-level connection relationship of an integrated package chip according to an embodiment of the present disclosure;

[0030] Figure 6 is a block diagram of an electronic device for implementing the verification method of the cross-level connection relationship of the integrated package chip according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] Exemplary embodiments of the present disclosure are described herein with reference to the accompanying drawings, which are cited as illustrative examples. Various details of the embodiments of the present disclosure are described herein in order to provide a thorough understanding of the embodiments. It will be understood by those of ordinary skill in the art that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Also, the descriptions of known functions and constructions are omitted herein for clarity and conciseness.

[0032] Figure 1 is a schematic diagram of a method for verifying a cross-level connection relationship of an integrated package chip according to an embodiment of the present disclosure. The embodiment of the present disclosure can be applied to a case where, after a cross-level topology mapping table is generated based on design elements of each design layer of an integrated package chip, each signal transmission path in the cross-level topology mapping table is verified for connectivity. The method can be executed by a device for verifying a cross-level connection relationship of an integrated package chip. The device can be implemented in software and / or hardware, and can generally be configured in an electronic device having a data processing function, such as various terminals or servers.

[0033] Accordingly, as shown in Figure 1 the method can specifically include:

[0034] S110, in design documents of each design layer of an integrated package chip, identifying each design element used to implement cross-level connection.

[0035] The integrated package chip can be understood as a system-level chip obtained by horizontally interconnecting multiple chips (also referred to as dies or Die) through a silicon interposer, or directly stacking in the vertical direction through a through-silicon via. For example, the integrated package chip can be various heterogeneous chips obtained by 2.5D packaging or 3D packaging.

[0036] In the embodiment, the complete development and design process of the integrated package chip can be hierarchically divided according to the packaging sequence. For example, for an integrated package chip obtained by 2.5D packaging, the integrated package chip can be divided into three design layers: chip layer, interposer layer, and packaging substrate layer. Then, the developers of different design layers can independently implement the design of the design layer and form the corresponding design documents.

[0037] The design element can be understood as a basic constituent unit in the design document. For example, in the design document of a chip layer, the design element can be a specific input / output (I / O) port in a specific chip, or a specific micro bump (also referred to as μBump), and so on. For example, in the design document of an interposer layer, the design element can be a specific through-silicon via (TSV) or a specific rerouting track, or in the design document of a package substrate layer, the design element can be a specific soldering point (also referred to as solder ball) on a specific ball grid array (BGA) pad or a specific layout routing track, and so on.

[0038] Optionally, in the design document of each design layer, specific design parameters of each design element included in the design layer, a specific layout position (relative or absolute position) of each design element in the design layer, a connection relationship between different design elements, and a connection relationship between each design element and one or more design elements in an adjacent one or more design layers, and the like design information are defined.

[0039] The design elements in the cross-layer connection can be understood as each circuit element (for example, an I / O port of a chip or a specific soldering point), a physical connection structure (for example, a specific micro bump or a specific through-silicon via), and a physical connection track, and the like required to be passed through by a cross-layer signal transmission path after an integrated package chip actually works.

[0040] The cross-layer signal transmission path specifically refers to a signal transmission path across design layers. For example, a signal transmission path from an I / O port of one chip to an I / O port of another chip through an interposer, or a signal transmission path from an I / O port of one chip to a specific soldering point on a BGA pad through an interposer and a package substrate, and so on.

[0041] In this embodiment, all possible design elements included in each type of cross-layer signal transmission path can be collected in advance, and the design document to which each design element belongs can be determined, and then each design element used to implement the cross-layer connection can be effectively identified in the design document of each design layer by means of keyword matching.

[0042] S120, generating a cross-layer specification naming of each design element, and converting each design element into a unified coordinate space to obtain a global normalized mapping result.

[0043] The cross-level normative naming can be a set of unified naming rules established for different levels and different types of design elements, so that the design element naming logic of each design level of the integrated package chip is consistent, and each design element through which a cross-level signal transmission path passes can be confirmed.

[0044] For example, a cross-level signal transmission path includes a chip input / output port of a chip layer, a through silicon via in an interposer layer, and a solder point in a ball grid array pad on a package substrate layer. The chip input / output port on the path can be named Die1_A1_P1, the through silicon via on the path can be named Interposer1_TSV1_0, and the solder point on the path can be named Package 1_BGA1_Ball1_0.

[0045] In the naming method, Die1, Interposer1, and Package1 are used to represent that the three design elements located in the chip layer, the interposer layer, and the package substrate layer, respectively, have a direct connection relationship, and the three design elements are located on a cross-level signal transmission path. A1_P1 represents a P1 port on an A1 chip in the chip layer, TSV1_0 represents a specific through silicon via identified as 1_0 in the interposer layer, and BGA1_Ball1_0 represents a Ball1_0 solder point in a BGA1 ball grid array pad in the package substrate layer.

[0046] The unified coordinate space can be a global coordinate system in which a plurality of local coordinate systems originally independent of each other are integrated through explicit mathematical rules (such as translation, rotation, or scaling), so that the positions of all objects can be uniquely and accurately described and calculated in the unified framework. For example, the origins and coordinate distance measurement units of the local coordinate systems of the chip, the interposer, and the package substrate are different. The unified coordinate space is a conversion of the three local coordinate systems to a unified global coordinate system, and the positions of the design elements of each level are represented in the same coordinate system. The conversion of the local coordinate system to the global coordinate system can use the following formula:

[0047] [X_global, Y_global] = T_rotation · S_scale · [X_local, Y_local] + [ΔX, ΔY] Wherein, X_global is the horizontal axis coordinate in the global coordinate system, Y_global is the vertical axis coordinate in the global coordinate system, X_local is the horizontal axis coordinate in the local coordinate system, Y_local is the vertical axis coordinate in the local coordinate system, T_rotation is a rotation matrix, S_scale is a scaling factor, and [ΔX, ΔY] is a translation vector.

[0048] The global normalized mapping result can be the result of unified, accurate and directly usable coordinate system data obtained after the local coordinate system of each design layer is converted into a unified global coordinate system. For example, in the above coordinate system conversion formula, the horizontal axis coordinate X_global in the global coordinate system and the vertical axis coordinate Y_global in the global coordinate system are both global normalized mapping results obtained after the coordinate conversion of each design layer unifies the coordinate space.

[0049] In the embodiment, the design elements can be named according to the cross-level signal transmission path to which they belong, and the electrical connection relationship between the design elements of different levels can be determined through the naming method of the design elements. In addition, by representing the positions of the design elements in the unified global coordinate system to obtain the global normalized mapping result, the design elements located at different levels or different planes can be labeled in a unified plane. Further, accurate reference data sources can be provided for subsequent cross-level connection relationship verification processes.

[0050] S130, according to the definition of each design element in each design document and the standardized naming of each design element, a cross-level topology mapping table is generated according to a preset at least one cross-level connection relationship diagram.

[0051] The cross-level topology mapping table can include a plurality of signal transmission paths, and each signal transmission path can include design elements located at different design layers.

[0052] The topology mapping table can be a structured data table or document used to clearly define the correspondence between design elements and signal paths in the chip integration process. It is used to confirm the accuracy and consistency of signal paths, design element calls and function implementations. For example, the topology mapping table records a cross-level signal transmission path and the design elements contained therein in the chip integration process. Whether the design elements belong to the same signal transmission path and are consistent with the design can be confirmed according to the naming of the design elements in the record.

[0053] In the embodiment, the connection relationship of each design element can be confirmed according to the definition and the standard naming of each design element in the design document, and the design elements with the connection relationship across the hierarchy confirmed are generated in the connection order to form a connection relationship graph. The signal transmission path formed according to the connection relationship in the relationship graph and the design elements contained are recorded uniformly, and different signal transmission paths and the records of the design elements located at different hierarchy levels contained can be obtained according to different connection relationship graphs, which together constitute the cross-hierarchy topology mapping table.

[0054] In other words, the reasonable construction form of the signal transmission path is defined in the cross-hierarchy connection relationship graph, for example, the signal flows from a port of a chip into another port in another chip through one or more through silicon vias, or the signal flows from a port in a chip into a solder joint in a ball grid array pad through multiple through silicon vias, etc. The above cross-hierarchy connection relationship graph can be obtained by analyzing the signal transmission characteristics of various system-level chips of the same type as the integrated package chip, and by manually processing or inputting into a large model.

[0055] Then, one or more cross-hierarchy connection relationship graphs constructed can be used as a template to generate a plurality of specific signal transmission paths suitable for the integrated package chip to form a cross-hierarchy topology mapping table.

[0056] S140, according to the global normalized mapping result, the connectivity of each signal transmission path in the cross-hierarchy topology mapping table is verified, and the cross-hierarchy connection relationship verification result of the integrated package chip is obtained.

[0057] The connectivity verification can include verifying whether the design elements located on the same signal transmission path are connected and the transmission effect of the signal after connection, and can also include verifying whether the design elements without connection relationship recorded in the cross-hierarchy topology mapping table are connected, and finally obtaining the verification result of the entire integrated package chip.

[0058] In the embodiment, the global normalized mapping result can represent the positions of the design elements located at different hierarchy levels in the same coordinate system, which facilitates accurate positioning of the positions of each design element according to the unified coordinate system standard. The connection relationship of each design element is recorded in the cross-hierarchy topology mapping table, and the design elements located on the same signal transmission path are represented by standard naming, and then the signal transmission path and the design elements contained can be confirmed according to the cross-hierarchy topology mapping table and the connectivity verification is performed.

[0059] The technical scheme of the embodiments of the present disclosure generates a global normalization mapping result by identifying each design element for realizing cross-level connection in the design documents of each design layer of the integrated package chip, generating a specification naming, and converting each design element into a unified coordinate space. According to the definition of each design element in each design document and the specification naming of each design element, a cross-level topology mapping table is generated according to a preset cross-level connection relationship diagram. Finally, according to the global normalization mapping result, the connectivity of each signal transmission path in the cross-level topology mapping table is verified, and a cross-level connection relationship verification result of the integrated package chip is obtained. The full-link automatic inspection of the multi-level package integrated package chip is realized, and the manual intervention is minimized. Through the topology mapping table, the conflict level is quickly located, the error is efficiently located, and the heterogeneous integration can be supported, and the multiple chips integrated by different processes are compatible. The physical alignment deviation of each design element in the integrated package chip can be found in advance, the packaging rework cost is reduced, and the purpose of preventing assembly failure is achieved.

[0060] Figure 2 is a schematic diagram of a method for verifying a cross-level connection relationship of an integrated package chip according to an embodiment of the present disclosure. Based on the above embodiments, the operation of "generating a cross-level topology mapping table according to the definition of each design element in each design document and the specification naming of each design element according to at least one preset cross-level connection relationship diagram" is specified as "obtaining a target cross-level connection relationship diagram to be processed, and obtaining a target node set according to the node connection order defined in the target cross-level connection relationship diagram; obtaining a plurality of first design element sets matched with the target node set according to the specification naming of each design element; obtaining a second design element set for connecting adjacent target design elements in each first design element set according to the design document of each design layer; combining each first design element set and the second design element set matched with each first design element set to form a plurality of signal transmission paths".

[0061] In addition, the operation of "verifying the connectivity of each signal transmission path in the cross-level topology mapping table according to the global normalization mapping result, and obtaining a cross-level connection relationship verification result of the integrated package chip" is specified as "detecting a first detection pair, a second detection pair, and a third detection pair, and matching each signal transmission path in the cross-level topology mapping table with a standard netlist of the target integrated package chip to obtain an abnormal signal transmission path inconsistent with the definition content of the standard netlist".

[0062] Correspondingly, as shown in Figure 2 , the method can specifically include:

[0063] S210, identifying each design element for implementing the cross-layer connection in the design document of each design layer of the integrated package chip.

[0064] In the embodiment, the integrated package chip can include a system-level chip formed by fixing multiple chips on a chip layer on a package substrate layer through an interposer. That is, the integrated package chip is a system-level chip packaged through a Die-Interposer-Package (chip-interposer-package) packaging technology.

[0065] S220, generating a specification name of each design element across layers, and converting each design element into a unified coordinate space to obtain a global normalized mapping result.

[0066] S230, obtaining a target cross-layer connection relationship graph currently processed, and obtaining a target node set according to a node connection order defined in the target cross-layer connection relationship graph.

[0067] Each cross-layer connection relationship graph is sequentially concatenated by at least two nodes and at least one edge; each node and each edge are the design elements of a specified type.

[0068] Specifically, in the embodiment, the cross-layer connection relationship graph is a signal transmission path. Figure 3 and Figure 4 Two optional cross-layer connection relationship graphs are respectively shown in the embodiment. In the cross-layer connection relationship graph as shown in the embodiment, an electrical signal can be transmitted from one input / output port of one chip to one of the solder joints in the ball grid array pad through a micro bump, a through silicon via, a redistribution track, and a package trace. Figure 3 Similarly, in the cross-layer connection relationship graph as shown in the embodiment, an electrical signal can be transmitted from one input / output port of one chip to one input / output port of another chip through a micro bump, a through silicon via, a redistribution track, and another micro bump.

[0069] Figure 4 Through the above setting, a standardized signal transmission path construction template can be formed, and a cross-layer topology mapping table can be obtained efficiently and accurately.

[0070] Through the above setting, a standardized signal transmission path construction template can be formed, and a cross-layer topology mapping table can be obtained efficiently and accurately.

[0071] ​As described above, when the integrated package chip is a Die-Interposer-Package chip, the node can include at least one of the following: an input / output port of each chip in the chip layer, a through-silicon via in the interposer layer, and a solder joint in a ball grid array pad on the package substrate layer.

[0072] Correspondingly, the edge can include at least one of the following: a micro bump in the chip layer, a redistribution layer in the interposer layer, and a package trace on the package substrate layer.

[0073] Optionally, as shown in Figure 3 the target node set corresponding to the target cross-level connection relationship diagram can include: an input / output port in a chip, at least one through-silicon via, and a solder joint in a ball grid array pad;

[0074] Alternatively, as shown in Figure 4 the target node set corresponding to the target cross-level connection relationship diagram can further include: an input / output port in a chip, a plurality of through-silicon vias, and an input / output port in another chip.

[0075] In the embodiment, the integrated package chip includes a chip layer, an interposer layer, and a package substrate layer. When the target node set includes: an input / output port in a chip, at least one through-silicon via, and a solder joint in a ball grid array pad, then the design element of a cross-level signal transmission path corresponding to the target node involves the three levels of the chip layer, the interposer layer, and the package substrate layer. When the target node set includes: an input / output port in a chip, a plurality of through-silicon vias, and an input / output port in another chip, then the design element of a cross-level signal transmission path corresponding to the target node involves the two levels of the chip layer and the interposer layer.

[0076] Through the above setting, the design element of the same cross-level signal transmission path can be quickly confirmed according to the different design element constitutions of the target node set, and a cross-level topology mapping table can be generated.

[0077] S240, according to the specification naming of each design element, obtaining a plurality of first design element sets matched with the target node set.

[0078] The first design element set can be a set of design elements according to the standard naming of the design elements, and the set of all nodes belonging to the same cross-level signal transmission path is identified. The nodes in the set can come from two different levels or three different levels. For example, by traversing the naming of the design elements, it is found that there is a chip input / output port named Die1_A1_P1, a through silicon via named Interposer1_TSV1_2, and a solder joint named Package1_BGA1_Ball1_0. The signal transmission path identifiers of the above design element names are all "1" (i.e., Die1, Interposer1, and Package1), indicating that the three design elements are located in the same cross-level signal transmission path. Therefore, the three design elements form a first design element set.

[0079] Correspondingly, in an optional embodiment of the embodiment, when the target node set corresponding to the target cross-level connection relationship graph is an input / output port in a chip, at least one through silicon via, and a solder joint in a ball grid array pad, the obtaining of the first design element set matched with the target node set according to the standard naming of each design element can include:

[0080] S2401, in the design document of the chip layer, obtaining a target input / output port corresponding to a target chip currently being processed.

[0081] Specifically, the standard naming of each design element is searched in the design document of the chip layer, and the input / output port corresponding to the target chip currently being processed is obtained through the chip attribute and port attribute indicated in the naming. For example, the target chip currently being processed is chip B0, and the target input / output port corresponding to the chip B0 is P2. By searching in the design document of the chip layer, a design element named Die0_B0_P2 is obtained in the chip layer design document, which is the port P2 on the chip B0. Based on Die0 in the Die0_B0_P2, it is indicated that the cross-level signal transmission path identifier of the design element is 0.

[0082] S2402, according to the standard naming of the target input / output port, obtaining at least one target through silicon via matched with the target input / output port in the design document of the intermediate layer.

[0083] Specifically, according to the naming of the target chip input and output port in the above steps, the identification of the cross-layer signal transmission path where the target chip input and output port is located is confirmed, and according to the identification, the normative naming of each design element in the design document of the interposer is searched, and the target through silicon via with the same identification as the searched cross-layer signal transmission path is confirmed through the through silicon via attribute indicated in the naming. For example, the normative naming of the target input and output port is Die0_B0_P2, the identification of the cross-layer signal transmission path where the target input and output port is located is 0, and it is assumed that the through silicon via named Interposer0_TSV0_1 is found in the design document of the interposer, then the through silicon via is the target through silicon via in the same cross-layer signal transmission path as the target input and output port Die0_B0_P2.

[0084] Further, it is assumed that Interposer0_TSV0_1 and Interposer0_TSV1_1 are found in the design document of the interposer at the same time, then the above two through silicon vias are both target through silicon vias in the same cross-layer signal transmission path as the target input and output port Die0_B0_P2.

[0085] S2403, according to the normative naming of each target through silicon via, detection is performed in the design document of the packaging substrate layer.

[0086] Similar to the operation of S2402, detection can also be continued in the design document of the packaging substrate layer according to the normative naming of each target through silicon via, and it is judged whether the packaging substrate layer has a target solder point on the target ball grid array pad in the same cross-layer signal transmission path as the target input and output port and each target through silicon via.

[0087] S2404, it is judged whether a target solder point on a target ball grid array pad matching the target through silicon via is detected, if yes, S2405 is executed, and if no, S2406 is executed.

[0088] Specifically, a cross-layer signal transmission path can be composed of different design elements of two levels of chip layer and interposer, or composed of different design elements of three levels of chip layer, interposer and packaging substrate layer, therefore, after confirming the input and output port from the chip layer and the through silicon via from the interposer in the same cross-layer signal transmission path according to the above steps, it is needed to judge whether the path contains a target solder point on a target ball grid array pad matching the target through silicon via from the packaging substrate layer, if the path contains the target solder point, S2405 is executed, otherwise, S2406 is executed.

[0089] S2405, if the target solder joint on the target ball grid array pad matching the target through silicon via is detected, the target input / output port of the target chip, at least one target through silicon via and the target solder joint on the target ball grid array pad are organized to obtain a first design element set.

[0090] Specifically, according to the normative naming of the target through silicon via in the above steps, the identification of the cross-level signal transmission path is confirmed, and according to the identification, the normative naming of each design element is searched in the design document of the packaging substrate layer to confirm the target solder joint on the target ball grid array pad matching the target through silicon via.

[0091] Continuing the previous example, the normative naming of the target through silicon via is Interposer0_TSV0_1, and the identification of the cross-level signal transmission path where it is located is 0. Further, if the solder joint named Package0_BGA1_Ball1_2 is found in the design document of the packaging substrate layer, it is determined that the target solder joint Ball1_2 on the target ball grid array pad BGA1 which is located in the same cross-level signal transmission path as the target input / output port and each target through silicon via is obtained.

[0092] S2406, return to execute the operation of obtaining a target input / output port corresponding to the target chip currently processed in the design document of the chip layer until the processing of all input / output ports of all chips in the chip layer is completed.

[0093] It can be understood that in the process of obtaining a plurality of first design element sets matching the target node set belonging to the same cross-level signal transmission path, the matching starts from the input / output port of each chip in the chip layer, and according to the normative naming of the target input / output port of each target chip, the identification of the cross-level signal transmission path where it is located is confirmed, and then the target through silicon via located in the interposer and the target solder joint on the target ball grid array pad located in the packaging substrate layer are sequentially confirmed to constitute the first design element set belonging to the same cross-level signal transmission path. The above steps are executed in a loop to complete the traversal of all input / output ports of the target chips in the chip layer, and finally the first design element set of all cross-level signal transmission paths corresponding to the target node set is confirmed.

[0094] Through the above setting, the chip input / output port in the chip layer, the target through silicon via in the interposer and the target solder joint on the target ball grid array pad in the packaging substrate layer belonging to the same cross-level signal transmission path can be confirmed, and the efficiency of sorting the nodes contained in the three levels of the cross-level signal transmission path is improved.

[0095] In another optional implementation of the embodiment, when the target node set corresponding to the target cross-level connection relationship graph can also include: an input / output port in a chip, a plurality of through silicon vias, and an input / output port in another chip, the obtaining, according to the canonical naming of each design element, of a plurality of first design element sets matched with the target node set can include:

[0096] S2411, in the design document of the chip layer, obtaining a target input / output port corresponding to a target chip currently processed.

[0097] Specifically, the design document of the chip layer records the canonical naming of the chip input / output port, which contains the identification information of the chip input / output port and the cross-level signal transmission path where the chip input / output port is located. Through the information, the canonical naming information of the target input / output port corresponding to the target chip currently processed can be obtained.

[0098] S2412, according to the canonical naming of the target input / output port, obtaining a plurality of target through silicon vias matched with the target input / output port in the design document of the interposer layer.

[0099] Specifically, the canonical naming of the target chip input / output port in the above step confirms the identification of the cross-level signal transmission path where the target chip input / output port is located. The canonical naming of each through silicon via in the design document of the interposer layer is searched, and the target through silicon via whose canonical naming is consistent with the confirmed identification of the cross-level signal transmission path is searched. When the cross-level signal transmission path only involves the chip layer and the interposer layer, the same cross-level signal transmission path can include a plurality of target through silicon vias for connecting the target input / output ports of different target chips. For example, the canonical naming of the target input / output port of the target chip confirmed in the above step is Die0_B0_P2, and the identification of the cross-level signal transmission path where the target input / output port is located is 0. The through silicon vias with canonical naming of Interposer0_TSV1_3 and Interposer0_TSV2_5 exist in the interposer layer, indicating that the identification of the cross-level signal transmission path where the two through silicon vias are located is 0. Therefore, Interposer0_TSV1_3 and Interposer0_TSV2_5 are both target through silicon vias.

[0100] S2413, according to the canonical naming of each target through silicon via, continuing to detect in the design document of the chip layer.

[0101] S2414, judging whether an associated input / output port of an associated chip matched with the target input / output port of the target chip is detected, if yes, executing S2415, and if no, executing S2416.

[0102] S2415, if the associated input / output port of the associated chip matching the target input / output port of the target chip is detected, the target input / output port of the target chip, the plurality of target through silicon vias and the associated input / output port of the associated chip are organized to obtain a first design element set.

[0103] Specifically, the identity of the cross-level signal transmission path where the target input / output port of the target chip is located is confirmed according to the canonical naming of the target input / output port of the target chip found in the above steps, and according to the identity, the associated chip input / output port with the same identity is found in the design document of the chip layer. The target input / output port of the target chip and its matching associated chip input / output port, and the plurality of target through silicon vias found together constitute a first design element set. For example, the canonical naming of the target input / output port of the target chip currently being processed obtained in S2411 is Die3_B1_P5, and it is known that the identity of the cross-level signal transmission path where it is located is 3. Two target through silicon vias belonging to the same cross-level signal transmission path, Interposer3_TSV1_2 and Interposer3_TSV2_3, can be found in the interposer layer accordingly, and further the associated chip input / output port belonging to the same cross-level signal transmission path, Die3_C1_P1, can be found in the chip layer. The above design elements Die3_B1_P5, Interposer3_TSV1_2, Interposer3_TSV2_3 and Die3_C1_P1 constitute a first design element set.

[0104] S2416, return to execute the operation of obtaining a target input / output port corresponding to the target chip currently being processed in the design document of the chip layer until the processing of all input / output ports of all chips in the chip layer is completed.

[0105] It can be understood that according to the canonical naming of the target input / output port of the target chip currently being processed, the identity of the cross-level signal transmission path where it is located is confirmed by matching from the chip layer, and then the target through silicon via located in the interposer layer and the associated chip input / output port located in the chip layer are sequentially confirmed to constitute the first design element set belonging to the same cross-level signal transmission path. Through the traversal of all target chip input / output ports in the chip layer, the above steps are completed, and finally the first design element set of all cross-level signal transmission paths corresponding to the target node set is confirmed.

[0106] Through the above setting, the chip input / output port of the chip layer and its associated chip input / output port belonging to the same cross-level signal transmission path, and the target through silicon via of the interposer layer can be confirmed, and the efficiency of combing the nodes of the chip layer and the interposer layer included in the cross-level signal transmission path is improved.

[0107] S250, according to the design document of each design layer, a second design element set for connecting adjacent target design elements in each of the first design element sets is obtained.

[0108] The second design element set can be a set of edges connecting different nodes in the same first design element set. For example, the nodes of the first design element set that have been confirmed include a chip input / output port Die0_A1_P0, a through-silicon via Interposer0_TSV1_2, and a target solder joint Package0_BGA1_Ball1_2 on a ball grid array pad. The cross-level signal transmission path identifiers of the above nodes are both "0". In the same cross-level signal transmission path, a micro bump μBump0_3 is used to connect the chip input / output port Die0_A1_P0 and the through-silicon via Interposer0_TSV1_2, and a package trace Trace1_0 is used to connect the through-silicon via Interposer0_TSV1_2 and the target solder joint Package0_BGA1_Ball1_2 on the ball grid array pad. Therefore, the micro bump μBump0_3 and the package trace Trace1_0 constitute a second design element set corresponding to the above-confirmed first design element set.

[0109] Correspondingly, in an optional implementation of the embodiment, the step of obtaining, according to the design document of each design layer, a second design element set for connecting adjacent target design elements in each of the first design element sets can include:

[0110] S2501, a target first design element set that is currently processed is obtained.

[0111] S2502, in the design document of the chip layer, a target micro bump that matches an input / output port of a chip included in the target first design element set is obtained.

[0112] Specifically, the nodes of the target first design element set include a chip input / output port located in the chip layer and a through-silicon via located in the interposer layer, and the edge connecting the two nodes is a micro bump. The specification name of the micro bump can be found in the design document of the chip layer, and the micro bump that matches the target chip input / output port can be found. For example, the chip input / output port in the target first design element set is Die0_A1_P0, and the identifier of the cross-level signal transmission path where the chip input / output port is located is "0". Therefore, the micro bump μBump0_5 located in the same cross-level signal transmission path can be found in the design document of the chip layer.

[0113] Alternatively, considering that the connection relationship of various design elements is also recorded in the design document of the interposer layer, typically, there is a one-to-one correspondence between the input / output port of the chip and the micro bump on the chip. Further, by directly searching in the design document of the interposer layer based on the input / output of the chip included in the target first design element set, the target micro bump can also be obtained.

[0114] S2503, in the design document of the interposer layer, obtaining a redistribution track for connecting two through silicon vias in the target first design element set, or a redistribution track connecting a target micro bump and a through silicon via in the target first design element set.

[0115] It can be understood that the same cross-level signal transmission path can include multiple through silicon vias connected by redistribution tracks in the redistribution layer. When the micro bump of the chip layer and the through silicon via of the interposer layer in the same cross-level signal transmission path are not aligned, the redistribution track can be connected. For example, a cross-level signal transmission path includes two through silicon vias Interposer0_TSV1_2 and Interposer0_TSV1_3 and a micro bump μBump0_5, wherein the through silicon via Interposer0_TSV1_2 is connected to the through silicon via Interposer0_TSV1_3 and the micro bump μBump0_5 of the chip layer, and the redistribution track Interposer0_RDL1 for connecting the micro bump μBump0_5 and the through silicon via Interposer0_TSV1_2 can be obtained by querying the standard naming of the redistribution track in the interposer layer, wherein the "0" in the standard naming Interposer0_RDL1 indicates the identification of the cross-level signal transmission path, and accordingly, the redistribution track Interposer0_RDL1 for connecting the two through silicon vias Interposer0_TSV1_2 and Interposer0_TSV1_3 can be found.

[0116] Similarly, considering that the connection relationship of various design elements is also recorded in the design document of the interposer layer, further, the corresponding redistribution track can be directly found in the design document of the interposer layer based on two through silicon vias in the target first design element set, or based on a target micro bump and a through silicon via in the target first design element set.

[0117] S2504, in the design document of the interposer layer, obtaining a redistribution track for connecting two through silicon vias in the target first design element set, or a redistribution track connecting a target micro bump and a through silicon via in the target first design element set.

[0118] Specifically, the nodes of the target first design element set include a through-silicon via located at the interposer layer and a solder joint on a ball grid array pad located at the package substrate layer, and the edge connecting the two nodes is a package trace. The package trace used to connect the through-silicon via and the solder joint on the ball grid array pad can be found through the normative naming of the package trace recorded in the design document of the package substrate layer. For example, the through-silicon via Interposer0_TSV1_0 and the target solder joint Package0_BGA1_Ball1_2 on the ball grid array pad in the target first design element set are located at the same cross-level signal transmission path with an identifier of "0", and the package trace Trace0_1 located at the same cross-level signal transmission path can be found through the design document of the package substrate layer.

[0119] S2505, the successfully acquired target micro-bump, re-wiring trace and package trace form a second design element set corresponding to the target first design element set.

[0120] Through the above arrangement, the edges used to connect adjacent nodes in the first design element set can be efficiently and accurately acquired, and the efficiency of constructing the signal transmission path is improved.

[0121] S260, the first design element set and the second design element set matched with the first design element set are combined to form a plurality of signal transmission paths.

[0122] Specifically, the first design element set contains nodes located at the same cross-level signal transmission path, and the second design element set contains edges located at the same cross-level signal transmission path as the corresponding first design element set. By combining the nodes and edges in the two sets according to the cross-level signal transmission path, a plurality of signal transmission paths involving the chip layer, the interposer layer and the package substrate layer can be obtained.

[0123] Through the above arrangement, the nodes and edges belonging to the same cross-level signal transmission path can be confirmed, and the efficiency of confirming the specific composition of the cross-level signal transmission path by combing the design elements is improved.

[0124] S270, according to the global normalized mapping result, the connectivity of each signal transmission path in the cross-level topology mapping table is verified to obtain a cross-level connection relationship verification result of the integrated package chip.

[0125] In an optional implementation of the embodiment, the target signal transmission path currently processed is obtained from the cross-level topology mapping table, and adjacent nodes and edges, and adjacent edges and nodes are sequentially extracted according to the path extension order of the target signal transmission path, to construct a plurality of first detection pairs; in the global normalized mapping result, the interval distance between the nodes and edges in each first detection pair is obtained, and a target first detection pair with an interval distance greater than a preset distance threshold is determined to exist signal open circuit abnormality.

[0126] Specifically, the signal transmission path in the cross-level topology mapping table includes a plurality of nodes and edges located in the chip layer, the interposer layer and the package substrate layer, and the sequentially directly connected nodes and edges, and the combination of edges and nodes on the path can be confirmed according to the order of the target signal transmission path currently processed. These combinations constitute first detection pairs, and whether a signal open circuit abnormality exists is determined by detecting whether the physical interval distance between the nodes and edges in the same detection pair is greater than a preset distance threshold.

[0127] For example, on the cross-level signal transmission path identified as 0, it includes a chip input / output port Die0_A1_P0, a through silicon via Interposer0_TSV1_2, and a micro bump Die0_μBump0_3 used to connect the two nodes. According to the order of extending from the chip layer to the interposer layer and then to the package substrate layer, the chip input / output port Die0_A1_P0 and the micro bump Die0_μBump0_3 can constitute a first detection pair composed of directly connected nodes and edges.

[0128] By obtaining the specific position coordinate range of Die0_A1_P0 and Die0_μBump0_3 in the global normalized mapping result, the physical interval distance between Die0_A1_P0 and Die0_μBump0_3 can be calculated. For example, the center point coordinates of Die0_A1_P0 and Die0_μBump0_3 can be obtained respectively, and then the distance between the above two center point coordinates is calculated as the above physical interval distance.

[0129] Further, if the physical interval distance of Die0_A1_P0 and Die0_μBump0_3 is greater than the preset distance threshold, it is determined that the first detection pair (i.e., between Die0_A1_P0 and Die0_μBump0_3) exists signal open circuit abnormality, and if the physical interval distance of Die0_A1_P0 and Die0_μBump0_3 is less than or equal to the preset distance threshold, it is determined that the signal connection relationship between Die0_A1_P0 and Die0_μBump0_3 is normal.

[0130] As described in the foregoing example, the micro bump Die0_μBump0_3 and the through silicon via Interposer0_TSV1_2 can constitute a first detection pair composed of a straight connection edge and a node. If the physical spacing distance between the Die0_μBump0_3 and the Interposer0_TSV1_2 is greater than a preset distance threshold, the first detection pair has a signal open circuit abnormality. Otherwise, the signal connection relationship of the first detection pair is normal.

[0131] Through the above setting, the adjacent nodes and edges and the spacing distance between the adjacent nodes and edges can be sequentially confirmed, and whether the connected nodes and edges have a signal open circuit abnormality can be efficiently confirmed.

[0132] In another optional embodiment of the present embodiment, in the global normalized mapping result, each second detection pair having a spacing distance less than or equal to a preset distance threshold is identified, wherein the second detection pair can include two design elements located at different design layers; in each signal transmission path in the cross-layer topology mapping table, whether the two design elements in each second detection pair have a straight connection relationship is detected; and a target second detection pair not having a straight connection relationship is determined to have a signal short circuit abnormality.

[0133] Specifically, according to the global normalized mapping result, the positions of the design elements located at different design layers can be represented in a unified global coordinate system. The physical positions of all design elements are traversed, and two design elements having a spacing distance less than or equal to a preset distance threshold constitute a second detection pair. According to the signal transmission paths recorded in the cross-layer topology mapping table, whether the two design elements in each second detection pair have a straight connection relationship is detected. If there is no straight connection relationship, the two design elements in the second detection pair have a short circuit abnormality.

[0134] Specifically, since the same design element can appear in different signal transmission paths, the design element has different names in different signal transmission paths when the design element is named in a cross-layer manner. When verifying some types of cross-layer connection relationships, considering that different design elements have unique identification marks, in order to avoid complexity, the naming for identifying the signal transmission path can be removed accordingly, for example, Die0_μBump1_3 is directly identified as μBump1_3.

[0135] In another example, the micro bump μBump1_3 and the through silicon via TSV1_2 are physically spaced apart by a distance less than a preset distance threshold, forming a second detection pair. If it is confirmed through searching the signal transmission paths recorded in the cross-level topology mapping table that the micro bump μBump1_3 and the through silicon via TSV1_2 are located in different signal transmission paths, that is, the micro bump μBump1_3 and the through silicon via TSV1_2 do not have an electrical connection relationship, it is confirmed that the micro bump μBump1_3 and the through silicon via TSV1_2 have a short circuit abnormality.

[0136] Through the above setting, two design elements not belonging to the same cross-level signal transmission path can be sorted out, and it can be efficiently confirmed whether the two design elements not having a direct connection relationship have a signal short circuit abnormality.

[0137] In another optional embodiment of the present embodiment, in each signal transmission path in the cross-level topology mapping table, the micro bump and the through silicon via having a direct connection relationship are obtained, and a plurality of third detection pairs are constructed. In the global normalized mapping result, the coverage area shape corresponding to each of the third detection pairs is obtained. The similarity between each coverage area shape and a standard circle is detected, and it is determined that a target third detection pair having a similarity less than or equal to a preset similarity threshold has an electrical characteristic abnormality.

[0138] Specifically, the signal transmission paths recorded in the cross-level topology mapping table can be used to confirm a plurality of nodes and edges located in the same path. According to the target signal transmission path currently processed, the micro bump and the through silicon via having a direct connection relationship form a third detection pair. Since the two types of design elements having a direct connection relationship are located in different design layers, the position coordinate range of each design element in each first detection pair in the global normalized mapping result is queried. Then, the similarity between the shape of the physical coverage area of the two design elements having a direct connection relationship and a standard circle is detected to confirm whether the third detection pair has an electrical characteristic abnormality. When the similarity is less than or equal to a preset similarity threshold, it is determined that the target third detection pair formed by the two elements having a direct connection relationship has an electrical characteristic abnormality, otherwise, the electrical characteristic is normal.

[0139] That is, when a specific micro bump and another specific through silicon via in the integrated package chip are connected by a direct connection method, the more the contact areas of the two coincide, the better the connectivity of the two is, and thus the better the electrical performance between the two is. Since the micro bump and the through silicon via are both circular structures, the physical coverage area between the two can be determined according to the position coordinate range of the two directly connected micro bump and through silicon via. The more the physical coverage area approaches a circle, the better the electrical performance of the two is; otherwise, it is determined that the electrical performance between the two has an electrical characteristic abnormality.

[0140] By the above setting, the position coordinate range of the micro-bump and the through silicon via having the direct connection relationship in the global normalization mapping result can be confirmed, and then whether the electrical characteristic abnormality exists between the two design elements can be efficiently confirmed through the similarity between the shape of the physical coverage area of the two design elements and the standard circle.

[0141] In another optional implementation of the embodiment, each signal transmission path in the cross-level topology mapping table is matched with the standard netlist of the target integrated package chip respectively, and an abnormal signal transmission path inconsistent with the definition content of the standard netlist is obtained.

[0142] The standard netlist can be a structured text file describing the connection relationship between all hardware units and signals inside a chip or a package in an industry general format. In the design and manufacturing process of the integrated package chip, it is used to connect different links such as chip front-end design, back-end layout and wiring, packaging collaborative design, simulation verification, and ensure that all participants have a complete understanding of how the hardware is connected.

[0143] Specifically, the cross-level topology mapping table is used to verify the cross-level connection relationship of the integrated package chip, and the cross-level signal transmission paths composed of each design element are recorded in the cross-level topology mapping table. The standard net of the target integrated package chip is used as a standard table for matching, and it is judged whether the signal transmission paths recorded in the cross-level topology mapping table are consistent. The signal transmission paths that are not consistent are regarded as abnormal.

[0144] Through the above setting, the standard net of the target integrated package chip can be used to efficiently confirm whether the signal transmission paths recorded in the generated cross-level topology mapping table are correct.

[0145] The technical scheme of the embodiment of the present disclosure identifies each design element for realizing cross-level connection in each design layer of the integrated package chip, generates a normative naming and converts each design element into a unified coordinate space respectively to obtain a global normalized mapping result. According to the definition of each design element in each design document and the normative naming of each design element, a cross-level topology mapping table is generated according to a preset cross-level connection relationship graph. Specifically, the first design element set and the corresponding second design element set of different target node sets are confirmed according to each signal transmission path in the cross-level topology mapping table, and different detection pairs are formed according to the connection relationship of nodes and edges in different levels. Detection is performed on open circuit, short circuit and electrical characteristics respectively, and the correctness of the cross-level topology mapping table is confirmed through the standard netlist of the target integrated package chip to complete the verification of the cross-level connection relationship of the entire integrated package chip. The connection of different nodes and edges in the Die-Interposer-Package full link is detected, and the open circuit, short circuit and electrical characteristic abnormalities that may exist in the link are detected. The physical alignment deviation of each design element of the chip and the electrical characteristics form a comprehensive and effective detection, and the cross-level topology mapping table for detection is matched and confirmed to ensure the verification effect of the cross-level relationship of the integrated package chip.

[0146] As an implementation of the method for verifying the cross-level connection relationship of the integrated package chip, the present disclosure further provides an optional embodiment of an execution device for implementing the method for verifying the cross-level connection relationship of the integrated package chip.

[0147] Figure 5 FIG. 5 is a structural diagram of a device for verifying the cross-level connection relationship of an integrated package chip according to an embodiment of the present disclosure. As shown in FIG. 5, the device can include a design element identification module 510, a design element specification conversion module 520, a topology mapping table generation module 530, and a transmission path verification module 540.

[0148] The design element identification module 510 is configured to identify each design element for realizing cross-level connection in the design document of each design layer of the integrated package chip.

[0149] The design element specification conversion module 520 is configured to generate a normative naming of each design element for cross-level connection, and convert each design element into a unified coordinate space respectively to obtain a global normalized mapping result.

[0150] The topology mapping table generation module 530 is configured to generate a cross-level topology mapping table according to the definition of each design element in each design document and the normative naming of each design element according to a preset cross-level connection relationship graph.

[0151] The cross-layer topology mapping table includes a plurality of signal transmission paths, and each signal transmission path includes design elements located at different design layers.

[0152] The transmission path verification module 540 is configured to perform connectivity verification on each signal transmission path in the cross-layer topology mapping table according to the global normalized mapping result, to obtain a cross-layer connection relationship verification result of the integrated package chip.

[0153] The technical solution of the embodiments of the present disclosure generates a global normalized mapping result by identifying each design element for realizing cross-layer connection in the design documents of each design layer of the integrated package chip, generating a standardized name, and converting each design element into a unified coordinate space. According to the definition of each design element in each design document and the standardized name of each design element, a cross-layer topology mapping table is generated according to a preset cross-layer connection relationship diagram. Finally, according to the global normalized mapping result, the connectivity of each signal transmission path in the cross-layer topology mapping table is verified, to obtain a cross-layer connection relationship verification result of the integrated package chip. The full-link automatic inspection of the multi-layer package integrated package chip is realized, and the manual intervention is minimized. By using the topology mapping table, the conflict layer can be quickly located, the error can be efficiently located, and the heterogeneous integration can be supported. The topology mapping table is compatible with multiple chips integrated by different processes. The physical alignment deviation of each design element of the chip is found in advance, the packaging rework cost is reduced, and the purpose of preventing assembly failure is achieved.

[0154] Optionally, the topology mapping table generation module 530 is further configured to: confirm that the cross-layer connection relationship diagram is composed of elements, and each cross-layer connection relationship diagram is sequentially concatenated by at least two nodes and at least one edge; each node and each edge are the design elements of a set type.

[0155] Optionally, the topology mapping table generation module 530 is further configured to: according to the definition of each design element in each design document and the standardized name of each design element, generate a cross-layer topology mapping table according to a preset cross-layer connection relationship diagram, including: obtaining a target cross-layer connection relationship diagram to be processed, and obtaining a target node set according to the node connection order defined in the target cross-layer connection relationship diagram; obtaining a plurality of first design element sets matched with the target node set according to the standardized name of each design element; obtaining a second design element set for connecting adjacent target design elements in each first design element set according to the design document of each design layer; and combining each first design element set and the second design element set matched with each first design element set to form a plurality of signal transmission paths.

[0156] Optionally, the topology mapping table generating module 530 is further configured to confirm nodes and edges constituting integrated package chip design elements, the integrated package chip including a system-level chip formed by fixing multiple chips on a chip layer on a package substrate layer through an interposer; the nodes including at least one of input / output ports of each chip on the chip layer, through silicon vias of the interposer, and each solder point on a ball grid array pad on the package substrate layer; and the edges including at least one of micro bumps in the chip layer, rewire layers in the interposer, and package traces on the package substrate layer.

[0157] Optionally, the topology mapping table generating module 530 is further configured to confirm a first design element set corresponding to a target node set, the target node set corresponding to a target cross-level connection relationship graph including input / output ports, at least one through silicon via, and a solder point on a ball grid array pad; and obtain a plurality of first design element sets matched with the target node set according to the canonical naming of each design element, including: in a design document of the chip layer, obtaining a target input / output port corresponding to a target chip currently processed; according to the canonical naming of the target input / output port, obtaining at least one target through silicon via matched with the target input / output port in a design document of the interposer; according to the canonical naming of each target through silicon via, detecting in a design document of the package substrate layer; if a target solder point on a target ball grid array pad matched with a target through silicon via is detected, organizing the target input / output port of the target chip, the at least one target through silicon via, and the target solder point on the target ball grid array pad to obtain a first design element set; and returning to perform the operation of obtaining a target input / output port corresponding to a target chip currently processed in a design document of the chip layer until processing of all input / output ports of all chips in the chip layer is completed.

[0158] Optionally, the topology mapping table generation module 530 is further configured to: confirm a first design element set corresponding to a target node set, the target node set corresponding to the target cross-level connection relationship graph comprises: an input / output port in a chip, a plurality of through silicon vias, and an input / output port in another chip; and obtain a plurality of first design element sets matched with the target node set according to the canonical naming of each design element, comprising: obtaining, in a design document of the chip layer, one target input / output port corresponding to a target chip currently being processed; obtaining, in a design document of the interposer layer, a plurality of target through silicon vias matched with the target input / output port according to the canonical naming of the target input / output port; continuing to detect in the design document of the chip layer according to the canonical naming of each target through silicon via; if an associated input / output port of an associated chip matched with the target input / output port of the target chip is detected, organizing the target input / output port of the target chip, the plurality of target through silicon vias, and the associated input / output port of the associated chip to obtain a first design element set; and returning to perform the operation of obtaining, in the design document of the chip layer, one target input / output port corresponding to a target chip currently being processed until the processing of all input / output ports of all chips in the chip layer is completed.

[0159] Optionally, the topology mapping table generation module 530 is further configured to: confirm a first design element set corresponding to a target node set, and obtain, in the design documents of each design layer, a second design element set for connecting adjacent target design elements in each first design element set, comprising: obtaining a target first design element set currently being processed; obtaining, in the design document of the chip layer, a target micro-bump matched with an input / output port of a chip included in the target first design element set; obtaining, in the design document of the interposer layer, a re-wiring track for connecting two through silicon vias in the target first design element set, or a re-wiring track for connecting a target micro-bump and a through silicon via in the target first design element set; and obtaining, in the design document of the package substrate layer, a package trace for connecting a through silicon via in the target first design element set and a solder point on a ball grid array pad; and forming a second design element set corresponding to the target first design element set by successfully obtaining the target micro-bump, the re-wiring track, and the package trace.

[0160] Optionally, the transmission path verification module 540 is further configured to perform connectivity verification on each of the signal transmission paths in the cross-level topology mapping table according to the global normalized mapping result, to obtain a cross-level connection relationship verification result of the integrated package chip, including: obtaining a target signal transmission path currently processed in the cross-level topology mapping table, and sequentially extracting adjacent nodes and edges, and adjacent edges and nodes according to a path extension order of the target signal transmission path, to construct a plurality of first detection pairs; and obtaining interval distances between nodes and edges in each of the first detection pairs in the global normalized mapping result, and determining that a target first detection pair with an interval distance greater than a preset distance threshold has a signal open circuit abnormality.

[0161] Optionally, the transmission path verification module 540 is further configured to perform connectivity verification on each of the signal transmission paths in the cross-level topology mapping table according to the global normalized mapping result, to obtain a cross-level connection relationship verification result of the integrated package chip, including: identifying each second detection pair with an interval distance less than or equal to a preset distance threshold in the global normalized mapping result, wherein the second detection pair includes two design elements located at different design layers; detecting whether the two design elements in each of the second detection pairs have a direct connection relationship in each of the signal transmission paths in the cross-level topology mapping table; and determining that a target second detection pair without the direct connection relationship has a signal short circuit abnormality.

[0162] Optionally, the transmission path verification module 540 is further configured to perform connectivity verification on each of the signal transmission paths in the cross-level topology mapping table according to the global normalized mapping result, to obtain a cross-level connection relationship verification result of the integrated package chip, including: obtaining micro-bumps and through silicon vias with a direct connection relationship, or through silicon vias and pads with a direct connection relationship in each of the signal transmission paths in the cross-level topology mapping table, to construct a plurality of third detection pairs; obtaining a coverage area shape corresponding to each of the third detection pairs in the global normalized mapping result; detecting a similarity between each coverage area shape and a standard circle, and determining that a target third detection pair with a similarity less than or equal to a preset similarity threshold has an electrical characteristic abnormality.

[0163] Optionally, the transmission path verification module 540 is further configured to perform connectivity verification on each of the signal transmission paths in the cross-level topology mapping table according to the global normalized mapping result, to obtain a cross-level connection relationship verification result of the integrated package chip, including: matching each of the signal transmission paths in the cross-level topology mapping table with a standard netlist of the target integrated package chip, to obtain an abnormal signal transmission path inconsistent with a definition content of the standard netlist.

[0164] The product can execute the method provided by any embodiment of the present disclosure, has the corresponding function module and beneficial effects of executing the method.

[0165] In the technical solution of the present disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved in the technical solution comply with relevant laws and regulations and do not violate public order and good customs.

[0166] According to embodiments of the present disclosure, the present disclosure further provides an electronic device, a readable storage medium and a computer program product.

[0167] Figure 6 A schematic block diagram of an example electronic device 600 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptops, desktops, tablets, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular telephones, smart phones, wearable devices, and other similar computing devices. The components shown here, their connections and relationships, and their functions, are meant to be examples only, and are not meant to limit implementations of the present disclosure described and / or claimed in this document.

[0168] As shown in Figure 4 The device 600 includes a computing unit 601 that can perform various appropriate actions and processes in accordance with a computer program stored in a read-only memory (ROM) 602 or a computer program loaded from a storage unit 608 into a random access memory (RAM) 603. Various programs and data required for the operation of the device 600 can also be stored in the RAM 603. The computing unit 601, the ROM 602, and the RAM 603 are connected to each other through a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0169] A plurality of components in the device 800 are connected to the I / O interface 605, including an input unit 606 such as a keyboard, a mouse, etc., an output unit 607 such as various types of displays, a speaker, etc., a storage unit 608 such as a magnetic disk, an optical disk, etc., and a communication unit 609 such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 609 allows the device 600 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0170] The computing unit 601 can be various general and / or special purpose processing components with processing and computing capabilities. Some examples of the computing unit 601 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The computing unit 601 performs various methods and processes described above, such as a method of verifying cross-tier connectivity of an integrated package chip.

[0171] That is, in the design documents of the design layers of the integrated package chip, each design element used to implement cross-tier connectivity is identified;

[0172] A cross-tier canonical naming of each of the design elements is generated, and each of the design elements is converted into a unified coordinate space to obtain a global normalized mapping result;

[0173] According to the definition of each of the design elements in each of the design documents and the canonical naming of each of the design elements, a cross-tier topology mapping table is generated according to a preset at least one cross-tier connectivity graph;

[0174] The cross-tier topology mapping table includes a plurality of signal transmission paths, and each of the signal transmission paths includes design elements located at different design layers;

[0175] According to the global normalized mapping result, the connectivity of each of the signal transmission paths in the cross-tier topology mapping table is verified to obtain a cross-tier connectivity verification result of the integrated package chip.

[0176] For example, in some embodiments, a method of verifying cross-tier connectivity of an integrated package chip can be implemented as a computer software program tangibly embodied in a machine-readable medium, such as the storage unit 608. In some embodiments, part or all of the computer program can be loaded and / or installed on the device 600 via the ROM 602 and / or the communication unit 609. When the computer program is loaded into the RAM 603 and executed by the computing unit 601, one or more steps of a method of verifying cross-tier connectivity of an integrated package chip described above can be performed. Alternatively, in other embodiments, the computing unit 601 can be configured to perform a method of verifying cross-tier connectivity of an integrated package chip by any other appropriate means, such as by means of firmware.

[0177] Various implementations of the systems and techniques described above can be realized in digital electronic circuitry, integrated circuitry, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on a chip (SOC), a complex programmable logic device (CPLD), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include implementation in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.

[0178] Program code for carrying out methods of the present disclosure can be written in any combination of one or more programming languages. The program code can be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the program code, when executed by the processor or controller, produces the functions / operations specified in the flowcharts and / or the block diagrams. The program code can be executed entirely on a machine, partially on a machine, partially on a machine as a stand-alone software package, partially on a machine and partially on a remote machine or entirely on a remote machine or server.

[0179] In the context of the present disclosure, a machine-readable medium can be a tangible medium that contains or stores a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include but is not limited to an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of the machine-readable storage medium will include one or more lines of electrical conductors, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0180] To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the computer. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including acoustic, speech, or tactile input.

[0181] The systems and techniques described here can be implemented in a computing system that includes a back end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front end component (e.g., a user computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0182] The computer system can include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. A server can be a cloud server, also known as cloud computing server or cloud host, which is a host product in the cloud computing service system, to solve the defects of large management difficulty and weak business scalability in traditional physical host and VPS service. The server can also be a server of a distributed system, or a server combined with a blockchain.

[0183] Artificial intelligence is a discipline that studies enabling computers to simulate some human thinking processes and intelligent behaviors (such as learning, reasoning, thinking, planning, etc.), both hardware and software technologies. Artificial intelligence hardware technology generally includes technologies such as sensors, special artificial intelligence chips, cloud computing, distributed storage, big data processing, etc.; artificial intelligence software technology mainly includes computer vision technology, speech recognition technology, natural language processing technology, and machine learning / deep learning technology, big data processing technology, knowledge graph technology, etc. several major directions.

[0184] Cloud computing refers to a technology system that accesses a pool of elastic and scalable shared physical or virtual resources through a network, and the resources can include servers, operating systems, networks, software, applications and storage devices, etc., and the resources can be deployed and managed in a self-service manner as needed. Through cloud computing technology, efficient and powerful data processing capabilities can be provided for artificial intelligence, blockchain and other technical applications and model training.

[0185] It should be understood that the various forms of flow shown above can be used to reorder, add or delete steps. For example, each step described in the present disclosure can be executed in parallel, sequentially or in a different order, as long as the desired results of the technical solutions provided by the present disclosure can be achieved, which is not limited herein.

[0186] The above specific embodiments do not constitute a limitation on the protection scope of the present disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A method for verifying cross-level interconnectivity of an integrated packaged chip, comprising: In the design documents of each design layer of the integrated package chip, identify the design elements used to implement cross-layer connections; Generate cross-level standardized names for each design element, and transform each design element into a unified coordinate space to obtain a globally normalized mapping result; Based on the definitions of each design element in each design document and the standardized naming of each design element, a cross-level topology mapping table is generated according to at least one preset cross-level connection relationship diagram. The cross-level topology mapping table includes multiple signal transmission paths, and each signal transmission path includes design elements located at different design layers. Based on the global normalized mapping result, the connectivity of each signal transmission path in the cross-level topology mapping table is verified to obtain the cross-level connection relationship verification result of the integrated package chip.

2. The method according to claim 1, wherein, Each of the cross-level connection graphs consists of at least two nodes and at least one edge connected in sequence; each node and each edge is a design element of a specified type.

3. The method according to claim 2, wherein, The step of generating a cross-level topology mapping table based on the definitions and standardized naming of each design element in each design document, according to at least one preset cross-level connection relationship diagram, includes: Obtain the target cross-level connection graph currently being processed, and obtain the target node set according to the node connection order defined in the target cross-level connection graph; Based on the standardized naming of each design element, obtain a set of multiple first design elements that match the target node set; Based on the design documents of each design layer, obtain the second design element set used to connect adjacent target design elements in each of the first design element sets; The first set of design elements and the second set of design elements that match each of the first set of design elements are combined to form multiple signal transmission paths.

4. The method according to claim 3, wherein, The integrated packaged chip includes a system-on-a-chip formed by fixing multiple chips on a chip layer onto a packaging substrate layer through an intermediary layer. The node includes at least one of the following: the input / output ports of each chip in the chip layer, the through-silicon vias of the interposer layer, and each solder joint in the ball grid array pads on the packaging substrate layer; The edge includes at least one of the following: microbumps in the chip layer, redistribution layers in the interposer layer, and packaging traces on the packaging substrate layer.

5. The method according to claim 4, wherein, The set of target nodes corresponding to the target cross-level connection relationship diagram includes: input / output ports in the chip, at least one through-silicon via, and solder joints in the ball grid array pads; The step of obtaining a set of multiple first design elements matching the target node set based on the standardized naming of each design element includes: In the design document of the chip layer, obtain a target input / output port corresponding to the target chip being processed; Based on the standardized naming of the target input / output ports, at least one target through-silicon via (TSV) matching the target input / output ports is obtained from the design document of the interposer layer; According to the standardized naming of each target through-silicon via, it is checked in the design document of the packaging substrate layer; If a target solder joint on the target ball grid array pad that matches the target through-silicon via is detected, the target input / output ports of the target chip, at least one target through-silicon via, and the target solder joint on the target ball grid array pad are organized into a first design element set. Return to the design document of the chip layer and obtain the operation of a target input / output port corresponding to the target chip being processed, until all input / output ports of all chips in the chip layer have been processed.

6. The method according to claim 4, wherein, The set of target nodes corresponding to the target cross-level connection graph includes: input / output ports in one chip, multiple through-silicon vias, and input / output ports in another chip; The step of obtaining a set of multiple first design elements matching the target node set based on the standardized naming of each design element includes: In the design document of the chip layer, obtain a target input / output port corresponding to the target chip being processed; Based on the standardized naming of the target input / output ports, obtain multiple target through-silicon vias (TSVs) that match the target input / output ports in the design document of the intermediary layer; According to the standardized naming of each target through-silicon via, the testing continues in the design document of the chip layer; If an associated input / output port of an associated chip that matches the target input / output port of the target chip is detected, the target input / output port of the target chip, the multiple target through-silicon vias, and the associated input / output port of the associated chip are organized into a first design element set. Return to the design document of the chip layer and obtain the operation of a target input / output port corresponding to the target chip being processed, until all input / output ports of all chips in the chip layer have been processed.

7. The method according to claim 4, wherein, The step of obtaining a second set of design elements, used to connect adjacent target design elements in each of the first set of design elements, based on the design documents of each design layer, includes: Get the set of the first design elements of the target currently being processed; In the chip layer design document, obtain target microbumps that match the input / output ports of the chips included in the target first design element set; In the design document of the intermediary layer, obtain the redistribution traces for connecting two vias in the target first design element set, or the redistribution traces for connecting the target microbumps to the vias in the target first design element set; and In the design document of the packaging substrate layer, obtain the packaging trace used to connect the through-silicon vias in the target first design element set to the solder joints on the ball grid array pads; The target microbump, the rewiring trajectory, and the package routing trajectory will be successfully acquired to form a second design element set corresponding to the first design element set of the target.

8. The method according to claim 3, wherein, The step of verifying the connectivity of each signal transmission path in the cross-level topology mapping table based on the global normalized mapping result to obtain the cross-level connection relationship verification result of the integrated package chip includes: Obtain the target signal transmission path currently being processed from the cross-level topology mapping table, and extract adjacent nodes and edges, as well as adjacent edges and nodes, in sequence according to the path extension order of the target signal transmission path to construct multiple first detection pairs. In the global normalized mapping result, the interval distance between each node and edge in each of the first detection pairs is obtained, and it is determined that the target first detection pair with an interval distance greater than a preset distance threshold has a signal open circuit anomaly.

9. The method according to claim 3, wherein, The step of verifying the connectivity of each signal transmission path in the cross-level topology mapping table based on the global normalized mapping result to obtain the cross-level connection relationship verification result of the integrated package chip includes: In the global normalized mapping result, each second detection pair with an interval distance less than or equal to a preset distance threshold is identified, wherein the second detection pair includes two design elements located in different design layers; In each signal transmission path of the cross-level topology mapping table, it is detected whether there is a direct connection between the two design elements in each second detection pair; The second detection pair of targets that are not directly connected is found to have a signal short-circuit anomaly.

10. The method according to claim 3, wherein, The step of verifying the connectivity of each signal transmission path in the cross-level topology mapping table based on the global normalized mapping result to obtain the cross-level connection relationship verification result of the integrated package chip includes: In each signal transmission path of the cross-level topology mapping table, microbumps and through-silicon vias with direct connections are obtained to construct multiple third detection pairs; In the global normalized mapping result, the shape of the coverage area corresponding to each of the third detection pairs is obtained; The similarity between the shape of each coverage area and a standard circle is detected, and the target third detection pair with a similarity less than or equal to a preset similarity threshold is identified as having abnormal electrical characteristics.

11. The method according to claim 3, wherein, The step of verifying the connectivity of each signal transmission path in the cross-level topology mapping table based on the global normalized mapping result to obtain the cross-level connection relationship verification result of the integrated package chip includes: Each signal transmission path in the cross-level topology mapping table is matched with the standard netlist of the target integrated package chip to obtain abnormal signal transmission paths that are inconsistent with the definition of the standard netlist.

12. An apparatus for verifying cross-level interconnectivity of an integrated packaged chip, comprising: The design element identification module is used to identify the design elements used to implement cross-level connections in the design documents of each design layer of the integrated package chip. The design element specification conversion module is used to generate cross-level specification names for each design element and convert each design element to a unified coordinate space to obtain a global normalized mapping result. The topology mapping table generation module is used to generate a cross-level topology mapping table according to the definition of each design element in each design document and the standardized naming of each design element, and according to at least one preset cross-level connection relationship diagram. The cross-level topology mapping table includes multiple signal transmission paths, and each signal transmission path includes design elements located at different design layers. The transmission path verification module is used to verify the connectivity of each signal transmission path in the cross-level topology mapping table based on the global normalized mapping result, and obtain the cross-level connection relationship verification result of the integrated package chip.

13. An electronic device, comprising: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform the method for verifying cross-level interconnection relationships of the integrated packaged chip according to any one of claims 1-11.

14. A non-transitory computer-readable storage medium storing computer instructions, wherein, The computer instructions are used to cause the computer to execute a method for verifying the cross-level interconnection relationship of an integrated packaged chip according to any one of claims 1-11.

15. A computer program product comprising a computer program that, when executed by a processor, implements the steps of a method for verifying cross-level interconnection relationships of an integrated packaged chip according to any one of claims 1-11.

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