Control device, motor driver and control equipment

Abstract

The invention provides a control device, a motor driver and control equipment. The control device comprises a master microcontroller and a plurality of slave microcontrollers which are arranged in series; a synchronous clock pin of the master microcontroller is connected with synchronous clock pins of the plurality of slave microcontrollers; the master microcontroller is used for synchronously outputting a timer synchronization signal to the plurality of slave microcontrollers through the synchronous clock pin, and sending first data to the first slave microcontroller through the second data pin; the first slave microcontroller is used for receiving first data sent by the master microcontroller through the first data pin according to the timer synchronizing signal, and sending second data to the second slave microcontroller through the second data pin; third data sent by the second slave microcontroller are received through the second data pin, and second data are sent to the master microcontroller through the first data pin; according to the control device, the peripheral resource occupation of the microcontrollers is reduced while bidirectional data interaction among the microcontrollers is realized.

Description

Technical Field

[0001] This disclosure relates to the field of control technology, and in particular to a control device, motor driver and control equipment. Background Technology

[0002] Currently, control schemes based on multiple microcontroller units (MCUs) are commonly used in the control field. Taking motor drivers (also known as motor controllers) as an example, they are electronic devices that convert electrical energy into mechanical energy. As the core hub between the control system, such as the PLC control system, and the motor, their basic principle is to receive low-voltage control signals and drive the motor to operate through power conversion and signal processing. Current motor drivers include single-axis and multi-axis solutions. Single-axis drivers are used to drive a single motor, while multi-axis drivers can independently control the operation of multiple motors. Multi-axis drivers are smaller and cheaper than multiple single-axis drivers. Therefore, the multi-axis nature of drive products is a technological trend that adapts to lower costs, greater flexibility, and higher performance requirements, and is being increasingly widely used in industrial automation control.

[0003] For multi-axis solutions, combining multiple MCU drivers into a multi-chip multi-axis solution is currently a relatively economical and flexible development approach. That is, each MCU acts as a control chip for one or more motor axes to control the operation of the motor. However, the multi-chip multi-axis solution also suffers from the lack of an efficient and economical data interaction mechanism between multiple MCUs. For example, data interaction between multiple MCU chips currently requires the use of chip peripheral resources as a communication method, but in most cases, chip peripheral resources are often insufficient, resulting in a contradiction between multi-chip data interaction and the shortage of chip peripheral resources. Summary of the Invention

[0004] In view of the above problems, this disclosure provides a control device, motor driver and control equipment that can realize bidirectional data interaction between multiple microcontrollers while reducing the peripheral resource occupation of microcontrollers.

[0005] In a first aspect, an embodiment provides the following technical solution: a control device includes a master microcontroller and a plurality of slave microcontrollers arranged in series. Each of the master microcontrollers and each of the slave microcontrollers is provided with a synchronization clock pin, a first data pin, and a second data pin. The synchronization clock pin of the master microcontroller is connected to the synchronization clock pins of the plurality of slave microcontrollers. The plurality of slave microcontrollers includes at least a first slave microcontroller and a second slave microcontroller. The first data pin of the master microcontroller is connected to a high-level signal terminal, and the second data pin is connected to the first data pin of the first slave microcontroller. The second data pin of the first slave microcontroller is connected to the first data pin of the second slave microcontroller. The master microcontroller is used to time a timer via the synchronization clock pin. A synchronization signal is synchronously output to the plurality of slave microcontrollers, and first data is sent to the first slave microcontroller via the second data pin; the first slave microcontroller is configured to: receive the first data sent by the master microcontroller via the first data pin according to the timer synchronization signal, and send the second data to the second slave microcontroller via the second data pin; and receive the third data sent by the second slave microcontroller via the second data pin, and send the second data to the master microcontroller via the first data pin; the second slave microcontroller is configured to: receive the second data via the first data pin according to the timer synchronization signal, and send the third data to the first slave microcontroller via the first data pin.

[0006] In some embodiments, the first slave microcontroller is further configured to: send the first data to the second slave microcontroller via the second data pin according to the timer synchronization signal, and send the third data to the master microcontroller via the first data pin.

[0007] In some embodiments, the master microcontroller includes a counter, and the synchronization clock pin of the master microcontroller is configured in output mode. The master microcontroller is configured to: determine the carrier period of the timer synchronization signal based on the auto-reload value of the counter and the clock frequency; obtain the duty cycle based on the auto-reload value and the target value of the timer synchronization signal; generate a PWM signal based on the duty cycle and the carrier period; and output the PWM signal as the timer synchronization signal to the plurality of slave microcontrollers.

[0008] In some embodiments, the synchronization clock pins of the first and second slave microcontrollers are configured to capture rising edges; the first slave microcontroller is configured to: when detecting that the PWM signal transitions from low to high, set the second data pin to an output state to send the second data, set the first data pin to an input state to receive the first data, and at a set time node of the carrier period, set the first data pin to an output state to send the second data, and set the second data pin to an input state to receive the third data; the second slave microcontroller is configured to: when detecting that the PWM signal transitions from low to high, set the first data pin to an input state to receive the second data, and at a set time node of the carrier period, set the first data pin to an output state to send the third data.

[0009] In some embodiments, the set time node is a half-cycle time node of the carrier period, or a time node corresponding to the carrier peak value within the carrier period.

[0010] In some embodiments, the synchronization clock pins of the first slave microcontroller and the second slave microcontroller are configured to capture rising edges and capture falling edges; the first slave microcontroller and the second slave microcontroller have multiple data transmission modes, and the first slave microcontroller and the second slave microcontroller are used to: obtain the time difference between the rising edge capture and the falling edge capture within one carrier cycle based on the PWM signal, determine the target value of the timer synchronization signal based on the time difference, the carrier cycle and the auto-reload value, and perform data transmission using a matching data transmission mode based on the target value.

[0011] In some embodiments, the plurality of slave microcontrollers includes N slave microcontrollers, where N ≥ 2 and is an integer; when N = 2, the second data pin of the second slave microcontroller is connected to a high-level signal terminal; when N > 2, the second data pin of the i-th slave microcontroller is connected to the first data pin of the (i+1)-th slave microcontroller, and the second data pin of the N-th slave microcontroller is connected to the high-level signal terminal, with i taking values ​​from 2 to N-1 sequentially; the i-th slave microcontroller is configured to: receive the i-th data sent by the (i-1)-th slave microcontroller through the first data pin according to the timer synchronization signal, and send the (i+1)-th data to the (i+1)-th microcontroller through the second data pin; and receive the (i+2)-th data sent by the (i+1)-th slave microcontroller through the second data pin, and send the (i+1)-th data to the (i-1)-th slave microcontroller through the first data pin; the N-th slave microcontroller is configured to: receive the N-th data sent by the (N-1)-th slave microcontroller through the first data pin according to the timer synchronization signal, and send the (N+1)-th data to the (N-1)-th slave microcontroller through the first data pin.

[0012] In some embodiments, the master microcontroller is configured to: during the initialization phase, send an initialization control signal as the timer synchronization signal to the N slave microcontrollers, and send initialization data to the first slave microcontroller via the second data pin; the first slave microcontroller is configured to: according to the initialization control signal, set the first data pin to the input state to receive the initialization data, and after an interval of one carrier cycle, set the second data pin to the output state to send the initialization data to the second slave microcontroller, and then set the second data pin to the input state to receive the initialization data returned by the second slave microcontroller; the i-th slave microcontroller is configured to: according to the initialization control signal, set the first data pin to the input state to receive the initialization data sent by the (i-1)-th slave microcontroller, and after an interval of one carrier cycle, set the second data pin to the output state to send the initialization data to the (i+1)-th slave microcontroller, and then set the second data pin to the input state; the N-th slave microcontroller is configured to: according to the initialization control signal, set the first data pin to the input state to receive the initialization data sent by the (N-1)-th slave microcontroller.

[0013] In some embodiments, the Nth slave microcontroller is further configured to: after receiving the initialization data and after an interval of one carrier cycle, set the first data pin to an output state to send the initialization data to the (N-1)th slave microcontroller; the i-th slave microcontroller is further configured to: receive the initialization data sent by the (i+1)th slave microcontroller, and after an interval of one carrier cycle, set the first data pin to an output state to send the initialization data to the (i-1)th slave microcontroller; the first slave microcontroller is further configured to: receive the initialization data sent by the second slave microcontroller, and after an interval of one carrier cycle, set the first data pin to an output state to send the initialization data to the master microcontroller; the master microcontroller is further configured to: receive the initialization data sent by the first slave microcontroller, and after an interval of one carrier cycle, set the second data pin to an output state to send the initialization data to the first slave microcontroller.

[0014] In some embodiments, the i-th slave microcontroller is further configured to: determine a first number of slave microcontrollers located on one side of the second data pin of the i-th slave microcontroller based on the carrier period and a first time difference; the first time difference being the time difference between the second data pin of the i-th slave microcontroller transmitting the initialization data and the second data pin receiving the initialization data; determine a second number of microcontrollers located on one side of the first data pin of the i-th slave microcontroller based on the carrier period and the second time difference; the second time difference being the time difference between the first data pin of the i-th slave microcontroller transmitting the initialization data and the first data pin receiving the initialization data; and determine the station number of the i-th slave microcontroller in the control device based on the first number and the second number.

[0015] Secondly, based on the same inventive concept, an embodiment provides the following technical solution: a motor driver, including any of the control devices provided in the first aspect embodiment.

[0016] Thirdly, based on the same inventive concept, an embodiment provides the following technical solution: a control device, including any of the control devices provided in the first aspect embodiment.

[0017] According to a technical solution in the above embodiments, the following beneficial effects or advantages are achieved: This disclosure provides a control device, including a master microcontroller and a microcontroller link formed by multiple slave microcontrollers connected in series. The master microcontroller is used for control signal output, using a timer synchronization signal as both a clock signal and a control signal, and outputs it to each slave microcontroller. Each slave microcontroller is used for control signal input and performs bidirectional data interaction based on the timer synchronization signal. Specifically, a first slave microcontroller is used to receive first data sent by the master microcontroller through a first data pin according to the timer synchronization signal, and to send second data to a second slave microcontroller through a second data pin; and to receive... through the second data pin... The second slave microcontroller receives the third data sent by the second slave microcontroller and sends the second data to the master microcontroller through the first data pin. The second slave microcontroller is used to: receive the second data through the first data pin according to the timer synchronization signal, and send the third data to the first slave microcontroller through the first data pin. Through the above data transmission process, each microcontroller can obtain data from the surrounding microcontrollers, realizing bidirectional data interaction. At the same time, the control device uses the timer synchronization signal as the clock signal, controls the data interaction process through the clock signal pin, and only needs to use two I / O interfaces of the microcontroller during data interaction: the first data pin and the second data pin, thereby reducing the peripheral resource occupation of the microcontroller.

[0018] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, specific embodiments of this disclosure are described below. Attached Figure Description

[0019] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this disclosure. Furthermore, the same reference numerals denote the same parts throughout the drawings; in the drawings…

[0020] Figure 1 A schematic diagram of a control device according to an embodiment of the present disclosure is shown.

[0021] Figure 2 A schematic diagram of a control device including N slave microcontrollers is shown according to an embodiment of the present disclosure.

[0022] Figure 3 An example of the timing of bidirectional data interaction between a first slave microcontroller and a carrier cycle is shown according to an embodiment of the present disclosure.

[0023] Figure 4The illustration shows control bit information defined from a microcontroller that only supports rising edge capture, according to one embodiment of the present disclosure.

[0024] Figure 5 The illustration shows control bit information defined when a microcontroller simultaneously supports rising edge capture and falling edge capture, according to one embodiment of the present disclosure.

[0025] Figure 6 A schematic diagram of the data interaction timing of a control device in the initialization process according to an embodiment of the present disclosure is shown.

[0026] Figure 7 It shows Figure 6 Another equivalent schematic diagram.

[0027] Figure 8 A schematic diagram is shown showing first data, second data, and third data cached in a corresponding microcontroller according to an embodiment of the present disclosure.

[0028] Figure 9 A schematic diagram of the data cache of each microcontroller after the first round of shifting is shown according to an embodiment of the present disclosure.

[0029] Figure 10 A schematic diagram of the data cache of each microcontroller after a second round of shifting is shown according to an embodiment of the present disclosure.

[0030] Figure 11 A schematic diagram of a motor driver according to an embodiment of the present disclosure is shown.

[0031] Figure 12 A schematic diagram of a control device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0032] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0033] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0034] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0035] To address the issues of data interaction between multiple microcontrollers and limited chip peripheral resources, in one optional embodiment, please refer to... Figure 1 A control device is provided, including a master microcontroller MCU0 and multiple slave microcontrollers arranged in series. The master microcontroller MCU0 and each slave microcontroller are provided with a synchronization clock pin CLK, a first data pin DL, and a second data pin DR. The synchronization clock pin CLK of the master microcontroller MCU0 is connected to the synchronization clock pins CLK of the multiple slave microcontrollers. The multiple slave microcontrollers include at least a first slave microcontroller MCU1 and a second slave microcontroller MCU2. The first data pin DL of the master microcontroller MCU0 is connected to a high-level signal terminal VCC, and the second data pin DR is connected to the first data pin DL of the first slave microcontroller MCU1. The second data pin DR of the first slave microcontroller MCU1 is connected to the first data pin DL of the second slave microcontroller MCU2. The master microcontroller MCU0 is used to synchronously output a timer synchronization signal to the multiple slave microcontrollers through the synchronization clock pin CLK.

[0036] Specifically, in collaborative control applications, the master microcontroller MCU0 acts as the leader, sending timer synchronization signals to multiple slave microcontrollers. The slave microcontrollers, acting as executors, complete their tasks based on these timer synchronization signals and feed back data information to the master microcontroller MCU0. In the control device provided in this embodiment, the serial connection of the master microcontroller MCU0 and multiple slave microcontrollers refers to their sequential connection to form a serial data link or MCU link. The master microcontroller MCU0 is at the beginning of the link, and the first slave microcontroller MCU1, the second slave microcontroller MCU2, etc., are sequentially connected in series. The second slave microcontroller MCU2, located at the end of the link, serves as the tail of the link. It should be noted that... Figure 1 The main microcontroller MCU0 is the chain-start MCU located on the left. In some embodiments, the main microcontroller MCU0 can also be the chain-start MCU located on the right, which, when reversed, is actually connected to the chain-start MCU on the left. Figure 1 Equivalent.

[0037] Whether it's the master microcontroller MCU0 or the slave microcontroller, each microcontroller chip has at least three pins involved in data interaction between the microcontrollers: the synchronization clock pin CLK, the first data pin DL, and the second data pin DR. The synchronization clock pin CLK is used to transmit the timer synchronization signal. The synchronization clock pins CLK of each microcontroller are of the same type. The synchronization clock pin CLK of the master microcontroller MCU0 is configured in timer output compare mode, outputting only the timer synchronization signal. The synchronization clock pins CLK of the other slave microcontrollers are configured in timer input capture mode, receiving only the timer synchronization signal output by the master microcontroller MCU0.

[0038] The timer synchronization signal is a synchronization signal provided by the master timer in the master microcontroller MCU0 to coordinate the operation of each slave microcontroller. It includes control bit information or control bit data for controlling the data interaction mode. The master timer can use the clock signal generated according to specific events, such as counter overflow or when the count reaches a preset value, as the timer synchronization signal. It is sent to the synchronization clock pin CLK of each slave microcontroller through the synchronization clock pin CLK of the master microcontroller MCU0. Each slave microcontroller performs corresponding data interaction according to the received or captured timer synchronization signal.

[0039] Data interaction between the microcontrollers is achieved through a first data pin DL and a second data pin DR. Both the first data pin DL and the second data pin DR are used as input / output interfaces (I / O ports), serving as data input and output pins. In some embodiments, the first data pin DL can be located on one side of the microcontroller, and the second data pin DR can be located on the other side of the microcontroller to facilitate bidirectional data interaction of the control device; for example, for... Figure 1 In the case where the main microcontroller MCU0 is located at the beginning of the left chain, the first data pin DL can be an I / O pin located on the left side of the MCU chip, and the second data pin DR can be an I / O pin located on the right side of the MCU chip. In other cases, such as when the main microcontroller MCU0 is located at the beginning of the right chain, the first data pin DL can be an I / O pin located on the right side of the MCU chip, and the second data pin DR can be an I / O pin located on the left side of the MCU chip.

[0040] In some embodiments, please refer to Figure 1The first data pin DL of the master microcontroller MCU0 is connected to the high-level signal terminal VCC through diode D1 and pull-up resistor R0. The second data pin DR of the second slave microcontroller MCU2 is connected to the high-level signal terminal VCC through diode D2 and pull-up resistor R3. Diodes D1 and D2 serve as electrostatic discharge protection and signal clamping to protect the microcontrollers from damage and ensure normal operation. In some embodiments, one end of resistor R1 is connected between the master microcontroller MCU0 and the first slave microcontroller MCU1, and the other end is grounded. One end of resistor R2 is connected between the first slave microcontroller MCU1 and the second slave microcontroller MCU2, and the other end is grounded. Resistors R1 and R2 can suppress noise and provide overcurrent protection to ensure the accuracy of data transmission.

[0041] The control device may include a greater number of microcontrollers; in some embodiments, please refer to [link to relevant documentation]. Figure 2 The multiple slave microcontrollers include N slave microcontrollers, where N≥2 and is an integer; when N=2, the second data pin DR of the second slave microcontroller MCU2 is connected to the high-level signal terminal VCC; when N>2, the second data pin DR of the i-th slave microcontroller is connected to the first data pin DL of the (i+1)-th slave microcontroller, and the second data pin DR of the N-th slave microcontroller MCUn is connected to the high-level signal terminal VCC, with i taking values ​​from 2 to N-1 in sequence.

[0042] In other words, if the control device includes only two slave microcontrollers, then the master microcontroller MCU0 is the head of the cascaded microcontroller chain, the second slave microcontroller MCU2 is the tail of the chain, and the first slave microcontroller MCU1 is the intermediate node; if N>2, then the master microcontroller MCU0 is the head of the chain, the Nth slave microcontroller MCUn is the tail of the chain, and the first slave microcontroller MCU1 to the (N-1)th slave microcontroller MCUn-1 are intermediate nodes; for any slave microcontroller at the intermediate node, its first data pin DL is connected to the second data pin DR of the previous slave microcontroller, and its second data pin DR is connected to the first data pin DL of the next slave microcontroller; the second data pin DR of the slave microcontroller located at the tail of the chain is connected to the high-level signal terminal VCC.

[0043] for Figure 2 In some embodiments of the control device, the second data pin DR of the Nth slave microcontroller MCUn is connected to the high-level signal terminal VCC through diode D2 and pull-up resistor Rn+1. A grounding resistor (R1, R2, ..., Rn-1, Rn) is provided between two adjacent slave microcontrollers. The function of diode D2 and grounding resistor is the same as in the aforementioned embodiments. Figure 1 The resistors R1 and R2 have the same function as the diode D2, which will not be elaborated here.

[0044] When the control device is powered on, the first data pin DL and the second data pin DR of all microcontrollers can be configured as input states. By reading the level values ​​of the first data pin DL and the second data pin DR, it can be determined whether it is the master microcontroller MCU0 or the slave microcontroller. For example, if the reading value shows that the first data pin DL is high and the second data pin DR is low, it indicates that the microcontroller is the master microcontroller MCU0, which is the head of the chain and has its first data pin DL connected to the high-level signal terminal VCC, acting as the master station for communication and synchronization. The synchronization clock pin CLK of this microcontroller is configured as the output state. If the reading value shows that the first data pin DL is low and the second data pin DR is high, it indicates that the microcontroller is the Nth slave microcontroller MCUn, which is the tail of the chain. If the reading values ​​of the first data pin DL and the second data pin DR are both low, it indicates that the microcontroller is the intermediate node of the link. Then, the slave microcontrollers located at the tail and intermediate nodes configure the synchronization clock pin CLK to input capture mode.

[0045] When conducting data interaction, Figure 1 Taking the provided control device as an example, the master microcontroller MCU0 is used to send first data to the first slave microcontroller MCU1 through the second data pin DR when synchronously outputting the timer synchronization signal to multiple slave microcontrollers; the first slave microcontroller MCU1 is used to: receive the first data sent by the master microcontroller MCU0 through the first data pin DL according to the timer synchronization signal, and send second data to the second slave microcontroller MCU2 through the second data pin DR; and receive the third data sent by the second slave microcontroller MCU2 through the second data pin DR, and send the second data to the master microcontroller MCU0 through the first data pin DL; the second slave microcontroller MCU2 is used to: receive the second data through the first data pin DL according to the timer synchronization signal, and send the third data to the first slave microcontroller MCU1 through the first data pin DL.

[0046] Specifically, the first data of the master microcontroller MCU0, the second data of the first slave microcontroller MCU1, and the third data of the second slave microcontroller MCU2 are data cached by each microcontroller according to the timer synchronization signal. Taking a motor driver as an example, the cached data can be the position and speed information of the motor controlled by each microcontroller. According to the configuration of the timer synchronization signal, different types and ranges of data can be cached for data interaction. In some embodiments, the data cached by each microcontroller can be data from different times, or data that is synchronously cached according to the timer synchronization signal. The synchronously cached data can enable each microcontroller to obtain the data of other microcontrollers at the same time, which can be better applied to the field of synchronous control.

[0047] The control signal during the data interaction process is a timer synchronization signal. When the master microcontroller MCU0 outputs the timer synchronization signal, it also sends the buffered first data to the first slave microcontroller MCU1. After receiving the timer synchronization signal, the first slave microcontroller MCU1 sends the buffered second data to the second slave microcontroller MCU2, and then sends the second data to the master microcontroller MCU0. After receiving the second data, the second slave microcontroller MCU2 sends the buffered third data to the first slave microcontroller MCU1. As mentioned in the previous embodiment, the timer synchronization signal can be a clock signal generated by the master timer when it encounters a specific event. It is a carrier signal and has periodicity. The corresponding period is called the carrier period. The master microcontroller MCU0 synchronously sends the timer synchronization signal to each slave microcontroller according to the carrier period. The above-mentioned interaction process is the first round of data interaction performed within the first carrier period after the master microcontroller MCU0 outputs the timer synchronization signal or the slave microcontroller receives the timer synchronization signal.

[0048] for Figure 2 In this control device with more slave microcontrollers, during data interaction, the i-th slave microcontroller is used to: receive the i-th data sent by the (i-1)-th slave microcontroller via the first data pin DL according to the timer synchronization signal, and send the i+1-th data to the (i+1)-th microcontroller via the second data pin DR; and receive the i+2-th data sent by the (i+1)-th slave microcontroller via the second data pin DR, and send the i+1-th data to the (i-1)-th slave microcontroller via the first data pin DL; the N-th slave microcontroller MCUn is used to: receive the N-th data sent by the (N-1)-th slave microcontroller MCUn-1 via the first data pin DL according to the timer synchronization signal, and send the N+1-th data to the (N-1)-th slave microcontroller MCUn-1 via the first data pin DL. In other words, for any intermediate node's slave microcontroller, when it receives the timer synchronization signal, it sends the buffered data to the slave microcontroller located on the second data pin DR side and to the slave microcontroller located on the first data pin DL side. The Nth slave microcontroller MCUn, which is the tail of the chain, receives the data sent by the (N-1)th slave microcontroller MCUn-1 and sends the buffered data to the (N-1)th microcontroller.

[0049] It can be seen that the multiple microcontrollers in the control device construct a bidirectional data link through the first data pin DL and the second data pin DR to transmit data streams, whether... Figure 1 still Figure 2 The provided control device has the same data interaction process for the slave microcontrollers located at the intermediate nodes. For clarity, the first slave microcontroller MCU1 will be used as an example. During the first carrier cycle (or control interrupt cycle) of the timer synchronization signal, its data interaction design is as follows: Figure 3 As shown, it illustrates four time points T0~T3 within one cycle of the pulse counting waveform of the counter.

[0050] T0: The first slave microcontroller MCU1 sets the first data pin DL as input and the second data pin DR as output, and outputs the second data to the second slave microcontroller MCU2. At this time, the direction of data transmission is from the first data pin DL to the second data pin DR.

[0051] T1: First, read the data from the first data pin DL of the microcontroller MCU1 to obtain the first data sent by the main microcontroller MCU0; this time point can be set between T0 and T2, and there is no need to strictly specify the specific time.

[0052] T2: First, the slave microcontroller MCU1 sets the first data pin DL to output and the second data pin DR to input, and outputs the second data to the master microcontroller MCU0. At this time, the data transmission direction is the direction from the second data pin DR to the first data pin DL. The timing of T2 needs to be determined by reading the level of the timer synchronization signal, so the reading time must be strictly specified.

[0053] T3: First, read the data from the second data pin DR of the microcontroller MCU1, and then obtain the third data sent by the microcontroller MCU2. This time point can be set after T2 and before the end of this cycle, and there is no need to strictly specify the specific time.

[0054] In summary, this disclosure provides a control device including a master microcontroller MCU0 and a microcontroller link formed by multiple slave microcontrollers connected in series. The master microcontroller MCU0 outputs control signals, using a timer synchronization signal as both a clock signal and a control signal, and outputs it to each slave microcontroller. Each slave microcontroller inputs control signals and performs bidirectional data interaction based on the timer synchronization signal. Specifically, the first slave microcontroller MCU1 receives first data sent by the master microcontroller MCU0 via a first data pin DL, and sends second data to the second slave microcontroller MCU2 via a second data pin DR, based on the timer synchronization signal. It also receives third data sent by the second slave microcontroller MCU2 via the second data pin DR and sends the second data back to the master microcontroller MCU0 via the first data pin DL. The second slave microcontroller MCU2 receives the second data via the first data pin DL and sends the third data to the first slave microcontroller MCU1 via the first data pin DL, based on the timer synchronization signal.

[0055] Through the above data transmission process, each microcontroller can obtain data from surrounding microcontrollers, realizing bidirectional data interaction between multiple microcontrollers. For example, for the master microcontroller MCU0, its bidirectional data interaction includes sending first data to the first slave microcontroller MCU1 and receiving second data sent by the first slave microcontroller MCU1. For the first slave microcontroller MCU1, its bidirectional data interaction includes receiving the first data sent by the master microcontroller MCU0, sending the second data to the third slave microcontroller MCU2, and receiving the third data sent by the second slave microcontroller MCU2 and sending the second data to the master microcontroller MCU0. For the second slave microcontroller MCU2, its bidirectional data interaction includes receiving the second data sent by the first slave microcontroller MCU1 and sending the third data to the first slave microcontroller MCU1.

[0056] Meanwhile, the control device uses the timer synchronization signal as the clock signal, controls the data interaction process through the clock signal pin, and only needs to use two I / O interfaces of the microcontroller during data interaction: the first data pin DL and the second data pin DR, thereby reducing the occupation of peripheral resources.

[0057] In some embodiments, for Figure 1 The provided control device, the first slave microcontroller MCU1, is also used to: send first data to the second slave microcontroller MCU2 through the second data pin DR according to the timer synchronization signal, and send third data to the master microcontroller MCU0 through the first data pin DL.

[0058] Specifically, when multiple microcontrollers perform collaborative or synchronous control, each microcontroller needs to obtain data from the other microcontrollers. Therefore, after the first slave microcontroller MCU1 receives the first data from the master microcontroller MCU0 and the third data from the second slave microcontroller MCU2 in the current cycle, it can send the first data from the master microcontroller MCU0 to the second slave microcontroller MCU2 according to the timer synchronization signal of the next cycle, and then send the third data from the second slave microcontroller MCU2 to the master microcontroller MCU0. In this way, each microcontroller can obtain data from all other microcontrollers equally. For example, for any one of the master microcontroller MCU0, the first slave microcontroller MCU1, and the second slave microcontroller MCU2, the first data, the second data, and the third data are stored to facilitate synchronous control and improve the accuracy of synchronous control.

[0059] In some embodiments, for Figure 2The provided control device, wherein the i-th slave microcontroller is further configured to: send the i-th data to the (i+1)-th slave microcontroller via the second data pin DR, and send the i+2-th data to the (i-1)-th slave microcontroller via the first data pin DL, according to the timer synchronization signal; that is, in the next cycle of the timer synchronization signal, the i-th slave microcontroller sends the i-th data of the (i-1)-th slave microcontroller to the (i+1)-th slave microcontroller, and sends the i+2-th data of the (i+1)-th slave microcontroller to the (i-1)-th slave microcontroller; by continuously forwarding the data of one side of the microcontroller to the other side, until after multiple cycles, each microcontroller on the MCU link obtains the data of all other microcontrollers equally, so as to facilitate synchronous control and improve the accuracy of synchronous control.

[0060] As mentioned in the foregoing embodiments, the timer synchronization signal can be a clock signal generated by the master timer when it encounters a specific event. In some embodiments, the master microcontroller MCU0 includes a counter, the synchronization clock pin CLK of the master microcontroller MCU0 is configured to output mode, and the master microcontroller MCU0 is configured to: determine the carrier period of the timer synchronization signal based on the auto-reload value of the counter and the clock frequency, obtain the duty cycle based on the auto-reload value and the target value of the timer synchronization signal, generate a PWM signal based on the duty cycle and the carrier period, and output the PWM signal as a timer synchronization signal to multiple slave microcontrollers.

[0061] Specifically, in microcontrollers, timers and counters often share the same hardware module. Within this module, the auto-reload value is managed through the Auto Reload register. The automatic reload register (ARR) is used to set the count limit of the counter. When the counter reaches the ARR value, it overflows, and the automatic reload register is reset to the initial count value. In upward counting mode, the counter starts counting from 0 until the set automatic reload value (ARR value) overflows, at which point the counter is reset to 0 and starts counting again. In center-aligned counting mode, it starts counting from 0, overflows at ARR-1, is reset to ARR, and starts counting downwards until it overflows at 1, at which point the counter is reset to 0 and starts counting again. In the above process, one complete counting cycle of the counter corresponds to the carrier cycle. Therefore, the frequency of the timer synchronization signal can be determined based on the counter's clock frequency and the ARR value, thus determining the time range of the carrier cycle. It can be seen that there is a mapping relationship between the carrier cycle of the timer synchronization signal and the automatic reload value. The duty cycle of the PWM signal can be determined based on the ratio between the target value of the timer synchronization signal and the automatic reload value. Based on this duty cycle and the carrier cycle, a square wave is generated through the timer output comparison function, i.e., the PWM signal serves as the timer synchronization signal.

[0062] The target value of the timer synchronization signal corresponds to the value of the control bit information. The control bit information can be used to define the data transmission mode of each microcontroller. The larger the range of values ​​of the control bit information, the more data transmission modes it can define, thereby increasing the data transmission efficiency and flexibility of the control device in different application scenarios.

[0063] For example, if a timer's clock frequency (counting frequency) is 120MHz and the frequency of the generated PWM signal is 20kHz, then the carrier period of the timer synchronization signal is 50μs. Therefore, within one carrier period, the timer counter needs to count 6000 times. At this time, the control bit information that the timer synchronization signal can transmit is 0~6000. It can be seen that, with a fixed carrier period, the range of control bit information values ​​is related to the timer's clock frequency. The higher the timer's clock frequency, the larger the data range that the PWM signal can transmit. The target value of the control bit information can be represented by the duty cycle of the PWM signal. For example, a duty cycle of 10% corresponds to a control bit information of 600, and a duty cycle of 20% corresponds to a control bit information of 1200. Therefore, the duty cycle of the timer synchronization signal can be used to transmit control bit information.

[0064] On the other hand, the capture method of the microcontroller's synchronous clock pin CLK also affects the setting of the control bit information; in some embodiments, the synchronous clock pin CLK of the first slave microcontroller MCU1 and the second slave microcontroller MCU2 is configured to capture on the rising edge; the first slave microcontroller MCU1 is used to: when the PWM signal is detected to jump from low level to high level, set the second data pin DR to the output state to send the second data, set the first data pin DL to the input state to receive the first data, and at a set time node of the carrier period, set the first data pin DL to the output state to send the second data, and set the second data pin DR to the input state to receive the third data; the second slave microcontroller MCU2 is used to: when the PWM signal is detected to jump from low level to high level, set the first data pin DL to the input state to receive the second data, and at a set time node of the carrier period, set the first data pin DL to the output state to send the third data.

[0065] Specifically, the above solution configures all microcontroller synchronous clock pins CLK to only support the capture of the rising edge of the PWM signal, and does not support the simultaneous capture of the rising and falling edges. This approach has the lowest functional requirements for the MCU's chip peripheral resources, and the control bit information of the timer synchronization signal is also minimal. When the microcontroller's synchronous clock pin CLK only supports the capture of the rising edge, the data transmission state can be controlled by two timer synchronization signals with different duty cycles. One duty cycle timer synchronization signal is used to indicate the data transmission state, and the other duty cycle timer synchronization signal is used to indicate the idle state.

[0066] In some embodiments, the time node is set as a half-cycle time node of the carrier period, or the time node corresponding to the carrier peak within the carrier period; taking the time node set as the time node corresponding to the carrier peak as an example, the microcontroller can be used to read the level of the timer synchronization signal at the carrier peak of the carrier period, which corresponds to... Figure 3 The carrier peak value is easy to locate at the T2 time node, which can meet the requirement that the T2 time node needs to be strictly specified, thereby improving the accuracy of data interaction.

[0067] Please see Figure 4 The waveform corresponding to "counter" is the pulse counting waveform of the counter in center-aligned counting mode, and the waveform of "CLK" is the PWM signal of the timer synchronization signal. The duty cycle of the PWM signal can be set to 25% or 75%, or other duty cycles. The level states read at the carrier peak of the "counter" waveform are 0 and 1, respectively. Duty cycles of 25% and 75% can be used to represent control bit states 0 and 1, respectively. 0 represents data transmission and 1 represents idle state, or 1 represents data transmission and 0 represents idle state. Unless otherwise specified, the former design is used in the embodiments of this disclosure.

[0068] In some embodiments, the synchronization clock pin CLK of the first slave microcontroller MCU1 and the second slave microcontroller MCU2 is configured to capture rising edge and capture falling edge; the first slave microcontroller MCU1 and the second slave microcontroller MCU2 have multiple data transmission modes, and the first slave microcontroller MCU1 and the second slave microcontroller MCU2 are used to: obtain the time difference between the rising edge capture and the falling edge capture within one carrier cycle according to the PWM signal, determine the target value of the timer synchronization signal according to the time difference, the carrier cycle and the auto-reload value, and perform data transmission using a matching data transmission mode according to the target value.

[0069] Specifically, when each microcontroller's synchronous clock pin CLK simultaneously supports rising edge capture and falling edge capture to different registers, more duty cycles can be configured as control bit information, enabling the transmission of multiple control bit information within a single carrier cycle; for example, please refer to... Figure 5 A duty cycle of 20% is defined as control bit information 20, indicating that the PWM duty cycle is 20%. Similarly, a duty cycle of 40% is defined as control bit information 40, a duty cycle of 60% is defined as control bit information 60, a duty cycle of 80% is defined as control bit information 80, and so on. Based on the above four types of control bit information, four different data transmission modes can be configured.

[0070] When the microcontroller captures the timer synchronization signal, within a carrier cycle, such as... Figure 5 As shown, the time node corresponding to the rising edge capture is defined as t1, and the time node corresponding to the falling edge capture is defined as t2. The time difference between the two is ∆t=t2-t1. This time difference is the mapping of control bit information. The master microcontroller MCU0 can transmit control bit information to the slave microcontroller by controlling the duty cycle of the timer synchronization signal.

[0071] Taking the control signal information that the main microcontroller MCU0 can transmit in the aforementioned embodiment as an example (0~6000), if the target value of the control bit information is 600, the main microcontroller MCU0 can set the duty cycle to 10% to generate a timer synchronization signal. The corresponding time difference between the falling edge capture and the rising edge capture received from the microcontroller is also 10% of the carrier period, and the control bit information can be parsed as 0.1×6000=600.

[0072] The more control bit information a timer synchronization signal can transmit, the more it improves the efficiency and flexibility of data transmission. For example, the control bit information represents the station number of the slave microcontroller. The master microcontroller MCU0 can specify to transmit data to a target slave microcontroller. It generates a timer synchronization signal and sends the data according to the duty cycle corresponding to the station number of the target slave microcontroller. For other slave microcontrollers, by parsing the duty cycle of the timer synchronization signal, it can be determined that the data does not need to be processed and can be directly forwarded to the next slave microcontroller until the target slave microcontroller obtains the data. This helps to save the computing resources of the slave microcontroller.

[0073] Whether it only supports rising edge capture or supports both rising and falling edge capture, the software design of the above schemes uses the rising edge of the timer synchronization signal (PWM) for interrupt start synchronization between various microcontrollers, and the duty cycle of the PWM is used for data communication synchronization.

[0074] The above embodiments illustrate the composition of the control device and the definition of the control bit information in the timer synchronization signal. In the following embodiments, the data interaction process will be described in further detail.

[0075] Initialization is necessary before data interaction. The initialization process needs to determine the following: the order of each microcontroller on the MCU link, and the number of microcontrollers on the MCU link. The number of microcontrollers can be used to determine the exact number of clock cycles required for a transmission process.

[0076] In some embodiments, with Figure 2 Taking the provided control device as an example, the master microcontroller MCU0 is used to: send the initialization control signal as a timer synchronization signal to N slave microcontrollers during the initialization phase, and send initialization data to the first slave microcontroller MCU1 through the second data pin DR; the first slave microcontroller MCU1 is used to: set the first data pin DL to the input state to receive the initialization data according to the initialization control signal, and after an interval of one carrier cycle, set the second data pin DR to the output state to send the initialization data to the second slave microcontroller MCU2, and then set the second data pin DR to the input state to receive the initialization data returned by the second slave microcontroller MCU2; the i-th slave microcontroller is used to: set the first data pin DL to the input state to receive the initialization data sent by the (i-1)-th slave microcontroller according to the initialization control signal, and after an interval of one carrier cycle, set the second data pin DR to the output state to send the initialization data to the (i+1)-th slave microcontroller, and then set the second data pin DR to the input state; the N-th slave microcontroller MCUn is used to: set the first data pin DL to the input state to receive the initialization data sent by the (N-1)-th slave microcontroller MCUn-1 according to the initialization control signal.

[0077] Specifically, the initialization control signal and initialization data can be configured according to requirements. To simplify the initialization process, the control bit of the timer synchronization signal can be set to "0" to trigger the initialization process, and the control bit should remain at 0 throughout the entire initialization process. The initialization data can be set to "1". Unlike the bidirectional data interaction in the data transmission phase, the transmission of initialization data within one carrier cycle in the initialization process is unidirectional. For details, please refer to [link to relevant documentation]. Figure 6The initialization process diagram shown illustrates the following timing sequence: In the first carrier cycle, the second data pin DR of the master microcontroller MCU0 at the head of the chain is set to a high level to output the initialization data 1, and the first data pin DL of the first slave microcontroller MCU1 is set to a high level to receive the initialization data. In the second carrier cycle, the second data pin DR of the first slave microcontroller MCU1 is set to a high level to output the initialization data, and the first data pin DL of the second slave microcontroller MCU2 is set to a high level to receive the initialization data. This process continues until the Nth carrier cycle, when the Nth slave microcontroller MCUn at the tail of the chain receives the initialization data.

[0078] In some embodiments, the Nth slave microcontroller MCUn is further configured to: after receiving initialization data and after an interval of one carrier cycle, set the first data pin DL to the output state to send initialization data to the (N-1)th slave microcontroller MCUn-1; the i-th slave microcontroller is further configured to: receive the initialization data sent by the (i+1)th slave microcontroller, and after an interval of one carrier cycle, set the first data pin DL to the output state to send initialization data to the (i-1)th slave microcontroller; the first slave microcontroller MCU1 is further configured to: receive the initialization data sent by the second slave microcontroller MCU2, and after an interval of one carrier cycle, set the first data pin DL to the output state to send initialization data to the master microcontroller MCU0; the master microcontroller MCU0 is further configured to: receive the initialization data sent by the first slave microcontroller MCU1, and after an interval of one carrier cycle, set the second data pin DR to the output state to send initialization data to the first slave microcontroller MCU1.

[0079] Specifically, the Nth slave microcontroller MCUn, acting as the tail of the chain, is used to send back the received initialization data. Please refer to [link to relevant documentation]. Figure 6 In the (N+1)th carrier cycle, the first data pin DL of the Nth slave microcontroller MCUn is set to a high level to send initialization data, and the second data pin DR of the (N-1)th slave microcontroller MCUn-1 is set to a high level to receive initialization data. In the (N+2)th carrier cycle, the first data pin DL of the (N-1)th slave microcontroller MCUn-1 is set to a high level to send initialization data, and the second data pin DR of the (N-2)th slave microcontroller is set to a high level to receive initialization data. This process continues until the 2Nth carrier cycle, when the master microcontroller MCU0, acting as the head of the chain, receives the initialization data again through the second data pin DR. Then, the process of sending initialization data from the master microcontroller MCU0 to the Nth slave microcontroller MCUn is repeated.

[0080] It should be noted that, Figure 2This scenario describes a situation where the main microcontroller MCU0 is located at the beginning of the MCU link on the left, and the Nth microcontroller is located at the end of the link on the right. Therefore, after the main microcontroller MCU0 sends its initialization data for the first time, the transmission process of the initialization data is first right-handed and then left-handed. Figure 6 A total of 4N carrier cycles of communication interaction are provided. The first to Nth carrier cycles represent the right-hand communication process for initialization data; the (N+1)th to 2Nth carrier cycles represent the left-hand communication process; the (2N+1)th to 3Nth carrier cycles represent the right-hand communication process for initialization data; and the (3N+1)th to 4Nth carrier cycles represent the left-hand communication process for initialization data. Figure 3 It can be seen that the starting point of the output waveform of the initialization data in the right-hand communication process is the rising edge of the PWM signal, while the starting point of the output waveform of the initialization data in the left-hand communication process is the peak value of the carrier wave.

[0081] In addition, Figure 6 The waveforms are distinguished based on the states of the first data pin DL and the second data pin DR of two adjacent microcontrollers. If the states of the first data pin DL and the second data pin DR are disregarded, and identical items are combined (for example, merging "MCU0 DR output & MCU1 DL input" and "MCU1 DL output & MCU0 DR input" into "MCU0DR & MCU1 DL"), then the following can be obtained: Figure 7 The timing diagram shown.

[0082] In summary, the Nth slave microcontroller MCUn at the tail of the chain only sends back the received initialization data towards the direction of the first data pin DL, while the master microcontroller MCU0 at the head of the chain, after sending the first initialization data, only sends back the initialization data received from the first slave microcontroller MCU1 through the second data pin DR, thus forming a circular data chain. During this process, if individual microcontroller nodes are not ready to forward data, the master microcontroller MCU0 at the head of the chain will not be able to receive the initialization data again. It can be configured to resend the initialization data after a sufficiently long time to restart the initialization process. If each microcontroller node is working properly, the initialization data can circulate several times on the MCU link network until the timer synchronization signal terminates the initialization process. For example, after receiving the initialization data a set number of times, the master microcontroller MCU0 can send a normal data frame transmission corresponding to the timer synchronization signal through the synchronization clock pin CLK, thereby causing all microcontrollers to exit the initialization phase.

[0083] Based on the above initialization process, in some embodiments, the i-th slave microcontroller is further configured to: determine a first number of slave microcontrollers located on one side of the second data pin DR of the i-th slave microcontroller according to the carrier period and a first time difference; the first time difference is the time difference between the second data pin DR of the i-th slave microcontroller transmitting initialization data and the second data pin DR receiving initialization data; determine a second number of microcontrollers located on one side of the first data pin DL of the i-th slave microcontroller according to the carrier period and the second time difference; the second time difference is the time difference between the first data pin DL of the i-th slave microcontroller transmitting initialization data and the first data pin DL receiving initialization data; and determine the station number of the i-th slave microcontroller in the control device according to the first number and the second number.

[0084] In simple terms, the number of microcontrollers on any node can be calculated by the time difference between the initialization data sent and received on a certain side. Specifically, based on the time difference between the initialization data output from the first data pin DL and the initialization data input from the first data pin DL, and the carrier period, the number of interval cycles on the first data pin DL side can be calculated, thereby obtaining the number of microcontrollers on the first data pin DL side. Similarly, based on the time difference between the initialization data output from the second data pin DR and the initialization data input from the second data pin DR, and the carrier period, the number of microcontrollers on the second data pin DR side can be calculated.

[0085] For example, for Figure 2 In a given M-th slave microcontroller, m MCUs are arranged on one side of its first data pin DL (referred to as the left side) and nm MCUs are arranged on one side of its second data pin DR (referred to as the right side). During the initialization phase, the master microcontroller MCU0 outputs control bit 0 as an initialization signal through the synchronization clock pin CLK, and simultaneously sends initialization data 1 through the second data pin DR. Let the receipt of data 1 by the first data pin DL of the M-th slave microcontroller MCUm be the 0th carrier cycle (or clock cycle), and the sending of data 1 by the second data pin DR be the first carrier cycle. When the second data pin DR of the M-th slave microcontroller MCUm receives data 1, the entire process takes 2 (nm) carrier cycles. Therefore, it can be determined that there are nm MCUs on the right side of the M-th slave microcontroller MCUm. At the same time, the sending of data 1 by the first data pin DL of the M-th slave microcontroller MCUm is the 2nd (nm) clock cycle. When the first data pin DL of the M-th slave microcontroller MCUm receives data 1, it is the 2nd (nm) + 2m cycle. This process takes 2m carrier cycles, so there are m MCUs on the left side of the M-th slave microcontroller MCUm.

[0086] After determining the number of MCUs located on both sides of the Mth slave microcontroller, the Mth slave microcontroller can deduce its station number (i.e., sequence number or position number) in the MCU link. Based on this station number, different data transmission modes can be configured to improve the flexibility and accuracy of data interaction.

[0087] After the initialization process is completed, the control device can enter the data transmission process. A typical transmission process can include three stages: synchronization, control, and data. The synchronization stage is usually initiated by a control bit 1. The control bit information is formed by combining the control bits of the subsequent carrier cycles. After the control stage ends, the data stage begins. Each microcontroller indexes the target data (i.e., the i+1th data of the i-th microcontroller) according to the control bit information and loads the target data into the shift register variable. Data transmission is completed in the subsequent carrier cycles. The specific number of cycles is determined by the total number of microcontrollers and the data length of a single microcontroller in a transmission process.

[0088] During data transmission, for each microcontroller on the MCU link, the data flow from the first data pin DL to the second data pin DR can obtain the data of the microcontroller located on the side of the first data pin DL, and the data flow from the second data pin DR to the first data pin DL can obtain the data of the microcontroller located on the side of the second data pin DR. This allows each microcontroller on the MCU link to obtain the data of all other microcontrollers equally.

[0089] Assuming the length of the control bit information is 'a' bits, 'n' is the total number of microcontrollers, and each microcontroller transmits 'x' bits of data per frame, then the final data frame format is: |synchronization bit 1 bit|control data a bit|data n×x bits|.

[0090] To more intuitively describe the data interaction process, Figure 1 Taking the provided control device as an example, one side of the first data pin DL is defined as the left side, and one side of the second data pin DR is defined as the right side; the first data to be sent by the master microcontroller MCU0, the second data to be sent by the first slave microcontroller MCU1, and the third data to be sent by the second slave microcontroller MCU2 can be found in the following reference. Figure 8 The diagram shows that during the control phase, each microcontroller indexes and caches information based on the control bit information of the timer synchronization signal.

[0091] Next, in the first carrier cycle of the data phase, the first round of shifting is performed. This first round of shifting includes right-hand data shifting and left-hand data shifting. During the right-hand data shift, the master microcontroller MCU0 sends the first data in its shift register to the first slave microcontroller MCU1, and the first slave microcontroller MCU1 sends the second data in its shift register to the second slave microcontroller MCU2. During the left-hand data shift, the second slave microcontroller MCU2 sends the third data in its shift register to the first slave microcontroller MCU1, and the first slave microcontroller MCU1 sends the second data in its shift register to the master microcontroller MCU0. At this point, the master microcontroller MCU0's registers buffer the first and second data, the first slave microcontroller MCU1's registers buffer the first, second, and third data, and the second slave microcontroller MCU2's registers buffer the second and third data. Figure 9 As shown.

[0092] Next, a second round of shifting is performed in the second carrier cycle, which also includes right-hand data shifting and left-hand data shifting. During the right-hand data shifting process, the first slave microcontroller MCU1 sends the first data from the master microcontroller MCU0 to the second slave microcontroller MCU2. During the left-hand data shifting process, the first slave microcontroller MCU1 sends the third data from the second slave microcontroller MCU2 to the master microcontroller MCU0. At this moment, the master microcontroller MCU0, the first slave microcontroller MCU1, and the second slave microcontroller MCU2 all have the first data, the second data, and the third data buffered in their registers.

[0093] In summary, the control device provided in this disclosure has the following characteristics.

[0094] 1) Bidirectional data interaction between multiple chips: The master microcontroller MCU0 uses the timer synchronization signal as the clock signal and the carrier period as the intermediate node. Bidirectional data communication can be achieved using two ordinary IO pins, which helps to reduce the occupation of chip peripheral resources. Among them, when the synchronization clock pin CLK of the slave microcontroller only supports rising edge capture, the functional requirements of peripheral resources are the lowest.

[0095] 2) When the synchronous clock pin CLK of the microcontroller supports capturing the rising and falling edges to different registers at the same time, the duty cycle of the timer synchronization signal of the master microcontroller MCU0 can be set to more values. The slave microcontroller determines the control bit information by receiving the time difference between the rising and falling edges, so that more bits of control information can be transmitted in one cycle. The more control information transmitted, the more beneficial it is to improve the efficiency and flexibility of data transmission.

[0096] 3) Automatic station number allocation: During the initialization phase, the control bit information can be kept as the initialization signal through the synchronous clock pin CLK of the main microcontroller MCU0. At the same time, the initialization data is sent to perform the initialization process. Sending data 1 from the second data pin DR of the main microcontroller MCU0 to receiving data 1 from the second data pin DR is an initialization process. By the number of carrier cycles experienced, each slave microcontroller can calculate its own station number, thereby improving the flexibility and accuracy of data interaction.

[0097] Secondly, based on the same inventive concept, in an optional embodiment, please refer to... Figure 11 A motor driver 100 is provided, including the control device 110 provided in the first aspect embodiment. Specifically, the motor driver 100 is a multi-axis driver that can independently control the operation of multiple motors. Each microcontroller (MCU) in the control device acts as a control chip for one motor axis to control the operation of one motor. The master microcontroller (MCU0) acts as the control chip for the master axis motor, and the slave microcontroller acts as the control chip for the slave axis motor. It can control the operation of each motor independently or control the operation of multiple motors synchronously.

[0098] Thirdly, based on the same inventive concept, in an optional embodiment, please refer to... Figure 12 A control device 200 is provided, including the control device 110 provided in the first aspect embodiment.

[0099] Although preferred embodiments of the present disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0100] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. A control device characterized by comprising: The master microcontroller and a plurality of slave microcontrollers are arranged in series, the master microcontroller and each of the slave microcontrollers are provided with a synchronization clock pin, a first data pin and a second data pin, the synchronization clock pin of the master microcontroller is connected to the synchronization clock pins of the plurality of slave microcontrollers; The plurality of slave microcontrollers at least includes a first slave microcontroller and a second slave microcontroller, the first data pin of the master microcontroller is connected to a high-level signal end, the second data pin of the master microcontroller is connected to the first data pin of the first slave microcontroller, and the second data pin of the first slave microcontroller is connected to the first data pin of the second slave microcontroller; The master microcontroller is configured to output a timer synchronization signal to the plurality of slave microcontrollers through the synchronization clock pin, and send first data to the first slave microcontroller through the second data pin; The first slave microcontroller is configured to receive the first data sent by the master microcontroller through the first data pin according to the timer synchronization signal, send second data to the second slave microcontroller through the second data pin, receive third data sent by the second slave microcontroller through the second data pin, and send the second data to the master microcontroller through the first data pin according to the timer synchronization signal. The second slave microcontroller is configured to receive the second data through the first data pin according to the timer synchronization signal, and send the third data to the first slave microcontroller through the first data pin.

2. The control device of claim 1, wherein The first slave microcontroller is further configured to: send the first data to the second slave microcontroller through the second data pin and send the third data to the master microcontroller through the first data pin according to the timer synchronization signal.

3. The control device of claim 1, wherein The master microcontroller includes a counter, the synchronization clock pin of the master microcontroller is configured to output a mode, and the master microcontroller is configured to determine a carrier period of the timer synchronization signal according to an automatic reload value of the counter and a clock frequency, determine a duty cycle according to the automatic reload value and a target value of the timer synchronization signal, generate a PWM signal according to the duty cycle and the carrier period, and output the PWM signal as the timer synchronization signal to the plurality of slave microcontrollers.

4. The control device of claim 3, wherein The synchronization clock pins of the first slave microcontroller and the second slave microcontroller are configured to capture rising edges; The first slave microcontroller is configured to set the second data pin to an output state to send the second data and set the first data pin to an input state to receive the first data when detecting that the PWM signal jumps from a low level to a high level, and set the first data pin to an output state to send the second data and set the second data pin to an input state to receive the third data at a set time node of the carrier period. The second slave microcontroller is configured to set the first data pin to an input state to receive the second data when detecting that the PWM signal jumps from a low level to a high level, and set the first data pin to an output state to send the third data at a set time node of the carrier cycle.

5. The control device of claim 4, wherein The set time node is a half cycle time node of the carrier cycle, or a time node corresponding to a carrier peak in the carrier cycle.

6. The control device of claim 3, wherein The synchronous clock pins of the first slave microcontroller and the second slave microcontroller are configured to rising edge capture and falling edge capture; The first slave microcontroller and the second slave microcontroller have multiple data transmission modes, and are configured to obtain a time difference between the rising edge capture and the falling edge capture in one carrier cycle according to the PWM signal, determine a target value of the timer synchronization signal according to the time difference, the carrier cycle and the auto-reload value, and adopt a matched data transmission mode for data transmission according to the target value.

7. The control device of claim 1, wherein The multiple slave microcontrollers include N slave microcontrollers, N≥2 and is an integer; When N=2, the second data pin of the second slave microcontroller is connected to a high level signal end; When N>2, the second data pin of the i-th slave microcontroller is connected to the first data pin of the i+1-th slave microcontroller, the second data pin of the N-th slave microcontroller is connected to the high level signal end, and i is sequentially taken as 2 to N-1; The i-th slave microcontroller is configured to receive i-th data sent by the i-1-th slave microcontroller through the first data pin and send i+1-th data to the i+1-th slave microcontroller through the second data pin according to the timer synchronization signal, and receive i+2-th data sent by the i+1-th slave microcontroller through the second data pin and send the i+1-th data to the i-1-th slave microcontroller through the first data pin according to the timer synchronization signal; The N-th slave microcontroller is configured to receive N-th data sent by the N-1-th slave microcontroller through the first data pin and send N+1-th data to the N-1-th slave microcontroller through the first data pin according to the timer synchronization signal.

8. The control device of claim 7, wherein The master microcontroller is configured to send an initialization control signal as the timer synchronization signal to the N slave microcontrollers and send initialization data to the first slave microcontroller through the second data pin in an initialization phase. The first slave microcontroller is configured to set the first data pin to an input state to receive the initialization data according to the initialization control signal, set the second data pin to an output state to send the initialization data to the second slave microcontroller after an interval of one carrier cycle, and then set the second data pin to an input state to receive the initialization data returned by the second slave microcontroller; the i-th slave microcontroller is configured to set the first data pin to an input state to receive the initialization data sent by the i-1-th slave microcontroller according to the initialization control signal, and set the second data pin to an output state to send the initialization data to the i+1-th slave microcontroller after an interval of one carrier cycle, and then set the second data pin to an input state again; the N-th slave microcontroller is configured to set the first data pin to an input state to receive the initialization data sent by the N-1-th slave microcontroller according to the initialization control signal.

9. The control device of claim 8, wherein the N-th slave microcontroller is further configured to set the first data pin to an output state to send the initialization data to the N-1-th slave microcontroller after receiving the initialization data and an interval of one carrier cycle; the i-th slave microcontroller is further configured to receive the initialization data sent by the i+1-th slave microcontroller, and set the first data pin to an output state to send the initialization data to the i-1-th slave microcontroller after an interval of one carrier cycle; the first slave microcontroller is further configured to receive the initialization data sent by the second slave microcontroller, and set the first data pin to an output state to send the initialization data to the master microcontroller after an interval of one carrier cycle; the master microcontroller is further configured to receive the initialization data sent by the first slave microcontroller, and set the second data pin to an output state to send the initialization data to the first slave microcontroller after an interval of one carrier cycle.

10. The control device of claim 9, wherein the i-th slave microcontroller is further configured to: determine a first number of slave microcontrollers located on one side of the second data pin of the i-th slave microcontroller according to the carrier cycle and a first time difference; the first time difference is a time difference between sending the initialization data by the second data pin of the i-th slave microcontroller and receiving the initialization data by the second data pin; determine a second number of microcontrollers located on one side of the first data pin of the i-th slave microcontroller according to the carrier cycle and a second time difference; the second time difference is a time difference between sending the initialization data by the first data pin of the i-th slave microcontroller and receiving the initialization data by the first data pin; determine a station number of the i-th slave microcontroller in the control device according to the first number and the second number.

11. An electric motor drive, characterized by The control device according to any one of claims 1 to 10.

12. A control device characterized by comprising: The control device according to any one of claims 1 to 10.

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