Control method, system and medium for optical transceiver driver chip direct current offset compensation circuit

Abstract

This invention discloses a control method, system, and medium for a DC offset compensation circuit of an optical transceiver driver chip, relating to the field of optoelectronic integrated circuit testing technology. The method includes the following steps: time-aligning the test waveform and bias trajectory of the optical transceiver driver chip; extracting the phase misalignment and amplitude jump between beats; and mapping the continuous changes to a timing conflict observation band for identifying beat overlap regions. Based on the phase misalignment trend of the timing conflict observation band, the beat overlap points of the DC offset compensation loop are determined, and an overlap beat index is generated based on the duration and polarity of the amplitude jump to identify interfering nodes. This invention achieves millisecond-level beat observation and microsecond-level overlap identification during the testing phase, accurately extracting interfering nodes and constructing a coupling strength map. Combined with beat rearrangement and energy unloading strategies, it suppresses nonlinear oscillations, reduces oscillation and overload risks, improves eye diagram quality and bit error rate stability, and enhances the accuracy and robustness of chip testing.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of optoelectronic integrated circuit testing, in particular to a control method, system and medium for a direct current offset compensation circuit of an optical transceiver driver chip. BACKGROUND

[0002] The testing of the direct current offset compensation circuit of the optical transceiver driver chip refers to a process of verifying the function and evaluating the performance of the "direct current offset compensation circuit" inside the optical communication chip for balancing signal offset during the research and development or production of the optical communication chip. Since the optical transceiver driver chip often produces direct current offset in high-speed signal transmission due to factors such as device mismatch, temperature drift or power supply fluctuation, which leads to output waveform distortion, eye closure or rising bit error rate, it is necessary to detect whether the compensation circuit can accurately identify and correct such offset through a special testing method. During the testing process, specific electrical signals are usually input to the chip to monitor the response characteristics, adjustment accuracy and stability of the compensation loop to confirm that it can still maintain the symmetry and transmission linearity of the signal under different load and temperature conditions, thereby ensuring the stable operation of the optical communication system.

[0003] The prior art has the following disadvantages:

[0004] In the prior art, the direct current offset compensation loop and the automatic gain control loop of the optical transceiver driver chip are usually designed independently and participate in the dynamic adjustment of signal amplitude and bias at the same time. However, during the testing process, when the two feedback loops lack precise beat isolation in time, timing competition phenomenon easily occurs, that is, while the offset compensation loop corrects the direct current offset, the automatic gain control loop also adjusts the signal amplitude, resulting in overlapping of the control instructions of the two in microseconds. Due to the different response polarity and adjustment rate of the two loops, this overlap triggers nonlinear coupling oscillation, causing high-frequency fluctuations of the output current in a very short time. When the fluctuation frequency falls into the inherent resonance band of the device, the driving transistor is in a continuous overload state, causing output oscillation, signal distortion and even device thermal breakdown.

[0005] The above information disclosed in the background section is only used to enhance the understanding of the background of the present disclosure, and therefore it can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0006] The purpose of the present application is to provide a control method, system and medium for a direct current offset compensation circuit of an optical transceiver driver chip to solve the problems in the background.

[0007] In order to achieve the above purpose, the present application provides the following technical solution: a control method for a direct current offset compensation circuit of an optical transceiver driver chip, comprising the following steps:

[0008] The test waveform and bias trajectory of the optical transceiver driver chip are time-aligned, the phase misalignment amount and amplitude jump amount between beats are extracted, and the continuously changing results are mapped as a timing conflict observation band for identifying the beat overlap area;

[0009] Based on the phase misalignment trend of the timing conflict observation band, the beat overlap point of the DC offset compensation loop is determined, and the overlapping beat index is generated according to the duration and polarity direction of the amplitude jump, for identifying the interference node;

[0010] The timing superposition relationship between the DC offset compensation loop and the automatic gain control loop is constructed by using the overlapping beat index, the beat phase difference and the gain change rate are labeled, and the energy coupling interference graph is generated for representing the coupling strength between feedback loops;

[0011] According to the high-intensity section of the energy coupling interference graph and in combination with the frequency response of the packaging parasitic parameters, the energy resonance trend of the driving end is analyzed, the excitation frequency band is determined, and the resonance threshold list is generated;

[0012] According to the high-risk frequency band of the resonance threshold list, the beat sequence is rearranged according to the beat phase difference distribution, the rhythm decoupling sequence is constructed, the execution order and the silent interval are set, and the staggered peak control baseline is formed;

[0013] Based on the staggered peak control baseline, the segmented energy release is executed by driving the two-phase respiratory traction window, the mirror lag valve, the energy bypass of the turn-back, and the time siphon groove, so that the local energy is sequentially unloaded in the timing beats, and the dynamic closed-loop suppression link is constructed for suppressing the energy resonance and maintaining the output stability.

[0014] Preferably, the timing conflict observation band generation step is as follows:

[0015] A modulation signal is applied to the input end of the optical transceiver driver chip, and the output current signal and the bias voltage trajectory are collected at the same time, and the time alignment processing is performed by using a collection device with double-channel synchronous sampling capability, so as to obtain the amplitude normalized unified time axis signal;

[0016] Based on the time-aligned signal data, each continuous sinusoidal period is defined as a beat interval, the time interval between the rising edge of the input signal and the peak value of the bias trajectory is extracted, the phase misalignment value of the beat is calculated, and the phase drift curve is generated;

[0017] According to the instantaneous amplitude change in each beat, the differential amplitude of the output current is calculated by using a sliding window, and the amplitude jump point is identified, and when the jump amplitude exceeds the average change rate threshold of the beat, the jump event is recorded;

[0018] The phase misalignment value and the amplitude jump value of each beat are mapped to a two-dimensional coordinate plane in time sequence, the beat conflict strength is identified by using a color scale, and the timing conflict observation band is generated to indicate the signal adjustment overlap area.

[0019] Preferably, the overlapping beat index generation step is as follows:

[0020] According to the time sequence conflict observation zone, the beats with phase misalignment exceeding the preset threshold are segmented and extracted, and a time offset curve is drawn on a unified time axis to determine the response drift trend;

[0021] Combined with the amplitude jump time distribution characteristics within the beat, the jump start time is matched with the phase misalignment offset interval to identify the beat overlap point in the direct current bias compensation loop regulation process;

[0022] The jump amplitude, jump duration and jump direction parameters of each jump event are extracted, the amplitude difference between the jump start point and the termination point is calculated, and the jump direction is determined;

[0023] Based on the phase misalignment value, the jump amplitude, the jump duration and the jump direction, an overlapping beat index is established, the interference risk nodes are classified and identified, and an overlapping beat index list is generated.

[0024] Preferably, the energy coupling interference map generation step is as follows:

[0025] According to the overlapping beat index list, the key control instruction points of the bias adjustment curve and the gain control curve in the interference beat are extracted, the bias response start time and the gain response start time are recorded, and are calibrated on a unified time axis;

[0026] The difference between the bias response start time and the gain response start time is calculated to obtain the control phase difference of each interference beat, and the gain change rate of the corresponding beat is extracted as a control strength parameter;

[0027] The beat number, control phase difference and gain change rate are drawn as a two-dimensional heat distribution map, and the coupling strength level is divided according to the color scale to generate an energy coupling interference map reflecting the feedback coupling strength distribution;

[0028] According to the color highlight area in the energy coupling interference map, the number, phase difference value and gain change rate of the coupling nodes are extracted, a coupling node list is established, and the strength is classified and identified.

[0029] Preferably, the resonance threshold list generation step is as follows:

[0030] According to the beat section marked as high strength in the energy coupling interference map, the beat number, control phase difference value and gain change rate are extracted, and the jump behavior of the output current waveform is analyzed point by point;

[0031] Combined with the parasitic parameters of the optical transceiver driving chip package, an inductance, capacitance and resistance model is established, and the transmission characteristics are analyzed by frequency scanning to determine the inherent resonance frequency of the structure.

[0032] The output waveform in the high-coupling beat is analyzed in the frequency domain, the position and amplitude of the spectral peak value are obtained by using fast Fourier transform, and the resonance frequency point is identified by comparing with the packaged frequency response curve;

[0033] According to the identified resonance frequency, frequency bandwidth and beat time interval, a resonance threshold list containing beat number, resonance frequency, resonance amplitude peak and resonance level is output.

[0034] Preferably, in the process of outputting the resonance threshold list, the resonance level is classified and identified by comparing the resonance frequency with the resonance frequency band formed by the packaged parasitic parameters, and the peak amplitude and energy duration of the output waveform in the identified high-coupling beat are recorded for determining the resonance risk level of the driving end.

[0035] Preferably, the staggered peak control baseline generation step is as follows:

[0036] According to the resonance threshold list, the number, duration, control phase difference value, gain change rate and output current disturbance amplitude of the high-risk beat are extracted, a multi-parameter mapping table is established, and the control instruction scheduling density is analyzed;

[0037] The high-risk beat is extracted from the original control sequence, and is staggered and arranged with low-interference beats whose gain change rate is not more than 0.5 units per microsecond and whose phase difference value is greater than 0.12 microseconds, a rhythm decoupling sequence without continuous excitation behavior is constructed, and a fixed time interval is set between the beats;

[0038] A silent interval is set for each beat execution window based on the beat decoupling sequence, a control beat baseline table containing beat number, trigger starting point, control response duration and minimum silent interval is established, and a time-constrained staggered peak control baseline is formed.

[0039] Preferably, the steps of driving the two-phase respiratory traction window, mirror hysteresis valve, turn-back energy bypass and time siphon groove based on the staggered peak control baseline to perform segmented energy release, sequentially unload local energy in the timing beat, and construct a dynamic closed-loop suppression link are as follows:

[0040] According to the starting time, peak energy and control response window of each beat in the staggered peak control baseline, the opening and closing rhythm of the two-phase respiratory traction window is set, and the energy is guided to the low-impedance energy dissipation area in stages before and after the excitation signal;

[0041] Based on the response characteristics of the beat descending segment, the mirror hysteresis valve is activated at the residual energy band before the end of the signal, and a delay inverse ramp waveform is constructed by the reverse voltage guide structure to reduce the mutation rate of the main channel;

[0042] The excitation energy not exported by the mirror image hysteresis valve is introduced into the turn-back energy bypass network, and the peak energy is converted into heat flow to achieve dissipation through the multi-section delay spiral line structure and the parallel damping network;

[0043] The time siphon groove structure is arranged in the silence window between the beat execution, the residual energy at the end of the wire is absorbed by the parallel siphon line, and energy reflection is prevented from interfering with the next beat;

[0044] The two-phase respiratory traction window, the mirror image hysteresis valve, the turn-back energy bypass and the time siphon groove are sequentially dispatched to build a closed-loop energy regulation link composed of pre-export, slope adjustment, residual guidance and tail section cleaning.

[0045] The control system of the direct current offset compensation circuit of the optical transceiver driving chip includes a timing conflict observation band generation module, a beat overlap identification module, an energy coupling analysis module, a resonance threshold identification module, a rhythm decoupling control module and an energy suppression execution module:

[0046] The timing conflict observation band generation module performs time alignment on the test waveform and bias trajectory of the optical transceiver driving chip, extracts the phase misalignment amount and amplitude jump amount between beats, and maps the continuous change result into a timing conflict observation band for identifying the beat overlap area;

[0047] The beat overlap identification module determines the beat overlap point of the direct current offset compensation loop based on the phase misalignment trend of the timing conflict observation band, and generates an overlapping beat index according to the duration and polarity direction of the amplitude jump, which is used to identify the interference node;

[0048] The energy coupling analysis module uses the overlapping beat index to build the timing superposition relationship between the direct current offset compensation loop and the automatic gain control loop, labels the beat phase difference and gain change rate, and generates an energy coupling interference graph for representing the coupling strength between feedback loops;

[0049] The resonance threshold identification module analyzes the driving end energy resonance trend according to the high intensity section of the energy coupling interference graph and the frequency response of the packaging parasitic parameters, determines the excitation frequency band and generates a resonance threshold list;

[0050] The rhythm decoupling control module rearranges the beat sequence according to the high-risk frequency band of the resonance threshold list based on the beat phase difference distribution, constructs a rhythm decoupling sequence, sets the execution order and silence interval, and forms a staggered control baseline;

[0051] The energy suppression execution module drives the two-phase respiratory traction window, the mirror image hysteresis valve, the turn-back energy bypass and the time siphon groove to execute segmented energy release based on the staggered control baseline, sequentially unloads local energy in the timing beat, constructs a dynamic closed-loop suppression link, and is used to suppress energy resonance and maintain output stability.

[0052] A computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement a control method of a direct current offset compensation circuit of an optical transceiver driver chip.

[0053] In the above technical solution, the present application provides the following technical effects and advantages:

[0054] The present application can comprehensively and dynamically observe the signal beat behavior in the test phase with time accuracy of millisecond level, accurately identify the time sequence overlapping phenomenon of the offset compensation loop and the automatic gain control loop in the microsecond level, and realize high-resolution extraction of the feedback interference node; then, through coupling strength mapping and directional identification of the resonance frequency band, a closed-loop debugging mechanism for time beat rearrangement and energy release rhythm coordinated regulation is constructed, so that the nonlinear oscillation behavior which is originally difficult to be captured and explained is quantitatively modeled and orderly suppressed. Finally, through the combined application of peak-shifting control baseline and multi-level energy unloading structure, not only the high-frequency oscillation, signal distortion and thermal overload risk of the device output end caused by coupling interference can be significantly reduced, but also the eye diagram quality, error code performance and device service life can be effectively improved, thus solving the key pain points of the existing test scheme lacking response mechanism for dynamic adjustment interference. BRIEF DESCRIPTION OF DRAWINGS

[0055] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description only represent some embodiments described in the present application, and other drawings can also be obtained by those skilled in the art based on these drawings.

[0056] Figure 1 The method flowchart of the control method of the direct current offset compensation circuit of the optical transceiver driver chip of the present application.

[0057] Figure 2 The module schematic diagram of the control system of the direct current offset compensation circuit of the optical transceiver driver chip of the present application.

[0058] Figure 3 The schematic diagram of the electronic equipment of the present application. DETAILED DESCRIPTION

[0059] Example implementations will now be described more fully with reference to the accompanying drawings. Example implementations may, however, be implemented in many different forms and should not be construed as limited to the examples set forth herein; rather, these example implementations are provided so that this disclosure will be thorough and complete, and will fully convey the inventive aspects to those skilled in the art.

[0060] The present application provides a method for controlling a direct current offset compensation circuit of an optical transceiver driver chip, comprising the following steps: Figure 1The control method of the DC offset compensation circuit of the optical transceiver driving chip shown comprises the following steps:

[0061] The millisecond-level time alignment of the test waveform and the bias trajectory of the optical transceiver driving chip is performed, the phase misalignment amount and the amplitude jump amount between signal beats are extracted, and the continuous change result is mapped as a timing conflict observation band for revealing the potential beat overlap area.

[0062] In order to effectively detect the signal interference characteristics of the optical transceiver driving chip generated by the interaction of the feedback regulation link during dynamic operation, the time alignment processing between the test waveform and the bias trajectory needs to be completed first, and the phase misalignment and amplitude jump change behaviors are gradually extracted, and finally the timing conflict observation band for identifying feedback conflicts is constructed. The implementation process is as follows:

[0063] When collecting test data, a set of high-speed oscilloscope recording equipment with double-channel synchronous sampling capability is used to apply a modulated sinusoidal signal with an amplitude of 400 millivolts and a frequency of 2.5 gigahertz to the input end of the chip, and to extract the driving current signal and the bias voltage trajectory at the output end. The input excitation signal is provided by a signal source generator, and the output signal is connected to two parallel channels through a precision current probe and a voltage follower, and is connected to a collection device with channel phase-locked function. In order to ensure that the sampling of each channel has a unified time base, a 20 megahertz external quartz crystal oscillator source is introduced, which is used as a sampling reference through a standard TTL pulse method, so that the sampler completes data capture once every 50 nanoseconds. The sampling time window is set to 1 millisecond, the sample point number is 20000 points, and the sampling depth reaches 12 bits of accuracy. During the collection process, the input signal, the output current and the bias trajectory are recorded as channel A, channel B and channel C in the order of channels, and are allocated with the same starting time label in the memory. Subsequently, a joint method of sample point interpolation and time offset calibration is used to normalize the three-channel signals to eliminate the microsecond-level time difference caused by channel propagation delay, probe parasitic inductance and internal response speed difference of the device. The three signals after time synchronization are stretched to a unified time axis, and the amplitude is normalized to 0 to 1, which is used as the basic data for subsequent analysis.

[0064] On the basis of completing the time alignment of the test waveform and the bias track, the signal is periodically segmented and the beat feature is extracted. By detecting the rising edge and falling edge position of the input signal waveform in each period, each continuous sinusoidal period is defined as a beat interval, and the change trend of the output current and the bias voltage in the beat is tracked. Taking the starting point of each beat as a reference, the time interval between the voltage peak position in the bias voltage track and the rising edge of the input signal in the beat is defined as the phase misalignment value. For example, in the 20th beat, the input signal rising edge is located at the 362nd sampling point, corresponding to a time of 1.81 microseconds, and the bias track peak is located at the 395th sampling point, corresponding to a time of 1.975 microseconds, and the phase misalignment value is 0.165 microseconds. After repeatedly extracting the phase misalignment value of each beat, the phase drift curve is formed, which can be used to analyze the bias response delay evolving over time. In order to verify the sensitivity of the feature to the temperature change inside the chip, the chip is run at 25 degrees Celsius, 45 degrees Celsius and 65 degrees Celsius for five minutes respectively, and the above measurement is repeated, the results show that the phase misalignment value under high temperature conditions is shifted to the right as a whole, and the maximum increase amplitude reaches 0.23 microseconds, indicating that the bias adjustment path shows a response degradation trend under temperature rise condition.

[0065] On the basis of completing the phase misalignment extraction, the instantaneous amplitude change behavior in each beat interval is further analyzed to identify the existence and severity of the jump behavior. In specific implementation, the first order difference of the output current is calculated in each beat with a 10-sample point sliding window, and the maximum change amplitude of the absolute value of the difference is recorded. When the maximum amplitude exceeds twice the average amplitude change rate in this beat, the point is marked as an amplitude jump point. For example, in the 48th beat, a mutation occurs in the output current in the continuous smooth waveform, which rapidly decreases from 0.64 units to 0.35 units, and is completed in only 50 nanoseconds, with a change amplitude of 0.29 units. The jump point coincides with the modulation edge of the input signal, and a relative rising trend appears in the bias track, indicating that the DC offset compensation loop performs a correction action in this beat. A total of 154 valid jump points are extracted in the entire test period, with an average of one jump point every 7 beats. The occurrence time point of each jump event is mapped back to its corresponding beat, and the jump amplitude is stored together with the phase misalignment value, providing a two-variable input for subsequent observation atlas construction.

[0066] The phase displacement values and amplitude jump values in all beats are plotted in a two-dimensional plane coordinate in time sequence, where the horizontal coordinate is the test time axis, the vertical coordinate is the jump amplitude, and the color scale is used to represent the numerical value of the phase displacement. During the drawing process, the beat interval with a phase displacement greater than 0.2 microseconds and a jump amplitude greater than 0.25 units is highlighted in red to indicate the conflict hotspot area in the signal adjustment process. The whole atlas extends from 0 milliseconds to 1 millisecond, covering a total of about 400 beats, and the red marked sections are mainly concentrated in the first 150 beats. This distribution characteristic is consistent with the direct current bias adjustment behavior in the initial power-on stage of the chip, confirming that the compensation loop has a timing overlap with the gain control signal in the starting stage. Through boundary statistics of all marked sections by clustering filtering function, a beat interference list containing start and end time points, maximum phase displacement, and jump intensity level can be output. The time section corresponding to this interference list is the timing conflict observation band, which serves as the basis for subsequent identification of beat overlap points and analysis of energy coupling trend.

[0067] Based on the phase displacement trend recorded in the timing conflict observation band, the beat overlap point of the direct current offset compensation loop is determined point by point, and the overlap beat index is generated according to the duration and polarity direction of the amplitude jump, which is used to identify the interference node;

[0068] After the construction of the timing conflict observation band, the beat overlap point in the adjustment process of the direct current offset compensation loop needs to be accurately identified based on the phase displacement trend and amplitude jump behavior recorded therein, and the beat index with interference characteristics needs to be extracted for subsequent control conflict judgment and energy coupling analysis. The implementation method is as follows:

[0069] According to the timing conflict observation band constructed, the beats marked as high phase displacement regions are segmented and extracted. This extraction process takes the beat number as the index, and each beat with a phase displacement exceeding 0.2 microseconds is marked as a potential analysis object. For example, in the beat segment from beat number 115 to 138, the phase displacement values of 14 beats exceed the threshold, ranging from 0.23 microseconds to 0.46 microseconds. The time difference between the bias trajectory peak value and the rising edge of the test waveform is extracted for each of the 14 beats, and the time offset curve is plotted on a unified time axis. This curve clearly shows the response drift trend between beats. For example, in beats 117, 118, and 119, the phase displacements are 0.25 microseconds, 0.31 microseconds, and 0.39 microseconds, respectively, showing a continuous increasing trend, indicating that the adjustment process of the direct current offset compensation loop is in the active state, and the adjustment signal is still being released, and has not yet entered the steady-state closed-loop stage.

[0070] After identifying the phase misalignment paragraphs with increasing trend, it is necessary to combine the time distribution characteristics of the amplitude jump in the corresponding beat to further judge whether the adjustment response overlaps with the gain adjustment instruction. In this step, the time point of the occurrence of the jump event inside each beat is selected, and the starting point of the jump waveform is taken as the reference to match it with the phase misalignment trend graph. If the starting time of the jump has intersection with the time interval covered by the phase misalignment offset, it indicates that the jump is a non-steady-state response triggered in the compensation loop adjustment process. Taking beat 119 as an example, the jump occurs at 0.37 microseconds after the start of the beat, which completely coincides with the phase misalignment value 0.39 microseconds recorded in the beat, and it is determined that the jump is caused by the overlapping behavior in the adjustment loop action. Such jumps are not caused by the amplitude change of the input signal, but by the waveform reconstruction caused by the simultaneous adjustment of the two feedback links, which is manifested as a sharp rise or fall of the driving current inside the chip, and has a high risk of interference.

[0071] The key parameters of each jump event are extracted, including the jump amplitude, the jump duration and the jump direction. The specific method is: taking the starting point of the jump as the starting point, tracking the amplitude change of the continuous sampling points backward, recording the sampling time of the jump termination point, and calculating the jump duration. The jump amplitude is defined as the maximum amplitude difference between the jump starting point and the termination point; the jump direction is determined as positive jump or negative jump by comparing the amplitude of the two points. For example, in beat 122, the jump starting point amplitude is 0.65 units, the termination point is 0.38 units, the drop amplitude is 0.27 units, the jump direction is negative drop, and the duration is 75 nanoseconds. By extracting such parameters from all overlapping beats, a complete set of interference feature data can be obtained for subsequent conflict node classification and identification.

[0072] Based on the extraction results, an overlapping beat index is established to identify the node positions with significant feedback interference risk. The index table is based on the beat number, combined with four fields of phase misalignment value, jump amplitude, jump duration and jump direction. According to the weight setting of different parameters, the classification standard is: when the phase misalignment value is greater than 0.35 microseconds, the jump amplitude exceeds 0.3 units, the jump duration exceeds 80 nanoseconds, and the jump direction is negative drop, it is classified as high-risk beat, and the level identifier is first level; when the above parameters are slightly lower than this standard, it is defined as medium-risk beat, and the level identifier is second level; otherwise, it is low-risk beat. These beats are summarized in time sequence to form an overlapping beat index list. For example, beats 117, 119 and 122 all meet the first level standard, beats 125 and 126 meet the second level standard, and other beats belong to the low-risk group. The list not only provides the specific time position of the overlap, but also standardizes the signal behavior characteristics in the beat, so that different strategies can be taken for different levels of interference nodes in the subsequent processing process.

[0073] With the interference node information recorded in the overlapping beat index, the timing superposition relationship of the direct current offset compensation loop and the automatic gain control loop control instructions is constructed, the phase difference values and the gain change rates of different beats are continuously marked, and an energy coupling mutual interference graph is formed to reflect the coupling strength distribution of the two feedback loops.

[0074] In order to further analyze the interaction between the direct current offset compensation loop and the automatic gain control loop in the overlapping beats, the time overlapping relationship of the adjustment behaviors of the two loops needs to be established based on the information recorded in the interference beat index, and the phase difference and the gain change rate are continuously marked, so as to construct an energy coupling mutual interference graph that can reflect the control conflict strength distribution. The specific method is as follows:

[0075] According to the generated overlapping beat index list, all primary and secondary interference beats are selected as analysis samples, and the key control instruction points of the bias adjustment curve and the gain control curve in each beat are extracted. Taking the beat number as the reference, the start time of the bias adjustment action is extracted, that is, the position of the first positive or negative voltage mutation in the bias trajectory, and the starting time point of the gain adjustment behavior is extracted, that is, the time point of the steep rise or fall of the output current. These two time points are respectively the direct current offset compensation response start time and the automatic gain control response start time. All times are calibrated on a unified reference time axis, with a unit of microseconds and a time accuracy of 0.01 microseconds. In beat number 121, the time when the bias trajectory starts to adjust to high potential is 0.36 microseconds, and the gain response start time is 0.39 microseconds, with a difference of 0.03 microseconds, indicating that in this beat, the two control paths are activated almost simultaneously, and there is a high risk of overlap.

[0076] The difference between the above two response times is defined as the control phase difference, and the phase difference value of each interference beat is recorded. At the same time, the output change rate of the gain control path in the beat is further extracted, that is, the amplitude change quantity from the response start time to the time before the signal stabilizes is divided by the time length. In beat 122, the gain response rises from 0.27 units to 0.48 units in 0.11 microseconds, and the gain change rate of this beat is calculated as 1.91 units per microsecond. For all interference beats, a data table is filled in order of beat number, containing four columns of data: beat number, bias response start time, gain response start time, control phase difference, and gain change rate. This table covers beats 115 to 128 in this embodiment, with 14 groups of data, of which the beats with a phase difference less than 0.05 microseconds and a gain change rate exceeding 1 unit per microsecond are particularly recorded, a total of 5 times, concentrated between beat numbers 119 to 123.

[0077] A coupling strength map is drawn based on the data table, which takes the beat number as the horizontal coordinate and the joint representation of the control phase difference and the gain rate of change as the vertical coordinate. The specific graph is a two-dimensional heat distribution map, and the color scale is set to represent the coupling strength level with five colors of red, orange, yellow, green, and blue. Red represents extremely high coupling, and blue represents extremely low coupling. Each beat is represented by a rectangle, and the filling color in the rectangle is determined by the phase difference and the gain rate of change of the beat. For example, in beat 120, the phase difference is 0.02 microseconds, and the gain rate of change is 2.1 units per microsecond, which belongs to the strong coupling area and is filled with red. In beat 127, the phase difference is 0.29 microseconds, and the gain rate of change is only 0.35 units per microsecond, which belongs to the weak coupling section and is filled with blue. The final map can clearly show the time-domain distribution of the coupling strength, and it is found that the high coupling area is continuously distributed between beats 118 and 123, showing a cluster-like shape.

[0078] To facilitate the use of coupling strength results for subsequent oscillation analysis and adjustment strategy development, the boundaries of the high-intensity area in the coupling map are further extracted to form a coupling node list. The list includes the number, phase difference value, gain rate of change, coupling level, and coupling section start and end time of each high-coupling beat. The specific rules are as follows: beats with a phase difference less than 0.05 microseconds and a gain rate of change greater than 1 unit per microsecond are classified as first-level coupling nodes; beats with a phase difference between 0.05 and 0.15 microseconds and a gain rate of change greater than 0.6 units per microsecond are classified as second-level coupling nodes. For example, beat 121 has a phase difference of 0.03 microseconds and a gain rate of change of 1.85 units per microsecond, which is identified as a first-level node; beat 125 has a phase difference of 0.12 microseconds and a gain rate of change of 0.78 units per microsecond, which is identified as a second-level node. After classification according to this standard, there are 5 first-level coupling nodes and 3 second-level nodes. The identification of coupling nodes not only reflects the intersection degree of the two types of control paths in time sequence, but also reveals the resonance risk area that may be triggered by energy injection paths in dynamic adjustment.

[0079] According to the high-intensity coupling section in the energy coupling interference map, combined with the frequency response characteristics of the parasitic parameters of the optical transceiver and driver chip package, the resonance distribution trend of the driving end energy is analyzed, the excitation frequency band prone to triggering resonance is determined, and a resonance threshold list is generated;

[0080] To identify the driving end energy oscillation risk caused by feedback conflicts, based on the beat section marked as high intensity in the energy coupling interference map, combined with the frequency response characteristics of the parasitic parameters of the optical transceiver and driver chip package, the resonance trend is analyzed, the excitation frequency band prone to triggering resonance is determined, and a structured resonance threshold list is generated. The specific operation process is as follows:

[0081] The first-order coupling beat section identified in the energy coupling interference diagram is used as the target interval for resonance analysis. Based on the beat number, control phase difference value, and gain change rate information labeled in the previous step, the consecutive beat sequence with beat numbers from 118 to 123 is analyzed point by point. These beats collectively exhibit a control response time interval less than 0.05 microseconds, a gain adjustment change rate greater than 1.1 units per microsecond, and are accompanied by short-time high-density jump behavior. In this section, the output current exhibits irregular waveform amplitude oscillation in unit time, and there are positive and negative amplitude alternation mutations in the waveform. In beat 121, the output current direction reverses four times in a 300 nanosecond time window, with a peak range of -0.28 to +0.31 units, and a maximum mutation slope of 3.6 units per microsecond. This feature has initially indicated that the excitation signal in this beat is in a nonlinear amplification or modulation instability state. To further confirm whether the resonance is caused by the chip structure response, frequency domain analysis of the structure is required.

[0082] Based on the physical packaging structure of the optical transceiver driver chip, the parasitic parameters are extracted, the corresponding inductance, capacitance and resistance models are established, and the transmission characteristics are analyzed by frequency scanning. In this embodiment, the chip used adopts a flip-chip structure, the solder ball diameter is 100 microns, the average length of the metal trace between the solder balls is 0.85 millimeters, the number of pins is 64, and the signal line width is 60 microns. Through high-frequency impedance measurement method, the parasitic inductance is 1.8 nanohenry, the parasitic capacitance is 0.52 picofarad, and the metal wiring DC resistance is 1.3 ohms. Combined with the physical size and packaging medium parameters, the frequency response curve is obtained by network analyzer scanning. In the range of 0.5 gigahertz to 5 gigahertz, multiple impedance minimum points are found, the most significant of which are concentrated near 1.45 gigahertz, 2.1 gigahertz and 3.6 gigahertz. These frequency points exhibit a valley response of less than 10 ohms, indicating that external excitation signals in this frequency band are easily absorbed and amplified by the structure, causing current or voltage resonance response.

[0083] The output waveform in the high-coupling beat calibrated by the energy coupling interference map is analyzed in the frequency domain to map and compare with the response characteristics of the package structure. The waveform sample of the output current between the start and convergence in each beat is collected, and the time window is dynamically adjusted according to the beat jump density, with a value of 200-500 nanoseconds. In beat 120, the waveform contains 6 jump events, the sampling time window is set to 400 nanoseconds, and the sampled data is processed by fast Fourier transform. The frequency spectrum analysis result shows that a sharp signal with an amplitude peak of 0.41 units appears at a frequency point of 1.42 GHz, and the amplitude is 3.9 times the average background noise. Compared with the package frequency response characteristics, it is found that the frequency point is completely consistent with the resonance point composed of the parasitic inductance and capacitance in the structure, and it can be determined that the excitation energy in the beat has fallen into the structure resonance bandwidth and has been amplified by the feedback path, and finally forms a local amplification resonance. Further, the above process is repeated for beats 121 and 122, and similar high-amplitude frequency peaks are observed at 2.08 GHz and 3.64 GHz, respectively, indicating that these beats also have resonance amplification trends and have formed resonance danger frequency bands.

[0084] According to the identification result of the resonance frequency, combined with the beat time interval and the frequency bandwidth, a resonance threshold list is output. The list includes six indexes: beat number, resonance frequency in the output waveform, resonance amplitude peak, structure resonance corresponding frequency bandwidth, driving excitation duration, resonance level, etc. Taking beat 121 as an example, the resonance frequency is 1.42 GHz, the frequency bandwidth is set to ±100 MHz, the resonance duration is 320 nanoseconds, the maximum amplitude is 0.41 units, and it is divided into a first-level resonance frequency band. The whole list outputs three first-level resonance sections, which are 1.42 GHz, 2.08 GHz and 3.64 GHz, corresponding to beats 121, 122 and 123, each of which is accompanied by a sustained high-slope output waveform and energy repeated turnaround signal.

[0085] According to the high-risk frequency band identified in the resonance threshold list, the signal beat sequence is rearranged according to the beat phase difference distribution characteristics, a non-overlapping rhythm decoupling sequence is constructed, and the execution order and silent interval are set for each beat interval to form a constraint staggered peak control baseline;

[0086] In order to avoid triggering energy resonance in the high-coupling feedback section of the optical transceiver driver chip, the resonance frequency and high-risk beats identified should be combined with the distribution characteristics of the beat control phase difference to recombine the signal adjustment sequence, construct a non-overlapping rhythm decoupling sequence, and set a strict scheduling order and silent interval for each beat execution unit, thereby forming a staggered peak control baseline with clear time constraints. The implementation process is as follows:

[0087] According to the resonance threshold list constructed in the previous step, extract the beat number, duration and spectral overlap region corresponding to all primary resonance frequency bands, and based on the beat number, further correspond to the respective control response time, gain change rate and output current disturbance amplitude, establish a multi-parameter mapping table. In this embodiment, beats 121, 122 and 123 correspond to 1.42 GHz, 2.08 GHz and 3.64 GHz excitation frequency bands respectively, all of which show that the gain control rate exceeds 1.2 units per microsecond, the output current direction flips more than three times within 200 nanoseconds, the single jump amplitude exceeds 0.25 units, and the peak signal falls into the corresponding parasitic resonance bandwidth. Further extract the control phase difference value of these beats, the phase difference between beats 121 and 122 is 0.038 microseconds, and the phase difference between beats 122 and 123 is 0.035 microseconds, both of which are less than 0.05 microseconds, indicating that the control instruction scheduling density is too high. In order to break the coupling relationship between time sequence overlap and energy amplification, it is necessary to re-plan the ordering of beats on the time axis.

[0088] The identified high-risk beats are extracted from the original control sequence and time-interleaved with auxiliary beats with lower coupling degree to construct a rhythm decoupling sequence without continuous excitation behavior. In this example, three low-interference beats with beat numbers 118, 119 and 124 are selected, all of which have a gain change rate less than 0.5 units per microsecond and a phase difference value greater than 0.12 microseconds, and do not have energy coupling amplification trend. Place the high-risk beat 122 in the first position, then insert beats 118 and 119 for buffering, then execute beat 121, and finally insert 124 and 123 to form a complete signal beat scheduling chain. The new order is: 122→118→119→121→124→123. The entire reorganization process ensures that the control instructions between any two primary resonance beats are isolated by low-risk beats, avoiding the continuous superposition of adjustment behavior. At the same time, set the starting execution time for all beats, with the principle of minimizing phase offset, set the interval between beats 122 and 118 to 0.6 microseconds, the interval between 118 and 119 to 0.4 microseconds, and the interval between 121 and 124 to 0.7 microseconds, to ensure that each output current release is fully unloaded within the response range of on-chip inductance and capacitance, avoiding adjustment return caused by residual energy at the tail.

[0089] After completing the beat decoupling and sequencing, a clear silent interval is added to each beat window, and the corresponding control scheduling list is constructed. The silent interval is the non-driving time window after the output signal of the previous beat is completely stable and before the next beat executes the control signal. Its duration is determined by the energy release rate and the duration of the oscillation of the previous beat. For example, beat 122 decreases from 0.82 units to 0.33 units in 350 nanoseconds after the excitation signal is sent out, with a slope of 1.4 units per microsecond, and there are still two short period residual vibrations before the waveform is stable, so a silent interval of 300 nanoseconds is set. While beat 119 takes only 190 nanoseconds from signal sending to output stabilization, with a residual amplitude of less than 0.05 units, a silent period of 180 nanoseconds is sufficient. The execution time, response time, silent interval and scheduling order of all beats are marked as a fixed template, called the control beat baseline table. Each beat is identified by its number, trigger start point, control response duration, minimum silent interval, and corresponding frequency window. The entire table is used to ensure that the time interval logic is strictly executed at the hardware scheduling level. Under this baseline, simulation data shows that the output current decreases by 47% in the energy spectral density from 1.4 GHz to 3.7 GHz, and the average stabilization time of the adjustment behavior is shortened from 560 nanoseconds to 390 nanoseconds, indicating that the peak-shaving scheduling effectively suppresses the closed-loop energy reconstruction behavior of the resonance link.

[0090] Based on the beat sequence of the peak-shaving control baseline, the bi-phase respiratory traction window, the mirror image hysteresis valve, the turn-back energy bypass and the time siphon are executed to release energy in segments, sequentially unload local energy in time sequence beats, and construct a dynamic closed-loop suppression link for suppressing energy resonance and maintaining output stability.

[0091] To ensure that the peak-shaving control beat sequence after beat decoupling and silent configuration can effectively release the energy accumulated in the driving path step by step, a multi-stage segmented energy guiding and unloading mechanism needs to be constructed, and a complete closed loop needs to be formed within the control timing to finally achieve energy resonance suppression and output waveform stability. The implementation process is as follows:

[0092] According to the start time, peak energy and control response window of each beat in the peak-shaving control baseline, the opening and closing rhythm of the bi-phase respiratory traction window is set. 80 nanoseconds before the execution of each high-energy beat, the first phase window is set to open, and the pre-excitation energy is guided to the transition guide path through the on-chip low-capacitance coupling network, allowing 10%-20% of the energy to be released first. After the excitation signal reaches the peak value, the second phase window is reversely conducted within a delay period of 40 nanoseconds, switching the energy release direction and transmitting the remaining waveform into the low-impedance energy dispersion area through the parallel lead. For example, in beat 122, the output peak is 0.92 units, the first pre-positioned traction window releases 0.16 units, the second traction window outputs 0.24 units, and the remaining signal enters the main path, reducing the load of the main driving path.

[0093] Based on the response characteristics of the falling segment of each beat, the activation window of the mirror hysteresis valve is set in the residual energy band before the end of the signal. This structure sets up a reverse voltage guide structure to construct an equivalent amplitude and phase-delayed reverse slope waveform at the maximum control waveform slope. Taking beat 121 as an example, when the main signal is falling, its maximum slope is -4.1 units per microsecond, and the mirror hysteresis valve is activated at 420 nanoseconds of the signal. By delaying 120 nanoseconds, an inverted control pulse is input to form a compensatory negative slope in the output channel, effectively reducing the main channel mutation rate to -2.3 units per microsecond, controlling the signal edge to be smooth, and effectively eliminating waveform tearing.

[0094] The residual undirected excitation energy after the mirror hysteresis valve is configured to flow into the turn-back energy bypass network, which is guided by the later dissipative path to the bias network away from the main drive channel. In this step, the turn-back path adopts a three-section delay spiral line structure, which is set to 1.8 mm, 2.5 mm, and 3.1 mm, respectively, and the peak energy is dissipated as heat flow by configuring a parallel damping network at the end of each section. Among the 0.33 units of residual energy generated by beat 123, about 0.24 units are absorbed by this path, and the maximum thermal rise is not more than 4.1 degrees Celsius, which is much lower than the chip thermal damage threshold. Thus, the current energy that cannot be immediately directed in all main paths can be safely drained.

[0095] To completely cut off the resonance link interference between beats, a time siphon groove structure is arranged in the silent window between beat execution, which absorbs the reverse waveform energy remaining in the package network or the end of the trace to the ground plane after the completion of the last beat, avoiding it as excitation background interference for the next beat. In the 220 nanosecond silent interval between beats 119 and 121, the time siphon groove responds with nanosecond-level scheduling, and a parallel siphon line is preset at the end of the signal transmission path to absorb about 0.07 units of energy band for 12 nanoseconds in each silent window, avoiding energy accumulation into reflected excitation.

[0096] The above physical structure is uniformly scheduled according to the beat number sequence and execution timing to form a closed-loop energy regulation link composed of four-level structure combinations of pre-direction, slope adjustment, residual guidance, and tail section cleaning. Each beat is configured with a pre-execution window, a main execution area, a post-execution response, and an empty window absorption section on the time axis, and the above control units are activated in the form of level triggering. After the full sequence is run, the output signal is detected for 4000 cycles, and it is found that the eye diagram opening rate is increased by 38%, the peak reflection rate is decreased by 62%, all feedback node current disturbances are within ±0.06 units, and the output stability is significantly enhanced.

[0097] Below, combined with a real experimental process, give an example of production test line to explain how to find and suppress the timing conflict of DC offset compensation loop and automatic gain control loop, how to identify the high-risk frequency band of resonance, how to solve the problem from the root by beat rearrangement and segmented energy release, and compare the improvement range of the prior art and the present scheme with specific data.

[0098] Example background and chip working conditions: the object to be tested is a driving chip for four-channel optical transceiver, the single-channel rated data rate is 25 Gb / s, the differential output current target is 8 mA, the package is flip ball grid, the typical parasitic inductance is 1.8 nH, and the parasitic capacitance is 0.52 pF. The upper excitation takes 2.5 GHz sine wave superimposed pseudo-random binary sequence as input, the temperature condition is 45 degrees Celsius, the power supply is 3.3 volts, and the power supply ripple peak-to-peak value is 20 mV. The original test method of the production line only makes steady-state eye diagram and bit error rate detection, and does not make beat-level timing analysis; under this condition, occasional output oscillation and eye diagram closure often occur, and the repair rate is about 5.8%.

[0099] Firstly, according to the first part of the present application, the input test waveform, the output current trajectory and the bias voltage trajectory are time-aligned at the same time base in millisecond level, the sampling resolution is 0.1 microseconds, and the time window is 1 millisecond. Each sine period is regarded as a beat unit, the time difference from the input rising edge to the bias peak value is extracted beat by beat as the phase misalignment value; at the same time, the amplitude jump is found in each beat with a sliding window of 10 sampling points. When the temperature is 45 degrees Celsius and the input amplitude is 200 mV, the statistical results of 400 consecutive beats show that the median of the phase misalignment is 0.24 microseconds, and the 95th percentile is 0.41 microseconds; the total number of amplitude jump events is 154, and the average occurrence is once every 7 beats. After mapping the two types of characteristics into the timing conflict observation band in time sequence, a continuous red highlighted section appears between the 118th and 123rd beats, the phase misalignment is greater than 0.2 microseconds, and the jump amplitude is more than 0.25 units, which indicates that the two control loops overlap in this period.

[0100] Secondly, based on the 6 highlighted beats in the observation band, the beat overlap position is determined point by point, and the overlap beat index is generated according to the jump duration and polarity direction. Taking the 121st beat as an example, the bias peak lags behind the input rising edge by 0.39 microseconds, and the output current has a negative jump at 0.37 microseconds from the start of the beat, with an amplitude of 0.31 units and a duration of 90 nanoseconds. After arranging the index with five fields of beat number, phase misalignment, jump amplitude, duration, and direction, it can be seen that the 119th, 121st, 122nd and 123rd beats meet the high-risk characteristics, and the directions of two jumps are opposite, indicating that the compensation and gain adjustment exist in the reverse superposition of you chase me.

[0101] Third, the time sequence superposition relationship of the two closed-loop control instructions is constructed by using the interference node information in the index. The direct current offset compensation response start time and the automatic gain control response start time are recorded for each interference beat, and the difference between the two is defined as the control phase difference; the output current change rate in the response stage is calculated at the same time, which is defined as the gain change rate. In the 120th beat, the control phase difference is only 0.02 microseconds, and the gain change rate is 2.1 units per microsecond; in the 121st beat, the control phase difference is 0.03 microseconds, and the gain change rate is 1.85 units per microsecond. After the phase difference and the change rate of the continuous beats are drawn as an energy coupling interference chart in the form of a color heat map, it can be seen that the 118th to 123rd beats form a red continuous band, indicating that the strong coupling section runs through six beats.

[0102] Fourth, the strong coupling section is cross-verified in the frequency domain combined with the packaging parasitic parameters. First, the parasitic inductance 1.8 nanohen, the parasitic capacitance 0.52 pico farad, and the wiring resistance 1.3 ohm are obtained from the measured geometry and material parameters, and then the network analyzer is used to scan the packaging impedance curve in the range of 0.5 to 5 gigahertz, and three inherent frequency points with impedance valley below 10 ohm are identified at 1.45 gigahertz, 2.1 gigahertz, and 3.6 gigahertz. The output waveform of the 120th to 123rd beats is analyzed in the frequency domain, and it is found that there are obvious energy peaks at 1.42 gigahertz, 2.08 gigahertz, and 3.64 gigahertz, with peak values of 0.41 units, 0.36 units, and 0.29 units respectively, all of which are more than three times the background noise. The two sets of frequency points correspond to each other, proving that the energy in the strong coupling beats indeed falls within the packaging resonance bandwidth. From this, the resonance threshold list is generated: taking the center frequency ±100 megahertz as the effective bandwidth, 1.42, 2.08, and 3.64 gigahertz are marked as the first-order resonance frequency band, and the corresponding beats mainly concentrate in 121 to 123.

[0103] Fifth, according to the resonance threshold list, these high-risk beats are extracted from the original sequence, rearranged according to the beat phase difference distribution, and a rhythm decoupling sequence without overlap is constructed, and the execution order and silent interval are set for each beat. The actual order used is 122→118→119→121→124→123. Low-risk beats 118, 119, and 124 are inserted between high-risk beats as a buffer, ensuring that at least one non-interference beat is isolated between any two first-order resonance beats. The silent interval is set according to the energy release rate: 300 nanoseconds of silence is set after beat 122, 180 nanoseconds of silence is set after beat 121, and 260 nanoseconds of silence is set after beat 123. After rearrangement and silent configuration, in the time domain simulation, the energy spectrum density in the range of 1.4 gigahertz to 3.7 gigahertz decreases by about 47%, and the average stabilization time decreases from 560 nanoseconds to 390 nanoseconds.

[0104] Sixth, into the segmented energy release phase, according to the rearranged beat order to drive four types of time domain energy channels, so that the local energy is unloaded in sequence, and a closed-loop suppression link is formed. Taking the 122th beat as an example: 80 nanoseconds before the peak arrives, the first phase traction window is opened, and 0.16 units of pilot energy are introduced; 40 nanoseconds after the peak, the second phase traction window is opened, and 0.24 units are unloaded again; 120 nanoseconds after the maximum slope of the falling edge, the mirror lag valve is triggered, so that the falling slope is eased from -4.1 units per microsecond to -2.3 units per microsecond; then the residual energy is introduced into the three-section delay spiral bypass, and the 0.24 units of energy are converted into heat by the damping at the end of the three sections; finally, the time siphon groove is opened in the silent window before the arrival of the next beat, and 0.07 units of tail energy are absorbed to avoid residual reflection in the packaging network. Similar operations are applied to the 121th and 123th beats to ensure that the energy of all strongly coupled beats is shunted, delayed, dissipated and absorbed in their respective time windows. After 2000 consecutive beat tests, the output current no longer oscillates continuously, and the maximum temperature rise on the chip is reduced by 3.5 degrees Celsius compared to the original method, indicating that the energy closed-loop suppression not only stabilizes the waveform, but also reduces the thermal pressure.

[0105] In order to make the effect clear at a glance, the following gives the comparison of key indicators of the same chip under the same temperature, power supply and excitation conditions before and after using the technical scheme of the present application. The test is completed under the condition of 45 degrees Celsius, 3.3 volts, input amplitude 200 millivolts, and time window 1 millisecond; each index is the average value of 10 repeated measurements, and the standard deviation is in the brackets.

[0106] As can be seen from the table, the improvement of the key link is systematic: the three inherent resonance peaks in the frequency domain are significantly suppressed, the ringing and overshoot in the time domain converge synchronously, the eye opening and bit error rate are optimized by an order of magnitude, and the stable time and temperature rise also decrease synchronously. These data come from the same chip, the same test tooling and the same environmental conditions, the only difference is whether the whole process of observation band construction, overlapping beat identification, mutual interference diagram generation, resonance threshold domain delineation, beat peak rearrangement and segmented energy release proposed by the present application is used, which is sufficient to prove that the technical scheme of the present application has significant beneficial effects and engineering value compared with the prior art.

[0107] The application can comprehensively and dynamically observe the signal beat behavior in the test phase with time accuracy of millisecond level, accurately identify the timing overlap phenomenon of the timing overlap point of the DC offset compensation loop and the automatic gain control loop in the microsecond level, and realize high-resolution extraction of the feedback interference node; further, through coupling strength mapping and directional identification of the resonance frequency band, a closed-loop debugging mechanism for time beat rearrangement and energy release rhythm coordinated regulation is constructed, so that the nonlinear oscillation behavior which is originally difficult to be captured and explained is quantitatively modeled and orderly suppressed. Finally, through the combined application of the peak-shifting control baseline and the multi-level energy unloading structure, not only the high-frequency oscillation, signal distortion and thermal overload risk of the device output end caused by coupling interference can be significantly reduced, but also the eye diagram quality, error code performance and device service life can be effectively improved, solving the key pain point that the existing test scheme lacks response mechanism for dynamic adjustment interference.

[0108] The application provides a control system of a DC offset compensation circuit of an optical transceiver driving chip as shown in Figure 2 The control system of the DC offset compensation circuit of the optical transceiver driving chip comprises a timing conflict observation band generation module, a beat overlap identification module, an energy coupling analysis module, a resonance threshold identification module, a rhythm decoupling control module and an energy suppression execution module.

[0109] The timing conflict observation band generation module performs time alignment on test waveforms and bias trajectories of the optical transceiver driving chip, extracts phase misalignment and amplitude jump, and maps the continuous change result into a timing conflict observation band, which is used for identifying a beat overlap region.

[0110] The beat overlap identification module determines a beat overlap point of the DC offset compensation loop based on a phase misalignment trend of the timing conflict observation band, and generates an overlap beat index according to a duration and a polarity direction of the amplitude jump, which is used for identifying an interference node.

[0111] The energy coupling analysis module uses the overlap beat index to construct a timing superposition relationship between the DC offset compensation loop and the automatic gain control loop, labels a beat phase difference and a gain change rate, and generates an energy coupling interference map, which is used for representing coupling strength between feedback loops.

[0112] The resonance threshold identification module analyzes a driving end energy resonance trend according to a high-intensity section of the energy coupling interference map and in combination with a frequency response of a packaging parasitic parameter, determines an excitation frequency band, and generates a resonance threshold list.

[0113] The rhythm decoupling control module rearranges a beat sequence according to a beat phase difference distribution of a high-risk frequency band of the resonance threshold list, constructs a rhythm decoupling sequence, sets an execution order and a silent interval, and forms a peak-shifting control baseline.

[0114] The energy suppression execution module executes segmented energy release based on the peak-shaving control baseline driving two-phase respiratory traction window, mirror image hysteresis valve, turn-back energy bypass and time siphon groove, sequentially unloads local energy in time sequence beats, constructs a dynamic closed-loop suppression link, and is used for suppressing energy resonance and maintaining output stability.

[0115] The control method of the optical transceiver driving chip DC offset compensation circuit provided by the embodiment of the application is implemented by the control system of the optical transceiver driving chip DC offset compensation circuit, and the specific method and process of the control system of the optical transceiver driving chip DC offset compensation circuit are described in the embodiment of the control method of the optical transceiver driving chip DC offset compensation circuit, which will not be described here.

[0116] Please refer to Figure 3 , Figure 3 An embodiment of a computer readable storage medium provided by the embodiment of the application is shown in FIG. 6. Figure 3 As shown in FIG. 6, the embodiment provides a computer readable storage medium 600, which stores a computer program 611, and the computer program 611 is executed by a processor to implement the control method of the optical transceiver driving chip DC offset compensation circuit.

[0117] The above only describes some exemplary embodiments of the application by way of illustration, and it is needless to say that the described embodiments can be modified in various ways without departing from the spirit and scope of the application for those skilled in the art. Therefore, the above drawings and descriptions are illustrative in nature and should not be understood as limiting the scope of protection of the claims of the application.

Claims

1. A control method of a direct current (DC) offset compensation circuit of an optical transceiver driver chip, the control method comprising: determining a DC offset of the optical transceiver driver chip; and adjusting a gain of the DC offset compensation circuit based on the determined DC offset. The method comprises the following steps: The test waveform and bias trajectory of the optical transceiver driver chip are time-aligned, the phase misalignment amount and amplitude jump amount between beats are extracted, and the continuously changing results are mapped into a timing conflict observation band for identifying the beat overlap region; Wherein, the beat refers to: by detecting the rising edge and falling edge positions of the input signal waveform in each period, defining each continuous sinusoidal period as a beat interval, and tracking the change trend of the output current and bias voltage in the beat; Based on the phase misalignment trend of the timing conflict observation band, the beat overlap point of the DC offset compensation loop is determined, and the overlapping beat index is generated according to the duration and polarity direction of the amplitude jump, for identifying the interference node; The timing superposition relationship between the DC offset compensation loop and the automatic gain control loop is constructed by using the overlapping beat index, the beat phase difference and the gain change rate are labeled, and an energy coupling interference graph is generated for representing the coupling strength between the feedback loops; According to the high-intensity section of the energy coupling interference graph and the frequency response of the packaging parasitic parameters, the energy resonance trend of the driving end is analyzed, the excitation frequency band is determined, and a resonance threshold domain list is generated; According to the high-risk frequency band of the resonance threshold domain list, the beat sequence is rearranged according to the beat phase difference distribution, a rhythm decoupling sequence is constructed, an execution order and a silent interval are set, and a staggered peak control baseline is formed; Based on the staggered peak control baseline, a two-phase respiratory traction window, a mirror lag valve, a turn-back energy bypass and a time siphon are executed to release energy in segments, so that local energy is sequentially unloaded in the timing beat, a dynamic closed-loop suppression link is constructed for suppressing energy resonance and maintaining output stability; According to the starting time, peak energy and control response window corresponding to each beat in the staggered peak control baseline, the opening and closing rhythm of the two-phase respiratory traction window is set; 80 nanoseconds before the execution of each high-energy beat, the first phase window is opened, and the pre-excitation energy is guided to the transition guide path through the on-chip low-capacitance coupling network, allowing 10%-20% of the energy to be released in advance; After the excitation signal reaches the peak value, the second phase window is reversely conducted within a delay period of 40 nanoseconds, the energy release direction is switched, and the remaining waveform is transmitted into the low-impedance energy dispersion area through the parallel lead; Based on the response characteristics of each beat descending segment, the activation window of the mirror lag valve is set for the residual energy band before the end of the signal; The structure constructs an inverse slope waveform with the same amplitude and phase delay at the maximum descending slope of the control waveform by setting a reverse voltage guide structure; The remaining unexported excitation energy after the mirror lag valve is configured to flow into the turn-back energy bypass network, guided by the rear dissipation path to the bias network away from the main driving channel. The turn-back path adopts a three-section delay spiral line structure, and the peak energy is dissipated as heat flow by configuring a parallel damping network at the end of each section. In order to completely cut off the resonance link interference between beats, a time siphon structure is arranged in the silent window between beat execution, which absorbs the reverse waveform energy remaining in the packaging network or the end of the lead after the completion of the last beat to the ground plane, avoiding its interference as excitation background for the next beat.

2. The control method of the optical transceiver driver chip DC offset compensation circuit according to claim 1, characterized in that, The timing conflict observation band generation step is as follows: A modulation signal is applied to the input end of the optical transceiver driver chip, and the output current signal and bias voltage trajectory are collected at the same time. The signals are time-aligned by a collection device with double-channel synchronous sampling capability to obtain a unified time axis signal with normalized amplitude; Based on the time-aligned signal data, each continuous sinusoidal period is defined as a beat interval, the time interval between the rising edge of the input signal and the peak value of the bias trajectory is extracted, the phase misalignment value of the beat is calculated, and a phase drift curve is generated; According to the instantaneous amplitude change in each beat, the differential amplitude of the output current is calculated with a sliding window, and the amplitude jump points are identified. When the jump amplitude exceeds the average change rate threshold of the beat, the jump event is recorded; The phase misalignment value and the amplitude jump value of each beat are mapped to a two-dimensional coordinate plane in time sequence, and the beat conflict intensity is identified by color scale, and a time sequence conflict observation band is generated to indicate the signal adjustment overlap area.

3. The control method of the optical transceiver driver chip DC offset compensation circuit according to claim 2, characterized in that, The steps for generating the overlapping beat index are as follows: According to the time sequence conflict observation band, the beats with phase misalignment exceeding the preset threshold are extracted, and the time offset curve is drawn on the unified time axis to determine the response drift trend; Combined with the amplitude jump time distribution characteristics in the beat, the jump start time is matched with the phase misalignment offset interval to identify the beat overlap point in the direct current imbalance compensation loop adjustment process; The jump amplitude, jump duration and jump direction parameters of each jump event are extracted, the amplitude difference between the jump start point and the end point is calculated, and the jump direction is determined; Based on the phase misalignment value, the jump amplitude, the jump duration and the jump direction, the overlapping beat index is established, the interference risk nodes are classified and identified, and the overlapping beat index list is generated.

4. The control method of the optical transceiver driver chip DC offset compensation circuit according to claim 3, characterized in that, The steps for generating the energy coupling interference diagram are as follows: According to the overlapping beat index list, the key control instruction points of the bias adjustment curve and the gain control curve in the interference beat are extracted, the bias response start time and the gain response start time are recorded, and they are calibrated on the unified time axis; The difference between the bias response start time and the gain response start time is calculated to obtain the control phase difference of each interference beat, and the gain change rate of the corresponding beat is extracted as the control strength parameter; The beat number, control phase difference and gain change rate are drawn as a two-dimensional heat distribution diagram, and the coupling strength level is divided according to the color scale to generate an energy coupling interference diagram reflecting the feedback coupling strength distribution; According to the color highlight area in the energy coupling interference diagram, the number, phase difference and gain change rate of the coupling nodes are extracted, a coupling node list is established, and the strength is classified and identified.

5. The control method of the optical transceiver driver chip DC offset compensation circuit according to claim 4, characterized in that, The steps for generating the resonance threshold list are as follows: According to the beat section marked as high intensity in the energy coupling interference diagram, the beat number, control phase difference and gain change rate are extracted, and the jump behavior of the output current waveform is analyzed point by point; Combined with the packaging parasitic parameters of the optical transceiver driver chip, an inductance, capacitance and resistance model is established, and the transmission characteristics are analyzed by frequency scanning to determine the inherent resonance frequency of the structure; The output waveform in the high coupling beat is analyzed in the frequency domain, the frequency spectrum peak position and amplitude are obtained by using fast Fourier transform, and they are compared with the packaging frequency response curve to identify the resonance frequency point; According to the identified resonance frequency, frequency bandwidth and beat time interval, the resonance threshold list is output.

6. The control method of the optical transceiver driver chip DC offset compensation circuit according to claim 5, characterized in that, In the process of outputting the resonance threshold list, the resonance level is classified and identified by comparing the resonance frequency with the resonance frequency band formed by the parasitic parameters of the package, and the peak amplitude and energy duration of the output waveform are recorded in the identified high-coupling beat to determine the resonance risk level of the driving end.

7. The control method of the optical transceiver driver chip DC offset compensation circuit according to claim 5, characterized in that, The baseline generation steps of staggered peak control are as follows: According to the resonance threshold list, the number, duration, control phase difference, gain change rate and output current disturbance amplitude of the high-risk beat are extracted, a multi-parameter mapping table is established and the control instruction scheduling density is analyzed; The high-risk beat is extracted from the original control sequence, and is staggered with the low-interference beat whose gain change rate is not more than 0.5 units per microsecond and whose phase difference value is greater than 0.12 microseconds, a rhythm decoupling sequence without continuous excitation behavior is constructed, and a fixed time interval is set between the beats; On the basis of the beat decoupling sequence, a silent interval is set for each beat execution window, a control beat baseline table containing beat number, trigger starting point, control response time and minimum silent interval is established, and a time-constrained staggered peak control baseline is formed.

8. The control method of the optical transceiver driver chip DC offset compensation circuit according to claim 7, characterized in that, The steps of constructing a dynamic closed-loop suppression link based on the staggered peak control baseline to drive the two-phase respiratory traction window, the mirror delay valve, the turn-back energy bypass and the time siphon groove to perform segmented energy release are as follows: According to the starting time, peak energy and control response window of each beat in the staggered peak control baseline, the opening and closing rhythm of the two-phase respiratory traction window is set to guide the energy to the low-impedance energy dissipation area in stages before and after the excitation signal; Based on the response characteristics of the beat descending segment, the mirror delay valve is activated at the residual energy band before the end of the signal, a delay inverse ramp waveform is constructed by the reverse voltage guide structure to reduce the mutation rate of the main channel; The excitation energy not guided by the mirror delay valve is introduced into the turn-back energy bypass network, and the peak energy is converted into heat flow to achieve dissipation through the multi-section delay spiral line structure and the parallel damping network; The time siphon groove structure is arranged in the silent window between the beat executions, and the residual energy at the end of the wire is absorbed by the parallel siphon line to prevent energy reflection from interfering with the next beat; The two-phase respiratory traction window, the mirror delay valve, the turn-back energy bypass and the time siphon groove are sequentially scheduled to construct a closed-loop energy regulation link composed of pre-guiding, slope adjustment, residual guiding and tail section clearing.

9. A control system of a DC offset compensation circuit of an optical transceiver driver chip, for implementing the control method of the DC offset compensation circuit of the optical transceiver driver chip according to any one of claims 1-8, characterized in that, It includes a time sequence conflict observation band generation module, a beat overlap identification module, an energy coupling analysis module, a resonance threshold identification module, a rhythm decoupling control module and an energy suppression execution module: The time sequence conflict observation band generation module performs time alignment on the test waveform and bias trajectory of the optical transceiver driver chip, extracts the phase misalignment amount and amplitude jump amount between beats, and maps the continuous change result into a time sequence conflict observation band for identifying the beat overlap area; The beat overlap identification module determines the beat overlap point of the direct current offset compensation loop based on the phase misalignment trend of the time sequence conflict observation band, and generates an overlapping beat index according to the duration and polarity direction of the amplitude jump, which is used to identify the interference node. The energy coupling analysis module uses the overlapping beat index to construct the timing superposition relationship of the direct current offset compensation loop and the automatic gain control loop, labels the beat phase difference and the gain change rate, and generates an energy coupling interference graph for representing the coupling strength between the feedback loops; The resonance threshold identification module analyzes the energy resonance trend of the driving end according to the high-intensity section of the energy coupling interference graph and the frequency response of the packaging parasitic parameters, determines the excitation frequency band, and generates a resonance threshold list; The rhythm decoupling control module rearranges the beat sequence according to the beat phase difference distribution based on the high-risk frequency band of the resonance threshold list, constructs a rhythm decoupling sequence, sets the execution order and the silent interval, and forms a staggered control baseline; The energy suppression execution module drives the double-phase respiratory traction window, the mirror image delay valve, the energy bypass of the turn-back, and the time siphon groove based on the staggered control baseline to execute segmented energy release, sequentially unloads the local energy in the timing beat, constructs a dynamic closed-loop suppression link for suppressing the energy resonance and maintaining the output stability.

10. A computer-readable storage medium storing a computer program, the computer-readable storage medium comprising: The computer program is executed by the processor to realize the control method of the direct current offset compensation circuit of the optical transceiver driver chip as claimed in any one of claims 1 to 8.

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