An equalizer and chip

Abstract

The application provides an equalizer and a chip, and relates to the field of artificial intelligence chips. The equalizer comprises a first-stage receiving circuit, which comprises a pre-stage amplification sub-circuit, a dynamic locking sub-circuit and a phase selection sub-circuit. The input end of the pre-stage amplification sub-circuit is electrically connected with the signal input end of the first-stage receiving circuit, the first output end of the pre-stage amplification sub-circuit is electrically connected with the first input end of the dynamic locking sub-circuit, the second output end of the pre-stage amplification sub-circuit is electrically connected with the second input end of the dynamic locking sub-circuit, the first output end of the dynamic locking sub-circuit is electrically connected with the first input end of the phase selection sub-circuit, the second output end of the dynamic locking sub-circuit is electrically connected with the second input end of the phase selection sub-circuit, and the first output end and the second output end of the phase selection sub-circuit are electrically connected with the signal output end of the first-stage receiving circuit. The application aims at improving the problems of large occupied area and high power consumption of the existing equalizer.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of artificial intelligence chips, in particular to an equalizer and a chip. BACKGROUND

[0002] With the rapid development of artificial intelligence, the total amount of data processing is growing, and the requirement for data transmission rate is also increasing. In the process of high-speed data transmission, it is necessary to ensure high-quality transmission of signals. By setting an equalizer circuit in the equalizer, channel loss can be compensated for, and signal distortion can be corrected, thereby ensuring reliable reception of data.

[0003] However, the current equalizer occupies a large area and has high power consumption, which cannot meet the application requirements in scenarios such as portable devices, high-density computing clusters, and other scenarios with strict requirements for chip area and energy efficiency. SUMMARY

[0004] The embodiments disclosed in the present application provide an equalizer and a chip, aiming to improve the problem of large area and high power consumption of the existing equalizer. The embodiments of the present application adopt the following technical solutions:

[0005] In a first aspect, an equalizer is provided, comprising: a first-stage receiving circuit, the first-stage receiving circuit comprising: a pre-stage amplification sub-circuit, a dynamic latching sub-circuit, and a phase selection sub-circuit,

[0006] The input end of the pre-stage amplification sub-circuit is electrically connected with the signal input end of the first-stage receiving circuit, the first output end of the pre-stage amplification sub-circuit is electrically connected with the first input end of the dynamic latching sub-circuit, the second output end of the pre-stage amplification sub-circuit is electrically connected with the second input end of the dynamic latching sub-circuit, the first output end of the dynamic latching sub-circuit is electrically connected with the first input end of the phase selection sub-circuit, the second output end of the dynamic latching sub-circuit is electrically connected with the second input end of the phase selection sub-circuit, the first output end of the phase selection sub-circuit is electrically connected with the signal output end of the first-stage receiving circuit, and the second output end of the phase selection sub-circuit is electrically connected with the signal output end of the first-stage receiving circuit.

[0007] The equalizer provided by the embodiment of the present application realizes amplification, shaping and phase selection of the differential input signal by sequentially arranging the pre-stage amplification sub-circuit, the dynamic latching sub-circuit and the phase selection sub-circuit in the overall structure. The pre-stage amplification sub-circuit provides controllable gain compensation for the input differential signal when enabled, and is a simple digital circuit structure when disabled, thereby effectively reducing the power consumption in the standby state. The dynamic latching sub-circuit can cross-couple and shape the differential signal amplified by the pre-stage, thereby improving the eye opening and noise immunity of the differential signal. The phase selection sub-circuit realizes optional switching of the output path through register control, so that the output phase can be selected to be consistent with the forward input or the reverse input as needed, thereby enhancing the compatibility of the circuit to different signal polarities. With the above structure, the equalizer of the present application not only can realize equalization compensation of high-frequency attenuated signals in the analog domain, thereby achieving the effect of replacing the traditional programmable gain amplifier, but also can significantly reduce the number of overall elements by virtue of the simplified transistor structure and the standard cell implementation, thereby having the advantages of small area, low power consumption, simple design and easy integration in high-speed digital interfaces.

[0008] In a possible implementation of the first aspect, the pre-stage amplification sub-circuit is configured to receive an initial differential signal and perform an amplification operation on the initial differential signal to obtain a first differential signal, the dynamic latching sub-circuit is configured to receive the first differential signal and perform a shaping operation on the first differential signal to obtain a second differential signal, and the phase selection sub-circuit is configured to receive the second differential signal and perform a phase selection operation on the second differential signal to obtain a target signal.

[0009] In a possible implementation of the first aspect, the first-stage receiving circuit further includes a first register sub-circuit, a control terminal of the first register sub-circuit is electrically connected with an input terminal of the pre-stage amplification sub-circuit, and the first register sub-circuit is configured to: output a first enable signal to make the pre-stage amplification sub-circuit in an off state, and output a second enable signal to make the pre-stage amplification sub-circuit in a conductive state to perform the amplification operation on the initial differential signal.

[0010] The equalizer provided by the embodiment of the present application realizes flexible switching between the off and on working modes of the entire equalizer by arranging the controllable first register sub-circuit. When the enable signal is in the off state, the pre-stage amplification sub-circuit does not participate in analog amplification, and the overall circuit is a simple digital logic link, thereby significantly reducing the static power consumption. When the enable signal is in the on state, the pre-stage amplification sub-circuit provides gain compensation for the high-frequency attenuated signal, thereby laying a signal amplitude foundation for subsequent dynamic latching shaping and phase selection.

[0011] In a possible implementation of the first aspect, the first-stage receiving circuit further includes a second register sub-circuit, a control end of the second register sub-circuit being electrically connected with the first input end and the second input end of the phase selection sub-circuit, and the second register sub-circuit being configured to switch a signal output path of the phase selection sub-circuit according to a type of the output enable signal.

[0012] The equalizer provided by the embodiments of the present application can flexibly adjust the phase of the output signal by setting the controllable second register sub-circuit, and realize different signal polarity and direction control. Specifically, the phase selection sub-circuit can provide flexible phase adjustment according to the requirements of different subsequent digital circuits by dynamically switching different signal paths, and ensure the consistency and stability of the signal in the transmission process.

[0013] In a possible implementation of the first aspect, the input end of the pre-stage amplification sub-circuit includes a first sub-input end and a second sub-input end, the first sub-input end being configured to receive a first initial differential sub-signal, and the second sub-input end being configured to receive a second initial differential sub-signal, and the second register sub-circuit is specifically configured to: when the first enable signal is output, make the target signal input into the phase selection sub-circuit have the same phase as the first initial differential sub-signal, and when the second enable signal is output, make the target signal output by the phase selection sub-circuit have the same phase as the second initial differential sub-signal.

[0014] The equalizer provided by the embodiments of the present application also has an inversion function, so that the output signal can be flexibly switched to the phase opposite to the input signal. This function not only facilitates the phase adjustment of the signal in different working states, but also provides convenience for the design of function test. Through the inversion function, the tester can easily generate and verify the forward and reverse signals, thereby simplifying the test cases of signal integrity and timing analysis, and ensuring the stability of the function and performance of the system in different working modes.

[0015] In a possible implementation of the first aspect, the pre-stage amplification sub-circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first constant current source, and a second constant current source, a first end of the first transistor is electrically connected with the first voltage terminal, a second end of the first transistor is electrically connected with a first end of the second transistor, a control end of the first transistor is electrically connected with the first sub-input terminal, a second end of the second transistor is electrically connected with a first end of the first constant current source, a control end of the second transistor is electrically connected with the first sub-input terminal, a first end of the third transistor is electrically connected with the second voltage terminal, a second end of the third transistor is electrically connected with the second end of the first transistor, a control end of the third transistor is electrically connected with the third voltage terminal, a first end of the fourth transistor is electrically connected with a first end of the second constant current source, a second end of the fourth transistor is electrically connected with a first end of the fifth transistor, a control end of the fourth transistor is electrically connected with the second sub-input terminal, a second end of the fifth transistor is electrically connected with the ground terminal, a control end of the fifth transistor is electrically connected with the second sub-input terminal, a first end of the sixth transistor is electrically connected with the second end of the fourth transistor, a second end of the sixth transistor is electrically connected with the ground terminal, a control end of the sixth transistor is electrically connected with the ground terminal, a second end of the first constant current source is electrically connected with the ground terminal, a second end of the second constant current source is electrically connected with the fourth voltage terminal, and the third transistor and the sixth transistor have the same amplification gain.

[0016] The equalizer provided by the embodiments of the present application has the third transistor and the sixth transistor with the same gain, so that the differential amplification path of the pre-stage amplification sub-circuit has good symmetry. The symmetry ensures that the two paths of the differential input signal obtain the same amplification processing, thereby improving the common-mode rejection ratio of the circuit, effectively suppressing the common-mode noise and power disturbance. Meanwhile, the output signal distortion caused by the gain mismatch of the two paths is avoided, the fidelity of the amplified signal waveform is ensured, a clear and symmetrical input signal is provided for the subsequent dynamic latch circuit, and finally the high-precision and high-linearity signal amplification function is realized.

[0017] In a possible implementation of the first aspect, the third transistor is a P-channel MOS transistor, and the sixth transistor is an N-channel MOS transistor.

[0018] In a possible implementation of the first aspect, the dynamic latch sub-circuit includes a first inverter and a second inverter, an input end of the first inverter is connected with an output end of the second inverter, and an input end of the second inverter is connected with an output end of the first inverter.

[0019] The equalizer provided by the embodiment of the present application realizes mutual compensation and shaping of signals by a dynamic latch composed of two inverters. When there is edge degradation or inter-symbol interference after the input signal is amplified, the internal positive feedback mechanism can be used to quickly and forcibly regenerate and lock the signal. The two inverters are mutually loaded and driven, and compensate and accelerate each other in the state switching process, so that the output signal can quickly escape from the unstable intermediate level and be shaped into a complete digital waveform with stable amplitude and steep edges. The noise and jitter are effectively suppressed, and the quality and integrity of the output signal are improved, so as to ensure that the equalizer can stably and reliably recover data in a high-speed data link.

[0020] In a possible implementation of the first aspect, the equalizer further includes a second-stage receiving circuit, a signal output end of the second-stage receiving circuit is electrically connected with a signal input end of the first-stage receiving circuit, and the second-stage receiving circuit is configured to perform suppression and recovery operations on the input signal to obtain an initial differential signal, and the first-stage receiving circuit is configured to perform amplification, shaping and phase selection operations on the input initial differential signal to obtain a target signal.

[0021] In a second aspect, a chip is provided, including a substrate and an equalizer disposed on the substrate, and the equalizer includes the equalizer of the first aspect.

[0022] It can be understood that the technical effects of the second aspect refer to those of the first aspect and any of the embodiments thereof, which are not repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 FIG. 1 is a circuit structure schematic diagram of an equalizer provided by an embodiment of the present application;

[0024] Figure 2 FIG. 2 is another circuit structure schematic diagram of an equalizer provided by an embodiment of the present application;

[0025] Figure 3 FIG. 3 is a third circuit structure schematic diagram of an equalizer provided by an embodiment of the present application;

[0026] Figure 4 FIG. 4 is a fourth circuit structure schematic diagram of an equalizer provided by an embodiment of the present application;

[0027] Figure 5 FIG. 5 is a fifth circuit structure schematic diagram of an equalizer provided by an embodiment of the present application;

[0028] Figure 6 FIG. 6 is a sixth circuit structure schematic diagram of an equalizer provided by an embodiment of the present application. DETAILED DESCRIPTION

[0029] With reference to the drawings, a clear and complete description of the technical solutions in the embodiments of the present application will be provided. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments provided in the present application, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present application.

[0030] Unless otherwise required by context, the term "comprises" in the specification and claims is to be construed as an open, inclusive meaning, i.e. "comprises, but is not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiment", "exemplary embodiments" or "some examples" are intended to mean that the particular feature, structure, material, or characteristic being described in connection with the embodiment or example includes at least one embodiment or example of the present application. The illustrative representations of the above terms are not necessarily meant to indicate the same embodiment or example. In addition, a particular feature, structure, material, or characteristic can be included in any suitable way in any one or more embodiments or examples.

[0031] Hereinafter, the terms "first", "second" are used only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0032] In describing some embodiments, "electrically connected" and its derivatives can be used. For example, the term "electrically connected" can be used to describe some embodiments to indicate that two or more components have direct physical or electrical contact, in which case "electrically connected" can also be described as "electrically connected". In addition, the term "electrically connected" can also mean that two or more components have no direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

[0033] "A, B, and C at least one of them" has the same meaning as "at least one of A, B, or C", which includes the following combinations of A, B, and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0034] “A and / or B” includes the following three combinations: only A, only B, and a combination of A and B. The use of “adapted to” or “configured to” herein means open and inclusive language that does not exclude devices adapted to or configured to perform additional tasks or steps. In addition, the use of “based on” means open and inclusive because a process, step, calculation, or other action that is “based on” one or more conditions or values can in practice be based on additional conditions or values beyond those that are listed.

[0035] The use of “configured to” herein means open and inclusive language that does not exclude devices adapted to or configured to perform additional tasks or steps.

[0036] In high-speed communication systems, the receive (RX) circuit is a key part of signal recovery and processing, and its performance directly affects the reliability and energy efficiency of the entire system. With the continuous progress of semiconductor technology and the rapid development of artificial intelligence, data transmission rates continue to increase, placing more stringent requirements on RX circuits. Not only do they need to implement complex functions in a limited area, but they also need to reduce power consumption as much as possible to meet the design needs of high-speed, high-integration communication chips.

[0037] In the process of signal transmission and reception by a radio frequency module, digital information is transmitted in the form of symbols in the channel, and each symbol carries several bits of data. However, due to actual physical conditions, signal waveforms often distort during transmission, causing adjacent symbols to overlap in the time domain, i.e., inter-symbol interference (ISI). The causes of ISI can include channel bandwidth limitations, time delay spread caused by multipath propagation, and nonlinear and frequency-selective fading of the transmission medium, among other factors. Bandwidth limitations can weaken high-frequency components of the signal, causing waveform broadening, and multipath effects can cause multiple delayed copies of the same signal to propagate through different paths and superimpose at the receiving end to form interference. In addition, imperfect receiver filter design can also exacerbate inter-symbol crosstalk. ISI can significantly increase the bit error rate and degrade signal quality, thereby limiting the upper limit of the system channel capacity and transmission rate.

[0038] To suppress the impact of ISI on signal integrity, an equalization circuit can be provided in the receiving path to compensate for the distortion introduced by the channel and reconstruct the original signal waveform. The equalization circuit can dynamically adjust its frequency response according to the channel characteristics, and commonly used equalization circuits can include a feed forward equalizer (FFE), a continuous time linear equalizer (CTLE), a decision feedback equalizer (DFE), etc.

[0039] FFE belongs to the typical time-domain linear equalization method, usually arranged at the front end of the receiving link. The core idea is to linearly superimpose the input signal with a number of historical symbol copies generated by different delays with preset weights, and by adjusting the weight of each tap, to compensate for the forward intersymbol interference caused by adjacent symbols in the channel. Due to the relatively simple structure, FFE is particularly suitable for processing the scene where the channel response is symmetric and the crosstalk is mainly contributed by the current and a small number of adjacent symbols. CTLE is also a linear equalization method, which is usually integrated in the analog front-end circuit to process the amplitude distortion problem caused by high-frequency attenuation. CTLE usually designs an analog filter network with high-frequency boosting characteristics to make the high-frequency component of the signal get additional amplification, so as to compensate for the high-frequency loss caused by limited channel bandwidth, and significantly improve the eye opening degree and signal edge quality. DFE is a class of nonlinear equalization architecture, which uses the symbols judged by the receiving end as feedback items to cancel the interference of the symbols being processed. Unlike FFE which only performs forward linear processing, DFE introduces a feedback loop that can compensate for residual interference caused by past symbols, and is particularly suitable for high-speed links where linear equalization cannot completely eliminate crosstalk. It can significantly improve the bit error rate performance under high code rate conditions.

[0040] In a feasible implementation, referring to a kind of equalizer 100 shown in Figure 1 It can include continuous time linear equalizer 101 and programmable gain amplifier 102 (Programmable Gain Amplifier, PGA), the differential output end of CTLE 101 is connected with the differential input end of PGA 102. Wherein, CTLE 101 is as the first stage processing unit of receiving path, is responsible for the equalization processing of continuous time domain to input signal, effectively suppresses high-frequency noise and recovers the target signal attenuated by channel. PGA 102 is then as the second stage, for adjusting signal amplitude, its gain can be configured according to system requirement.

[0041] However, in the above embodiments, the circuit structure of the PGA is relatively complex, thus occupying a larger physical area, which is contrary to the design trend of modern chips with small area and high integration. In addition, in order to ensure stable gain performance under various process deviations, voltage fluctuations and temperature changes, the PGA needs to consider sufficient performance margin in the design stage, and perform complex gain configuration and calibration after production or during operation. This not only increases the time and cost of chip testing and calibration, but also brings challenges to the overall reliability of the circuit. The core function of the PGA is to linearly amplify the signal within the target frequency band. In high-speed data communication, the signal bandwidth is extremely wide, which requires the PGA to have a high enough unit gain bandwidth. In order to achieve this wideband amplification characteristic, the PGA often uses a large bias current, thus significantly increasing the overall static power consumption of the PGA module. This high power consumption cost for achieving bandwidth seriously restricts the applicability of the receiving circuit in power-sensitive application scenarios (such as mobile devices).

[0042] To improve the above problems, an equalizer is provided in the embodiments of the present application, which is used to replace the function of the PGA by using a simpler circuit structure and fewer components.

[0043] The equalizer can include a first-stage receiving circuit. For example, refer to the circuit module structure diagram of the first-stage receiving circuit 200 shown in Figure 2 The first-stage receiving circuit 200 can include a pre-stage amplification sub-circuit 201, a dynamic latching sub-circuit 202, and a phase selection sub-circuit 203. The input end of the pre-stage amplification sub-circuit 201 is electrically connected to the signal input end of the first-stage receiving circuit 200. The first output end of the pre-stage amplification sub-circuit 201 is electrically connected to the first input end of the dynamic latching sub-circuit 202, and the second output end of the pre-stage amplification sub-circuit 201 is electrically connected to the second input end of the dynamic latching sub-circuit 202. The first output end of the dynamic latching sub-circuit 202 is electrically connected to the first input end of the phase selection sub-circuit 203, and the second output end of the dynamic latching sub-circuit 202 is electrically connected to the second input end of the phase selection sub-circuit 203. The first output end and the second output end of the phase selection sub-circuit 203 are electrically connected to the signal output end of the first-stage receiving circuit 200.

[0044] In order to realize the equalization output of the high-speed differential signal, the first-stage receiving circuit 200 completes the whole process of signal enhancement, shaping and phase selection in a step-by-step processing manner. First, the pre-stage amplification sub-circuit 201 receives the initial differential signal from the signal input end, enhances the amplitude of the initial differential signal through the internal amplification structure, and suppresses the high-frequency attenuation caused by the link loss, thereby obtaining the first differential signal. Then, the dynamic latching sub-circuit 202 obtains the first differential signal output by the pre-stage amplification sub-circuit 201, and uses the dynamic latching structure composed of two inverters to shape and compensate the edges of the differential signal, thereby enhancing the amplitude and transition speed of the signal, and forming the second differential signal with better transition characteristics. Finally, the phase selection sub-circuit 203 receives the second differential signal output by the dynamic latching sub-circuit 202, and selects different signal paths based on the enable control signal from the register, and outputs the signal corresponding to the first end or the second end as the final target signal, thereby realizing flexible selection of the phase of the output signal.

[0045] Through the above step-by-step processing link, the equalizer of the embodiment of the application not only can realize the equalization compensation of the high-frequency attenuation signal in the analog domain, and achieve the effect of replacing the traditional programmable gain amplifier, but also can significantly reduce the number of overall elements by relying on the simplified transistor structure and the standard cell implementation manner, thereby having the advantages of small area, low power consumption, simple design and easy integration in the high-speed digital interface.

[0046] In order to enable the pre-stage amplification sub-circuit to flexibly switch between different working modes, the system power consumption can be reduced and the analog noise interference can be reduced when the amplification function is not needed, and the normal working gain can be quickly restored when the equalization function is needed, in a feasible implementation manner, the equalizer can further include a first register sub-circuit.

[0047] As an example, referring to Figure 3 , the first-stage receiving circuit 200 can further include a first register sub-circuit 204, the control end of the first register sub-circuit 204 is electrically connected with the input end of the pre-stage amplification sub-circuit 201, for providing the enable control signal EN to the pre-stage amplification sub-circuit 201. In a specific implementation, when the enable signal EN output by the first register sub-circuit 204 is 0, the pre-stage amplification sub-circuit 201 is turned off, and the internal transistor is in the off or weak conduction state, so that the amplification path is no longer working, at this time, the front end of the equalizer is equivalent to a pure digital logic structure, which can significantly reduce the static power consumption and avoid the noise and bias error caused by the analog amplification process. When the enable signal EN output by the first register sub-circuit 204 is 1, the pre-stage amplification sub-circuit 201 is turned on, the differential input path is re-established working bias, and the circuit enters the analog gain mode, and performs the amplification operation on the input initial differential signal, thereby providing the first differential signal with improved amplitude and edge for the subsequent dynamic latching shaping and phase selection.

[0048] By setting the first register sub-circuit, the equalizer of the embodiment of the present application can be flexibly switched between the off-on two modes. In the off state, the equalizer is a pure digital circuit structure, which has extremely low power consumption, stable structure and is suitable for system waiting or low load state. In the on state, the equalizer is an analog gain circuit, which provides differential amplification capability, makes up for the high frequency loss of the previous stage link, and realizes effective equalization.

[0049] Therefore, not only the power efficiency of the entire equalization link is improved, but also the reliability and flexibility of the analog front end are improved, which ensures the best performance under different system conditions.

[0050] In a feasible implementation, in order to accurately control the phase of the equalizer output signal and keep an adjustable and stable phase relationship with the input differential signal, the equalizer can further include a second register sub-circuit.

[0051] As an example, continuing to refer to Figure 3 , the first-stage receiving circuit 200 can further include a second register sub-circuit 205, the control end of the second register sub-circuit 205 is electrically connected with the first input end and the second input end of the phase selection sub-circuit 203 respectively, for providing an enable control signal EN to the phase selection sub-circuit 203 to control the phase selection sub-circuit to switch the output between different differential paths.

[0052] Specifically, when the enable control signal EN is in the first state, the second register sub-circuit 205 outputs corresponding enable signals to make the phase selection sub-circuit 203 select the output path that keeps the first phase relationship with the input differential signal. When the enable control signal EN is in the second state, the second register sub-circuit 205 outputs another group of enable signals to make the phase selection sub-circuit 203 convert to the output path that keeps the second phase relationship with the input differential signal.

[0053] As an example, the input end of the pre-stage amplification sub-circuit includes a first sub-input end and a second sub-input end, the first sub-input end is used to receive a first initial differential sub-signal, and the second sub-input end is used to receive a second initial differential sub-signal. When the enable signal EN output by the second register sub-circuit 205 is 1, the target signal output by the phase selection sub-circuit is the same in phase as the first initial differential sub-signal, and when the enable signal EN output by the second register sub-circuit 205 is 0, the target signal output by the phase selection sub-circuit is the same in phase as the second initial differential sub-signal. Or when the enable signal EN output by the second register sub-circuit 205 is 0, the target signal output by the phase selection sub-circuit is the same in phase as the first initial differential sub-signal, and when the enable signal EN output by the second register sub-circuit 205 is 1, the target signal output by the phase selection sub-circuit is the same in phase as the second initial differential sub-signal. The specific matching relationship can be adjusted according to actual needs, and the embodiment of the present application does not limit this.

[0054] In the above manner, the second register sub-circuit 205 can dynamically select the path selection of the phase selection sub-circuit 203, so that the equalizer can dynamically adjust the phase relationship of the output signal according to actual needs.

[0055] Referring to Figure 4 The circuit architecture schematic diagram of the first-stage receiving circuit 200 is shown, the dynamic latching sub-circuit 202 can include a first inverter 2021 and a second inverter 2022, which are used to shape and compensate the input differential signal. Specifically, the amplified differential signal is output to the dynamic latching sub-circuit 202 and then passes through the first inverter 2021 and the second inverter 2022 to form a complementary dynamic latching structure. In this structure, the two inverters feedback to each other, and the differential signal is quickly compensated and shaped through dynamic latching.

[0056] The circuit structure of the pre-stage amplification sub-circuit can linearly amplify the input differential signal and provide sufficient driving capability to ensure that the post-stage dynamic latching sub-circuit can obtain a first differential signal with stable amplitude and moderate swing under high-speed conditions.

[0057] As an example, referring to Figure 5The equivalent circuit diagram of the pre-stage amplification sub-circuit is shown. The pre-stage amplification sub-circuit 201 can include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a first constant current source I1, and a second constant current source I2. The first end of the first transistor M1 is electrically connected to a first voltage terminal, the second end of the first transistor M1 is electrically connected to the first end of the second transistor M2, the control end of the first transistor M1 is electrically connected to a first sub-input terminal, the second end of the second transistor M2 is electrically connected to the first end of the first constant current source I1, and the control end of the second transistor M2 is electrically connected to the first sub-input terminal. The first end of the third transistor M3 is electrically connected to a second voltage terminal, the second end of the third transistor M3 is electrically connected to the second end of the first transistor M1, and the control end of the third transistor M3 is electrically connected to a third voltage terminal. The first end of the fourth transistor M4 is electrically connected to the second voltage terminal, the second end of the fourth transistor M4 is electrically connected to the first end of the fifth transistor M5, and the control end of the fourth transistor M4 is electrically connected to a second sub-input terminal. The second end of the fifth transistor M5 is electrically connected to a ground terminal, and the control end of the fifth transistor M5 is electrically connected to the second sub-input terminal. The first end of the sixth transistor M6 is electrically connected to the second end of the fourth transistor M4, the second end of the sixth transistor M6 is electrically connected to the ground terminal, and the control end of the sixth transistor M6 is electrically connected to the ground terminal. The second end of the first constant current source I1 is electrically connected to the ground terminal, and the second end of the second constant current source is electrically connected to a fourth voltage terminal.

[0058] In a feasible implementation, the third transistor M3 can be a P-channel MOS transistor, and the sixth transistor M6 can be an N-channel MOS transistor. The source of the third transistor M3 is connected to the second voltage terminal, for providing pull-up current to the differential node, the drain is connected to the connection node of the first transistor M1 and the second transistor M2, for performing pull-up driving on the amplification node, and the gate is connected to the third voltage terminal, for controlling the conduction state of the PMOS.

[0059] The source of the sixth transistor M6 is connected to the ground terminal, for providing a fast discharge path for the connection node of the fourth transistor M4 and the fifth transistor M5, the drain is connected to the second end of the fourth transistor M4, for performing pull-down driving on the differential node, and the gate is connected to the ground terminal or a fixed low level, for keeping the transistor in an off state, thereby providing a stable bias condition for the common-mode level.

[0060] In addition, in order to ensure that the differential amplification structure obtains consistent current driving capability and voltage gain on the two amplification paths, in an optional implementation, the third transistor M3 and the sixth transistor M6 can adopt the same size, so that the amplification gain of the two differential paths remains the same.

[0061] The third transistor and the sixth transistor with the same gain are arranged, so that the differential amplification path of the pre-stage amplification sub-circuit has better symmetry. The symmetry ensures that the two paths of the differential input signal obtain consistent amplification processing, thereby improving the common-mode rejection ratio of the circuit, effectively suppressing the common-mode noise and power disturbance. At the same time, the output signal distortion caused by the gain mismatch of the two paths is avoided, the fidelity of the amplified signal waveform is ensured, a clear and symmetric input signal is provided for the subsequent dynamic latch circuit, and finally the high-precision and high-linearity signal amplification function is realized.

[0062] The embodiment also provides an equalizer, referring to Figure 6 The equalizer 300 can include a continuous-time linear equalizer 101 (a second-stage receiving circuit) and a first-stage receiving circuit 200, the continuous-time linear equalizer 101 and the first-stage receiving circuit 200 are electrically connected, the continuous-time linear equalizer 101 is configured to perform suppression and recovery operations on an input signal to obtain an initial differential signal, and the first-stage receiving circuit 200 is configured to perform amplification, shaping and phase selection operations on the input initial differential signal to obtain a target signal.

[0063] In a third aspect, a chip is provided, including a substrate and an equalizer disposed on the substrate, and the equalizer includes the equalizer provided in the above embodiments.

[0064] It should be noted that the chip provided in the embodiments of the present application can be any one of a central processing unit (CPU), a graphics processing unit (GPU), a tensor processing unit (TPU), a neural network processing unit (NPU), a deep learning processing unit (DPU), an accelerated processing unit (APU) and a general-purpose graphics processing unit (GPGPU).

[0065] It should be noted that the division of the above modules is only a functional division adopted for ease of description, and in actual implementation, one module can be implemented by multiple modules, and the functions of multiple modules can be implemented by one module. These modules can be located in the same device or in different devices.

[0066] The hardware module in the embodiments can be realized mechanically or electronically. For example, a hardware module can include a specially designed permanent circuit or logic device (such as a special-purpose processor, such as an FPGA or an ASIC) for completing a specific operation. For example, a specific operation can be completed in various types of chips (for example, artificial intelligence chips). The hardware module can also include a programmable logic device or circuit temporarily configured by software (such as a general-purpose processor or other programmable processor) for performing a specific operation. As for the specific implementation of the hardware module, whether it is mechanically implemented, or implemented by a special permanent circuit, or implemented by a temporarily configured circuit (such as configured by software), it can be determined based on cost and time considerations.

[0067] The technical features of the above embodiments can be combined in any manner. In order to make the description simple, not all possible combinations of the technical features in the above embodiments are described, however, as long as the combination of the technical features does not contradict, it should be considered as the scope of the present disclosure. The above embodiments only express several embodiments of the present application, and the description is more specific and detailed, but it should not be considered as limiting the scope of the patent of the present application. It should be noted that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the scope of the present application. Therefore, the scope of the present application should be subject to the appended claims.

[0068] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features in the formula; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An equalizer characterized by, The first-stage receiving circuit comprises a pre-amplification sub-circuit, a dynamic locking sub-circuit and a phase selection sub-circuit, and is used for realizing equalization output of a differential signal. An input end of the pre-amplification sub-circuit is electrically connected with a signal input end of the first-stage receiving circuit, a first output end of the pre-amplification sub-circuit is electrically connected with a first input end of the dynamic locking sub-circuit, and a second output end of the pre-amplification sub-circuit is electrically connected with a second input end of the dynamic locking sub-circuit. A first output end of the dynamic locking sub-circuit is electrically connected with a first input end of the phase selection sub-circuit, and a second output end of the dynamic locking sub-circuit is electrically connected with a second input end of the phase selection sub-circuit. A first output end of the phase selection sub-circuit is electrically connected with a signal output end of the first-stage receiving circuit, and a second output end of the phase selection sub-circuit is electrically connected with the signal output end of the first-stage receiving circuit. The pre-amplification sub-circuit is used for receiving an initial differential signal, and performing amplification operation on the initial differential signal to obtain a first differential signal. The dynamic locking sub-circuit is used for receiving the first differential signal, and performing shaping operation on the first differential signal to obtain a second differential signal. The phase selection sub-circuit is used for receiving the second differential signal, and performing phase selection operation on the second differential signal to obtain a target signal. The input end of the pre-amplification sub-circuit comprises a first sub-input end and a second sub-input end, the first sub-input end is used for receiving a first initial differential sub-signal, and the second sub-input end is used for receiving a second initial differential sub-signal.

2. The equalizer of claim 1, wherein, The first-stage receiving circuit further comprises a first register sub-circuit, and a control end of the first register sub-circuit is electrically connected with the input end of the pre-amplification sub-circuit. The first register sub-circuit is used for: when a first enable signal is output, making the pre-amplification sub-circuit in an off state; and when a second enable signal is output, making the pre-amplification sub-circuit in an on state to perform amplification operation on the initial differential signal. The first-stage receiving circuit further comprises a second register sub-circuit, and a control end of the second register sub-circuit is electrically connected with a first input end and a second input end of the phase selection sub-circuit.

3. The equalizer of claim 1, wherein, The second register sub-circuit is used for: according to a type of an output enable signal, switching a signal output path of the phase selection sub-circuit. The second register sub-circuit is specifically used for: when the first enable signal is output, making a target signal output by the phase selection sub-circuit have a same phase as the first initial differential sub-signal; and when the second enable signal is output, making the target signal output by the phase selection sub-circuit have a same phase as the second initial differential sub-signal.

4. The equalizer of claim 3, wherein, The pre-amplification sub-circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first constant current source and a second constant current source. ​ 5. The equalizer of claim 4, wherein, ​ The first end of the first transistor is electrically connected with a first voltage terminal, the second end of the first transistor is electrically connected with the first end of the second transistor, and the control end of the first transistor is electrically connected with the first sub-input terminal; The second end of the second transistor is electrically connected with the first end of a first constant current source, and the control end of the second transistor is electrically connected with the first sub-input terminal; The first end of the third transistor is electrically connected with a second voltage terminal, the second end of the third transistor is electrically connected with the second end of the first transistor, and the control end of the third transistor is electrically connected with a third voltage terminal; The first end of the fourth transistor is electrically connected with the first end of a second constant current source, the second end of the fourth transistor is electrically connected with the first end of the fifth transistor, and the control end of the fourth transistor is electrically connected with the second sub-input terminal; The second end of the fifth transistor is electrically connected with a ground terminal, and the control end of the fifth transistor is electrically connected with the second sub-input terminal; The first end of the sixth transistor is electrically connected with the second end of the fourth transistor, the second end of the sixth transistor is electrically connected with the ground terminal, and the control end of the sixth transistor is electrically connected with the ground terminal; The second end of the first constant current source is electrically connected with the ground terminal. The second end of the second constant current source is electrically connected with a fourth voltage terminal, and the third transistor has the same amplification gain as the sixth transistor.

6. The equalizer of claim 5, wherein, The third transistor is a P-channel MOS transistor, and the sixth transistor is an N-channel MOS transistor.

7. The equalizer of claim 1, wherein, The dynamic latch sub-circuit comprises a first inverter and a second inverter. The input end of the first inverter is connected with the output end of the second inverter. The input end of the second inverter is connected with the output end of the first inverter.

8. The equalizer according to any one of claims 1 to 7, characterized in that The equalizer further comprises a second-stage receiving circuit, a signal output end of the second-stage receiving circuit is electrically connected with a signal input end of the first-stage receiving circuit, the second-stage receiving circuit is used for performing suppression and recovery operations on an input signal to obtain an initial differential signal, and the first-stage receiving circuit is used for performing amplification, shaping and phase selection operations on the input initial differential signal to obtain a target signal.

9. A chip, characterized by An equalizer comprises a substrate and an equalizer arranged on the substrate, and the equalizer comprises the equalizer according to any one of claims 1-8.

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