A method, apparatus, and medium for CPU-sampling-oriented dynamic caching of graph neural network training

Abstract

This invention provides a method, apparatus, and medium for dynamic caching of graph neural network training based on CPU sampling, belonging to the field of graph neural network training technology. The method includes: dividing the graph data for graph neural network training into partitions equal to the number of accelerator cards; dividing the memory of each accelerator card into T, F, L, and R regions; the host CPU samples each partition and generates sampled subgraphs, obtaining vertex labels based on the sampled subgraphs and distributing them to the accelerator cards; in the first round of training, obtaining vertex features of the current sampled subgraph from the host memory; in subsequent rounds of training, sequentially searching for vertex features in the F, L, and R regions of the current accelerator card, and if no match is found, obtaining them across accelerator cards or from the host memory; periodically migrating vertex features in the F region with a frequency greater than a preset threshold to the L region based on the number of times the vertex features entered the F region and a preset threshold; and updating the model parameters on each accelerator card. This invention significantly improves the overall training efficiency of graph neural networks.

Description

TECHNICAL FIELD

[0001] The application relates to a CPU sampling-oriented graph neural network training dynamic cache method, device and medium, and belongs to the technical field of graph neural network training. BACKGROUND

[0002] In the training process of a graph neural network (GNN), processing large-scale graph data is a highly challenging task. A graph neural network updates the feature representation of a target vertex by aggregating the information of neighboring vertices, which involves a large number of graph traversal and feature access operations. With the dramatic growth of graph data, how to efficiently manage and access graph data and its features becomes a key factor restricting the training efficiency of graph neural networks.

[0003] Traditionally, the training of a graph neural network relies on a static cache strategy, which mainly caches hot features based on the principle of locality, that is, it prioritizes caching vertex features that are frequently accessed during training. However, the static cache strategy is not up to the task when faced with dynamically changing graph data access patterns, as it cannot dynamically adjust the cache content according to the actual access situation, resulting in low cache hit rates.

[0004] On the other hand, although traditional dynamic cache strategies take into account the principle of locality, they attempt to improve hit rates by caching recently accessed data, but in the training scenario of a graph neural network, due to the complexity of the graph structure and the diversity of access patterns, the principle of locality alone often fails to effectively predict future access demands. In particular, when processing multi-order neighbor sampling, traditional dynamic cache strategies are even less able to cope with cross-accelerator, cross-partition vertex feature access demands, thus limiting the further improvement of training efficiency.

[0005] Therefore, in view of the large-scale graph data management problem in the training process of a graph neural network, a new cache strategy is urgently needed to improve cache hit rates, reduce data transmission overheads and improve overall training efficiency. SUMMARY

[0006] The application aims to provide a CPU sampling-oriented graph neural network training dynamic cache method, device and medium, which effectively solves the above problems through a three-level cache cooperative management module.

[0007] To achieve the above-mentioned purpose, the application is implemented through the following technical solutions:

[0008] A CPU sampling-oriented graph neural network training dynamic cache method, comprising the following steps:

[0009] Divide the graph data of the graph neural network training into partitions equal in number to the number of accelerators, and initialize the cross-accelerator transmission times for each vertex;

[0010] The memory of each acceleration card is divided into a T area, an F area, an L area, and an R area, wherein the T area is used to execute graph neural network training, and the F area, the L area, and the R area are used to store vertex features;

[0011] In each training round, each partition is sampled by a host CPU and a sampling subgraph is generated, vertex labels are obtained according to the sampling subgraph, and are distributed to the corresponding acceleration card;

[0012] In the first round of training, vertex features of the current sampling subgraph are obtained from the host memory, and in the non-first round of training, the vertex features are sequentially searched in the F area, the L area, and the R area of the current acceleration card, and if not hit, the vertex features are obtained through cross-acceleration card or host memory;

[0013] Periodically, according to the round of the vertex feature entering the F area and a preset threshold, vertex features with a round greater than the preset threshold in the F area are migrated to the L area.

[0014] Each acceleration card uses vertex features in the T area for forward propagation, loss calculation, and gradient update, and synchronizes model parameters.

[0015] Preferably, the capacity of the F area is greater than the capacity of the L area, and the capacity of the L area is greater than the capacity of the R area.

[0016] Preferably, in the first round of training, vertex features of the current sampling subgraph are obtained from the host memory and stored in the F area and the T area.

[0017] In the non-first round of training, it is sequentially searched whether the vertex features exist in the F area, the L area, and the R area, and if the vertex features are found, the vertex features are immediately stored in the T area.

[0018] If the vertex features are not found, it is searched whether the vertex features exist in the F area or the L area of other acceleration cards, and if the vertex features are found, the vertex features are immediately stored in the T area of the current acceleration card.

[0019] If the vertex features are not found in other acceleration cards, the vertex features are obtained from the host memory to the F area and the T area of the current acceleration card.

[0020] The non-first round of training is repeated until the features of all vertices in the sampling subgraph stored in the acceleration card are stored in the T area.

[0021] Preferably, the F area is managed using a first-in-first-out strategy, the L area is managed using a least recently used strategy, and the R area is managed using a cross-acceleration card cache strategy.

[0022] Preferably, the cross-accelerator cache strategy is as follows: according to the cross-accelerator transmission frequency of the vertex feature and a preset threshold, it is determined whether the vertex feature is stored in the R area; the cross-accelerator transmission frequency is incremented when the vertex feature is obtained from other accelerators through a high-speed interface, and the vertex feature is stored in the R area of the current accelerator when the preset threshold is reached and the R area is not full.

[0023] Preferably, the vertex feature in the F area whose round is greater than the preset threshold is migrated to the L area according to the round of the vertex feature entering the F area and the preset threshold, and specifically includes:

[0024] The vertex set in the F area whose loading round is greater than or equal to the set transfer threshold is obtained and stored in the L area;

[0025] If the L area capacity is insufficient, part of the vertex feature is eliminated according to the LRU strategy, and the vertex feature meeting the condition is migrated from the F area to the L area.

[0026] Preferably, the accelerators communicate through a high-speed interface, and the accelerators and the host CPU and memory communicate through a low-speed interface.

[0027] Preferably, the graph neural network training method is applicable to any one of GCN, GraphSAGE or GAT.

[0028] The advantages of the present application are that the three-level cache architecture (FIFO, LRU and cross-accelerator static cache strategy) adopted by the present application can dynamically adjust the cache content according to the actual access mode in the graph neural network training process. Compared with the traditional static cache strategy which relies on hot features and the traditional dynamic cache strategy which relies on data locality, the present method can more accurately predict and cache vertex features that may be frequently accessed in the future, thereby significantly improving the cache hit rate.

[0029] In a distributed training environment, the graph data is usually divided into multiple partitions and allocated to different accelerators. The traditional cache strategy often needs frequent data transmission when processing cross-accelerator and partition vertex feature access, increasing the communication overhead. The present application can cache more vertex features that may be accessed by other accelerators on the local accelerator through the three-level cache architecture, especially the cross-accelerator static cache strategy, thereby reducing the number of cross-accelerator data transmissions and reducing the communication overhead.

[0030] Due to the improvement of cache hit rate and the reduction of data transmission overhead, the method of the present application can significantly improve the overall training efficiency of the graph neural network. In the training process, the accelerator can obtain the required vertex feature faster, reducing the idle time caused by waiting for data, thereby improving the utilization rate of computing resources. BRIEF DESCRIPTION OF DRAWINGS

[0031] The accompanying drawings are included to provide a further understanding of the application, and are incorporated in and constitute a part of the specification, illustrate embodiments of the application, and are used to explain the present application, but do not limit the present application.

[0032] Fig. 1 The flowchart of the method of the present application is shown.

[0033] Fig. 2 The flowchart of the training of the graph neural network provided by the embodiment of the present application is shown.

[0034] Fig. 3 The three-level cache architecture and data flow diagram provided by the embodiment of the present application is shown. DETAILED DESCRIPTION

[0035] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0036] Embodiment 1

[0037] The special-purpose acceleration card for training of the graph neural network is referred to as an acceleration card, and the present application is used in a computing device (referred to as a host) with at least two acceleration cards. The different acceleration cards in the host communicate with each other by using high-speed interface technology, the central processing unit (CPU) and the memory in the host communicate with the acceleration cards by using low-speed interface technology, and the internal communication of the acceleration cards is faster than the former two.

[0038] The present application is directed to the graph neural network using the small-batch and multi-order neighbor sampling method, such as GCN (Graph Convolution Networks), GraphSAGE (Graph Sample and Aggregate), GAT (Graph Attention Networks), etc.

[0039] The data set for training of the graph neural network includes graph structure, vertex feature data and label, the graph structure represents the connection relationship between the graph vertices, and each vertex in the graph has its own vertex feature and label.

[0040] As shown in Figs. 1-3 A dynamic cache method for CPU sampling of the training of the graph neural network includes the following steps:

[0041] S1: dividing the graph data for training of the graph neural network into partitions equal to the number of acceleration cards, and initializing the number of cross-acceleration card transmission times for each vertex;

[0042] S2: memory of each accelerator card is divided into T area, F area, L area and R area, wherein the T area is used for executing graph neural network training, and the F area, the L area and the R area are used for storing vertex features;

[0043] S3: in each training round, each partition is sampled by the host CPU and a sampling subgraph is generated, a vertex label is obtained according to the sampling subgraph, and is distributed to the corresponding accelerator card;

[0044] S4: in the first round of training, the vertex features of the current sampling subgraph are obtained from the host memory, and in the non-first round of training, the vertex features are sequentially searched in the F area, the L area and the R area of the current accelerator card, and if not hit, the vertex features are obtained through cross-accelerator or host memory;

[0045] S5: periodically, according to the round of the vertex feature entering the F area and the preset threshold, the vertex features with the round greater than the preset threshold in the F area are migrated to the L area;

[0046] S6: each accelerator card uses the vertex features in the T area for forward propagation, loss calculation and gradient update, and synchronizes the model parameters.

[0047] As a refinement of the above embodiment, the capacity of the F area is greater than the capacity of the L area, and the capacity of the L area is greater than the capacity of the R area.

[0048] As a refinement of the above embodiment, in the first round of training, the vertex features of the current sampling subgraph are obtained from the host memory and stored in the F area and the T area.

[0049] In the non-first round of training, whether the vertex features exist in the F area, the L area and the R area is sequentially searched, and if the vertex features are found, the vertex features are immediately stored in the T area.

[0050] If the vertex features are not found, whether the vertex features exist in the F area or the L area of other accelerator cards is searched, and if the vertex features are found, the vertex features are immediately stored in the T area of the current accelerator card.

[0051] If the vertex features are not found in other accelerator cards, the vertex features are obtained from the host memory to the F area and the T area of the current accelerator card.

[0052] The step of repeating the non-first round of training is repeated until the features of all vertices in the sampling subgraph stored in the accelerator card are stored in the T area.

[0053] Specifically, the implementation steps are as follows:

[0054] S401: if t (training round) is 1, that is, the first round of training, the accelerator card obtains the vertex features of the sampling subgraph stored in the host memory, and stores the vertex features in the F area and the T area of the current accelerator card memory.

[0055] S402: If t is not 1, i.e. non-first round training, the accelerator needs to process the vertex features of the current round stored subgraph vertices as follows:

[0056] S4021: Let v be a training vertex whose vertex feature needs to be obtained, if v is in the F region of the current accelerator, store the vertex feature of v into the T region, and go to step S4027; otherwise go to step S4022.

[0057] S4022: If v is in the L region of the current accelerator, store the vertex feature of v into the T region, and go to step S4027; otherwise go to step S4023.

[0058] S4023: If v is in the R region of the current accelerator, store the vertex feature of v into the T region, and go to step S4027; otherwise go to step S4024.

[0059] S4024: The current accelerator sends a request for obtaining the vertex feature of v to other accelerators through the high-speed interface, and other accelerators check whether the vertex feature of v exists in the F region or the L region thereof, if the vertex feature of v exists, the vertex feature of v is transmitted to the T region of the current accelerator through the high-speed interface, and the number of times of transmitting the vertex v across accelerators is incremented by 1, and go to step S4025; otherwise go to step S4026.

[0060] S4025: If and the R region of the current accelerator is not full, copy the vertex feature of v to the R region of the current accelerator, wherein r is a pre-set threshold value of the vertex feature that can be stored in the R region, and go to step S4027; otherwise go directly to step S4027.

[0061] S4026: If the vertex feature is not found by other accelerators, obtain the vertex feature from the host memory to the F region and the T region of the current accelerator, and go to step S4027.

[0062] S4027: Repeat steps S4021 to S4026 to obtain the vertex features of other training vertices, until all vertex features of vertices in the subgraph stored by the accelerator are stored in the T region.

[0063] As a refinement of the above embodiment, the F region is managed by a first-in first-out strategy (FIFO), the L region is managed by a least recently used strategy (LRU), and the R region is managed by a cross-accelerator cache strategy.

[0064] ​​(1) the F area adopts a first-in first-out strategy as follows: if the F area of the acceleration card is full, the vertex feature that enters the F area earliest is deleted according to the FIFO principle, and the vertex v feature is loaded from the host memory to the F area and the T area of the acceleration card through the low-speed interface; if the F area of the acceleration card is not full, the vertex v feature is loaded from the host memory to the F area and the T area of the acceleration card through the low-speed interface.

[0065] (2) the R area cross-acceleration card caching strategy is as follows: according to the vertex feature cross-acceleration card transmission times and a preset threshold, it is determined whether to store the vertex feature into the R area; the cross-acceleration card transmission times is incremented when the vertex feature is acquired from other acceleration cards through the high-speed interface, and the vertex feature is stored into the current acceleration card R area when the preset threshold is reached and the R area is not full. The R area becomes a static cache after being full, and no replacement operation is performed.

[0066] (3) the L area least recently used strategy is executed as follows:

[0067] periodically, according to the round of the vertex feature entering the F area and a preset threshold, the vertex features with the round greater than the preset threshold in the F area are migrated to the L area, including: acquiring a vertex set with the loading round greater than or equal to the set migration threshold in the F area, and storing the vertex set into the L area; if the L area capacity is insufficient, part of the vertex features are eliminated according to the LRU strategy, and the vertex features meeting the conditions are migrated from the F area to the L area.

[0068] As a refinement of the above embodiment, the acceleration cards communicate with each other through a high-speed interface, and the acceleration cards communicate with the host CPU and the memory through a low-speed interface.

[0069] As a refinement of the above embodiment, the graph neural network training method is applicable to any one of GCN, GraphSAGE or GAT.

[0070] As a refinement of the above embodiment, in step S5, the acceleration card trains the data in the T area, uses the vertex feature to perform forward propagation to obtain the predicted label of the vertex, calculates the loss and gradient according to the predicted label and the real label. The global gradient is obtained by aggregating the gradients of each acceleration card, the model parameters are updated using the global gradient, and the updated parameters are synchronized to each acceleration card.

[0071] As a refinement of the above embodiment, in step S6, t=t+1, steps 3 to 5 are repeated until the training round t reaches the preset maximum training round.

[0072] ​To comprehensively evaluate the effectiveness of the three-level dynamic caching, the experiment selects two representative graph neural network models, GCN and GraphSAGE, and conducts a comparative analysis of cache hit rates on four different scale datasets, Reddit, Products, Yelp, and Livejournal, with PaGraph and DGL, the two existing training frameworks. DGL is the most basic graph neural network training framework, using a non-optimized cache management method, while PaGraph is an optimization of DGL's cache in recent years, which filters out high-degree vertices for caching.

[0073] (1) Experimental setup and evaluation metrics

[0074] The experiment uses cache hit rate as the core evaluation metric, defined as the ratio of the number of times the vertex features are successfully obtained from the cache to the total number of feature requests during training. The experimental environment is configured consistently, and each framework is run under the same hardware conditions to ensure fairness. For each dataset-model combination, the experiment records the average cache hit rate during the entire training process.

[0075] (2) Comparative analysis of cache hit rates

[0076] GCN model experimental results:

[0077] As shown in Tables 1-4, on the GCN model, the three-level dynamic cache has shown significant cache performance advantages. On the Reddit dataset, the three-level dynamic cache achieved a cache hit rate of 92%, significantly higher than PaGraph's 78% and DGL's 42%. On the larger Products dataset, the three-level dynamic cache achieved a cache hit rate of 90%, while PaGraph and DGL achieved 75% and 41%, respectively. On the Yelp and Livejournal commercial social network datasets, the three-level dynamic cache also maintained stable performance advantages, with cache hit rates of 80% and 85%, respectively.

[0078] GraphSAGE model experimental results:

[0079] As shown in Tables 1-4, the experimental results of the GraphSAGE model further verify the effectiveness of the three-level dynamic cache. On the Reddit dataset, the three-level dynamic cache achieved a cache hit rate of 95%, significantly higher than PaGraph's 77% and DGL's 42%. For the Products dataset, the three-level dynamic cache achieved a hit rate of 93%, significantly higher than the comparison methods. On the Yelp and Livejournal datasets, the three-level dynamic cache achieved cache hit rates of 91% and 88%, respectively, consistently demonstrating excellent cache performance.

[0080] Table 1 Dataset: Cache hit rate of Reddit

[0081]

[0082] Table 2 Dataset: Cache hit rate of Products

[0083]

[0084] Table 3 Dataset: Cache hit rate of Yelp

[0085]

[0086] Table 4 Dataset: Cache hit rate of Livejournal

[0087]

[0088] (3) Result analysis

[0089] Three-level dynamic caching shows stable and significant cache hit rate advantages on different datasets and models, mainly due to its multi-level optimization design:

[0090] First, the vertex grouping module ensures that each GPU processes a highly connected subgraph through partitioning strategies, significantly improving data access locality. Second, the grouping sampling module uses a correlation score mechanism to generate training batches with strong topological correlation, enabling highly spatial locality in vertex feature access within the same batch, greatly improving cache utilization efficiency. Most importantly, the three-level dynamic caching module takes full advantage of GPU memory resources through hierarchical storage management and data migration strategies. The coordinated work of F, L, and R zones, combined with regular cache reorganization mechanisms, ensures fast access to hot data while providing appropriate cache space for warm data.

[0091] Compared with PaGraph, three-level dynamic caching effectively utilizes the logical cache capacity of multi-GPU systems, reducing host memory access due to cache misses. Compared with DGL, the original unoptimized training framework, there is a clear advantage.

[0092] As the dataset size increases (from Reddit to Livejournal), the cache hit rate of all frameworks shows a downward trend, but the decline of three-level dynamic caching is the most gentle, indicating that its architecture has better scalability for large-scale graph data.

[0093] In summary, the experimental results show that the three-level dynamic cache, through systematic optimization design, significantly outperforms the existing PaGraph and DGL frameworks in cache hit rate, providing an efficient data loading solution for large-scale graph neural network training.

[0094] Embodiment 2

[0095] The embodiments of the present disclosure further provide a graph neural network training dynamic cache device for CPU sampling, comprising a processor and a memory. Optionally, the device can further comprise a communication interface and a bus. Wherein the processor, the communication interface and the memory can complete mutual communication through the bus. The communication interface can be used for information transmission. The processor can call the logical instructions in the memory to execute the graph neural network training dynamic cache method for CPU sampling of the above-mentioned embodiments.

[0096] In addition, the logical instructions in the memory described above can be implemented in the form of a software functional unit and sold or used as an independent product, which can be stored in a computer readable storage medium.

[0097] The memory as a computer readable storage medium can be used to store software programs, computer executable programs, such as program instructions / modules corresponding to the method in the embodiments of the present disclosure. The processor executes the program instructions / modules stored in the memory to perform function applications and data processing, that is, to implement the graph neural network training dynamic cache method for CPU sampling in the above-mentioned embodiments.

[0098] The memory can include a program storage area and a data storage area, wherein the program storage area can store an operating system and at least one application required by a function; the data storage area can store data created according to the use of the terminal device, etc. In addition, the memory can include a high-speed random access memory, and can also include a non-volatile memory.

[0099] The embodiments of the present disclosure provide a computer readable storage medium, which stores computer executable instructions, and the computer executable instructions are set to execute the above-mentioned graph neural network training dynamic cache method for CPU sampling.

[0100] The computer readable storage medium described above can be a transitory computer readable storage medium or a non-transitory computer readable storage medium.

[0101] The technical solutions of the embodiments of the present disclosure can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes one or more instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the method described in the embodiments of the present disclosure. The aforementioned storage medium can be a non-transitory storage medium, including: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes, and can also be a transitory storage medium.

[0102] Finally, it should be noted that: the above only describes the preferred embodiments of the present application, and is not used to limit the present application, although the present application has been described in detail with reference to the foregoing embodiments, and for those skilled in the art, the technical solutions recorded in the foregoing embodiments can be modified, or some technical features can be replaced. Any modification, equivalent replacement, improvement, etc. within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A CPU sample-oriented graph neural network training dynamic cache method, characterized in that, The method comprises the following steps: dividing the graph data trained by the graph neural network into partitions equal to the number of acceleration cards and initializing the number of cross-acceleration card transmissions for each vertex; the data set trained by the graph neural network comprises a graph structure, vertex feature data and a label, the graph structure represents the connection relationship between graph vertices, and each vertex in the graph has corresponding vertex features and a label; dividing the memory of each acceleration card into T, F, L and R areas, wherein the T area is used to execute graph neural network training, and the F, L and R areas are used to store vertex features; in each training round, sampling each partition by the host CPU and generating a sampled subgraph, obtaining vertex labels from the sampled subgraph and distributing them to the corresponding acceleration card; in the first round of training, obtaining the vertex features of the current sampled subgraph from the host memory, and in the non-first round of training, sequentially searching for the vertex features in the F, L and R areas of the current acceleration card, and if the search is not successful, obtaining the vertex features from the cross-acceleration card or the host memory; periodically migrating the vertex features in the F area to the L area according to the round of the vertex features entering the F area and a preset threshold; each acceleration card uses the vertex features in the T area for forward propagation, loss calculation and gradient update, and synchronizes the model parameters; in the first round of training, obtaining the vertex features of the current sampled subgraph from the host memory and storing them in the F and T areas; in the non-first round of training, sequentially searching for the vertex features in the F, L and R areas, and if the vertex features are found, immediately storing them in the T area; if the vertex features are not found, searching for the vertex features from the F or L area of other acceleration cards, and if the vertex features are found, immediately storing them in the T area of the current acceleration card; if the vertex features are not found in other acceleration cards, obtaining the vertex features from the host memory and storing them in the F and T areas of the current acceleration card; repeating the non-first round of training until all the vertex features of the sampled subgraph stored in the acceleration card are stored in the T area; the F area is managed using a first-in-first-out strategy, the L area is managed using a least recently used strategy, and the R area is managed using a cross-acceleration card caching strategy; the cross-acceleration card caching strategy is as follows: according to the number of cross-acceleration card transmissions of the vertex features and a preset threshold, it is determined whether to store the vertex features in the R area; the number of cross-acceleration card transmissions is incremented when the vertex features are obtained from other acceleration cards through a high-speed interface, and when the preset threshold is reached and the R area is not full, the vertex features are stored in the R area of the current acceleration card.

2. The CPU -sampled graph neural network training dynamic caching method according to claim 1, wherein, The capacity of the F area is greater than that of the L area, and the capacity of the L area is greater than that of the R area.

3. The CPU -sampled graph neural network training dynamic caching method of claim 1, wherein, The method of periodically migrating the vertex features in the F area to the L area according to the round of the vertex features entering the F area and a preset threshold comprises: obtaining a set of vertices in the F area whose loading round is greater than or equal to a set transfer threshold and storing them in the L area; if the capacity of the L area is insufficient, part of the vertex features is eliminated according to the LRU strategy, and the vertex features that meet the conditions are migrated from the F area to the L area.

4. The method of claim 1, wherein, The acceleration cards communicate through a high-speed interface, and the acceleration cards and the host CPU and memory communicate through a low-speed interface.

5. The method of any one of claims 1-4, wherein, The graph neural network training method is applicable to any of GCN, GraphSAGE or GAT.

6. A CPU sample-oriented graph neural network training dynamic cache apparatus, comprising a processor and a memory storing program instructions, characterized in that, The processor is configured to execute, when running the program instructions, the CPU sample-oriented graph neural network training dynamic cache method as claimed in any one of claims 1-5.

7. A computer readable storage medium characterized in that, A computer program is stored thereon, which is executed by a processor to implement the CPU sample-oriented graph neural network training dynamic cache method as claimed in any one of claims 1-5.

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