A frequency domain superposition peak finding method and system based on field-programmable gate array (FPGA)

Abstract

This invention provides a frequency domain superposition peak finding method and system based on a field-programmable gate array (FPGA), belonging to the field of FPGA signal processing technology. The method includes: acquiring and parsing optoelectronic radio frequency analog signal data based on a multiprocessor system chip to obtain analog-to-digital conversion (ADC) data; expanding the ADC data and performing frequency domain superposition peak finding to obtain superimposed frequency domain analog and peak data, which are then cached; monitoring the cached data and moving it to a preset cache; in response to the completion of the data burst move, setting the data validity status to valid; and in response to successfully reading the data validity status, sending a status monitor signal and performing multiple rounds of frequency domain superposition peak finding to complete the frequency domain superposition peak finding. This invention solves the problem of existing frequency domain superposition peak finding methods failing to achieve a reasonable balance between fast response, stability, accuracy, lightweight design, and low power consumption.

Description

Technical Field

[0001] This invention belongs to the field of field-programmable gate array (FPGA) signal processing technology, and particularly relates to a frequency domain superposition peak finding method and system based on FPGA. Background Technology

[0002] Frequency domain peak finding is mainly used in the field of signal processing, especially in scenarios where it is necessary to extract specific frequency components or features from complex signals.

[0003] Some common application areas: vibration analysis and fault detection; in mechanical engineering, frequency superposition peak finding is often used to analyze the vibration signals of rotating machinery (such as motors, pumps, fans, etc.); by identifying the characteristic frequencies in the vibration signal, equipment faults can be diagnosed; optical radar and sonar signal processing, in radar or sonar systems, frequency superposition peak finding is used to detect the characteristic frequencies of the target's echo signal, helping to identify the target type, distance, or speed, especially in extracting weak signals in noisy environments;

[0004] Earthquake and geological detection; In seismic wave analysis or geological exploration, frequency superposition peak finding can be used to analyze the frequency components of seismic waves or underground reflected waves, helping to identify geological structures or underground resources;

[0005] In biomedical signal processing, frequency superposition peak finding can be used to extract key frequency components such as heart rate and brain wave rhythm when processing biological signals such as ECG (electrocardiogram) and EEG (electroencephalogram), thus assisting in medical diagnosis.

[0006] Frequency superposition peak finding usually requires combining high-speed ADC (analog-to-digital converter) data acquisition, filtering, discrete Fourier transform, short-time Fourier transform, or wavelet transform, etc., to enhance signal characteristics and suppress noise by superimposing multiple frequency components, thereby accurately locating the peak frequency in the signal. Summary of the Invention

[0007] To address the aforementioned shortcomings in existing technologies, this invention provides a frequency domain superposition peak finding method and system based on field-programmable gate arrays, which solves the problem that existing frequency domain superposition peak finding methods cannot achieve a reasonable balance between fast response, stability and accuracy and lightweight and low power consumption.

[0008] To achieve the above objectives, the technical solution adopted by the present invention is as follows: On one hand, a frequency domain superposition peak-finding method based on a field-programmable gate array (FPGA) is provided, comprising the following steps:

[0009] S1. Based on a multi-processor system chip, digital acquisition of optoelectronic radio frequency analog signal data is performed, and a preset analog-to-digital conversion configuration is set. By parsing the optoelectronic radio frequency analog signal data, analog-to-digital conversion data and data validity identification signals are obtained.

[0010] S2. Based on the valid data identification signal, the analog-to-digital conversion data is expanded through first-in-first-out, and the expanded analog-to-digital conversion data is then subjected to frequency domain superposition to find the peak, resulting in superimposed frequency domain analog-to-digital data and peak-to-peak data.

[0011] S3. Cache the superimposed frequency domain modulus data and peak data, monitor the cached data, and move the cached data to the preset cache of the high-performance processor system by sending a request data burst transmission command. In response to the completion of the data burst transmission, set the data validity status to valid.

[0012] S4. In response to the high-performance processor system successfully reading the data validity status, the data validity status is set to invalid, and a status monitor signal is sent. It is determined whether the status monitor signal is valid. If it is, the process returns to step S2. Otherwise, the next round of operation is not started, and the frequency domain superposition peak finding is completed.

[0013] The beneficial effects of this invention are as follows: This invention acquires and expands photoelectric radio frequency analog signal data through high-speed analog-to-digital conversion, achieves fast response through frequency domain superposition peak finding and cache monitoring, and achieves a reasonable balance between stability and accuracy with lightweight and low power consumption.

[0014] Further, S1 includes the following steps:

[0015] S101, Based on a multi-processor system chip, digitally acquires optoelectronic radio frequency analog signal data, and sets the analog-to-digital conversion crystal oscillator frequency configuration, analog-to-digital conversion clock buffer configuration, and analog-to-digital conversion parameter configuration;

[0016] S102. Receive and analyze the collected photoelectric radio frequency analog signal data through a preset transmission protocol to obtain analog-to-digital conversion data and data validity identification signal.

[0017] Furthermore, S2 includes the following steps:

[0018] S201. Based on the data validity identification signal, the data bit width of the analog-to-digital conversion data is expanded by first-in-first-out to obtain the expanded analog-to-digital conversion data.

[0019] S202. Perform cross-clock domain operations on the expanded analog-to-digital conversion data to obtain cross-clock domain analog-to-digital conversion data, and use the cross-clock domain analog-to-digital conversion data as the original sample set;

[0020] S203. The original sample set is halved to obtain halved sampled data, and the halved sampled data is superimposed on the halved spectrum to obtain the halved spectrum superimposed result data.

[0021] S204. Perform quarter sampling on the original sample set to obtain quarter sampling data, and perform quarter spectrum superposition on the quarter sampling data to obtain the quarter spectrum superposition result data.

[0022] S205. Perform full-spectrum overlay on the original sample set to obtain the full-spectrum overlay result data;

[0023] S206. By using a ring-shaped computing unit designed with a data ring rolling superposition method, the preset points in the half-spectrum superposition result data, the quarter-spectrum superposition result data and the full-spectrum superposition result data are summed respectively to obtain the superimposed frequency domain modulus data.

[0024] S207. By shifting the frequency of the preset points in the frequency domain and subtracting the spectrum symmetrically, the peak value data of the superimposed frequency domain modulus is obtained by performing a frequency peak finding operation.

[0025] Furthermore, the half-spectrum superposition, quarter-spectrum superposition, and full-spectrum superposition are specifically as follows:

[0026] Half-spectral superposition:

[0027] The original sample set is halved to obtain halved sample data. Then, a finite impulse response filter containing a preset window function is used to perform low-pass filtering on the halved sample data to obtain filtered halved sample data.

[0028] Perform a Fast Fourier Transform (FFT) on the filtered half-sampled data at preset points to obtain the half-FFT data set;

[0029] The data sets of half-fast Fourier transform are subjected to modulo summation and rounding. The two sets of modulo summation and rounding results are calculated and added together to obtain the half-spectral superposition result data.

[0030] Quarter-spectrum superposition:

[0031] The original sample set is sampled in quarters to obtain quarter-sampled data. Then, a finite impulse response filter containing a preset window function is used to perform low-pass filtering on the quarter-sampled data to obtain filtered quarter-sampled data.

[0032] Perform a Fast Fourier Transform on the filtered quarter-sampled data at preset points to obtain a quarter-Fast Fourier Transform data set.

[0033] The quarter-fast Fourier transform data sets are subjected to modulo accumulation and rounding to obtain four sets of modulo accumulation and rounding results, which are then added together to obtain the quarter-spectrum superposition result data.

[0034] Full spectrum overlay:

[0035] Using a finite impulse response filter with a preset window function, all the original data in the original sample set are low-pass filtered to obtain filtered sampled data.

[0036] Perform a Fast Fourier Transform (FFT) on the filtered sampled data at preset points to obtain the FFT data set.

[0037] The fast Fourier transform data sets are subjected to modulo accumulation and rounding to obtain the full sampling processing result, resulting in the full spectrum superposition result data.

[0038] Furthermore, the expression for the half-spectrum superposition result data is as follows:

[0039] ;

[0040] ;

[0041] ;

[0042] in, This represents the data resulting from the superposition of half-spectrum data. Indicates the first j indivual, Indicates the total number of packages. Indicates the first i Bag, This represents the result of modulo summation and integer division of the first set of data from the 1 / 2 Fast Fourier Transform. This represents the result of modulo summation and integer division of the second set of data from the 1 / 2 Fast Fourier Transform. This indicates that the processed result is an integer. This indicates that a logarithmic operation is performed on the modulus. This indicates taking the modulus of the frequency domain data. This represents the first data in the first group of half-fast Fourier transform data. i The first of the packages j One data point, This represents the second group of data in the 1 / 2 Fast Fourier Transform dataset. i The first of the packages j One data point;

[0043] The expression for the quarter-spectrum overlay result data is shown below:

[0044] ;

[0045] ;

[0046] ;

[0047] ;

[0048] ;

[0049] in, This represents the data from the quarter-spectrum overlay. This represents the result of modulo summation and integer division of the first set of data from the quarter-fast Fourier transform. This represents the result of modulo summation and integer division of the second set of data from the quarter-fast Fourier transform. This represents the result of modulo summation and integer division of the third set of data from the quarter-fast Fourier transform. This represents the result of modulo summation and integer division of the fourth set of data from the quarter-fast Fourier transform. This represents the first data in the first group of the quarter-fast Fourier transform data. i The first of the packages j One data point, This represents the first data in the first group of the quarter-fast Fourier transform data. i The first of the packages j One data point, This represents the first data in the first group of the quarter-fast Fourier transform data. i The first of the packages j One data point, This represents the first data in the first group of the quarter-fast Fourier transform data. i The first of the packages j Data points.

[0050] The beneficial effects of the above-mentioned further solutions are as follows: This invention can preserve key frame details by combining full-spectrum data processing, half-spectrum data processing, and quarter-spectrum data processing, while reducing resource consumption in non-critical areas, thus improving computational efficiency and resource optimization; frequency domain filtering in the half-spectrum and quarter-spectrum processes noise avoids additional interference introduced by the full spectrum, thereby improving the overall system signal-to-noise ratio; and comparison of results can improve the robustness of the analysis, thereby improving the overall measurement accuracy.

[0051] A ring-shaped computing unit was designed to achieve the summation of preset points. The data is superimposed in a ring-shaped manner, which eliminates the time for data caching, copying and transmission. It does not occupy the valuable internal storage resources of the field-programmable gate array, saves hardware resources and improves data processing efficiency.

[0052] Furthermore, step S3 includes the following steps:

[0053] S301. Cache the superimposed frequency domain modulus data and peak data, monitor the cached data, and send a request for data burst transmission command when the cached data reaches the preset data processing volume.

[0054] S302. According to the request data burst transmission command, the processed frequency domain modulus data and peak data are moved to the preset buffer through the high-performance advanced scalable interface bus according to the preset address and data length.

[0055] S303. In response to the completion of the data burst transfer, a status valid command is sent and the data valid status is set to valid.

[0056] Furthermore, step S4 includes the following steps:

[0057] S401. In response to the high-performance processor system successfully reading the data validity status, the data validity status is set to invalid, and a status monitor signal containing the data validity status and the start validity instruction is sent.

[0058] S402. Determine whether the status monitor signal is valid. If yes, return to step S2 to perform the next round of data buffering and data processing. Otherwise, do not start the next round of operation and complete the frequency domain superposition peak finding.

[0059] The beneficial effects of the above-mentioned further solutions are as follows: By caching and monitoring data, the present invention accurately responds to and sends burst transmission commands for requested data, and combines a high-performance advanced scalable interface bus to realize data transfer and generate status monitor signals to control the next round of data buffering and data processing. This effectively realizes the backpressure operation mechanism in the data transmission process, avoids the risk of data loss or overflow, ensures the integrity and reliability of data transmission, and improves the stable processing capability of the frequency domain superposition peak finding system in high-concurrency scenarios.

[0060] On the other hand, a frequency domain superposition peak-finding system based on a field-programmable gate array is provided, including:

[0061] The analog-to-digital conversion subsystem is used to digitally acquire photoelectric radio frequency analog signal data, set preset analog-to-digital conversion configurations, and obtain analog-to-digital conversion data and data validity identification signals by parsing the photoelectric radio frequency analog signal data;

[0062] The data buffer subsystem is used to identify the start valid command sent by the start data processing module. In response to the start valid command being valid and the data valid identification signal being valid, the analog-to-digital conversion data is expanded according to the data valid identification signal through first-in-first-out, and the superimposed frequency domain analog value data and peak data in the data processing subsystem are buffered, and the buffered data is monitored.

[0063] The data processing subsystem is used to find the peak value in the frequency domain by superimposing the extended analog-to-digital conversion data in the frequency domain, and obtain the superimposed frequency domain modulus data and peak value data.

[0064] The data output subsystem should, upon successful reading of the data validity status from the high-performance processor system, set the data validity status to invalid and send a status monitor signal to determine whether the status monitor signal is valid. If it is valid, it should return to the data buffer subsystem and pass through the data processing subsystem again; otherwise, it should not start the next round of operations to complete the frequency domain superposition peak finding.

[0065] Furthermore, the data processing subsystem includes:

[0066] The cross-clock domain module is used to perform cross-clock domain operations on the extended analog-to-digital conversion data to obtain cross-clock domain analog-to-digital conversion data, and use the cross-clock domain analog-to-digital conversion data as the original sample set;

[0067] The first finite impulse response filter module is used to halve the original sample set to obtain halved sampled data, and then use a finite impulse response filter containing a preset window function to perform low-pass filtering on the halved sampled data to obtain filtered halved sampled data.

[0068] The second finite impulse response filter module is used to perform low-pass filtering on all the original data in the original sample set using a finite impulse response filter containing a preset window function, so as to obtain filtered sampled data.

[0069] The third finite impulse response filter module is used to perform quarter sampling on the original sample set to obtain quarter sample data, and then use a finite impulse response filter containing a preset window function to perform low-pass filtering on the quarter sample data to obtain filtered quarter sample data.

[0070] The Fast Fourier Transform (FFT) module is used to perform FFT on the filtered half-sampled data, filtered sampled data, and filtered quarter-sampled data at preset points to obtain the half-FFT data set, the FFT data set, and the quarter-FFT data set, respectively.

[0071] The modulus module is used to obtain the modulus values ​​of each point in the half-fast Fourier transform data set, the fast Fourier transform data set, and the quarter-fast Fourier transform data set;

[0072] The full-spectrum overlay module is used to perform modulo accumulation and rounding on the fast Fourier transform data sets to calculate the full sampling processing result and obtain the full-spectrum overlay result data.

[0073] The half-spectrum superposition module is used to perform modulo accumulation and rounding on half-fast Fourier transform data sets, calculate two sets of modulo accumulation and rounding results, and add them together to obtain the half-spectrum superposition result data;

[0074] The quarter-spectrum overlay module is used to perform modulo accumulation and rounding on the quarter-fast Fourier transform data sets, calculate four sets of modulo accumulation and rounding results, and add them together to obtain the quarter-spectrum overlay result data;

[0075] The peak finding module is used to sum preset points in the half-spectrum superposition result data, quarter-spectrum superposition result data and full-spectrum superposition result data by using a ring computing unit designed with a data ring rolling superposition method to obtain the superimposed frequency domain modulus data. By frequency shifting the preset points in the frequency domain and symmetrically subtracting the spectrum, the module performs frequency peak finding operation on the superimposed frequency domain modulus data to obtain the peak data.

[0076] Furthermore, the analog-to-digital conversion subsystem includes:

[0077] A high-speed analog-to-digital converter module is used for the digital acquisition of optoelectronic radio frequency analog signal data;

[0078] The high-speed analog-to-digital converter controller module is used to receive and parse the collected optoelectronic radio frequency analog signal data by setting the analog-to-digital conversion crystal oscillator frequency configuration, analog-to-digital conversion clock buffer configuration, and analog-to-digital conversion parameter configuration, and to obtain analog-to-digital conversion data and data validity identification signal through a preset transmission protocol;

[0079] The data buffer subsystem includes:

[0080] The first data buffer module is used to identify the start valid command sent by the start data processing module, and according to the data valid identification signal, to expand the data bit width of the analog-to-digital conversion data through first-in-first-out to obtain the expanded analog-to-digital conversion data;

[0081] The second data buffer module is used to cache the superimposed frequency domain modulus data and peak data, and monitor the cached data. In response to the cached data reaching the preset data processing volume, it sends a request for data burst transmission command. In response to the completion of data burst transfer, it sends a status valid command to the data output subsystem.

[0082] The data output subsystem includes:

[0083] The direct memory access module is used to move the processed frequency domain modulus data and peak data to a preset buffer according to the requested data burst transfer command via a high-performance advanced scalable interface bus, based on the preset address and data length.

[0084] The status monitor module is used to set the data validity status to valid and monitor it according to the status validity instruction. In response to the high-performance processor system successfully reading the data validity status, it sets the data validity status to invalid and sends a status monitor signal containing the data validity status and the start validity instruction.

[0085] The data processing module is activated to identify valid signals from the status monitor and determine whether the status monitor signal is valid. If it is valid, the data processing module is activated to start the next round of data buffering and data processing. Otherwise, the next round of operation is not activated, and the frequency domain superposition peak finding is completed.

[0086] The beneficial effects of the above-mentioned further solutions are as follows: This invention not only performs full-spectrum iterative peak finding on the collected raw data, but also performs half-spectrum iterative peak finding and quarter-spectrum iterative peak finding on the raw data; it can effectively improve the spectral resolution, design different finite impulse response filters to process the data, improve the overall signal-to-noise ratio, and thus improve the overall measurement accuracy. Attached Figure Description

[0087] Figure 1 This is a flowchart of the method of the present invention.

[0088] Figure 2 This is a diagram of the frequency domain superposition peak finding architecture in this embodiment.

[0089] Figure 3 This is a schematic diagram of the circular rolling overlay method in this embodiment.

[0090] Figure 4 This is a system structure diagram in this embodiment.

[0091] Figure 5 This is a hardware architecture diagram for this embodiment. Detailed Implementation

[0092] The specific embodiments of the present invention are described below to enable those skilled in the art to understand the present invention. However, it should be understood that the present invention is not limited to the scope of the specific embodiments. For those skilled in the art, various changes are obvious as long as they are within the spirit and scope of the present invention as defined and determined by the appended claims. All inventions utilizing the concept of the present invention are protected.

[0093] Before describing this embodiment, the following terms will be explained:

[0094] FPGA: Field Programmable Gate Array;

[0095] JESD204B: A serial interface standard for communication between high-speed data converters and receivers;

[0096] MPSOC: Multiprocessor System-on-Chip;

[0097] PSOC: System-on-a-Chip processor;

[0098] FIFO: First In, First Out;

[0099] PS: PSOC is a high-performance processor system;

[0100] PL: Programmable logic section of the PSOC;

[0101] ARM: Advanced Reduced Instruction Set Machine;

[0102] AXI: Advanced Extensible Interface;

[0103] DSP: Digital Signal Processor;

[0104] ADC: Analog-to-Digital Conversion;

[0105] FIR: Finite Impulse Response Filter;

[0106] HP-AXI: High-performance, advanced, and scalable interface;

[0107] DDR3: Third-generation Double Data Synchronous Dynamic Random Access Memory;

[0108] FFT Transform: Fast Fourier Transform.

[0109] Example 1

[0110] like Figure 1 As shown, this invention provides a frequency domain superposition peak finding method based on field-programmable gate arrays, the implementation method of which is as follows:

[0111] S1. Based on a multi-processor system chip, digital acquisition of optoelectronic radio frequency analog signal data is performed, and a preset analog-to-digital conversion configuration is set. By parsing the optoelectronic radio frequency analog signal data, analog-to-digital conversion data and data validity identification signals are obtained. The specific steps are as follows:

[0112] S101, Based on a multi-processor system chip, digitally acquires optoelectronic radio frequency analog signal data, and sets the analog-to-digital conversion crystal oscillator frequency configuration, analog-to-digital conversion clock buffer configuration, and analog-to-digital conversion parameter configuration;

[0113] S102. Receive and analyze the collected photoelectric radio frequency analog signal data through a preset transmission protocol to obtain analog-to-digital conversion data and data validity identification signal.

[0114] In this embodiment, based on the MPSOC multiprocessor system chip, the digital acquisition of photoelectric radio frequency analog signals is realized, and high-frequency data acquisition is required. The photoelectric radio frequency analog signal data is received and parsed through the preset transmission protocol JESD204B to obtain analog-to-digital conversion data and data validity identification signal, and then continuously transmitted.

[0115] S2. Based on the valid data identification signal, the analog-to-digital conversion data is expanded using a first-in-first-out (FIFO) method. The expanded analog-to-digital conversion data is then subjected to frequency domain superposition to find the peak values, resulting in the superimposed frequency domain analog-to-digital and peak-to-peak data. The specific steps are as follows:

[0116] S201. Based on the data validity identification signal, the data bit width of the analog-to-digital conversion data is expanded by first-in-first-out to obtain the expanded analog-to-digital conversion data.

[0117] S202. Perform cross-clock domain operations on the extended analog-to-digital conversion data to obtain cross-clock domain analog-to-digital conversion data, and use the cross-clock domain analog-to-digital conversion data as the original sample set.

[0118] In this embodiment, a valid data identification signal is identified. If valid, analog-to-digital conversion data is received. First-in-first-out is used to avoid data processing speed and data buffer buffer speed being inconsistent, which would cause sampling data loss. The data bit width of the analog-to-digital conversion data is expanded to improve data throughput and obtain expanded analog-to-digital conversion data.

[0119] The extended analog-to-digital conversion data is processed through a FIFO to operate across clock domains, enabling data to stably move from the slow clock domain to the fast clock domain. This improves data processing efficiency, shortens data processing time, and enhances the real-time performance of data processing, resulting in cross-clock domain analog-to-digital conversion data, which is then used as the original sample set.

[0120] S203. The original sample set is halved to obtain halved sampled data, and the halved sampled data is superimposed on the halved spectrum to obtain the halved spectrum superimposed result data.

[0121] S204. Perform quarter sampling on the original sample set to obtain quarter sampling data, and perform quarter spectrum superposition on the quarter sampling data to obtain the quarter spectrum superposition result data.

[0122] S205. Perform full-spectrum overlay on the original sample set to obtain the full-spectrum overlay result data.

[0123] In this embodiment, as Figure 2As shown, frequency domain superposition peak finding based on a field-programmable gate array (FPGA) requires data processing including FIR filtering of the acquired data, 1 / 2 sampling of the data, 1 / 4 sampling of the data, FFT processing, obtaining the modulus of the FFT-processed data, modulus superposition, log operation of the modulus, symmetric subtraction denoising, and peak finding. The processed data is then transmitted back to the data. Specifically:

[0124] Based on the original sample set, pre-determine all sampling sample points: a total of one set, each set... m Packets, each pack n Data, total The data is expressed as follows:

[0125] ;

[0126] in, Indicates the number of all sampled points. i The first of the packages j The data point, i.e., the first data point of the full sample. One data point;

[0127] Half-spectral superposition:

[0128] The original sample set is halved to obtain halved sample data. An FIR filter with a preset window function is then used to perform low-pass filtering on the halved sample data to remove noise interference, improve the system signal-to-noise ratio, and enhance measurement accuracy under weak signal conditions. This results in filtered halved sample data, which consists of two sets, each set... m / 2 packets, with the original data volume remaining unchanged, can obtain m Data that has been sampled by half can significantly reduce data caching space and collection time, thereby improving processing efficiency.

[0129] The expression for 1 / 2 sample data is shown below:

[0130] ;

[0131] ;

[0132] in, This indicates that in the first group of a 1 / 2 sampling, the first... i The first of the packages j The data point, i.e., the first data point of the full sample. One data point, This indicates that in the second group of a 1 / 2 sampling, the first... i The first of the packages j The data point, i.e., the first data point of the full sample. Data, of which ;

[0133] The default window function is the Kaiser window, with default parameters. The FIR filter uses an 81st order, and the filter cutoff frequency is close to... ,in This indicates the ADC sampling frequency.

[0134] In this embodiment, the filtered 1 / 2 sampled data is subjected to a preset 2048-point FFT transform to obtain a 1 / 2 Fast Fourier Transform data set, as shown in the following expression:

[0135] ;

[0136] ;

[0137] in, This represents the first data group of the 1 / 2 Fast Fourier Transform data. i The first of the packages j One data point, This represents the second group of data in the 1 / 2 Fast Fourier Transform dataset. i The first of the packages j Data, of which ;

[0138] Then take the first number of each group j The data at each location is used to perform modulo summation and rounding to obtain two sets of modulo summation and rounding results, as shown in the following expression:

[0139] ;

[0140] ;

[0141] in, This represents the result of modulo summation and integer division of the first set of data from a 1 / 2 Fast Fourier Transform. This represents the result of modulo summation and integer division of the second set of data from the 1 / 2 Fast Fourier Transform. This indicates that the processed result is an integer. This indicates that a logarithmic operation is performed on the modulus. This indicates taking the modulus of the frequency domain data;

[0142] The two sets of results are then added together to obtain the half-spectrum superposition result data, as shown in the following expression:

[0143] ;

[0144] in, This represents the result of superimposing half-spectrum data.

[0145] In this embodiment, quarter-spectrum superposition is used:

[0146] The original sample set is quarter-sampled to obtain quarter-sampled data. This quarter-sampled data is then low-pass filtered using an FIR filter with a preset window function to remove noise interference, improve the system signal-to-noise ratio, and enhance measurement accuracy under weak signal conditions. This results in filtered quarter-sampled data, which consists of four sets, each set containing... m / 4 packets, with the original data volume remaining unchanged, can obtain m Data that has been sampled by 1 / 4 can significantly reduce data caching space and collection time, thereby improving processing efficiency.

[0147] The expression for 1 / 4 sample data is shown below:

[0148] ;

[0149] ;

[0150] ;

[0151] ;

[0152] in, This indicates that in the first group of a 1 / 4 sample, the first... i The first of the packages j The data point, i.e., the first data point of the full sample. One data point, This indicates that in the second group of a 1 / 4 sample, the first... i The first of the packages j The data point, i.e., the first data point of the full sample. One data point, This indicates that in the 3rd group of the 1 / 4 sampling, the first... i The first of the packages j The data point, i.e., the first data point of the full sample. One data point, This indicates that in the 4th group of a 1 / 4 sample, the first... i The first of the packages j The data point, i.e., the first data point of the full sample. Data, of which ;

[0153] The default window function is the Kaiser window, with default parameters. The FIR filter uses an 81st order, and the filter cutoff frequency is close to... .

[0154] In this embodiment, the filtered 1 / 4 sampled data is subjected to a preset 2048-point FFT transform to obtain a 1 / 4 Fast Fourier Transform data set, as shown in the following expression:

[0155] ;

[0156] ;

[0157] ;

[0158] ;

[0159] in, This represents the first data in the first group of 1 / 4 Fast Fourier Transform data. i The first of the packages j One data point, This represents the second group of 1 / 4 Fast Fourier Transform data. i The first of the packages j One data point, This represents the 3rd group of 1 / 4 Fast Fourier Transform data. i The first of the packages j One data point, This represents the fourth group of data in the 1 / 4 Fast Fourier Transform dataset. i The first of the packages j One data point;

[0160] Then take the first number of each group j The data at each location is used to perform modulo summation and rounding to obtain four sets of modulo summation and rounding results, as shown in the following expression:

[0161] ;

[0162] ;

[0163] ;

[0164] ;

[0165] in, This represents the result of modulo summation and integer division of the first set of data from the quarter-fast Fourier transform. This represents the result of modulo summation and integer division of the second set of data from the quarter-fast Fourier transform. This represents the result of modulo summation and integer division of the third set of data from the quarter-fast Fourier transform. This represents the result of modulo summation and integer division of the fourth set of data from the quarter-fast Fourier transform.

[0166] The four sets of results are then added together to obtain the 1 / 4 spectrum superposition result data, as shown in the following expression:

[0167] ;

[0168] in, This represents the data from the 1 / 4 spectral overlay, where .

[0169] In this embodiment, the entire spectrum is superimposed:

[0170] Using an FIR filter with a preset window function, all the original data in the original sample set are low-pass filtered to obtain filtered sampled data.

[0171] The filtered sampled data is subjected to a preset 2048-point FFT transformation to obtain the Fast Fourier Transform (FFT) data set, as shown in the following expression:

[0172] ;

[0173] in, Indicates the first j The result of the point-wise FFT transformation is a complex number. Represents the first data group of the Fast Fourier Transform (FFT) i The first of the packages j One data point;

[0174] The default window function is the Kaiser window, with default parameters. The FIR filter uses an 81st order, and the filter cutoff frequency is close to... ;

[0175] The signal has been transformed from the time domain to the frequency domain, obtaining the amplitude information of signals with different frequency components. Then, the amplitude information of each packet is... j The full spectrum overlay result is obtained by performing modulo summation and rounding on the data from each location, as shown in the following expression:

[0176] ;

[0177] in, This represents the full-spectrum overlay result data, where .

[0178] S206. By using a ring-shaped computing unit designed with a data ring rolling superposition method, the preset points in the half-spectrum superposition result data, the quarter-spectrum superposition result data and the full-spectrum superposition result data are summed respectively to obtain the superimposed frequency domain modulus data.

[0179] S207. By shifting the frequency of the preset points in the frequency domain and subtracting the spectrum symmetrically, the peak value data of the superimposed frequency domain modulus is obtained by performing a frequency peak finding operation.

[0180] In this embodiment, as Figure 3As shown, a ring computing unit is designed, employing a ring-shaped rolling superposition method to sum the data between multiple packets in a rolling manner. This eliminates the need to occupy the valuable internal storage resources of the FPGA, significantly saving hardware resources. Because the time spent on data caching, copying, and transmission is eliminated, data processing efficiency is improved. Each packet of data moves in a ring. After 2048 moves, the first data of the current packet is aligned with the first data of the next packet for addition. The addition result continues to move in a ring until each group of data is added. 2048 result data are output from the ring computing structure to obtain the superimposed frequency domain modulus data. This design eliminates the time spent on data caching, copying, and transmission, avoids occupying the valuable internal storage resources of the FPGA, significantly saves hardware resources, and improves data processing efficiency.

[0181] The frequency domain of 2048 points is frequency shifted, and the spectrum is symmetrically subtracted after the frequency shift to further eliminate interference and improve the signal-to-noise ratio. The superimposed frequency domain modulus data is then subjected to frequency peak finding to obtain useful frequency values ​​and thus obtain peak data.

[0182] S3. Cache the superimposed frequency domain magnitude data and peak data, monitor the cached data, and move the cached data to the preset cache of the high-performance processor system by sending a request for data burst transfer command. In response to the completion of the data burst transfer, set the data validity status to valid. The specific steps are as follows:

[0183] S301. Cache the superimposed frequency domain modulus data and peak data, monitor the cached data, and send a request for data burst transmission command when the cached data reaches the preset data processing volume.

[0184] S302. According to the request data burst transmission command, the processed frequency domain modulus data and peak data are moved to the preset buffer through the high-performance advanced scalable interface bus according to the preset address and data length.

[0185] S303. In response to the completion of the data burst transfer, a status valid command is sent and the data valid status is set to valid.

[0186] In this embodiment, the received data processing module caches the superimposed frequency domain modulus data and peak data, and monitors whether the cached data reaches the specified data processing volume. If the specified data volume is reached, a request for data burst transmission is sent and the DMA is monitored to ensure that the data burst transfer is completed.

[0187] According to the request data burst transfer command, the DMA directly moves the processed frequency domain modulus data and peak data to the PS's DDR3 cache via the PS's HP-AXI bus, according to the agreed address and data length.

[0188] Once the DMA completes the data burst transfer, it sends a status valid command and sets the data valid status to valid so that the PS cycle can query and read the data valid status. By using a first-in-first-out (FIFO) FIFO in First Word fall-through mode, it facilitates interconnection with the HP-AXI AXI bus and avoids using RAM to read data by address, thus reducing the efficiency of DMA data transfer.

[0189] S4. In response to the high-performance processor system successfully reading the data validity status, the data validity status is set to invalid, and a status monitor signal is sent. It is determined whether the status monitor signal is valid. If it is, the process returns to step S2; otherwise, the next round of operation is not started, and the frequency domain superposition peak finding is completed. The specific steps are as follows:

[0190] S401. In response to the high-performance processor system successfully reading the data validity status, the data validity status is set to invalid, and a status monitor signal containing the data validity status and the start validity instruction is sent.

[0191] S402. Determine whether the status monitor signal is valid. If yes, return to step S2 to perform the next round of data buffering and data processing. Otherwise, do not start the next round of operation and complete the frequency domain superposition peak finding.

[0192] In this embodiment, when the PS successfully reads the data validity status, it actively invalidates the data validity status and simultaneously sends a status monitor signal containing the data validity status and the start validity instruction.

[0193] Identify and determine the status monitor signal containing the data validity status and the start valid command. If the status monitor signal is valid, return to the step of receiving analog-to-digital conversion data and start the next round of data buffering and data processing. If the status monitor signal is invalid, do not start the next round of operation and complete the frequency domain superposition peak finding.

[0194] Example 2

[0195] like Figure 4 As shown, the present invention provides a frequency domain superposition peak finding system based on field-programmable gate array, including: an analog-to-digital conversion subsystem, a data buffer subsystem, a data processing subsystem, and a data output subsystem.

[0196] In this embodiment, the system processor is implemented using an MPSOC series FPGA. This type of chip comprises two parts: a PS (Power Supply) and a PL (Logical Processing). The PS integrates a multi-core ARM processor, while the PL utilizes the FPGA's logic resources. The PS and PL communicate via a high-speed AXI bus. This invention abandons the traditional dual-chip design of DSP+FPGA, adopting a single-chip MPSOC architecture. This leverages the advantages of parallel logic data processing while allowing multiple ARM cores to perform a small amount of data computation similar to DSP. Furthermore, the single-chip hardware circuit requires only one power supply system to meet the requirements, simplifying power supply design complexity. Simultaneously, it reduces the hardware circuit area, optimizing size and weight.

[0197] The analog-to-digital conversion subsystem is used to digitally acquire photoelectric radio frequency analog signal data, set preset analog-to-digital conversion configurations, and obtain analog-to-digital conversion data and data validity identification signals by parsing the photoelectric radio frequency analog signal data, including:

[0198] A high-speed analog-to-digital converter module is used for the digital acquisition of optoelectronic radio frequency analog signal data;

[0199] The high-speed analog-to-digital converter controller module is used to receive and parse the acquired optoelectronic radio frequency analog signal data by setting the analog-to-digital converter crystal oscillator frequency configuration, analog-to-digital converter clock buffer configuration, and analog-to-digital converter parameter configuration, and to obtain analog-to-digital conversion data and data validity identification signal through a preset transmission protocol.

[0200] In this embodiment, the high-speed ADC module mainly realizes the digital acquisition of photoelectric radio frequency analog signals. Since the frequency domain superposition peak finding system needs to support high-frequency data acquisition, the JESD204B protocol is used to transmit sampling data, and devices that support high-frequency sampling rates are used. The high-speed ADC design requires that the number of sampling channels, sampling rate, and JESD204B transmission channel parameters are all configurable to maximize compatibility with system applications.

[0201] After power-on, the high-speed ADC controller module first completes the configuration of the ADC crystal oscillator frequency, the ADC clock buffer, and the ADC parameters. After the configuration is completed, it receives the photoelectric radio frequency analog signal data collected by the ADC through the preset JESD204B protocol, parses the photoelectric radio frequency analog signal data, and continuously transmits the data validity identification signal and ADC data to the subsequent stage.

[0202] The data buffer subsystem is used to identify the start-up valid command sent by the start-up data processing module. In response to the valid start-up command and the valid data validity flag signal, it expands the analog-to-digital conversion data according to the data validity flag signal using a first-in-first-out (FIFO) method. It also buffers the superimposed frequency domain analog-to-digital data and peak data in the data processing subsystem and monitors the buffered data, including:

[0203] The first data buffer module is used to identify the start valid command sent by the start data processing module, and according to the data valid identification signal, to expand the data bit width of the analog-to-digital conversion data through first-in-first-out to obtain the expanded analog-to-digital conversion data;

[0204] The second data buffer module is used to cache the superimposed frequency domain modulus data and peak data, and monitor the cached data. In response to the cached data reaching the preset data processing volume, it sends a request for data burst transmission command. In response to the completion of data burst transfer, it sends a status valid command to the data output subsystem.

[0205] In this embodiment, the first data buffer module identifies a valid instruction sent by the start data processing module. The instruction is valid and the data validity indicator signal is valid. The first data buffer receives ADC data and expands the data bit width to improve the data throughput of the data processing module.

[0206] The first data buffer is implemented using a first-in-first-out (FIFO) to avoid data processing speed being inconsistent with the buffer speed of data buffer 1, which could lead to loss of sampled data.

[0207] The second data buffer module operates after the data processing subsystem outputs the superimposed frequency domain modulus data and peak data. It receives the superimposed frequency domain modulus data and peak data output by the data processing module and buffers them. It monitors whether the buffered data reaches the specified data processing volume. If the specified data volume is reached, the second data buffer sends a request for data burst transfer command to the DMA module. At the same time, the second data buffer monitors whether the DMA has completed the data burst transfer. If the DMA has completed the data burst transfer, the second data buffer sends a status valid command to the status monitor module.

[0208] The second data buffer is implemented using a first-in-first-out (FIFO) mode. The FIFO uses the first word fall-through mode to facilitate interconnection with the HP-AXI AXI bus and avoid using RAM to read data by address, which would reduce DMA data transfer efficiency.

[0209] The data processing subsystem is used to perform peak finding on the extended analog-to-digital conversion data through frequency domain superposition to obtain superimposed frequency domain modulus data and peak value data, including:

[0210] The cross-clock domain module is used to perform cross-clock domain operations on the extended analog-to-digital conversion data to obtain cross-clock domain analog-to-digital conversion data, and use the cross-clock domain analog-to-digital conversion data as the original sample set;

[0211] The first finite impulse response filter module is used to halve the original sample set to obtain halved sampled data, and then use a finite impulse response filter containing a preset window function to perform low-pass filtering on the halved sampled data to obtain filtered halved sampled data.

[0212] The second finite impulse response filter module is used to perform low-pass filtering on all the original data in the original sample set using a finite impulse response filter containing a preset window function, so as to obtain filtered sampled data.

[0213] The third finite impulse response filter module is used to perform quarter sampling on the original sample set to obtain quarter sample data, and then use a finite impulse response filter containing a preset window function to perform low-pass filtering on the quarter sample data to obtain filtered quarter sample data.

[0214] The Fast Fourier Transform (FFT) module is used to perform FFT on the filtered half-sampled data, filtered sampled data, and filtered quarter-sampled data at preset points to obtain the half-FFT data set, the FFT data set, and the quarter-FFT data set, respectively.

[0215] The modulus module is used to obtain the modulus values ​​of each point in the half-fast Fourier transform data set, the fast Fourier transform data set, and the quarter-fast Fourier transform data set;

[0216] The full-spectrum overlay module is used to perform modulo accumulation and rounding on the fast Fourier transform data sets to calculate the full sampling processing result and obtain the full-spectrum overlay result data.

[0217] The half-spectrum superposition module is used to perform modulo accumulation and rounding on half-fast Fourier transform data sets, calculate two sets of modulo accumulation and rounding results, and add them together to obtain the half-spectrum superposition result data;

[0218] The quarter-spectrum overlay module is used to perform modulo accumulation and rounding on the quarter-fast Fourier transform data sets, calculate four sets of modulo accumulation and rounding results, and add them together to obtain the quarter-spectrum overlay result data;

[0219] The peak finding module is used to sum preset points in the half-spectrum superposition result data, quarter-spectrum superposition result data and full-spectrum superposition result data by using a ring computing unit designed with a data ring rolling superposition method to obtain the superimposed frequency domain modulus data. By frequency shifting the preset points in the frequency domain and symmetrically subtracting the spectrum, the module performs frequency peak finding operation on the superimposed frequency domain modulus data to obtain the peak data.

[0220] In this embodiment, the data processing subsystem not only performs full-spectrum iterative peak finding on the collected raw data, but also performs 1 / 2-spectrum iterative peak finding and 1 / 4-spectrum iterative peak finding on the raw data; this can effectively improve the spectral resolution, and different FIR filters can be designed to process the data, thereby improving the overall signal-to-noise ratio and thus improving the overall measurement accuracy.

[0221] The data processing subsystem includes:

[0222] The cross-clock domain module receives data from the first data buffer module and performs cross-clock domain operations through FIFO, so that the data can stably enter the fast clock domain from the slow clock domain, thereby improving data processing efficiency, shortening data processing time, and improving the real-time performance of data processing.

[0223] The first FIR filter module performs 1 / 2 sampling on the original sample set and uses a finite impulse response filter containing a preset window function to perform low-pass filtering on the 1 / 2 sampled data to filter out noise interference, improve the system signal-to-noise ratio, improve the measurement accuracy under weak signal conditions, and obtain filtered 1 / 2 sampled data.

[0224] The default window function is the Kaiser window, which can achieve higher stopband attenuation than other window functions, making it very suitable for applications that require strong noise suppression, and it can also achieve a flexible trade-off between main lobe width and side lobe attenuation.

[0225] The second FIR filter module uses a finite impulse response filter containing a preset window function to perform low-pass filtering on all the original data in the original sample set to obtain filtered sampled data.

[0226] The third FIR filter module performs 1 / 4 sampling on the original sample set to obtain 1 / 4 sampled data, and uses a finite impulse response filter containing a preset window function to perform low-pass filtering on the 1 / 4 sampled data to obtain filtered 1 / 4 sampled data.

[0227] The FFT module implements a 2048-point Fast Fourier Transform. The Fast Fourier Transform adopts a pipelined mode, which can perform Fourier Transform continuously in the form of a data stream to improve data processing speed. The FFT is performed on the filtered 1 / 2 sampled data, filtered sampled data, and filtered 1 / 4 sampled data at preset points to obtain 1 / 2 Fast Fourier Transform data groups, Fast Fourier Transform data groups, and 1 / 4 Fast Fourier Transform data groups, respectively.

[0228] The modulus module obtains the modulus values ​​of each point after the Fast Fourier Transform. The interface of this module adopts the Streaming IO interface, which can be seamlessly connected with the pipelined interface of the FFT module to avoid interface timing conversion and waste of clock cycles.

[0229] The full-spectrum overlay module is used to perform modulo accumulation and rounding on the fast Fourier transform data sets to calculate the full sampling processing result and obtain the full-spectrum overlay result data.

[0230] The 1 / 2 spectrum superposition module is used to perform modulo accumulation and rounding on the 1 / 2 fast Fourier transform data group, calculate the two sets of modulo accumulation and rounding results, and add them together to obtain the 1 / 2 spectrum superposition result data;

[0231] The 1 / 4 spectrum overlay module is used to perform modulo accumulation and rounding on the 1 / 4 fast Fourier transform data set, calculate four sets of modulo accumulation and rounding results, and add them together to obtain the quarter spectrum overlay result data;

[0232] The peak finding module is used to sum preset points in the half-spectrum superposition result data, quarter-spectrum superposition result data and full-spectrum superposition result data by using a ring computing unit designed with a data ring rolling superposition method to obtain the superimposed frequency domain modulus data. By frequency shifting the preset points in the frequency domain and symmetrically subtracting the spectrum, the module performs frequency peak finding operation on the superimposed frequency domain modulus data to obtain the peak data.

[0233] In this embodiment, the data received from the first data buffer module is processed through a FIFO across clock domains to ensure stable data flow from the slow clock domain to the fast clock domain, thereby improving data processing efficiency, shortening processing time, and enhancing real-time performance. To filter out noise interference and improve the system signal-to-noise ratio and the measurement accuracy of weak signals, the raw data output from the first data buffer module is low-pass filtered to obtain 1 / 2 sampled data and 1 / 4 sampled data. The raw data, 1 / 2 sampled data, and 1 / 4 sampled data are each subjected to a 2048-point Fast Fourier Transform (FFT) to obtain the modulus. The FFT data sets, 1 / 2 FFT data sets, and 1 / 4 FFT data sets are then superimposed and summed at 2048 points to obtain three sets of data. These three sets of 2048-point frequency domain data are then frequency-shifted, and the spectrum is symmetrically subtracted after the frequency shift to further eliminate interference and improve the signal-to-noise ratio. After summing each set, a frequency peak-finding operation is performed to obtain useful frequency values, which are then stored in the second data buffer module.

[0234] The data output subsystem should, upon successful reading of the data validity status from the high-performance processor system, set the data validity status to invalid and send a status monitor signal to determine whether the status monitor signal is valid. If valid, it should return to the data buffer subsystem and pass through the data processing subsystem again; otherwise, it should not start the next round of operations to complete the frequency domain superposition peak finding, including:

[0235] The direct memory access module is used to move the processed frequency domain modulus data and peak data to a preset buffer according to the requested data burst transfer command via a high-performance advanced scalable interface bus, based on the preset address and data length.

[0236] The status monitor module is used to set the data validity status to valid and monitor it according to the status validity instruction. In response to the high-performance processor system successfully reading the data validity status, it sets the data validity status to invalid and sends a status monitor signal containing the data validity status and the start validity instruction.

[0237] The data processing module is activated to identify valid signals from the status monitor and determine whether the status monitor signal is valid. If it is valid, the data processing module is activated to start the next round of data buffering and data processing. Otherwise, the next round of operation is not activated, and the frequency domain superposition peak finding is completed.

[0238] In this embodiment, the DMA module directly moves the processed data to the PS's DDR3 cache according to the agreed address and data length via the PS's HP-AXI bus; PL and PS can share the same DDR3 cache via the HP-AXI bus, and PL does not need to be configured with a separate DDR3 external cache, saving hardware resources, power consumption, area, and reducing hardware costs;

[0239] PL and PS can share the same DDR3 cache via the HP-AXI bus. Data exchange between PL and PS does not require repeated copying between registers. Instead, data exchange is performed directly through the Daosu DDR3, which can effectively improve the data access speed between the two and improve the system's fast response.

[0240] Status Monitor Module: Based on the valid instructions from the second data buffer module, the status monitor sets the data validity status to be valid so that the PS can periodically query and read the data validity status; at the same time, it monitors the PS to read the data validity status identifier; if the PS successfully reads the data validity status identifier, the status monitor will actively set the data validity status to invalid and send a valid instruction to the start data processing module.

[0241] Start the data processing module: Identify valid signals from the status monitor. If the status monitor signal is valid, start the data processing subsystem to initiate the next round of data buffering and data processing. If the status monitor signal is invalid, do not initiate the next round of operation.

Claims

1. A frequency domain superposition peak finding method based on field-programmable gate arrays, characterized in that, Includes the following steps: S1. Based on the multiprocessor system chip MPSOC, the optoelectronic radio frequency analog signal data is digitally acquired, and a preset analog-to-digital conversion configuration is set. By parsing the optoelectronic radio frequency analog signal data, analog-to-digital conversion data and data validity identification signal are obtained. S2. Based on the valid data identification signal, the analog-to-digital conversion data is expanded using a first-in-first-out (FIFO) method. The expanded analog-to-digital conversion data is then subjected to frequency domain superposition for peak finding to obtain the superimposed frequency domain analog-to-digital and peak-to-peak data. Specifically: S201. Based on the data validity identification signal, the data bit width of the analog-to-digital conversion data is expanded by first-in-first-out to obtain the expanded analog-to-digital conversion data. S202. Perform cross-clock domain operations on the expanded analog-to-digital conversion data to obtain cross-clock domain analog-to-digital conversion data, and use the cross-clock domain analog-to-digital conversion data as the original sample set; S203. The original sample set is halved to obtain halved sampled data, and the halved sampled data is superimposed on the halved spectrum to obtain the halved spectrum superimposed result data. S204. Perform quarter sampling on the original sample set to obtain quarter sampling data, and perform quarter spectrum superposition on the quarter sampling data to obtain the quarter spectrum superposition result data. S205. Perform full-spectrum overlay on the original sample set to obtain the full-spectrum overlay result data; S206. By using a ring-shaped computing unit designed with a data ring rolling superposition method, the preset points in the half-spectrum superposition result data, the quarter-spectrum superposition result data and the full-spectrum superposition result data are summed respectively to obtain the superimposed frequency domain modulus data. S207. By shifting the frequency of preset points in the frequency domain and subtracting the spectrum symmetrically, the peak value data of the superimposed frequency domain modulus data is obtained by performing frequency peak finding operation on the superimposed frequency domain modulus data. S3. Cache the superimposed frequency domain modulus data and peak data, monitor the cached data, and move the cached data to the preset cache of the high-performance processor system PS by sending a request data burst transmission command. In response to the completion of the data burst transmission, set the data validity status to valid. S4. In response to the high-performance processor system PS successfully reading the data validity status, the data validity status is set to invalid, and a status monitor signal is sent. The system then determines whether the status monitor signal is valid. If it is, the process returns to step S2; otherwise, the next round of operations is not initiated, and the frequency domain superposition peak finding is completed. Specifically: S401, In response to the high-performance processor system PS successfully reading the data validity status, sets the data validity status to invalid and sends a status monitor signal containing the data validity status and the start validity instruction; S402. Determine whether the status monitor signal is valid. If yes, return to step S2 to perform the next round of data buffering and data processing. Otherwise, do not start the next round of operation and complete the frequency domain superposition peak finding.

2. The frequency domain superposition peak finding method based on field-programmable gate array according to claim 1, characterized in that, S1 includes the following steps: S101, based on the multiprocessor system chip MPSOC, digitally acquires optoelectronic radio frequency analog signal data, and sets the analog-to-digital conversion crystal oscillator frequency configuration, analog-to-digital conversion clock buffer configuration, and analog-to-digital conversion parameter configuration; S102. Receive and analyze the collected photoelectric radio frequency analog signal data through a preset transmission protocol to obtain analog-to-digital conversion data and data validity identification signal.

3. The frequency domain superposition peak finding method based on field-programmable gate array according to claim 1, characterized in that, The half-spectrum superposition, quarter-spectrum superposition, and full-spectrum superposition are specifically as follows: Half-spectral superposition: The original sample set is halved to obtain halved sample data. Then, a finite impulse response filter containing a preset window function is used to perform low-pass filtering on the halved sample data to obtain filtered halved sample data. Perform a Fast Fourier Transform (FFT) on the filtered half-sampled data at preset points to obtain the half-FFT data set; The data sets of half-fast Fourier transform are subjected to modulo summation and rounding. The two sets of modulo summation and rounding results are calculated and added together to obtain the half-spectral superposition result data. Quarter-spectrum superposition: The original sample set is sampled in quarters to obtain quarter-sampled data. Then, a finite impulse response filter containing a preset window function is used to perform low-pass filtering on the quarter-sampled data to obtain filtered quarter-sampled data. Perform a Fast Fourier Transform on the filtered quarter-sampled data at preset points to obtain a quarter-Fast Fourier Transform data set. The quarter-fast Fourier transform data sets are subjected to modulo accumulation and rounding to obtain four sets of modulo accumulation and rounding results, which are then added together to obtain the quarter-spectrum superposition result data. Full spectrum overlay: Using a finite impulse response filter with a preset window function, all the original data in the original sample set are low-pass filtered to obtain filtered sampled data. Perform a Fast Fourier Transform (FFT) on the filtered sampled data at preset points to obtain the FFT data set. The fast Fourier transform data sets are subjected to modulo accumulation and rounding to obtain the full sampling processing result, resulting in the full spectrum superposition result data.

4. The frequency domain superposition peak finding method based on field-programmable gate array according to claim 1, characterized in that, The expression for the half-spectrum superposition result data is shown below: in, This represents the data resulting from the superposition of half-spectrum data. Indicates the first j indivual, Indicates the total number of packages. Indicates the first i Bag, This represents the result of modulo summation and integer division of the first set of data from the 1 / 2 Fast Fourier Transform. This represents the result of modulo summation and integer division of the second set of data from the 1 / 2 Fast Fourier Transform. This indicates that the processed result is an integer. This indicates that a logarithmic operation is performed on the modulus. This indicates taking the modulus of the frequency domain data. This represents the first data in the first group of half-fast Fourier transform data. i The first of the packages j One data point, This represents the second group of data in the 1 / 2 Fast Fourier Transform dataset. i The first of the packages j One data point; The expression for the quarter-spectrum overlay result data is shown below: in, This represents the data from the quarter-spectrum overlay. This represents the result of modulo summation and integer division of the first set of data from the quarter-fast Fourier transform. This represents the result of modulo summation and integer division of the second set of data from the quarter-fast Fourier transform. This represents the result of modulo summation and integer division of the third set of data from the quarter-fast Fourier transform. This represents the result of modulo summation and integer division of the fourth set of data from the quarter-fast Fourier transform. This represents the first data in the first group of the quarter-fast Fourier transform data. i The first of the packages j One data point, This represents the data in group 2 of the quarter-fast Fourier transform dataset. i The first of the packages j One data point, This represents the third set of data in the quarter-fast Fourier transform dataset. i The first of the packages j One data point, This represents the fourth set of data in the quarter-fast Fourier transform dataset. i The first of the packages j Data points.

5. The frequency domain superposition peak finding method based on field-programmable gate array according to claim 1, characterized in that, S3 includes the following steps: S301. Cache the superimposed frequency domain modulus data and peak data, monitor the cached data, and send a request for data burst transmission command when the cached data reaches the preset data processing volume. S302. According to the request data burst transmission command, the processed frequency domain modulus data and peak data are moved to the preset buffer through the high-performance advanced scalable interface bus according to the preset address and data length. S303. In response to the completion of the data burst transfer, a status valid command is sent and the data valid status is set to valid.

6. A frequency domain superposition peak finding system based on a field-programmable gate array (FPGA), applied to the frequency domain superposition peak finding method based on a FPGA as described in any one of claims 1-5, characterized in that, include: The analog-to-digital conversion subsystem is used to digitally acquire photoelectric radio frequency analog signal data, set preset analog-to-digital conversion configurations, and obtain analog-to-digital conversion data and data validity identification signals by parsing the photoelectric radio frequency analog signal data; The data buffer subsystem is used to identify the start valid command sent by the start data processing module. In response to the start valid command being valid and the data valid identification signal being valid, the analog-to-digital conversion data is expanded according to the data valid identification signal through first-in-first-out, and the superimposed frequency domain analog value data and peak data in the data processing subsystem are buffered, and the buffered data is monitored. The data processing subsystem is used to find the peak value in the frequency domain by superimposing the extended analog-to-digital conversion data in the frequency domain, and obtain the superimposed frequency domain modulus data and peak value data. The data output subsystem, in response to the high-performance processor system successfully reading the data validity status, sets the data validity status to invalid and sends a status monitor signal to determine whether the status monitor signal is valid. If it is, it returns to the data buffer subsystem to perform the next round of operation through the data processing subsystem. Otherwise, it does not start the next round of operation and completes the frequency domain superposition peak finding.

7. The frequency domain superposition peak-finding system based on field-programmable gate array according to claim 6, characterized in that, The data processing subsystem includes: The cross-clock domain module is used to perform cross-clock domain operations on the extended analog-to-digital conversion data to obtain cross-clock domain analog-to-digital conversion data, and use the cross-clock domain analog-to-digital conversion data as the original sample set; The first finite impulse response filter module is used to halve the original sample set to obtain halved sampled data, and then use a finite impulse response filter containing a preset window function to perform low-pass filtering on the halved sampled data to obtain filtered halved sampled data. The second finite impulse response filter module is used to perform low-pass filtering on all the original data in the original sample set using a finite impulse response filter containing a preset window function, so as to obtain filtered sampled data. The third finite impulse response filter module is used to perform quarter sampling on the original sample set to obtain quarter sample data, and then use a finite impulse response filter containing a preset window function to perform low-pass filtering on the quarter sample data to obtain filtered quarter sample data. The Fast Fourier Transform (FFT) module is used to perform FFT on the filtered half-sampled data, filtered sampled data, and filtered quarter-sampled data at preset points to obtain the half-FFT data set, the FFT data set, and the quarter-FFT data set, respectively. The modulus module is used to obtain the modulus values ​​of each point in the half-fast Fourier transform data set, the fast Fourier transform data set, and the quarter-fast Fourier transform data set; The full-spectrum overlay module is used to perform modulo accumulation and rounding on the fast Fourier transform data sets to calculate the full sampling processing result and obtain the full-spectrum overlay result data; The half-spectrum superposition module is used to perform modulo accumulation and rounding on half-fast Fourier transform data sets, calculate two sets of modulo accumulation and rounding results, and add them together to obtain the half-spectrum superposition result data; The quarter-spectrum overlay module is used to perform modulo accumulation and rounding on the quarter-fast Fourier transform data sets, calculate four sets of modulo accumulation and rounding results, and add them together to obtain the quarter-spectrum overlay result data; The peak finding module is used to sum preset points in the half-spectrum superposition result data, quarter-spectrum superposition result data and full-spectrum superposition result data by using a ring computing unit designed with a data ring rolling superposition method to obtain the superimposed frequency domain modulus data. By frequency shifting the preset points in the frequency domain and symmetrically subtracting the spectrum, the module performs frequency peak finding operation on the superimposed frequency domain modulus data to obtain the peak data.

8. The frequency domain superposition peak-finding system based on field-programmable gate array according to claim 6, characterized in that, The analog-to-digital conversion subsystem includes: A high-speed analog-to-digital converter module is used for the digital acquisition of optoelectronic radio frequency analog signal data; The high-speed analog-to-digital converter controller module is used to receive and parse the collected optoelectronic radio frequency analog signal data by setting the analog-to-digital conversion crystal oscillator frequency configuration, analog-to-digital conversion clock buffer configuration, and analog-to-digital conversion parameter configuration, and to obtain analog-to-digital conversion data and data validity identification signal through a preset transmission protocol; The data buffer subsystem includes: The first data buffer module is used to identify the start valid command sent by the start data processing module, and according to the data valid identification signal, to expand the data bit width of the analog-to-digital conversion data through first-in-first-out to obtain the expanded analog-to-digital conversion data; The second data buffer module is used to cache the superimposed frequency domain modulus data and peak data, and monitor the cached data. In response to the cached data reaching the preset data processing volume, it sends a request for data burst transmission command. In response to the completion of data burst transfer, it sends a status valid command to the data output subsystem. The data output subsystem includes: The direct memory access module is used to move the processed frequency domain modulus data and peak data to a preset buffer according to the requested data burst transfer command via a high-performance advanced scalable interface bus, based on the preset address and data length. The status monitor module is used to set the data validity status to valid and monitor it according to the status validity instruction. In response to the high-performance processor system PS successfully reading the data validity status, it sets the data validity status to invalid and sends a status monitor signal containing the data validity status and the start validity instruction. The data processing module is activated to identify valid signals from the status monitor and determine whether the status monitor signal is valid. If it is valid, the data processing module is activated to start the next round of data buffering and data processing. Otherwise, the next round of operation is not activated, and the frequency domain superposition peak finding is completed.

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