6u dual-core radio frequency signal processing method and system based on heterogeneous computing architecture

Abstract

This invention discloses a 6U dual-core radio frequency (RF) signal processing method and system based on a heterogeneous computing architecture, belonging to the field of RF signal processing technology. The method includes: an embedded processing unit parsing external task instructions and distributing them to an RF direct sampling unit; the RF direct sampling unit acquiring RF signals and generating a noisy baseband data stream; an auxiliary sampling ADC synchronously acquiring broadband switching noise and generating an interference signal through a timing AI model; a hardware acceleration unit canceling the baseband data stream based on the interference signal to generate a clean data stream; and hardware acceleration processing being performed on the clean data stream and written to a shared memory unit. This solves the technical problem of broadband synchronous switching noise generated by digital circuits interfering with the RF receiving link, leading to a deterioration in baseband data stream quality. It achieves the technical effect of improving the accuracy, reliability, and real-time performance of RF signal processing through real-time noise cancellation and hardware acceleration processing.

Description

Technical Field

[0001] This invention relates to the field of radio frequency signal processing technology, and more specifically to a 6U dual-core radio frequency signal processing method and system based on a heterogeneous computing architecture. Background Technology

[0002] Against the backdrop of the continuous evolution of modern communications, the demand for signal processing in core areas such as base station RF access and broadband transmission is rapidly increasing. With the dramatic expansion of signal bandwidth, the increasing complexity of signal modulation methods, and the continuous emergence of multi-source heterogeneous signal environments, traditional RF signal processing systems face unprecedented challenges. On the one hand, the direct sampling and processing requirements of broadband RF signals place stringent demands on the sampling rate, dynamic range, and processing capabilities of hardware. A single computing power model (such as a general-purpose CPU or a dedicated DSP) struggles to achieve an ideal balance between power consumption, cost, and performance. On the other hand, interference problems caused by non-ideal factors such as synchronous switching noise (SSN) in digital circuits are becoming increasingly prominent during high-speed signal processing. This noise is coupled to the RF receiving link through the power distribution network, leading to signal quality degradation and potentially masking weak target signals, severely impacting system performance. Summary of the Invention

[0003] This application provides a 6U dual-core radio frequency signal processing method and system based on a heterogeneous computing architecture, which solves the technical problem that broadband synchronous switching noise generated by digital circuits interferes with the radio frequency receiving link, resulting in a decrease in the quality of the baseband data stream.

[0004] The first aspect of this application provides a 6U dual-core radio frequency signal processing method based on a heterogeneous computing architecture, the method comprising:

[0005] The embedded processing unit receives and parses external task instructions, and distributes the task instructions to the RF direct sampling unit. The RF direct sampling unit responds to the instructions, performs direct sampling and data conversion of the RF signal, and generates a baseband data stream containing real signals and noise interference. Through an auxiliary sampling ADC deployed at a key location on the board, broadband synchronous switching noise generated by the digital circuit is synchronously acquired, input to a pre-trained timing AI model, and outputs the interference signal generated by the broadband synchronous switching noise on the RF receiving link. In the hardware acceleration unit, the baseband data stream is canceled based on the interference signal to generate a clean baseband data stream. The clean baseband data stream is subjected to hardware-level acceleration processing in the hardware acceleration unit, and the final processing result is written to the shared memory unit.

[0006] A second aspect of this application provides a 6U dual-core radio frequency signal processing system based on a heterogeneous computing architecture, the system comprising:

[0007] Instruction parsing module: The embedded processing unit receives and parses external task instructions, and distributes the task instructions to the RF direct sampling unit; Signal sampling and conversion module: The RF direct sampling unit responds to the instructions, performs direct sampling and data conversion of the RF signal, and generates a baseband data stream containing real signals and noise interference; Interference signal generation module: Through auxiliary sampling ADCs deployed at key locations on the board, broadband synchronous switching noise generated by the digital circuit is synchronously collected, input to a pre-trained timing AI model, and outputs the interference signal generated by the broadband synchronous switching noise on the RF receiving link; Data cancellation module: In the hardware acceleration unit, the baseband data stream is cancelled based on the interference signal to generate a clean baseband data stream; Acceleration processing module: The clean baseband data stream is subjected to hardware-level acceleration processing in the hardware acceleration unit, and the final processing result is written to the shared memory unit.

[0008] One or more technical solutions provided in this application have at least the following technical effects or advantages:

[0009] First, the embedded processing unit receives and parses external task instructions, distributing them to the RF direct sampling unit for RF signal acquisition and conversion, generating a baseband data stream containing both real signals and noise interference. Simultaneously, auxiliary sampling ADCs are deployed at key locations on the board to synchronously acquire broadband synchronous switching noise generated by the digital circuitry. Then, a timing AI model analyzes the noise, outputting interference signals. Next, in the hardware acceleration unit, these interference signals are used to cancel the baseband data stream, removing interference and generating a clean baseband data stream. Finally, the clean baseband data stream undergoes hardware-level acceleration processing, and the processing results are stored in a shared memory unit to achieve efficient RF signal processing. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a schematic flowchart of a 6U dual-core radio frequency signal processing method based on a heterogeneous computing architecture, provided in an embodiment of this application.

[0012] Figure 2 This is a schematic diagram of a 6U dual-core radio frequency signal processing system based on a heterogeneous computing architecture, provided in an embodiment of this application.

[0013] Explanation of reference numerals in the attached diagram: 11. Instruction parsing module; 12. Signal sampling and conversion module; 13. Interference signal generation module; 14. Data cancellation module; 15. Acceleration processing module. Detailed Implementation

[0014] To further illustrate the technical means and effects of the present invention in achieving its intended purpose, the following detailed description of the specific implementation methods, structures, features, and effects of the present invention, in conjunction with the accompanying drawings and preferred embodiments, is provided below.

[0015] Example 1, as Figure 1 As shown, this application provides a 6U dual-core radio frequency signal processing method based on a heterogeneous computing architecture, the method comprising:

[0016] The embedded processing unit receives and parses external task instructions and distributes the task instructions to the RF direct sampling unit.

[0017] In this embodiment, the main function of the embedded processing unit is to receive externally sent task instructions and parse and process these instructions. The external task instructions may originate from the system's control module, upper-layer applications, or user input. The instructions include detailed information such as the type of RF signal to be processed, parameter configuration, sampling frequency, center frequency, and bandwidth. As the core of data scheduling for the high-performance RF front-end in the system, the embedded processing unit formats and parses these instructions according to their key names, ensuring stable and accurate instruction parsing capabilities even in the operating environment of high-end communication equipment. After parsing, the embedded processing unit converts these parameters of the task instructions into specific control signals or configuration instructions, which are then distributed to the RF direct sampling unit to begin signal sampling. This allows for precise configuration within the wideband, high dynamic range RF acquisition link, achieving precise control of signal acquisition.

[0018] The radio frequency direct sampling unit responds to instructions to perform direct sampling and data conversion of radio frequency signals, generating a baseband data stream containing real signals and noise interference.

[0019] In one embodiment, the function of the RF direct sampling unit is to perform RF signal sampling and data conversion upon receiving a task instruction signal from the embedded processing unit. During this process, the RF direct sampling unit directly samples the signal using its internal high-speed digital-to-digital converter (ADC) according to the instructions provided by the embedded processing unit, generating a digitized signal stream. This signal stream is then processed to obtain a baseband data stream with a rate that meets preset processing requirements. This baseband data stream includes the actual signal as well as noise interference from various sources, providing raw sampling data for subsequent signal processing stages.

[0020] Furthermore, the RF direct sampling unit responds to commands, performs direct sampling and data conversion of the RF signal, and generates a baseband data stream containing the real signal and noise interference, including:

[0021] The embedded processing unit sends RF parameter commands, including center frequency, bandwidth, and sampling rate, to the RF direct sampling unit via a configuration bus. The phase-locked loop and clock management circuit inside the RF direct sampling unit generate a sampling clock according to the RF parameter commands. After the RF signal passes through the analog front-end link, it is directly sampled by a high-speed ADC under the control of the sampling clock, converting the analog RF signal into a high-speed digital signal stream. The high-speed digital signal stream is processed by a digital down-conversion link, including mixing, filtering, and decimation, to generate the baseband data stream with a rate that meets the preset processing requirements.

[0022] Preferably, the embedded processing unit parses parameters including center frequency, bandwidth, and sampling rate from externally input task instructions and assembles them into RF parameter instructions. These parameters define the sampling frequency range, signal bandwidth, and signal sampling accuracy. These instructions are then transmitted to the RF direct sampling unit via a configuration bus to set key parameters for the sampling process. Upon receiving the RF parameter instructions, the phase-locked loop (PLL) and clock management circuit within the RF direct sampling unit generate a precise sampling clock according to the sampling rate requirements in the instructions. The PLL ensures the system can generate a stable sampling clock signal by synchronizing with the input signal frequency. This sampling clock signal is used to control subsequent sampling processes. The clock management circuit is responsible for adjusting the clock frequency according to system requirements to ensure that the RF signal sampling is synchronized with timing. Subsequently, the RF signal undergoes pre-processing via an analog front-end to ensure it reaches a suitable sampling frequency range. This analog front-end typically includes an RF amplifier, filters, and a mixer. The RF amplifier enhances the amplitude of the input RF signal, the filter removes unwanted frequency components, and the mixer mixes the input RF signal with the local oscillator (LO) signal, thereby converting the signal frequency to an intermediate frequency (IF) range suitable for sampling and processing. After the RF signal has been processed by the analog front-end, the high-speed analog-to-digital converter (ADC), under the control of the sampling clock, samples the RF signal. At this point, the ADC converts the analog RF signal into a digital signal, accurately capturing the amplitude and phase information of the RF signal, thus generating a high-speed digital signal stream. The generated digital signal stream is then input into a digital down-conversion link for further processing. During this process, the high-speed digital signal stream is mixed with the local oscillator signal to convert the signal frequency to a suitable processing range. The mixed signal is then filtered to remove unwanted frequency components, retaining the target signal frequency band. The sampling rate of the signal is reduced through a decimation process (e.g., downsampling) to reduce the data volume to a rate that meets processing requirements, thereby reducing the complexity of subsequent calculations. After digital down-conversion processing, a baseband data stream that meets preset processing requirements is finally generated. This baseband data stream contains the main characteristics of the signal and provides compliant input data for further signal processing.

[0023] Furthermore, the digital downconversion link includes a first-stage numerically controlled oscillator, a second-stage cascaded integrator-comb filter, and a third-stage finite-length unit impulse response filter.

[0024] Optionally, the digital down-conversion link includes a first-stage numerically controlled oscillator (CNC), a second-stage cascaded integrator-comb filter, and a third-stage finite-length unit impulse response (FIR) filter. The CNC generates a local oscillator signal, which is mixed with the received high-speed digital signal stream. That is, the mixer multiplies the local oscillator signal with the digital signal stream to generate a down-converted signal. Based on a preset target frequency (baseband or intermediate frequency), the frequency of the mixed signal will be shifted to a more suitable target frequency range for subsequent processing, typically baseband or intermediate frequency. After mixing, the signal may still contain high-frequency noise or aliasing. Therefore, the second-stage cascaded integrator-comb filter performs high-speed decimation and preliminary anti-aliasing filtering on the down-converted signal. In this process, the decimation operation reduces the signal sampling rate, decreases the data volume, and alleviates the computational burden of subsequent processing. The unique structure of the second-stage cascaded integrator-comb filter filters out unwanted high-frequency components in the spectrum, avoiding aliasing and laying the foundation for subsequent fine processing. The signal, after initial filtering and decimation, undergoes further finer filtering and rate conversion using a third-stage finite-length unit impulse response (FROM) filter. This further removes unwanted frequency components and retains the useful signal. Fine filtering, based on the predetermined filtering characteristics of the third-stage FROM filter (such as cutoff frequency and bandwidth), processes the input signal in the time domain, removing unsuitable frequency components. For example, it filters out frequencies above a certain cutoff frequency, retaining only valid signals below that frequency. Rate conversion reduces the sampling rate by a specified decimation factor. This decimation factor is the multiple by which the sampling rate is reduced. For example, a decimation factor of 2 means that only one of every two samples is retained, thus reducing the amount of data. After these three stages of processing, the final output signal is a baseband data stream that meets the preset processing requirements. This baseband data stream has a suitable sampling rate and spectral characteristics, providing a clear and interference-free input signal for subsequent digital signal processing.

[0025] By deploying auxiliary sampling ADCs at key locations on the board, broadband synchronous switching noise generated by the digital circuit is synchronously acquired, input to a pre-trained timing AI model, and outputs the interference signal generated by the broadband synchronous switching noise on the radio frequency receiving link.

[0026] In one embodiment, to effectively suppress noise interference generated by digital circuits in RF signal processing, an auxiliary sampling ADC is deployed at key locations on the board, typically near power distribution networks or high-frequency circuits, to effectively acquire interference signals such as power supply noise and clock noise generated by digital circuits. Through precise synchronous sampling, the auxiliary sampling ADC can capture broadband synchronous switching noise generated by the periodic switching of operating states by digital circuits. Subsequently, the obtained broadband synchronous switching noise is used as interference source data and transmitted to a pre-trained time-series AI model for analysis. This time-series AI model is trained based on historical data and noise-interference relationships, and can identify the interference impact of noise on the RF receiving link based on the input noise characteristics. The time-series AI model uses methods such as recurrent neural networks or long short-term memory networks to process time-series data and predict and model the impact of noise signals, thereby outputting a predicted interference signal. This interference signal reflects the degree of impact of broadband synchronous switching noise on the RF receiving link, typically including parameters such as the amplitude and phase of the interference signal, and will be used for subsequent noise suppression or cancellation processing to improve the quality of the RF signal and the anti-interference capability of RF signal processing.

[0027] Furthermore, the time-series AI model is constructed using a recurrent neural network model, including:

[0028] The control digital circuit operates in different working modes to excite synchronous switching noise with different characteristics; the noise data output by the auxiliary sampling ADC is collected synchronously, and the output of the RF direct sampling unit when there is no external RF signal input is measured as real interference feature data; a training dataset is constructed with synchronous switching noise with different characteristics as input and real interference feature data as output, and the recurrent neural network model is trained to generate the time-series AI model whose prediction accuracy of the noise-interference mapping relationship meets the preset convergence accuracy.

[0029] Preferably, to excite synchronous switching noise with different characteristics, the digital circuit is first controlled to operate in different modes. Different modes of the digital circuit, such as high frequency, low frequency, and load variations, will generate different synchronous switching noise characteristics. By adjusting the operating state of the digital circuit, different types of noise can be specifically excited and captured. The variations in amplitude, frequency, and time domain of these noises can reflect the impact of the digital circuit on the radio frequency signal under different operating conditions. After the digital circuit's operating mode changes, the broadband synchronous switching noise generated by the digital circuit is synchronously acquired by an auxiliary sampling ADC. Simultaneously, the output signal of the RF direct sampling unit when there is no external RF signal input is also recorded. At this time, the output signal of the RF direct sampling unit only contains the interference signal caused by the synchronous switching noise and is unaffected by any external RF signal. In this way, real interference characteristic data can be obtained, which will be used as the target output for training. Subsequently, the synchronous switching noise characteristic data excited in different operating modes is used as input, and the real interference characteristic data output by the RF direct sampling unit is used as output to construct a training dataset. Each pair of data samples consists of a set of synchronous switching noise characteristics and corresponding interference signal characteristics, which can fully reflect the relationship between different noise characteristics and interference signals. Next, the recurrent neural network (RNN) is trained using the constructed training dataset. The training steps include forward propagation, loss calculation, backpropagation, and parameter optimization. By learning the mapping relationship between noise feature data and interference signals, the RNN can accurately predict the impact of different types of noise on the RF receiving link. After training, the RNN is evaluated using independent validation data to determine if the accuracy of the predicted interference signal based on the mapping relationship between noise feature data and interference signals meets the preset convergence accuracy requirements of the Manufacturer. If it is greater than or equal to the required accuracy, it has converged, and the RNN is used as a time-series AI model. Conversely, if the accuracy is lower, hyperparameters such as the learning rate and the number of training batches are adjusted to further improve the prediction accuracy of the interference signal, thus providing efficient predictive support for subsequent interference signal suppression and optimization.

[0030] Furthermore, after the time-series AI model generates a noise-interference mapping relationship with a prediction accuracy that meets a preset convergence accuracy, it also includes:

[0031] Configure a calibration period, temporarily disconnect the external RF signal input during the calibration period, and collect the output of the RF direct sampling unit at this time to obtain pure noise interference; compare the pure noise interference with the interference predicted by the time-series AI model and calculate the residual; based on the residual, perform dynamic fine-tuning of the time-series AI model parameters and select and execute the cancellation gain configuration.

[0032] Optionally, a calibration period is first configured. During this period, the system temporarily disconnects the external RF signal input, ensuring that the input of the RF direct sampling unit only receives noise signals generated by the internal digital circuitry and the system itself. This ensures that the collected pure noise interference contains only noise interference and is unaffected by the RF signal, providing clean baseline data for subsequent interference analysis and model optimization. Subsequently, the collected pure noise interference is compared with the interference data predicted by the time-series AI model. The residual between the two is calculated using the mean squared error, quantifying the difference between the actual noise signal and the model's prediction. If the residual is small, it indicates high prediction accuracy and good processing performance. In this case, the model is slightly fine-tuned, for example, by adjusting some weight values ​​or parameters of specific layers to further improve its prediction accuracy. If the residual is large, it indicates that the model's prediction ability needs improvement. In this case, dynamic fine-tuning is performed, adjusting the model's training parameters, such as the learning rate, number of training epochs, or network structure, to improve model accuracy and reduce residuals. Furthermore, the residual calculation results directly affect the cancellation gain configuration. This cancellation gain refers to the method used in signal processing to eliminate interference by generating an anti-noise signal with the opposite amplitude and phase to the noise signal. Depending on the magnitude of the residual, the system adjusts the selection of the cancellation gain. If the residual is small, the current cancellation gain configuration is usually maintained, or fine-tuned to optimize noise suppression. If the residual is large, the cancellation gain is increased, i.e., the amplitude of the cancellation signal is increased, and the phase offset is adjusted to allow it to better superimpose with the interference signal, enhancing the ability to suppress interference and thus ensuring the quality of the RF signal and the overall performance of the system.

[0033] Furthermore, by deploying auxiliary sampling ADCs at key locations on the board, broadband synchronous switching noise generated by the digital circuitry is simultaneously acquired, including:

[0034] Configure a sampling clock synchronized with the RF direct sampling unit for the auxiliary sampling ADC; continuously acquire voltage fluctuation signals at key locations on the board to obtain the broadband synchronous switching noise.

[0035] Preferably, to ensure timing synchronization between the auxiliary sampling ADC and the RF direct sampling unit, the auxiliary sampling ADC is first configured with a sampling clock synchronized with the RF direct sampling unit. This ensures that the clock source of the RF direct sampling unit simultaneously drives the auxiliary sampling ADC, allowing simultaneous sampling of the RF signal and synchronous switching noise generated by the digital circuitry within the same time period, thereby eliminating any timing deviations or errors. Subsequently, voltage fluctuation signals at key locations on the board are continuously acquired, capturing high-frequency noise generated by the switching operations of the digital circuitry, thus forming broadband synchronous switching noise. These broadband synchronous switching noise signals are fed into the subsequent timing AI model for processing, providing necessary reference data for subsequent noise suppression or cancellation, ensuring the accuracy and effectiveness of RF signal processing.

[0036] Furthermore, determining the key locations of the board includes:

[0037] A digital circuit board card integrating an RF direct sampling unit, a hardware acceleration unit, an embedded processing unit, and a shared memory unit is identified. A simulation model of the power distribution network of the digital circuit board card is established. Through simulation, noise hotspots with voltage fluctuations in the power network are identified during the synchronous switching of the digital circuit. On the prototype of the digital circuit board card, a high-frequency voltage probe is used to measure the power ground plane relative to the noise in the noise hotspot area. Areas where the measured synchronous switching noise amplitude and energy meet the preset interference threshold are identified as key locations of the circuit board card.

[0038] Optionally, to effectively identify and suppress noise interference caused by synchronous switching operations in digital circuit boards, the overall design of the digital circuit board, including RF direct sampling units, hardware acceleration units, embedded processing units, and shared memory units, is first determined. These units are connected by precise circuits to form a fully functional RF signal processing device with powerful signal acquisition, processing, acceleration, and storage capabilities. After determining these core components, the power distribution network architecture parameters such as power input, power rails, buck converters, and decoupling capacitors, the power demand parameters such as voltage, current, and power of each digital circuit unit, and the noise source parameters such as clock frequency, switching frequency, and load changes generated by digital circuit operations are uniformly input into an electromagnetic simulation tool or circuit simulation software to construct a simulation model of the power distribution network of the digital circuit board. This model is used to simulate the power fluctuations and interference that may occur during the operation of the circuit board. Through simulation, the voltage fluctuations in the power network during the synchronous switching of digital circuits can be analyzed in detail. The regions with the largest voltage fluctuation amplitude, the most drastic changes, and the most concentrated energy can be captured and defined as noise hotspots, which may negatively affect the quality of RF signals. Next, a prototype of the digital circuit board was fabricated, and these noise hotspots were measured using a high-frequency voltage probe. The high-frequency voltage probe can accurately measure voltage fluctuations on the power ground plane, and is particularly effective at capturing high-frequency noise generated during synchronous switching operations of digital circuits. This measurement allows for the acquisition of real-time noise signal amplitude, frequency, and energy characteristics, further validating the accuracy of the simulation results. Then, based on the measured synchronous switching noise amplitude and energy, noise hotspots were identified. If the noise amplitude and energy of a hotspot exceeded a preset interference threshold, that hotspot was considered a critical location on the circuit board, providing a location reference for subsequent noise acquisition.

[0039] In the hardware acceleration unit, the baseband data stream is canceled based on the interference signal to generate a clean baseband data stream.

[0040] In one embodiment, after receiving the baseband data stream generated by the RF direct sampling unit, the hardware acceleration unit performs cancellation based on the amplitude and phase of the scrambling signal through two steps: numerical inversion and synchronization alignment. This cancels out the interference components in the baseband data stream, thereby reducing the impact of noise on the valid signal. After the cancellation operation is completed, the signal output by the hardware acceleration unit is the clean baseband data stream after noise cancellation. This clean baseband data stream contains almost no noise components, retains the valid information of the RF signal, and is ready for subsequent signal processing, analysis, or transmission.

[0041] Furthermore, in the hardware acceleration unit, the baseband data stream is canceled based on the interference signal to generate a clean baseband data stream, including:

[0042] Within the hardware acceleration unit, an anti-noise signal with opposite amplitude and phase is generated by numerical inversion based on the amplitude and phase of the interference signal; the anti-noise signal and the baseband data stream are synchronized and aligned in the digital domain, a signal superposition operation is performed, and the clean baseband data stream is output.

[0043] Preferably, within the hardware acceleration unit, a numerical inversion operation is first performed based on the amplitude and phase information of the received interference signal to generate an anti-noise signal with opposite amplitude and phase. This anti-noise signal reduces or eliminates the impact of interference on the baseband data stream by canceling out the noise interference components. Subsequently, to ensure that the interference components of the anti-noise signal effectively cancel out the noise interference components in the baseband data stream, the hardware acceleration unit adjusts the time delay, amplitude, and phase of the anti-noise signal to synchronize it with the digital domain of the baseband data stream. That is, they act on the noise components in the baseband data stream at the same time, ensuring accurate matching between the anti-noise signal and the interference components. Then, the anti-noise signal is superimposed on the noise interference components in the baseband data stream; that is, the anti-noise signal is added to the noise portion of the baseband data stream, causing the anti-noise signal and the noise interference signal to cancel each other out during superposition, thus effectively removing the noise components. The clean baseband data stream obtained after the superposition operation no longer contains noise interference components, providing a high-quality signal input for subsequent signal processing, analysis, or transmission, ensuring signal accuracy and reliability.

[0044] The clean baseband data stream undergoes hardware-level acceleration processing in the hardware acceleration unit, and the final processing result is written to the shared memory unit.

[0045] In one embodiment, after noise cancellation processing is performed on the clean baseband data stream, the data stream is transmitted in real time to the hardware acceleration unit via a high-speed interconnect interface. In the hardware acceleration unit, the reconfigurable logic resources of the FPGA (Field-Programmable Gate Array) are used to execute accelerated computations of various hardware-level digital signal processing algorithms, including but not limited to Fast Fourier Transform, digital filtering, signal detection and demodulation, thereby achieving real-time analysis and feature extraction of the clean baseband data stream with extremely low latency and high throughput. After the accelerated processing is complete, the processing results are written sequentially into the shared memory unit through the memory controller according to a preset data structure and address mapping rules. The shared memory unit, serving as a data exchange area between multiple modules in the system, ensures rapid transmission of processed data between different modules, thereby avoiding data transmission delays and improving the overall efficiency of the system.

[0046] Furthermore, the RF direct sampling unit and the embedded processing unit are integrated in the RFSoC; the hardware acceleration unit is implemented by an FPGA; and the shared memory unit is implemented by DDR4 synchronous dynamic random access memory.

[0047] Preferably, the RF direct sampling unit and the embedded processing unit are integrated into the RFSoC (Radio System-on-a-Chip) to achieve efficient RF signal acquisition and processing. The RF direct sampling unit is responsible for directly acquiring RF signals and converting them into digital signals. These signals are then preliminarily processed and analyzed by the embedded processing unit. The embedded processing unit not only performs routine computational tasks but also coordinates the operation and task scheduling of various modules in the system, ensuring efficient signal flow processing. By integrating the RF direct sampling unit and the embedded processing unit, the RFSoC significantly improves the system's integration and performance, reduces communication latency and power consumption between multiple hardware components in traditional architectures, and provides a more compact and efficient solution. The hardware acceleration unit is implemented by an FPGA, responsible for high-speed parallel computing to accelerate the RF signal processing. By processing multiple signal paths in parallel, the FPGA significantly improves the speed and efficiency of signal processing, especially in complex real-time signal processing, providing processing capabilities far exceeding those of traditional processors. The shared memory unit is implemented by DDR4 synchronous dynamic random access memory, used to store data generated during processing, ensuring efficient and real-time data exchange between processing units. DDR4 memory offers high-speed read and write capabilities, supporting the access of large amounts of data, and is suitable for high-speed signal processing and data storage needs. During system operation, baseband data streams, processing results, and intermediate calculation results can all be accessed through shared memory units, thereby ensuring smooth data transfer between processing units and further improving the overall system performance and real-time response capabilities.

[0048] In summary, the embodiments of this application have at least the following technical effects:

[0049] First, the embedded processing unit receives and parses external task instructions, distributing them to the RF direct sampling unit. Next, the RF direct sampling unit responds to the instructions, performing direct sampling and data conversion of the RF signal to generate a baseband data stream containing both real signal and noise interference. Then, an auxiliary sampling ADC deployed at a key location on the board synchronously acquires broadband synchronous switching noise generated by the digital circuitry, inputting it to a pre-trained timing AI model, which outputs the interference signal generated by the broadband synchronous switching noise on the RF receiving link. Then, in the hardware acceleration unit, the baseband data stream is canceled based on the interference signal to generate a clean baseband data stream. Finally, the clean baseband data stream undergoes hardware-level acceleration processing in the hardware acceleration unit, and the final processing result is written to a shared memory unit. This solves the problem of broadband synchronous switching noise generated by digital circuitry interfering with the RF receiving link, leading to a decrease in baseband data stream quality. It achieves the technical effect of improving the accuracy, reliability, and real-time performance of RF signal processing through real-time noise cancellation and hardware acceleration processing.

[0050] Example 2, based on the same inventive concept as the 6U dual-core RF signal processing method based on heterogeneous computing architecture in the foregoing examples, such as... Figure 2 As shown, this application provides a 6U dual-core radio frequency signal processing system based on a heterogeneous computing architecture. The system includes:

[0051] Instruction parsing module 11: The embedded processing unit receives and parses external task instructions, and distributes the task instructions to the RF direct sampling unit; Signal sampling and conversion module 12: The RF direct sampling unit responds to the instructions, performs direct sampling and data conversion of the RF signal, and generates a baseband data stream containing real signals and noise interference; Interference signal generation module 13: Through auxiliary sampling ADCs deployed at key locations on the board, it synchronously collects broadband synchronous switching noise generated by digital circuits, inputs it to a pre-trained timing AI model, and outputs the interference signal generated by the broadband synchronous switching noise on the RF receiving link; Data cancellation module 14: In the hardware acceleration unit, it cancels the baseband data stream based on the interference signal to generate a clean baseband data stream; Acceleration processing module 15: It performs hardware-level acceleration processing on the clean baseband data stream in the hardware acceleration unit and writes the final processing result to the shared memory unit.

[0052] Furthermore, the signal sampling and conversion module 12 is used to perform the following method:

[0053] The embedded processing unit sends RF parameter commands, including center frequency, bandwidth, and sampling rate, to the RF direct sampling unit via a configuration bus. The phase-locked loop and clock management circuit inside the RF direct sampling unit generate a sampling clock according to the RF parameter commands. After the RF signal passes through the analog front-end link, it is directly sampled by a high-speed ADC under the control of the sampling clock, converting the analog RF signal into a high-speed digital signal stream. The high-speed digital signal stream is processed by a digital down-conversion link, including mixing, filtering, and decimation, to generate the baseband data stream with a rate that meets the preset processing requirements.

[0054] Furthermore, the signal sampling and conversion module 12 is used to perform the following method:

[0055] The digital downconversion link includes a first-stage numerically controlled oscillator, a second-stage cascaded integrator-comb filter, and a third-stage finite-length unit impulse response filter.

[0056] Furthermore, the interference signal generation module 13 is used to perform the following method:

[0057] The control digital circuit operates in different working modes to excite synchronous switching noise with different characteristics; the noise data output by the auxiliary sampling ADC is collected synchronously, and the output of the RF direct sampling unit when there is no external RF signal input is measured as real interference feature data; a training dataset is constructed with synchronous switching noise with different characteristics as input and real interference feature data as output, and the recurrent neural network model is trained to generate the time-series AI model whose prediction accuracy of the noise-interference mapping relationship meets the preset convergence accuracy.

[0058] Furthermore, the interference signal generation module 13 is used to perform the following method:

[0059] Configure a sampling clock synchronized with the RF direct sampling unit for the auxiliary sampling ADC; continuously acquire voltage fluctuation signals at key locations on the board to obtain the broadband synchronous switching noise.

[0060] Furthermore, the interference signal generation module 13 is used to perform the following method:

[0061] A digital circuit board card integrating an RF direct sampling unit, a hardware acceleration unit, an embedded processing unit, and a shared memory unit is identified. A simulation model of the power distribution network of the digital circuit board card is established. Through simulation, noise hotspots with voltage fluctuations in the power network are identified during the synchronous switching of the digital circuit. On the prototype of the digital circuit board card, a high-frequency voltage probe is used to measure the power ground plane relative to the noise in the noise hotspot area. Areas where the measured synchronous switching noise amplitude and energy meet the preset interference threshold are identified as key locations of the circuit board card.

[0062] Furthermore, the interference signal generation module 13 is used to perform the following method:

[0063] Configure a calibration period, temporarily disconnect the external RF signal input during the calibration period, and collect the output of the RF direct sampling unit at this time to obtain pure noise interference; compare the pure noise interference with the interference predicted by the time-series AI model and calculate the residual; based on the residual, perform dynamic fine-tuning of the time-series AI model parameters and select and execute the cancellation gain configuration.

[0064] Furthermore, the data cancellation module 14 is used to perform the following method:

[0065] Within the hardware acceleration unit, an anti-noise signal with opposite amplitude and phase is generated by numerical inversion based on the amplitude and phase of the interference signal; the anti-noise signal and the baseband data stream are synchronized and aligned in the digital domain, a signal superposition operation is performed, and the clean baseband data stream is output.

[0066] Furthermore, including:

[0067] The radio frequency direct sampling unit and the embedded processing unit are integrated in the RFSoC; the hardware acceleration unit is implemented by an FPGA; and the shared memory unit is implemented by DDR4 synchronous dynamic random access memory.

[0068] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A 6U dual-core radio frequency signal processing method based on a heterogeneous computing architecture, characterized in that, The embedded processing unit receives and analyzes external task instructions, and distributes the task instructions to the radio frequency direct sampling unit. The radio frequency direct sampling unit responds to the instructions, performs direct sampling and data conversion of the radio frequency signal, and generates a baseband data stream containing real signals and noise interference; By deploying auxiliary sampling ADCs at key positions on the board card, the wideband synchronous switching noise generated by the digital circuit is synchronously collected and input into a pre-trained timing AI model, and the interference signal generated by the wideband synchronous switching noise to the radio frequency receiving link is output, wherein the timing AI model is constructed by using a recurrent neural network model, and the specific steps include: Controlling the digital circuit to run in different modes to excite synchronous switching noise with different characteristics; Synchronously collecting the noise data output by the auxiliary sampling ADC, and measuring the output of the radio frequency direct sampling unit at this time when there is no external radio frequency signal input as real interference characteristic data; Constructing a training data set with different characteristics of the synchronous switching noise as input and the real interference characteristic data as output, training the recurrent neural network model, and generating the timing AI model with a prediction accuracy of the noise-interference mapping relationship satisfying a preset convergence accuracy; In the hardware acceleration unit, the baseband data stream is cancelled based on the interference signal to generate a clean baseband data stream; Performing hardware-level acceleration processing on the clean baseband data stream in the hardware acceleration unit, and writing the final processing result to a shared memory unit. The radio frequency direct sampling unit and the embedded processing unit are integrated in an RFSoC; the hardware acceleration unit is implemented by an FPGA; and the shared memory unit is implemented by a DDR4 synchronous dynamic random memory.

2. The 6U dual-core radio frequency signal processing method based on heterogeneous computing architecture of claim 1, wherein, The radio frequency direct sampling unit responds to the instructions, performs direct sampling and data conversion of the radio frequency signal, and generates a baseband data stream containing real signals and noise interference, including:

3. The 6U dual-core radio frequency signal processing method based on heterogeneous computing architecture as claimed in claim 1, wherein, The embedded processing unit transmits radio frequency parameter instructions containing center frequency, bandwidth and sampling rate to the radio frequency direct sampling unit through a configuration bus; The phase-locked loop and clock management circuit inside the radio frequency direct sampling unit generates a sampling clock according to the radio frequency parameter instructions; After the radio frequency signal passes through the analog front-end link, the high-speed ADC performs direct sampling under the control of the sampling clock, and converts the analog radio frequency signal into a high-speed digital signal stream; The high-speed digital signal stream is processed through the digital down-conversion link, including mixing, filtering and decimation, to generate the baseband data stream with a rate meeting the preset processing requirements. In the hardware acceleration unit, the baseband data stream is cancelled based on the interference signal to generate a clean baseband data stream, including:

4. The 6U dual-core radio frequency signal processing method based on heterogeneous computing architecture as claimed in claim 1, wherein, In the hardware acceleration unit, an anti-noise signal with opposite amplitude and phase is generated through numerical negation operation according to the amplitude and phase of the interference signal; The anti-noise signal and the baseband data stream are synchronously aligned in the digital domain, and a signal superposition operation is performed to output the clean baseband data stream. By deploying auxiliary sampling ADCs at key positions on the board card, the wideband synchronous switching noise generated by the digital circuit is synchronously collected and input into a pre-trained timing AI model, and the interference signal generated by the wideband synchronous switching noise to the radio frequency receiving link is output, wherein the timing AI model is constructed by using a recurrent neural network model, and the specific steps include:

5. The 6U dual-core radio frequency signal processing method based on heterogeneous computing architecture as claimed in claim 1, wherein, ​ configuring a sampling clock synchronized with the radio frequency direct sampling unit for the auxiliary sampling ADC; The voltage fluctuation signal at the key position of the board card is continuously collected to obtain the wideband synchronous switch noise.

6. The 6U dual-core radio frequency signal processing method based on heterogeneous computing architecture of claim 5, wherein, The determination of the key position of the board card includes: determine a digital circuit board card integrating a radio frequency direct sampling unit, a hardware acceleration unit, an embedded processing unit, and a shared memory unit; An simulation model of a power distribution network of the digital circuit board card is established, and through simulation, it is determined that at the moment of synchronous switching of the digital circuit, there is a noise hot spot area of voltage fluctuation in the power network; On the board card prototype of the digital circuit board card, the power ground plane of the noise hot spot area is measured using a high-frequency voltage probe, and the area where the measured synchronous switching noise amplitude and energy meet the preset interference threshold is determined as the key position of the board card.

7. The heterogeneous computing architecture based 6U dual core radio frequency signal processing method as claimed in claim 1, wherein, After the prediction accuracy of the noise-interference mapping relationship of the time sequence AI model meets the preset convergence accuracy, the method further includes: configure a calibration period, temporarily disconnect the external radio frequency signal input during the calibration period, collect the output of the radio frequency direct sampling unit at this time, and obtain pure noise interference; Compare the pure noise interference with the interference predicted by the time sequence AI model to calculate the residual error; According to the residual error, perform dynamic fine tuning of the time sequence AI model parameters and selection of the cancellation gain configuration.

8. The 6U dual-core radio frequency signal processing method based on heterogeneous computing architecture as claimed in claim 3, wherein, The digital down-conversion link includes a first-stage numerically controlled oscillator, a second-stage cascaded integral comb filter, and a third-stage finite-length unit impulse response filter.

9. A 6U dual-core radio frequency signal processing system based on a heterogeneous computing architecture, characterized in that, The method for implementing the 6U dual-core radio frequency signal processing method based on the heterogeneous computing architecture according to any one of claims 1-8, comprising: An instruction analysis module: The embedded processing unit receives and analyzes external task instructions, and distributes the task instructions to the radio frequency direct sampling unit. A signal sampling and conversion module: The radio frequency direct sampling unit responds to the instructions, performs direct sampling and data conversion of the radio frequency signal, and generates a baseband data stream containing real signals and noise interference. An interference signal generation module: The auxiliary sampling ADC deployed at the key position of the board card synchronously collects the wideband synchronous switch noise generated by the digital circuit and inputs it into the pre-trained time sequence AI model to output the interference signal generated by the wideband synchronous switch noise to the radio frequency receiving link. A data cancellation module: In the hardware acceleration unit, the interference signal is used to cancel the baseband data stream to generate clean baseband data stream. An acceleration processing module: The clean baseband data stream is processed in the hardware acceleration unit, and the final processing result is written into the shared memory unit.

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