A method for manufacturing a semiconductor structure, a semiconductor structure and a memory
By forming a protective layer on the surface of the lower electrode and gradually removing it, the problems of short circuit and damage to the lower electrode caused by dry etching are solved, thus achieving effective isolation of the capacitor and improving its performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN XINRUI STORAGE TECHNOLOGY (BEIJING) CO LTD
- Filing Date
- 2025-12-03
- Publication Date
- 2026-04-17
AI Technical Summary
In 3D memory, dry etching can cause short circuits and damage to the lower electrode, leading to problems such as reduced capacitance and increased leakage current, resulting in deteriorated electrical properties.
A protective layer is formed on the surface of the lower electrode. The protective layer and part of the insulating layer are gradually removed to achieve isolation between each electrode layer. The dielectric layer and the second electrode are deposited in sequence to avoid short circuits and damage to the lower electrode caused by direct dry etching.
By gradually removing the protective layer, the integrity of the lower electrode is ensured, the performance of the capacitor is improved, short circuits and damage are avoided, and the electrical performance of the capacitor is enhanced.
Smart Images
Figure CN121262826B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor structure, a semiconductor structure, and a memory. Background Technology
[0002] With the continuous advancement of semiconductor processes and technologies, chips and electronic devices are developing towards miniaturization, high density, and high performance. Integrating chips with higher performance and more functions within a limited area has become an inevitable trend, giving rise to three-dimensional (3D) memory.
[0003] In 3D memory, dry etching is usually used to isolate the lower electrodes in capacitors. However, dry etching can cause short circuits and damage to the lower electrodes, resulting in a decrease in capacitance, an increase in leakage current, and other deterioration in electrical properties. Summary of the Invention
[0004] This disclosure provides a method for fabricating a semiconductor structure, a semiconductor structure, and a memory.
[0005] In a first aspect, embodiments of this disclosure provide a method for fabricating a semiconductor structure, the method comprising:
[0006] Provide substrate;
[0007] An initial structure is formed on the substrate, the initial structure including an insulating layer, a silicon layer, trenches, a plurality of recesses, and a first electrode; the insulating layer and the silicon layer are alternately stacked along a first direction, the trenches penetrate the insulating layer and the silicon layer along the first direction, the recesses are located on the side of the silicon layer near the trenches, and the openings of the recesses face the trenches; the first electrode covers the inner walls of the trenches and the plurality of recesses; the first direction is perpendicular to the plane containing the surface of the substrate;
[0008] A protective layer is formed on the surface of the first electrode;
[0009] Remove the protective layer located on the inner wall of the trench and the first electrode located on the inner wall of the trench;
[0010] Remove the protective layer located on the inner wall of the groove and part of the insulating layer near the groove to expose the first electrode on the surface of the groove;
[0011] On the exposed surface of the first electrode, a dielectric layer covering the first electrode and a second electrode covering the dielectric layer are sequentially formed.
[0012] In some embodiments, removing the protective layer located on the inner wall of the trench and the first electrode located on the inner wall of the trench includes:
[0013] Remove the protective layer located on the inner wall of the trench to expose the first electrode located on the inner wall of the trench;
[0014] Remove the first electrode located on the inner wall of the trench.
[0015] In some embodiments, the protective layer located on the inner wall of the groove has a dimension along the first direction smaller than the opening width of the groove.
[0016] In some embodiments, the opening width of the groove is smaller than the opening width of the trench.
[0017] In some embodiments, under the same etching conditions, the etching rates of the protective layer and the insulating layer are the same.
[0018] In some embodiments, under the same etching conditions, the etching rates of the protective layer and the first electrode are different.
[0019] In some embodiments, the material of the protective layer includes low-temperature silicon dioxide.
[0020] In some embodiments, forming the initial structure over the substrate includes:
[0021] The insulating layer and the silicon layer are alternately formed over the substrate to form a stacked structure;
[0022] The stacked structure is etched to form the trench penetrating the stacked structure along the first direction;
[0023] Based on the trench, a portion of the silicon layer near the trench is laterally etched to form a plurality of the grooves.
[0024] In some embodiments, after forming the stacked structure, the method further includes:
[0025] Forming word lines and bit lines;
[0026] The bit line extends through the insulating layer and the silicon layer along the first direction and is located on the side away from the trench; the word line extends along the second direction and is located on both sides of the silicon layer in the first direction; the second direction is perpendicular to the first direction.
[0027] In a second aspect, embodiments of this disclosure provide a semiconductor structure, including an insulating layer, a silicon layer, a trench, a plurality of recesses, a first electrode, a dielectric layer, and a second electrode;
[0028] The insulating layer and the silicon layer are stacked alternately along a first direction, the trench penetrates the insulating layer and the silicon layer along the first direction, the groove is located on the side of the silicon layer near the trench, and the opening of the groove faces the trench; the first electrode covers the inner wall of the trench and the plurality of grooves, the dielectric layer covers the first electrode, and the second electrode covers the dielectric layer.
[0029] Thirdly, embodiments of this disclosure provide a memory comprising the semiconductor structure described in the second aspect.
[0030] This disclosure provides a method for fabricating a semiconductor structure, a semiconductor structure, and a memory. The method includes: providing a substrate; forming an initial structure over the substrate, the initial structure including an insulating layer, a silicon layer, a trench, a plurality of grooves, and a first electrode; the insulating layer and the silicon layer are alternately stacked along a first direction, the trench penetrates the insulating layer and the silicon layer along the first direction, the grooves are located on the side of the silicon layer near the trench, and the openings of the grooves face the trenches; the first electrode covers the inner walls of the trenches and the plurality of grooves; the first direction is perpendicular to the plane containing the surface of the substrate; forming a protective layer on the surface of the first electrode; removing the protective layer and the first electrode located on the inner wall of the trench; removing the protective layer and part of the insulating layer near the trench on the inner wall of the groove, exposing the first electrode on the surface of the groove; and sequentially forming a dielectric layer covering the first electrode and a second electrode covering the dielectric layer on the exposed surface of the first electrode. In this way, by first forming a protective layer on the surface of the first electrode to protect it, and then removing the protective layer and the first electrode located on the inner wall of the trench, the layer separation of the first electrode is completed. Next, the protective layer on the inner wall of the groove and part of the insulating layer near the trench are removed, ensuring that the first electrode in each layer is isolated. Finally, the dielectric layer and the second electrode are deposited sequentially, completing the design of multiple capacitors connected in parallel. This disclosure, by forming a protective layer first and then gradually removing it, avoids the problems of short circuits and damage to the lower electrode caused by direct dry etching. While achieving lower electrode isolation, the integrity of the lower electrode is ensured, thus improving the performance of the capacitor. Attached Figure Description
[0031] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.
[0032] Figure 1 A schematic diagram of the composition structure of a semiconductor structure provided for related technologies. Figure 1 ;
[0033] Figure 2 A schematic diagram of the composition structure of a semiconductor structure provided for related technologies. Figure 2 ;
[0034] Figure 3 A schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure;
[0035] Figure 4 A schematic diagram of the structure obtained during the fabrication process of the semiconductor structure provided in the embodiments of this disclosure. Figure 1 ;
[0036] Figure 5 A schematic diagram of the structure obtained during the fabrication process of the semiconductor structure provided in the embodiments of this disclosure. Figure 2 ;
[0037] Figure 6 A schematic diagram of the structure obtained during the fabrication process of the semiconductor structure provided in the embodiments of this disclosure. Figure 3 ;
[0038] Figure 7 A schematic diagram of the structure obtained during the fabrication process of the semiconductor structure provided in the embodiments of this disclosure. Figure 4 ;
[0039] Figure 8 A schematic diagram of the structure obtained during the fabrication process of the semiconductor structure provided in the embodiments of this disclosure. Figure 5 ;
[0040] Figure 9 A schematic diagram of the structure obtained during the fabrication process of the semiconductor structure provided in the embodiments of this disclosure. Figure 6 ;
[0041] Figure 10 A schematic diagram of the structure obtained during the fabrication process of the semiconductor structure provided in the embodiments of this disclosure. Figure 7 ;
[0042] Figure 11 A schematic diagram of the structure obtained during the fabrication process of the semiconductor structure provided in the embodiments of this disclosure. Figure 8 ;
[0043] Figure 12 This is a schematic diagram of the composition structure of a memory provided in an embodiment of this disclosure. Detailed Implementation
[0044] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
[0045] In the following description, numerous details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.
[0046] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.
[0047] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.
[0048] The terminology used herein is intended only to describe particular embodiments and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of said features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0049] In 3D memories, such as 3D Dynamic Random Access Memory (DRAM), silicon (Si) and silicon oxide (SiO2) are typically used as active regions and isolation layers, and the two are stacked to create multilayer capacitors. According to the device design requirements, the lower plates (also called lower electrodes) of the capacitors between different layers need to be isolated, and only on this basis can the design of multiple capacitors connected in parallel be completed.
[0050] See Figure 1 It illustrates a schematic diagram of the composition of a semiconductor structure provided by related technologies. Figure 1 Specifically, it is a two-dimensional (2D) DRAM. For example... Figure 1 As shown, the semiconductor structure 10 may include a substrate 11 and a lower electrode 12 in a capacitor; specifically, Figure 1 (a) shows the structure obtained after deposition to form the lower electrode 12. Figure 1 (b) in the diagram shows the structure obtained after disconnecting the lower electrode 12.
[0051] It should be noted that the material of the lower electrode 12 can be titanium nitride (TiN).
[0052] In 2D DRAM, dry etching is typically used to separate the lower electrodes 12.
[0053] See Figure 2 It illustrates a schematic diagram of the composition of a semiconductor structure provided by related technologies. Figure 2 Specifically, it is a type of 3D DRAM. For example... Figure 2 As shown, the semiconductor structure 20 may include a substrate 21, a lower electrode 22 in a capacitor, and a sacrificial structure 23; specifically, Figure 2 (a) shows the structure obtained after deposition to form the lower electrode 22. Figure 2 (b) in the diagram shows the structure obtained after disconnecting the lower electrode 22.
[0054] It should be noted that an insulating layer 24 and a silicon layer 25 are alternately stacked on top of the substrate 21, and the sacrificial structure 23 penetrates the insulating layer 24 and the silicon layer 25 along a first direction; the first direction is perpendicular to the plane where the surface of the substrate 21 is located.
[0055] It should also be noted that the material of the lower electrode 22 can be titanium nitride; the material of the sacrificial structure 23 can be polycrystalline silicon, and the sacrificial structure 23 is subsequently used to prepare bit lines; the material of the insulating layer 24 can be an oxide, such as silicon oxide.
[0056] It should also be noted that, Figure 1 Semiconductor structure 10 and Figure 2 The remaining structures in the semiconductor structure 20 can be understood by referring to relevant technologies, and will not be elaborated here.
[0057] In 3D DRAM, dry etching is typically used to isolate the lower electrodes 22. However, the lateral etching capability of dry etching is limited, resulting in incomplete isolation of the lower electrodes between different layers (e.g., Figure 2 (as shown in the dashed box in (b)) causes a short circuit in the lower electrode; in addition, plasma sputtering during the dry etching process can damage the electrode material through the cavity between the lower electrodes, causing damage to the lower electrode (e.g. Figure 2 (as shown by the dashed circle in (b)), which leads to phenomena such as decreased capacitance and increased leakage current, resulting in deterioration of electrical properties.
[0058] Based on this, the present disclosure provides a method for fabricating a semiconductor structure, the method comprising: providing a substrate; forming an initial structure on the substrate, the initial structure including an insulating layer, a silicon layer, a trench, a plurality of grooves, and a first electrode; the insulating layer and the silicon layer are alternately stacked along a first direction, the trench penetrates the insulating layer and the silicon layer along the first direction, the groove is located on the side of the silicon layer near the trench, and the opening of the groove faces the trench; the first electrode covers the inner walls of the trench and the plurality of grooves; the first direction is perpendicular to the plane containing the surface of the substrate; forming a protective layer on the surface of the first electrode; removing the protective layer and the first electrode located on the inner wall of the trench; removing the protective layer and part of the insulating layer near the trench located on the inner wall of the groove, exposing the first electrode on the surface of the groove; and sequentially forming a dielectric layer covering the first electrode and a second electrode covering the dielectric layer on the exposed surface of the first electrode. In this way, by first forming a protective layer on the surface of the first electrode to protect it, and then removing the protective layer and the first electrode located on the inner wall of the trench, the layer separation of the first electrode is completed. Next, the protective layer on the inner wall of the groove and part of the insulating layer near the trench are removed, ensuring that the first electrode in each layer is isolated. Finally, the dielectric layer and the second electrode are deposited sequentially, completing the design of multiple capacitors connected in parallel. This disclosure, by forming a protective layer first and then gradually removing it, avoids the problems of short circuits and damage to the lower electrode caused by direct dry etching. While achieving lower electrode isolation, the integrity of the lower electrode is ensured, thus improving the performance of the capacitor.
[0059] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.
[0060] In one embodiment of this disclosure, see [link to embodiment]. Figure 3 This illustration shows a schematic flowchart of a method for fabricating a semiconductor structure according to an embodiment of this disclosure. Figure 3 As shown, the method may include:
[0061] S301: Provides a substrate.
[0062] It should be noted that this disclosure relates to the memory field, such as the DRAM field, and particularly to wafer manufacturing, utilizing 3D structured capacitors in the capacitor fabrication process.
[0063] In this embodiment, the first direction (also referred to as the Z direction) is perpendicular to the plane containing the surface of the substrate, and the second direction (also referred to as the Y direction) intersects with and is parallel to the plane containing the surface of the substrate. Specifically, the second direction and the third direction can be perpendicular to each other or intersect at other angles, without specific limitation. Exemplarily, the specific implementation of this embodiment will be described in detail with the example of the second direction and the third direction being perpendicular to each other.
[0064] Figures 4-10 This is a schematic diagram of the structure obtained during the fabrication process of the semiconductor structure provided in the embodiments of this disclosure. The following is in conjunction with... Figures 4-10 The fabrication process of the semiconductor structure provided in the embodiments of this disclosure will be described in detail. Figures 4-10 The diagrams are cross-sectional views. Specifically, (a) is the front view (i.e., the cross-sectional view of the XZ plane), (b) is the side view (i.e., the cross-sectional view of the YZ plane), and (c) is the top view (i.e., the cross-sectional view of the XY plane). Further details will not be provided later.
[0065] like Figure 4 As shown, substrate 41 can be a silicon substrate, or it can include other semiconductor elements, such as germanium (Ge), or semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb), or other semiconductor alloys, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP) or combinations thereof. This disclosure does not specifically limit the specific application of these elements.
[0066] S302: An initial structure is formed above a substrate. The initial structure includes an insulating layer, a silicon layer, a trench, a plurality of grooves, and a first electrode. The insulating layer and the silicon layer are stacked alternately along a first direction. The trench penetrates the insulating layer and the silicon layer along the first direction. The groove is located on the side of the silicon layer near the trench, and the opening of the groove faces the trench. The first electrode covers the inner walls of the trench and the plurality of grooves. The first direction is perpendicular to the plane containing the surface of the substrate.
[0067] In some embodiments, forming an initial structure over a substrate may include:
[0068] An insulating layer and a silicon layer are alternately formed on the substrate to form a stacked structure;
[0069] Etch the stacked structure to form a trench that penetrates the stacked structure along a first direction;
[0070] Based on the trenches, the silicon layer near the trenches is etched laterally to form multiple grooves.
[0071] like Figure 4 As shown, after the substrate 41 is formed, a stacked structure (not shown) is first formed on top of the substrate 41. The stacked structure may include an insulating layer 421 and a silicon layer 422 stacked along a first direction.
[0072] In this embodiment, the number of insulating layer 421 and silicon layer 422 can be set according to the required storage density (or capacitance density). The more insulating layer 421 and silicon layer 422 there are, the higher the integration and capacitance density of the formed semiconductor device. The top layer of the stacked structure can be either insulating layer 421 or silicon layer 422, without specific limitation. For example, a stacked structure including 6 insulating layers 421, 5 silicon layers 422, and an insulating layer 421 as the top layer is described in detail for the specific implementation of this embodiment. Furthermore, the thickness of insulating layer 421 and silicon layer 422 can be set according to actual needs, without specific limitation.
[0073] Here, the insulating layer 421 can be made of an oxide, such as silicon oxide; the silicon layer 422 can be made of polycrystalline silicon. The insulating layer 421 and the silicon layer 422 can be formed by any of the following deposition processes: epitaxial process, chemical vapor deposition (CVD) process, physical vapor deposition (PVD) process, atomic layer deposition (ALD) process, spin coating process, coating process, or thin film process, etc.; for example, the insulating layer 421 and the silicon layer 422 can be sequentially formed on the semiconductor substrate 41 by an epitaxial process.
[0074] like Figure 4 As shown, after obtaining the stacked structure, a trench 423 penetrating the stacked structure along a first direction can be obtained through photolithography and etching. Exemplarily, a mask layer can be formed on the surface of the stacked structure, the mask layer having a pattern required to remove a portion of the stacked structure; after forming the mask layer, a portion of the stacked structure is removed according to the pattern to form the trench 423; after forming the trench 423, the mask layer is removed.
[0075] It should be noted that etching can be used to remove parts of the stacked structure, and it can also be used to remove the mask layer. Dry etching or wet etching processes can be employed. Dry etching can use one or any combination of gases such as trifluoromethane (CHF3), carbon tetrafluoride (CF4), difluoromethane (CH2F2), hydrobromic acid (HBr), chlorine (Cl2), or sulfur hexafluoride (SF6). Wet etching can use strong acids such as concentrated sulfuric acid, hydrofluoric acid, or concentrated nitric acid.
[0076] It should also be noted that, based on the trench 423, the exposed silicon layer 422 is etched laterally, and a portion of the silicon layer 422 near the trench 423 is etched to form a plurality of grooves 424, which are located on both sides of the trench 423 along a third direction. Understandably, each silicon layer 422 has a groove 424, the opening of which faces the trench 423 along a third direction; the groove 424 is closer to the trench 423 than the bit line. Furthermore, the grooves 424 can be formed by any suitable etching process, without specific limitation. In some embodiments, after forming the stacked structure, the method may further include:
[0077] Forming word lines and bit lines;
[0078] The bit line extends through the insulating layer and the silicon layer along the first direction and is located on the side away from the trench; the word line extends along the second direction and is located on both sides of the silicon layer in the first direction; the second direction is perpendicular to the first direction.
[0079] like Figure 4 As shown, after obtaining the stacked structure, word lines (WL) 43 and bit lines (BL) 44 can be formed. It should be noted that after forming the stacked structure, there is no specific limitation on the order in which the grooves 423, recesses 424, word lines 43 and bit lines 44 are formed.
[0080] It should be noted that the order in which word lines 43 and bit lines 44 are formed and the methods for their fabrication can vary and need to be determined based on the specific circumstances. The following provides an exemplary method for fabricating word lines 43 and bit lines 44.
[0081] An active region is formed in the silicon layer 422, which can be divided into multiple doped regions with different doping types, such as N-type doping (providing free electrons) and P-type doping (providing holes). N-type doping can be done with pentavalent impurity elements such as phosphorus, antimony, and arsenic; P-type doping can be done with trivalent impurity elements such as boron, gallium, and indium. Each word line 43 passes through multiple active regions in the same silicon layer 422. The active region below the word line 43 has a different doping type than the active regions on either side of the word line 43, thus forming a transistor. The word line 43 leads out the gate of the transistor. The bit line 44 passes through multiple active regions in different silicon layers 422, thus leading out the drain or source of the transistor.
[0082] For example, a dry etching process or a wet etching process can be used to expose the silicon layer 422 in the area where word lines 43 need to be fabricated, and then the word line layer can be fabricated. The word line layer may include a gate oxide layer and a gate electrode layer. Specifically, a gate oxide layer is first deposited on the surface of the silicon layer 422, and after depositing the gate oxide layer, a gate electrode layer is deposited on the surface of the silicon layer 422 to obtain the word line 43.
[0083] For example, after forming the stacked structure, bit line trenches (not shown in the figure) can be etched first, and then bit line layers can be fabricated in the bit line trenches. The bit line layers may include bit line dielectric layers and bit line metal layers. The bit line dielectric layers and bit line metal layers are formed sequentially in the bit line trenches. Specifically, the bit line dielectric layer is first fabricated on the surface of the bit line trenches, and after fabricating the bit line dielectric layer, the bit line metal layer is fabricated on the surface of the bit line trenches to obtain bit line 44.
[0084] It should be noted that the gate oxide layer, gate electrode layer, bit line dielectric layer, and bit line metal layer can be formed by any suitable deposition process, and no specific limitation is made.
[0085] It should also be noted that after depositing the word line layer and bit line layer, chemical mechanical polishing (CMP) can be performed to make the top surface of the semiconductor structure 40 flat.
[0086] like Figure 5 As shown, the initial structure 42 (which can be represented as an Incoming Layer) includes not only an insulating layer 421, a silicon layer 422, trenches 423, and multiple recesses 424, but also a first electrode 425. After the insulating layer 421, silicon layer 422, trenches 423, and multiple recesses 424 are formed, the first electrode 425 is formed on the exposed surfaces of the trenches 423 and multiple recesses 424, i.e., on the inner walls of the trenches 423 and multiple recesses 424.
[0087] It should be noted that the initial structure 42 can also be called the front layer structure. The initial structure 42 is a structure that has completed the front-end processes such as shallow trench isolation (STI), word lines and bit lines, and has completed the deposition of the first electrode 425 in the capacitor. At this time, the first electrode 425 in each layer of capacitor has not yet been isolated.
[0088] It should be noted that the first electrode 425 refers to the lower electrode in the capacitor.
[0089] Here, the material of the first electrode 425 may include metal nitrides or metal silicides, such as titanium nitride. Furthermore, the first electrode 425 can be formed by any suitable deposition process, without specific limitation.
[0090] S303: A protective layer is formed on the surface of the first electrode.
[0091] like Figure 6 As shown, after the first electrode 425 is formed, a protective layer 45 is formed on the surface of the first electrode 425. The protective layer 45 can be formed by any suitable deposition process, and there is no specific limitation thereto.
[0092] It should be noted that the protective layer 45 can also be called the sacrificial layer. By first forming the protective layer 45 on the surface of the first electrode 425 and then gradually removing the protective layer 45, the problems of short circuit and damage to the lower electrode caused by the direct dry etching process of the isolated lower electrode in related technologies can be avoided, thus ensuring the integrity of the lower electrode.
[0093] It should also be noted that the material of the protective layer 45 is similar to that of the interlayer insulating material of the capacitor, and the material of the protective layer 45 has good chemical compatibility with the material of the first electrode 425. In this embodiment, the interlayer insulation of the capacitor is achieved through the insulating layer 421, and it is understood that the material of the protective layer 45 is similar to that of the insulating layer 421.
[0094] In some embodiments, the material of the protective layer includes low-temperature silicon dioxide.
[0095] It should be noted that low-temperature silica refers to silica deposited at temperatures far below those of traditional thermal oxidation methods. Low-temperature deposition techniques are typically performed in the range of room temperature to 450°C, such as 75°C, 200°C, and 300°C. For example, when the material of the protective layer 45 includes low-temperature silica, the protective layer 45 is formed by atomic layer deposition (75°C ALD) performed at a process temperature of 75°C.
[0096] It should also be noted that the choice of low-temperature silicon dioxide as the material for the protective layer 45 can avoid the problem of high-temperature damage to the metal during the preparation of normal silicon dioxide, such as the oxidation of the first electrode 425.
[0097] In this embodiment, the material of the protective layer 45 includes, but is not limited to, low-temperature silicon dioxide and other oxides, and is not specifically limited thereto.
[0098] In some embodiments, such as Figure 6 As shown, the protective layer 45 located on the inner wall of the groove 424 has a dimension in the first direction that is smaller than the opening width of the groove 424.
[0099] It should be noted that the opening width of the groove 424 refers to the dimension of the opening of the groove 424 along the first direction. In other words, the protective layer 45 does not need to completely fill the inner wall of the groove 424 (i.e., the cavity of the capacitor). After filling, gaps need to be left to prevent etching gases or reagents from entering. In addition, the thickness of the protective layer 45 can be determined according to the actual situation to ensure that the gaps are not too large and to guarantee the subsequent etching effect.
[0100] S304: Remove the protective layer located on the inner wall of the trench and the first electrode located on the inner wall of the trench.
[0101] like Figure 7 and Figure 8 As shown, after the protective layer 45 is formed, the protective layer 45 on the inner wall of the trench 423 and the first electrode 425 on the inner wall of the trench 423 are removed sequentially. Specifically, the first electrode 425 on the inner wall of the trench 423 refers to the first electrode 425 located under the protective layer 45 on the inner wall of the trench 423. At this time, if the gap in the groove 424 after the protective layer 45 is deposited is too large, etching gas or reagents will enter the gap, causing the protective layer 45 on the inner wall of the groove 424 to also be removed. In this embodiment, by controlling the parameters for forming the protective layer 45, the protective layer 45 on the inner wall of the trench 423 is removed first, and the process of removing the protective layer 45 on the inner wall of the trench 423 does not affect the protective layer 45 on the inner wall of the groove 424, and does not affect the protective effect of the protective layer 45 on the first electrode 425.
[0102] In some embodiments, the opening width of the groove 424 is smaller than the opening width of the trench 423.
[0103] It should be noted that the opening width of the groove 423 refers to the dimension of the opening of the groove 423 along a third direction.
[0104] In this embodiment, the opening width of the groove 424 is smaller than that of the trench 423, which makes it difficult for etching gas or reagents to enter the groove 424. This avoids damaging the protective layer 45 on the inner wall of the groove 424 during the removal of the protective layer 45 on the inner wall of the trench 423, thus avoiding affecting the protective effect of the protective layer 45 on the first electrode 425.
[0105] It should be noted that the protective layer 45 on the surface of the first electrode 425 is partially removed by dry etching or wet etching process, exposing part of the first electrode 425, and then the exposed first electrode 425 is removed.
[0106] In some embodiments, removing the protective layer located on the inner wall of the trench and the first electrode located on the inner wall of the trench may include:
[0107] Remove the protective layer on the inner wall of the trench to expose the first electrode on the inner wall of the trench;
[0108] Remove the first electrode located on the inner wall of the trench.
[0109] like Figure 7As shown, after the protective layer 45 is formed, it is first partially removed to expose part of the first electrode 425. Specifically, the protective layer 45 on the inner wall of the trench 423 is removed, exposing the first electrode 425 on the inner wall of the trench 423. Alternatively, the protective layer 45 on the inner wall of the trench 423 can be removed by any suitable etching process, and the partial removal of the protective layer 45 can be achieved by controlling the etching parameters; no specific limitation is made in this regard.
[0110] It should be noted that after the partial etching of the protective layer 45 is completed, part of the first electrode 425 should be exposed, while most of the first electrode 425 is covered by the protective layer 45. Specifically, only the protective layer 45 on the inner wall of the trench 423 is removed, but the protective layer 45 on the inner wall of the groove 424 is not removed. The first electrode 425 on the inner wall of the groove 424 is still covered by the protective layer 45.
[0111] It should also be noted that when removing the protective layer 45 on the inner wall of the trench 423, the protective layer 45 on the upper surface of the semiconductor structure 40 can be removed at the same time.
[0112] like Figure 8 As shown, after exposing the first electrode 425 located on the inner wall of the trench 423, the exposed first electrode 425 is removed, that is, the first electrode 425 located on the inner wall of the trench 423 is removed, thereby completing the interlayer separation of the first electrode 425, that is, the first electrode 425 connected to the interlayer is completely removed. Alternatively, the first electrode 425 located on the inner wall of the trench 423 can be removed by any suitable etching process, and there is no specific limitation thereto.
[0113] In some embodiments, under the same etching conditions, the etching rates of the protective layer 45 and the first electrode 425 are different.
[0114] It should be noted that the same etching conditions refer to the same equipment, process conditions, time, etc. In other words, apart from the material being etched, all other conditions are exactly the same.
[0115] In this embodiment, the different etching rates of the protective layer 45 and the first electrode 425 allow for selective etching of either the protective layer 45 or the first electrode 425 according to the actual situation, thereby achieving precise etching.
[0116] In some embodiments, under the same etching conditions, the etching rate of the protective layer 45 is less than the etching rate of the first electrode 425.
[0117] In some embodiments, under the same etching conditions, the etching selectivity ratio of the protective layer 45 and the first electrode 425 is greater than 1.
[0118] It should be noted that when the material of the protective layer 45 includes low-temperature silicon dioxide and the material of the first electrode 425 includes titanium nitride, the etching selectivity ratio between the two can be greater than 1 and can reach several hundred. The specific value depends on the actual process selected, and no specific limitation is made. With a high etching selectivity between the protective layer 45 and the first electrode 425, during the etching process of the first electrode 425 located on the inner wall of the trench 423, only the exposed portion of the first electrode 425 will be etched.
[0119] S305: Remove the protective layer on the inner wall of the groove and part of the insulating layer near the groove to expose the first electrode on the surface of the groove.
[0120] like Figure 9 As shown, after removing the protective layer 45 on the inner wall of the trench 423 and the first electrode 425 on the inner wall of the trench 423, the protective layer 45 on the inner wall of the groove 424 and part of the insulating layer 421 near the trench 423 are simultaneously removed, exposing the first electrode 425 on the surface of the groove 424. Specifically, the inner sidewall and at least part of the outer sidewall of the first electrode 425 are exposed. Understandably, during the etching process of the protective layer 45 on the inner wall of the groove 424, the protective layer 45 and part of the interlayer insulating material (i.e., the insulating layer 421) of the capacitor are removed simultaneously, thereby isolating the first electrode 425 in each capacitor layer.
[0121] It should be noted that the materials of the protective layer 45 and the insulating layer 421 are similar, so the protective layer 45 on the inner wall of the groove 424 and part of the insulating layer 421 near the trench 423 can be completely removed by a one-step dry etching or wet etching process. Alternatively, any suitable etching process can be used to remove the protective layer 45 on the inner wall of the groove 424 and part of the insulating layer 421 near the trench 423; no specific limitation is made in this regard.
[0122] In this embodiment, removing both the protective layer 45 and the insulating layer 421 simultaneously reduces process steps and improves efficiency. Furthermore, removing a portion of the insulating layer 421 near the trench 423 exposes part of the sidewall of the first electrode 425, thereby increasing the capacitor's area and improving its performance.
[0123] In some embodiments, under the same etching conditions, the etching rates of the protective layer 45 and the insulating layer 421 are the same.
[0124] It should be noted that the "same etching rate" mentioned in this embodiment means that the etching rate is within a preset accuracy range, that is, the etching rates of the protective layer 45 and the insulating layer 421 are completely equal or similar, so that the protective layer 45 and the insulating layer 421 can be removed at the same time.
[0125] In some embodiments, under the same etching conditions, the etching selectivity ratio of the protective layer 45 and the insulating layer 421 is equal to 1.
[0126] It should be noted that the "etch selectivity ratio equal to 1" mentioned in this embodiment means that the etch selectivity ratio is within a preset accuracy range, that is, the etch selectivity ratio of the protective layer 45 and the insulating layer 421 is equal to or close to 1, so that the protective layer 45 and the insulating layer 421 can be removed at the same time.
[0127] S306: On the surface of the first electrode exposed, a dielectric layer covering the first electrode and a second electrode covering the dielectric layer are sequentially formed.
[0128] like Figure 10 As shown, after the first electrode 425 exposes the surface of the groove 424, a dielectric layer 46 and a second electrode 47 are sequentially formed on the exposed surface of the first electrode 425, i.e. on the sidewall inside the first electrode 425 and at least part of the sidewall outside the first electrode 425.
[0129] It should be noted that the second electrode 47 refers to the upper electrode in the capacitor.
[0130] It should also be noted that the material of the dielectric layer 46 can be a high-dielectric material (High-K), wherein any material with a dielectric constant greater than that of silicon dioxide (3.9) can be called a high-dielectric material. Examples include one or any combination of lanthanum oxide (La₂O₃), aluminum oxide (Al₂O₃), hafnium oxide (HfO₂), hafnium oxynitride (HfON), hafnium silicate (HfSiOx), or zirconium oxide (ZrO₂). The material of the second electrode 47 can include metal nitrides or metal silicides, such as titanium nitride. Figure 10 In the text, the first electrode 425 and the second electrode 47 are represented by the same filler.
[0131] In addition, the dielectric layer 46 and the second electrode 47 can be formed by any suitable deposition process, without any specific limitation.
[0132] In this embodiment, after the deposition of the dielectric layer 46 and the second electrode 47 is completed on the surface exposed by the first electrode 425, a capacitor in a 3D DRAM is obtained.
[0133] See Figure 11 It illustrates a schematic diagram of the structure obtained during the fabrication process of a semiconductor structure provided in this disclosure embodiment. Figure 8 Specifically, the main view. For example... Figure 11 As shown, Figure 11 (a) is a schematic diagram of the structure obtained after forming grooves 423 and multiple recesses 424 in the initial structure 42. Figure 11(b) is a schematic diagram of the structure obtained after forming the first electrode 425 on the exposed surfaces of the trench 423 and the plurality of grooves 424. Figure 11 (c) is a schematic diagram of the structure obtained after the protective layer 45 is formed on the surface of the first electrode 425. Figure 11 (d) in the diagram is a schematic diagram of the structure obtained after removing the protective layer 45 located on the inner wall of the trench 423. Figure 11 (e) in the diagram is a schematic diagram of the structure obtained after removing the first electrode 425 located on the inner wall of the trench 423. Figure 11 (f) is a schematic diagram of the structure obtained after simultaneously removing the protective layer 45 on the inner wall of the groove 424 and part of the insulating layer 421 near the trench 423.
[0134] It should be noted that, Figure 11 Word line 43 and bit line 44 are not shown in the figure, and the sacrificial structure 48 is subsequently used to prepare bit line 44.
[0135] It should also be noted that, in Figures 4 to 11 In the semiconductor structure 40, the surface and interior are also filled with other dielectric materials. Please refer to the relevant technologies for understanding, and we will not go into details here.
[0136] This disclosure provides a method for fabricating a semiconductor structure 40, specifically a method for isolating a first electrode 425 in a capacitor. The method involves growing a sacrificial material (i.e., a protective layer 45) on the first electrode 425 to protect it. Specifically, firstly, a material similar to the interlayer barrier material (i.e., insulating layer 421) of the capacitor, such as low-temperature silicon dioxide, is grown on the first electrode 425. The protective layer 45 does not need to completely fill the capacitor cavity; after filling, gaps are left to prevent the entry of etching gases or reagents. The sacrificial material on the first electrode 425 is partially removed by wet or dry etching, exposing part of the first electrode 425. The exposed first electrode 425 is then removed by wet or dry etching. Since the sacrificial material and the interlayer barrier material are similar, the complete removal of the sacrificial material and the interlayer barrier material (i.e., the protective layer 45 located on the inner wall of the trench 424 and part of the insulating layer 421 near the trench 423) can be achieved through a single wet or dry etching step.
[0137] It should be noted that in related technologies, the structure before etching the lower electrode 22 is as follows: Figure 2 As shown in (a) above, the structure after etching the lower electrode 22 is as follows: Figure 2 As shown in (b), etching the lower electrode 22 causes a short circuit and damage to the lower electrode; in this disclosure, the structure before etching the first electrode 425 is as follows Figure 11 As shown in (b) above, the structure after etching the first electrode 425 is as follows: Figure 11As shown in (e) and (f) in the figure. This disclosure solves the problem of adverse effects caused by the uniformity of the bottom electrode isolation process in 3D DRAM, such as bottom electrode short circuit and bottom electrode damage. It achieves the isolation of the bottom electrode in the capacitor between different layers, and can avoid the incomplete isolation of the bottom electrode caused by direct dry etching. Furthermore, by growing a protective layer 45 on the bottom electrode, it can avoid the damage to the bottom electrode caused by direct dry etching.
[0138] In another embodiment of this disclosure, such as Figure 10 As shown, the semiconductor structure 40 may include an insulating layer 421, a silicon layer 422, a trench 423, a plurality of recesses 424, a first electrode 425, a dielectric layer 46, and a second electrode 47.
[0139] In this configuration, insulating layer 421 and silicon layer 422 are stacked alternately along a first direction, trench 423 penetrates insulating layer 421 and silicon layer 422 along the first direction, groove 424 is located on the side of silicon layer 422 near trench 423, and the opening of groove 424 faces trench 423; first electrode 425 covers the inner wall of trench 423 and multiple grooves 424, dielectric layer 46 covers first electrode 425, and second electrode 47 covers dielectric layer 46.
[0140] In some embodiments, such as Figure 10 As shown, the semiconductor structure 40 may also include word lines 43 and bit lines 44;
[0141] The bit line 44 extends through the insulating layer 421 and the silicon layer 422 along the first direction and is located on the side away from the trench 423; the word line 43 extends along the second direction and is located on both sides of the silicon layer 422 in the first direction.
[0142] This disclosure provides a semiconductor structure 40, including a capacitor for 3D DRAM. During the fabrication of the semiconductor structure 40, isolation of the first electrode 425 of the capacitor between different layers is achieved, and the integrity of the first electrode 425 is guaranteed.
[0143] In another embodiment of this disclosure, see [reference needed]. Figure 12 This illustration shows a schematic diagram of the composition structure of a memory provided in an embodiment of this disclosure. For example... Figure 12 As shown, the memory 50 may include the aforementioned semiconductor structure 40.
[0144] It should be noted that the memory 50 can be such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate SDRAM (DDRSDRAM), etc., and no specific limitation is made here.
[0145] Furthermore, in some embodiments, the memory 50 may include a DRAM chip. The DRAM chip may conform to memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, and DDR6, as well as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, and LPDDR6; no specific limitation is made here.
[0146] For details not disclosed in the embodiments of this disclosure, please refer to the description of the foregoing embodiments for understanding.
[0147] In the several embodiments provided in this disclosure, it should be understood that the disclosed structures and methods can be implemented in a non-target manner. The structural embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the various components shown or discussed are coupled to each other or directly coupled.
[0148] The features disclosed in the several method or structural embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or structural embodiments.
[0149] The above are merely some embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.
Claims
1. A method of fabricating a semiconductor structure, characterized by, The method includes: Provide substrate; An initial structure is formed on the substrate, the initial structure including an insulating layer, a silicon layer, trenches, a plurality of recesses, and a first electrode; the insulating layer and the silicon layer are alternately stacked along a first direction, the trenches penetrate the insulating layer and the silicon layer along the first direction, the recesses are located on the side of the silicon layer near the trenches, and the openings of the recesses face the trenches; the first electrode covers the inner walls of the trenches and the plurality of recesses; the first direction is perpendicular to the plane containing the surface of the substrate; A protective layer is formed on the surface of the first electrode; Remove the protective layer located on the inner wall of the trench and the first electrode located on the inner wall of the trench; Remove the protective layer on the inner wall of the groove and part of the insulating layer near the groove to expose the first electrode on the surface of the groove, wherein the inner sidewall and at least part of the outer sidewall of the first electrode are exposed. On the exposed surface of the first electrode, a dielectric layer covering the first electrode and a second electrode covering the dielectric layer are sequentially formed. Under the same etching conditions, the protective layer and the first electrode have a high etching selectivity.
2. The method of claim 1, wherein, The removal of the protective layer located on the inner wall of the trench and the first electrode located on the inner wall of the trench includes: Remove the protective layer located on the inner wall of the trench to expose the first electrode located on the inner wall of the trench; Remove the first electrode located on the inner wall of the trench.
3. The method of claim 1, wherein, The protective layer located on the inner wall of the groove has a dimension along the first direction smaller than the opening width of the groove.
4. The method of claim 1, wherein, The opening width of the groove is smaller than the opening width of the trench.
5. The method of claim 1, wherein, Under the same etching conditions, the etching rates of the protective layer and the insulating layer are the same.
6. The method of claim 1, wherein, The material of the protective layer includes low-temperature silicon dioxide.
7. The method of claim 1, wherein, The formation of the initial structure over the substrate includes: The insulating layer and the silicon layer are alternately formed over the substrate to form a stacked structure; The stacked structure is etched to form the trench penetrating the stacked structure along the first direction; Based on the trench, a portion of the silicon layer near the trench is laterally etched to form a plurality of the grooves.
8. The method of claim 7, wherein, After forming the stacked structure, the method further includes: Forming word lines and bit lines; The bit line extends through the insulating layer and the silicon layer along the first direction and is located on the side away from the trench; the word line extends along the second direction and is located on both sides of the silicon layer in the first direction; the second direction is perpendicular to the first direction.
9. A semiconductor structure, characterized by The semiconductor structure is prepared by the semiconductor structure preparation method according to any one of claims 1 to 8, and the semiconductor structure includes an insulating layer, a silicon layer, a trench, a plurality of grooves, a first electrode, a dielectric layer and a second electrode. The insulating layer and the silicon layer are stacked alternately along a first direction, the trench penetrates the insulating layer and the silicon layer along the first direction, the groove is located on the side of the silicon layer near the trench, and the opening of the groove faces the trench; the first electrode covers the inner wall of the plurality of grooves, the dielectric layer covers the first electrode, and the second electrode covers the dielectric layer.
10. A memory, comprising: The memory includes the semiconductor structure as described in claim 9.
Citation Information
Patent Citations
Semiconductor device and preparation method thereof, and electronic equipment
CN118317601A
Semiconductor device and preparation method thereof
CN119697991A