A device for weak bioelectric signal acquisition

Abstract

This disclosure relates to a device for acquiring weak bioelectrical signals, comprising: an amplification circuit configured to amplify an initial signal; and an analog-to-digital converter (ADC) circuit connected to the output of the amplification circuit and configured to convert the amplified initial signal into a digital signal, wherein the ADC circuit includes a continuous-mode Δ-Σ ADC, and the continuous-mode Δ-Σ ADC includes a fully differential passive adder.

Description

Technical Field

[0001] This disclosure relates to the field of electronic circuit technology, and more specifically, to a device for acquiring weak bioelectrical signals. Background Technology

[0002] Electroencephalogram (EEG) signals are frequently used in research in psychology, criminal investigation, and clinical medicine. Subtle changes in EEG signals can be used to observe emotional fluctuations and can also aid in the diagnosis and treatment of certain brain diseases. To collect EEG signals, numerous electrodes are typically placed directly on the scalp or surface cortex; this is a non-invasive method. The amplitude of EEG signals usually ranges from 1 to 50 μV, and the frequency distribution ranges from 0.5 to 100 Hz.

[0003] Electrocorticography (ECOG) is a method of measuring signals by placing electrodes invasively into the cerebral cortex. The signal amplitude typically ranges from 1 to 500 μV, distributed across frequencies below 500 Hz, such as 1 to 200 Hz. Compared to electroencephalography (EEG), ECOG offers higher spatial resolution. Furthermore, compared to fully implantable systems for detecting neuronal firing activity, ECOG signal monitoring causes less damage to neural tissue and exhibits better long-term stability, making it a promising technology for clinical rehabilitation.

[0004] Both of the above-mentioned bioelectric signals are characterized by low frequency and weak amplitude. Therefore, it is necessary to design a high-performance signal acquisition device to acquire EEG and ECOG signals. Summary of the Invention

[0005] To address the technical problem of acquiring weak bioelectrical signals, this disclosure provides a device for acquiring weak bioelectrical signals, comprising:

[0006] An amplifier circuit, configured to amplify an initial signal; and,

[0007] An analog-to-digital converter (ADC) circuit is connected to the output of the amplifier circuit and configured to convert an amplified initial signal into a digital signal. The ADC circuit includes a continuous-mode Δ-Σ ADC, which includes a fully differential passive adder. The amplified initial signal from the amplifier circuit is directly provided to the fully differential passive adder.

[0008] In some embodiments, the continuous Δ-Σ analog-to-digital converter further includes a plurality of cascaded integrators, quantizers, and digital-to-analog converters, wherein:

[0009] The fully differential passive adder is connected between each of the cascaded integrators and the quantizer, and the fully differential passive adder is configured to perform a weighted summation of the input signal of the continuous Δ-Σ analog-to-digital converter and the multiple output signals of the cascaded integrators to produce a summed signal.

[0010] The quantizer is configured to generate a digital signal based on the summed signal; and

[0011] The digital-to-analog converter is connected between the quantizer and the first-stage integrator in the cascaded plurality of integrators, and the digital-to-analog converter is configured to generate an analog signal based on the digital signal and feed the analog signal back to the first-stage integrator.

[0012] In some embodiments, the cascaded integrators consist of a first integrator and a second integrator.

[0013] In some embodiments, the fully differential passive adder includes:

[0014] Multiple pairs of differential signal branches, each pair of differential signal branches is configured to receive a pair of differential signals. Each differential signal branch in each pair of differential signal branches includes a first switch, a second switch and a first capacitor. The first terminal of the first switch is configured to receive one of the differential signals in the corresponding pair of differential signals, the first terminal of the second switch is configured to receive a common signal, and the second terminals of the first switch, the second terminal of the second switch and the first terminal of the first capacitor are connected to each other.

[0015] A pair of differential summation paths, which are connected to the plurality of differential signal branches and configured to perform weighted summation on the plurality of differential signals.

[0016] In some embodiments, the amplification circuit includes:

[0017] A chopper modulator configured to convert the initial signal into a modulated signal at a higher frequency band;

[0018] An amplifier connected to the output of the chopper modulator and configured to amplify the modulated signal;

[0019] A chopper demodulator, connected to the output of the amplifier, configured to convert the amplified modulation signal into a demodulated signal in the same frequency band as the initial signal and to convert noise to a higher frequency band; and,

[0020] A low-pass filter is connected to the output of the chopper demodulator and is configured to allow at least a portion of the demodulated signal to pass through and filter out noise at higher frequencies to generate the amplified initial signal.

[0021] In some embodiments, the amplifier includes a resistive programmable gain amplifier or a capacitive programmable gain amplifier.

[0022] In some embodiments, the low-pass filter includes a first-order RC low-pass filter.

[0023] In some embodiments, the initial signal is a differential signal.

[0024] In some embodiments, the device is configured to acquire at least one of electroencephalogram (EEG) signals and cortical electroencephalogram (EEG).

[0025] In the device for acquiring weak bioelectrical signals disclosed herein, the fully differential passive adder can control the opening and closing of switches based on a non-overlapping clock, and scale the signals of the integrator output and feedforward input using the proportional relationship of capacitance values. This capacitor-switched adder improves the accuracy of circuit summation and maintains the high stability of the device. Compared with active adders, the fully differential passive adder used in the embodiments of this disclosure can effectively reduce the power consumption and area of ​​the chip and simplify the circuit structure. Moreover, the fully differential passive adder of this disclosure can use capacitance ratio for summation, which is more beneficial to reducing the impact of device mismatch during manufacturing than resistance ratio, and avoids the signal-to-noise ratio reduction caused by thermal noise generated by resistors. Furthermore, the fully differential passive adder of the embodiments of this disclosure can modulate one end of the capacitor to the Vcm common-mode point within half a clock cycle, avoiding the error caused by the inconsistency of the common-mode point of the feedforward branch output signal to the summation result of the adder. In addition, this adder structure is perfectly matched with the quantizer controlled by the back-end clock, and the clocks of the two can be controlled separately using non-overlapping clocks. Furthermore, in some embodiments, a chopper amplifier combined with a feedforward continuous-mode Δ-Σ analog-to-digital converter (ADC) can be used to acquire the signal, achieving low power consumption and low noise. The input reference noise can be below 1 μVrms, and the effective number of bits (ENOB) can be above 15 bits. Additionally, in the signal chain circuit architecture design, a low-pass filter can eliminate high-frequency noise after chopping, also functioning as an anti-aliasing filter. Moreover, the Δ-Σ ADC has a feedforward branch that directly superimposes the input signal onto the adder before finally entering the quantizer. Thus, the filter is multiplexed while simultaneously providing anti-aliasing performance.

[0026] Other features and advantages of this disclosure will become clearer from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0027] The accompanying drawings, which form part of this specification, illustrate embodiments of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0028] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, wherein:

[0029] Figure 1 A schematic diagram of a device for acquiring weak bioelectrical signals according to some embodiments of the present disclosure is shown;

[0030] Figure 2 The amplitude-frequency characteristics of an amplifier at different gains in a device for acquiring weak bioelectrical signals according to some embodiments of the present disclosure are shown.

[0031] Figure 3 A simulation diagram of the input reference noise of an amplifier in a device for acquiring weak bioelectrical signals according to some embodiments of the present disclosure is shown;

[0032] Figure 4 A schematic diagram of the modulator of a continuous Δ-Σ analog-to-digital converter in a device for weak bioelectrical signal acquisition according to some embodiments of the present disclosure is shown;

[0033] Figure 5 It shows Figure 4 A linear model of a continuous Δ-Σ analog-to-digital converter;

[0034] Figure 6 A schematic diagram of the structure of a fully differential passive adder in a continuous Δ-Σ analog-to-digital converter for weak bioelectrical signal acquisition according to some embodiments of the present disclosure is shown.

[0035] Figure 7 The power spectral density plot of the fast Fourier transform of the output signal of a continuous Δ-Σ analog-to-digital converter of a device for acquiring weak bioelectrical signals according to some embodiments of the present disclosure is shown.

[0036] Note that in the embodiments described below, the same reference numerals are sometimes used across different figures to denote the same parts or parts having the same function, and repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to denote similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0037] For ease of understanding, the positions, dimensions, and extents of the structures shown in the accompanying drawings and other materials may not represent actual positions, dimensions, and extents. Therefore, the disclosed invention is not limited to the positions, dimensions, and extents disclosed in the accompanying drawings and other materials. Furthermore, the drawings are not necessarily drawn to scale, and some features may be enlarged to show details of specific components. Detailed Implementation

[0038] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.

[0039] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use. Those skilled in the art will understand that they merely illustrate exemplary ways that can be used to implement this disclosure, and are not exhaustive.

[0040] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0041] To acquire low-frequency signals with weak amplitudes, a low-noise amplifier circuit can be designed to amplify the signal amplitude, and then combined with an analog-to-digital converter circuit to achieve signal acquisition. However, in order to achieve low input-referred noise (IRN), high dynamic range, and excellent anti-interference capability, current signal acquisition equipment occupies a large chip area and has high power consumption (e.g., about 5mW / single channel).

[0042] To address at least one of the aforementioned problems, this disclosure proposes a device for acquiring weak bioelectrical signals, which can be configured to acquire at least one of electroencephalogram (EEG) signals and electrocorticography (ECG). The EEG signal bandwidth is typically in the range of 0.5–100 Hz, and the signal amplitude is in the range of 1–50 μV; while the ECG signal bandwidth is typically in the range of 1–200 Hz, and the signal amplitude is in the range of 1–500 μV. It is understood that the device of this disclosure can also be used to acquire other types of weak low-frequency electrical signals, and this is not a limitation. Furthermore, in some embodiments, to achieve better anti-interference performance, lower electromagnetic radiation, and lower power consumption, the initial signal acquired by the device of this disclosure can be a differential signal, i.e., represented by a pair of signals with equal amplitude and opposite phase. Accordingly, the device of this disclosure may include circuits designed according to the characteristics of differential signals, which may include a pair of symmetrical or substantially symmetrical circuit paths, each of which can process one of the corresponding differential signals in the pair.

[0043] In some embodiments of this disclosure, such as Figure 1As shown, a device for acquiring weak bioelectrical signals may include an amplifier circuit 100 and an analog-to-digital converter circuit 200 connected to the output of the amplifier circuit 100. The amplifier circuit 100 may be configured to amplify an initial signal (e.g., a pair of differential signals VIP and VIN), and the analog-to-digital converter circuit 200 may be configured to convert the amplified initial signal into a digital signal Dout for further processing.

[0044] Specifically, in some embodiments, such as Figure 1 As shown, the amplifier circuit 100 may include a chopper modulator 110, an amplifier 120 connected to the output of the chopper modulator 110, a chopper demodulator 130 connected to the output of the amplifier 120, and a low-pass filter 140 connected to the output of the chopper demodulator 130. The amplifier 120 may be configured to amplify a signal (e.g., a modulated signal from the chopper modulator 110), i.e., amplify the amplitude of the signal. In some embodiments, the amplifier 120 may include a programmable gain amplifier (PGA), such as a resistive PGA or a capacitive PGA. A resistive PGA can have a higher input impedance than a capacitive PGA, but a capacitive PGA can better suppress external common-mode interference; the appropriate amplifier 120 can be selected as needed. Figure 2 This paper illustrates the amplitude-frequency characteristics of a programmable gain amplifier at different gains. Figure 2 In the figure, the curves from top to bottom show the amplitude-frequency characteristics of the programmable gain amplifier at gains of 33.47dB, 30.21dB, 27.87dB, 22.26dB and 9.54dB, respectively.

[0045] It is understandable that some noise may be introduced during the amplification process of amplifier 120, including flicker noise (1 / f noise) and DC offset. To suppress the above noise, in some embodiments, a chopper modulator 110, a chopper demodulator 130, and a low-pass filter 140 can be provided in the amplifier circuit 100. The chopper modulator 110 can be configured to convert the initial signal (e.g., a directly acquired EEG signal or ECOG signal) into a modulated signal at a higher frequency. The chopper demodulator 130 can be configured to convert the amplified modulated signal from amplifier 120 into a demodulated signal at the same frequency band as the initial signal and convert the noise to a higher frequency band. That is, because the valid initial signal is chopped twice by the chopper modulator 110 and the chopper demodulator 130, it is restored to its original frequency band, while noise, including flicker noise and DC offset, is only chopped once by the chopper demodulator 130 and thus converted to a higher frequency band. In this way, effective frequency separation between the initial signal and noise is achieved through the chopper modulator 110 and the chopper demodulator 130. In addition, the use of the chopper modulator 110 and the chopper demodulator 130 can also improve the common-mode rejection ratio of the front-end circuit (including the amplifier circuit 100) to a certain extent, thereby improving the signal quality. Figure 3 A simulation diagram of the input reference noise of an amplifier is shown, illustrating how noise is shifted to a higher frequency band when chopping is enabled. Then, a low-pass filter 140 can be configured to allow at least a portion of the demodulated signal to pass through and filter out noise at higher frequencies to generate an amplified initial signal, thus extracting and amplifying a valid initial signal (e.g., an EEG or ECOG signal) from complex interference sources. In some embodiments, such as... Figure 1 As shown, the low-pass filter 140 may include a first-order RC low-pass filter, which includes a resistor R and a capacitor C. It is understood that in some other embodiments, other forms of low-pass filters may be selected depending on the characteristics of the initial signal and noise, and this is not a limitation.

[0046] Furthermore, such as Figure 1As shown, an analog-to-digital converter (ADC) 200 can be connected to the output of the amplifier circuit 100. In some embodiments, the ADC 200 may include a continuous-mode Δ-Σ analog-to-digital converter (ADC). Compared to a discrete-mode Δ-Σ ADC, the continuous-mode Δ-Σ ADC has two significant advantages: firstly, the inherent anti-aliasing characteristics of the loop filter; and secondly, when using the same signal-to-noise-and-distortion ratio (SNDR) design specifications, the chip area of ​​the continuous-mode Δ-Σ ADC is more advantageous than that of the discrete-mode Δ-Σ ADC.

[0047] In some embodiments, a continuous Δ-Σ analog-to-digital converter may include a cascade of integrators with feed-forward (CIFF) modulator. For example... Figure 4 As shown, the modulator may include a plurality of integrators 211 cascaded together (forming an integrator group 210), a fully differential passive adder 220, a quantizer 230, and a digital-to-analog converter (DAC) 240. The fully differential passive adder 220 may be connected between each of the cascaded integrators 211 and the quantizer 230, and may be configured to perform a weighted summation of the input signal of the continuous Δ-Σ analog-to-digital converter and the multiple output signals of the cascaded integrators 211 to produce a summed signal. In some embodiments, the amplified initial signal from the amplifier circuit 100 (e.g., a pair of differential signals VIP and VIN after chopping, demodulation, and low-pass filtering) may be directly provided to a branch of the fully differential passive adder 220, which helps to significantly improve the signal-to-noise ratio. Figure 4In the specific example shown, the continuous-mode Δ-Σ analog-to-digital converter (AM-DC converter) may include a second-order feedforward cascaded integrator modulator, where the stability requirements of the second-order integrator are lower than those of higher-order integrators. Here, the cascaded multiple integrators 211 may consist of a first integrator and a second integrator connected to the output of the first integrator. Accordingly, the fully differential passive adder 220 may be configured to perform a weighted summation of the input signals of the continuous-mode Δ-Σ AM-DC converter (including a pair of differential signals VIP and VIN), the output signals of the first integrator (including a pair of differential signals VOP1 and VON1), and the output signals of the second integrator (including a pair of differential signals VOP2 and VON2) to produce a summed signal (i.e., k1×(VIP-VIN)+k2×(VOP1-VON1)+k3×(VOP2-VON2)), where VIN, VON1, and VON2 are negative, and the weights k1, k2, and k3 are proportional to the input signals of the second integrator. Figure 6 The values ​​of the first capacitor C1, the second capacitor C2, and the third capacitor C3 in the fully differential passive adder 220 shown are related. Figure 4 As shown, the first integrator (RC integrator) includes resistor R1, capacitor Cint1, and amplifier Gm1, and the second integrator (RC integrator) includes resistor R2, capacitor Cint2, and amplifier Gm2. Then, the quantizer 230 (e.g., a multi-bit flash analog-to-digital converter (flash ADC)) can be configured to generate a digital signal based on the summed signal. The digital-to-analog converter 240 can be connected between the quantizer 230 and the first-stage integrator 211 in a cascaded network of integrators 211, and the digital-to-analog converter 240 can be configured to generate an analog signal based on the digital signal and feed the analog signal back to the first-stage integrator 211. Specifically, the quantizer 230 can quantize the summed signal from the fully differential passive adder 220, and the resulting multi-bit digital signal controls the switching of the digital-to-analog converter 240. The converted analog signal is fed back to the input of the first-stage integrator 211 (e.g., the converted analog signal is subtracted from the input signal and used as the input of the first-stage integrator 211), thus forming a loop. In some embodiments, a continuous-mode Δ-Σ analog-to-digital converter (ADC) may include a plurality of digital-to-analog converters 240 (e.g., resistive digital-to-analog converters, RDACs), the number of which may be equal to twice the number of bits in the digital signal, to process each bit of each signal in a pair of differential signals accordingly. Figure 4In this configuration, quantizer 230 can generate a 16-bit digital signal Dout[15:0], and correspondingly, a total of 32 digital-to-analog converters 240 can be configured. Each bit of the digital signal Dout[15:0] from quantizer 230 can individually control the on / off state of the corresponding digital-to-analog converter 240. DAC After the switch is closed, the reference voltages Vref and VGND are fed back to the input terminal in a certain proportion to be subtracted from the input signal. Figure 5 It shows Figure 4 The linear model of the continuous Δ-Σ analog-to-digital converter shows that it has only one feedback branch, thus reducing the chip area. Figure 5 In this context, Vin is the input signal, and k1, k2, and k3 are feedforward coefficients, corresponding to... Figure 6 The weighting coefficients of the capacitors are given by g0 and g1, which are the input and feedback gain coefficients, respectively. g2 and g3 are the amplifier gain coefficients, I1(s) and I2(s) are the transfer functions of the first and second integrators, fs is the clock signal frequency controlling the quantizer, and Dout is the digital output signal. Furthermore, compared to a feedback cascaded integrator modulator, the integrator output in the modulator of the continuous-mode Δ-Σ analog-to-digital converter of this disclosure does not need to bear the signal component, but only quantization noise. This greatly alleviates the integrator output burden, reduces the amplifier linearity requirements, and also reduces overall power consumption. In addition, in the continuous-mode Δ-Σ analog-to-digital converter of this disclosure, a branch is directly fed from the input to the fully differential passive adder 220 before the quantizer 230, so the input signal directly appears at the loop output, improving the signal-to-noise ratio (SNDR) of the analog-to-digital converter. Figure 7 The power spectral density plot of the output signal of a continuous-mode Δ-Σ analog-to-digital converter is shown. The slope of 40 dB / decade indicates the modulator's second-order noise shaping capability, while ENOB reaches 15.3 bits and SNDR reaches 95.5 dB, demonstrating the converter's ability to acquire weak low-frequency signals.

[0048] Furthermore, in some embodiments, such as Figure 6As shown, the fully differential passive adder 220 described above may include multiple pairs of differential signal branches 221 (each pair of differential signal branches 221 includes a first differential signal branch 221a and a second differential signal branch 221b) and a pair of differential summing paths (including a first differential summing path 222a and a second differential summing path 222b). Each pair of differential signal branches 221 can be configured to receive a pair of differential signals. One differential signal branch in each pair of differential signal branches 221 may include two switches and a first capacitor C1. The first terminal of the first switch can be configured to receive one of the differential signals in the corresponding pair (e.g., VIP, VOP1, or VOP2), and the first terminal of the second switch can be configured to receive a common signal (e.g., a common-mode potential Vcm, which can provide a stable potential and prevent the quantizer input signal amplitude from exceeding the normal operating range). The second terminals of the two switches and the first terminal of the first capacitor C1 are connected to each other. Figure 6 In the specific example shown, there are a total of three pairs of differential signal branches 221. Furthermore, a pair of differential summing paths can be connected to multiple pairs of differential signal branches 221 and configured to perform weighted summation of multiple pairs of differential signals. In some embodiments, such as Figure 6 As shown, one of the differential summation paths in a pair can include three switches and capacitor C4, and according to... Figure 6 The connection shown provides, to some extent, the ability to adjust the amplitude of the summation output signal and perform weighted summation. It is understood that, as needed, more or fewer differential signal branches 221 can be configured, or other circuit structures can be used to implement each pair of differential signal branches 221 or differential summation paths; no limitations are imposed here. Figure 6 Voutp and Voutn in the equation are the difference outputs after summation.

[0049] In the device for acquiring weak bioelectrical signals disclosed herein, the fully differential passive adder can control the opening and closing of switches based on a non-overlapping clock, and scale the signals of the integrator output and feedforward input using the proportional relationship of capacitance values. This capacitor-switched adder improves the accuracy of circuit summation and maintains the high stability of the device. Compared with active adders, the fully differential passive adder used in the embodiments of this disclosure can effectively reduce the power consumption and area of ​​the chip and simplify the circuit structure. Moreover, the fully differential passive adder of this disclosure can use capacitance ratio for summation, which is more beneficial to reducing the impact of device mismatch during manufacturing than resistance ratio, and avoids the signal-to-noise ratio reduction caused by thermal noise generated by resistors. Furthermore, the fully differential passive adder of the embodiments of this disclosure can modulate one end of the capacitor to the Vcm common-mode point within half a clock cycle, avoiding the error caused by the inconsistency of the common-mode point of the feedforward branch output signal to the summation result of the adder. In addition, this adder structure is perfectly matched with the quantizer controlled by the back-end clock, and the clocks of the two can be controlled separately using non-overlapping clocks. Furthermore, in some embodiments, a chopper amplifier combined with a feedforward continuous-mode Δ-Σ analog-to-digital converter (ADC) can be used to acquire the signal, achieving low power consumption and low noise. The input reference noise can be below 1 μVrms, and the effective number of bits (ENOB) can be above 15 bits. Additionally, in the signal chain circuit architecture design, a low-pass filter can eliminate high-frequency noise after chopping, also functioning as an anti-aliasing filter. Moreover, the Δ-Σ ADC has a feedforward branch that directly superimposes the input signal onto the adder before finally entering the quantizer. Thus, the filter is multiplexed while simultaneously providing anti-aliasing performance.

[0050] The foregoing has described one or more exemplary embodiments of this disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0051] The terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, product, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, product, or apparatus. Without further limitation, the presence of other identical or equivalent elements in the process, method, product, or apparatus that includes said elements is not excluded. For example, the use of terms such as "first" or "second" to denote names does not indicate any particular order.

[0052] The same or similar parts between the various embodiments of this disclosure can be referred to mutually, and each embodiment focuses on describing the differences from other embodiments. In the description of this disclosure, the reference to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," "exemplary," etc., means that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. In this disclosure, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this disclosure and the features of the different embodiments or examples.

[0053] Additionally, when used in this disclosure, the terms “here,” “above,” “below,” “below,” “in the following,” “overall,” and similar terms should refer to the entirety of this disclosure and not any particular part thereof. Furthermore, unless expressly stated otherwise or otherwise understood in the context in which they are used, conditional language used herein, such as “may,” “possibly,” “for example,” “like,” etc., is generally intended to express that certain embodiments include, while other embodiments do not, certain features, elements, and / or states. Therefore, such conditional language is not generally intended to imply that one or more embodiments require features, elements, and / or states in any way, or whether such features, elements, and / or states are included or performed in any particular embodiment.

[0054] The above description is merely an embodiment of one or more embodiments of this disclosure and is not intended to limit the scope of the one or more embodiments of this disclosure. Various modifications and variations can be made to the one or more embodiments of this disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of the claims.

Claims

1. A device for acquiring weak bioelectrical signals, characterized in that, The device includes: An amplifier circuit configured to amplify an initial signal, wherein the amplifier circuit includes: A chopper modulator configured to convert the initial signal into a modulated signal at a higher frequency band. An amplifier, connected to the output of the chopper modulator, is configured to amplify the modulated signal. A chopper demodulator, connected to the output of the amplifier, is configured to convert the amplified modulation signal into a demodulated signal in the same frequency band as the initial signal and to convert noise to a higher frequency band. A low-pass filter, connected to the output of the chopper demodulator, is configured to allow at least a portion of the demodulated signal to pass through and filter out noise at higher frequencies to generate the amplified initial signal; and, An analog-to-digital converter (ADC) circuit is connected to the output of the amplifier circuit and configured to convert an amplified initial signal into a digital signal. The ADC circuit includes a continuous-mode Δ-Σ ADC comprising a fully differential passive adder and a plurality of cascaded integrators. The amplified initial signal from the amplifier circuit is directly provided to the fully differential passive adder. Each integrator includes a resistive input but not a switch.

2. The device according to claim 1, characterized in that, The continuous Δ-Σ analog-to-digital converter further includes a quantizer and a digital-to-analog converter, wherein: The fully differential passive adder is connected between each of the cascaded integrators and the quantizer, and the fully differential passive adder is configured to perform a weighted summation of the input signal of the continuous Δ-Σ analog-to-digital converter and the multiple output signals of the cascaded integrators to produce a summed signal. The quantizer is configured to generate a digital signal based on the summed signal; and The digital-to-analog converter is connected between the quantizer and the first-stage integrator in the cascaded plurality of integrators, and the digital-to-analog converter is configured to generate an analog signal based on the digital signal and feed the analog signal back to the first-stage integrator.

3. The device according to claim 2, characterized in that, The cascaded integrators consist of a first integrator and a second integrator.

4. The device according to claim 1, characterized in that, The fully differential passive adder includes: Multiple pairs of differential signal branches, each pair of differential signal branches is configured to receive a pair of differential signals. Each differential signal branch in each pair of differential signal branches includes a first switch, a second switch and a first capacitor. The first terminal of the first switch is configured to receive one of the differential signals in the corresponding pair of differential signals, the first terminal of the second switch is configured to receive a common signal, and the second terminals of the first switch, the second terminal of the second switch and the first terminal of the first capacitor are connected to each other. A pair of differential summation paths, which are connected to the plurality of differential signal branches and configured to perform weighted summation on the plurality of differential signals.

5. The device according to claim 1, characterized in that, The amplifier includes a resistive programmable gain amplifier or a capacitive programmable gain amplifier.

6. The device according to claim 1, characterized in that, The low-pass filter includes a first-order RC low-pass filter.

7. The device according to claim 1, characterized in that, The initial signal is a differential signal.

8. The device according to any one of claims 1 to 7, characterized in that, The device is configured to acquire at least one of electroencephalogram (EEG) signals and cortical electroencephalogram (EEG).

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