Packaging substrate, manufacturing method thereof and semiconductor packaging structure

Abstract

The invention relates to a packaging substrate, a manufacturing method thereof and a semiconductor packaging structure. The packaging substrate comprises a core layer, a first power supply layer, a second power supply layer and at least one first impedance adjusting structure. The core layer is provided with at least one first embedding cavity. The first power supply layer and the second power supply layer are respectively arranged on the upper and lower sides of the core layer. The first impedance adjusting structure is arranged in the first embedded cavity and comprises a plurality of first conducting layers and a plurality of second conducting layers which are alternately stacked at intervals in the first direction perpendicular to the core layer, and any adjacent first conducting layer and second conducting layer are insulated. Wherein the plurality of first conductive layers are electrically connected with at least one of the first power supply layer and the second power supply layer, and the plurality of second conductive layers are electrically connected with at least one of the first power supply layer and the second power supply layer. According to the invention, the impedance of the power supply network in the packaging substrate can be reduced, so that the power supply integrity of the packaging substrate is ensured and improved.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a packaging substrate and its manufacturing method, and a semiconductor packaging structure. Background Technology

[0002] As device performance continues to improve, integrated circuits are becoming increasingly more integrated, signal transmission rates are increasing, chip power consumption is rising, and the demand for transient current within the chip is also increasing, posing significant challenges to the power integrity (PI) design of the packaging substrate. Summary of the Invention

[0003] Therefore, it is necessary to provide a packaging substrate and its manufacturing method, as well as a semiconductor packaging structure, to address the above-mentioned technical problems, so as to reduce the impedance of the power network in the packaging substrate and ensure and improve the power integrity of the packaging substrate.

[0004] In a first aspect, embodiments of this disclosure provide a packaging substrate, including: a core layer, a first power layer, a second power layer, and at least one first impedance adjustment structure. The core layer has at least one first buried cavity. The first power layer and the second power layer are respectively disposed on the upper and lower sides of the core layer. The first impedance adjustment structure is disposed within the first buried cavity and includes multiple layers of first conductive layers and multiple layers of second conductive layers alternately and spaced apart along a first direction perpendicular to the core layer, wherein any adjacent first conductive layers and second conductive layers are insulated from each other. The multiple layers of first conductive layers are electrically connected to at least one of the first power layer and the second power layer, and the multiple layers of second conductive layers are electrically connected to at least one of the first power layer and the second power layer.

[0005] In some embodiments of this disclosure, the first impedance adjustment structure further includes: a first electroplated layer located on a first sidewall of the first embedded cavity, and a second electroplated layer located on a second sidewall of the first embedded cavity; wherein the first sidewall and the second sidewall are opposite to each other in a second direction parallel to the core layer. The first electroplated layer is electrically connected to each of the first conductive layers, and there is a gap between the end of the first conductive layer away from the first electroplated layer and the second electroplated layer in the second direction. The second electroplated layer is electrically connected to each of the second conductive layers, and there is a gap between the end of the second conductive layer away from the second electroplated layer and the first electroplated layer in the second direction.

[0006] In some embodiments of this disclosure, the first electroplated layer and the second electroplated layer extend along a first direction. The top surface of the first electroplated layer and the top surface of the second electroplated layer are respectively in contact with and connected to the first power layer. The bottom surface of the first electroplated layer and the bottom surface of the second electroplated layer are respectively in contact with and connected to the second power layer.

[0007] In some embodiments of this disclosure, the first impedance adjustment structure further includes: a first electrode plate located on the same layer as the first power layer and electrically connected to the first power layer, and a second electrode plate located on the same layer as the second power layer and electrically connected to the second power layer. The orthographic projections of the first electrode plate and the second electrode plate along a first direction coincide with the orthographic projection of the first conductive layer along the first direction; or, the orthographic projections of the first electrode plate and the second electrode plate along the first direction coincide with the orthographic projection of the second conductive layer along the first direction.

[0008] In some embodiments of this disclosure, the first electrode plate and the first power layer have the same film thickness. The second electrode plate and the second power layer have the same film thickness.

[0009] In some embodiments of this disclosure, the packaging substrate further includes: a redistribution structure disposed on the side of the first power layer away from the core layer and / or disposed on the side of the second power layer away from the core layer.

[0010] In some embodiments of this disclosure, the redistribution structure includes at least one second buried cavity. The packaging substrate further includes a second impedance adjustment structure disposed within the second buried cavity. The second impedance adjustment structure includes multiple layers of third conductive layers and multiple layers of fourth conductive layers stacked alternately and at intervals along a first direction perpendicular to the core layer, wherein any adjacent third conductive layers and fourth conductive layers are insulated from each other. The multiple layers of third conductive layers and multiple layers of fourth conductive layers are electrically connected to adjacent power layers, respectively.

[0011] Secondly, this disclosure provides a method for manufacturing a packaging substrate, used to manufacture the packaging substrate as described in any of the preceding embodiments. The manufacturing method includes:

[0012] A core layer is prepared, and at least one first embedded cavity is formed within the core layer;

[0013] A first impedance adjustment structure is formed in the first embedded cavity; the first impedance adjustment structure includes multiple layers of first conductive layers and multiple layers of second conductive layers that are alternately and spaced apart along a first direction perpendicular to the core layer, and any adjacent first conductive layers and second conductive layers are insulated from each other.

[0014] A first power layer and a second power layer are formed on the upper and lower sides of the core layer, respectively, such that multiple first conductive layers are electrically connected to at least one of the first power layer and the second power layer, and multiple second conductive layers are electrically connected to at least one of the first power layer and the second power layer.

[0015] In some embodiments of this disclosure, the first impedance adjustment structure further includes a first electroplated layer electrically connected to each of the first conductive layers and a second electroplated layer electrically connected to each of the second conductive layers. Accordingly, a first impedance adjustment structure is formed within the first embedded cavity, comprising:

[0016] A first electroplated layer is formed on the first sidewall of the first embedding cavity, and a second electroplated layer is formed on the second sidewall of the first embedding cavity; the first sidewall and the second sidewall are opposite to each other in a second direction parallel to the core layer;

[0017] Multiple insulating dielectric layers and multiple conductive dielectric layers are alternately stacked in the first embedded cavity, such that the conductive dielectric layer electrically connected to the first electroplated layer and spaced apart from the second electroplated layer constitutes the first conductive layer, and the conductive dielectric layer electrically connected to the second electroplated layer and spaced apart from the first electroplated layer constitutes the second conductive layer.

[0018] In some embodiments of this disclosure, a first power layer and a second power layer are formed after a first electroplated layer is formed on a first sidewall of the first embedded cavity, after a second electroplated layer is formed on a second sidewall of the first embedded cavity, and before multiple layers of insulating dielectric layers and multiple layers of conductive dielectric layers are alternately stacked within the first embedded cavity. The first power layer further covers the top surface of the first electroplated layer and the top surface of the second electroplated layer; the second power layer further covers the bottom surface of the first electroplated layer and the bottom surface of the second electroplated layer.

[0019] In some embodiments of this disclosure, the first impedance adjustment structure further includes: a first electrode plate located on the same layer as the first power layer and electrically connected thereto, and a second electrode plate located on the same layer as the second power layer and electrically connected thereto. After alternately stacking multiple layers of insulating dielectric layers and multiple layers of conductive dielectric layers within the first buried cavity, the first impedance adjustment structure is formed within the first buried cavity, further including:

[0020] A first electrode plate is formed on the side of the core layer where the first power layer is located, and the first electrode plate is electrically connected to the first power layer.

[0021] A second electrode plate is formed on the side of the core layer where the second power layer is located, and the second electrode plate is electrically connected to the second power layer.

[0022] Optionally, the orthographic projection of the first electrode plate and the second electrode plate along the first direction coincides with the orthographic projection of the first conductive layer along the first direction; or, the orthographic projection of the first electrode plate and the second electrode plate along the first direction coincides with the orthographic projection of the second conductive layer along the first direction.

[0023] In some embodiments of this disclosure, the method for manufacturing the packaging substrate further includes:

[0024] Pattern the first power layer and the second power layer respectively;

[0025] A rewiring structure is formed on the side of the first power layer away from the core layer and / or the side of the second power layer away from the core layer.

[0026] In some embodiments of this disclosure, the method for manufacturing the packaging substrate further includes:

[0027] At least one second embedded cavity is formed in the rewiring structure;

[0028] A second impedance adjustment structure is formed in the second embedded cavity; the second impedance adjustment structure includes multiple layers of third conductive layers and multiple layers of fourth conductive layers that are alternately and spaced apart along the first direction, and any adjacent third conductive layers and fourth conductive layers are insulated from each other; the multiple layers of third conductive layers and multiple layers of fourth conductive layers are electrically connected to adjacent power supply layers respectively.

[0029] Thirdly, this disclosure provides a semiconductor packaging structure, including: a packaging substrate as described in any of the preceding embodiments, and a chip and a printed circuit board respectively packaged on the upper and lower sides of the packaging substrate.

[0030] In some embodiments of this disclosure, the chip has conductive portions.

[0031] Optionally, the orthographic projection of the first impedance adjustment structure along the first direction overlaps with the orthographic projection of the conductive part along the first direction;

[0032] Alternatively, the distance between the orthographic projection of the first impedance adjustment structure along the first direction and the orthographic projection of the conductive part along the first direction in the direction parallel to the core layer is less than the target threshold.

[0033] The embodiments disclosed herein may have, or at least have, the following advantages:

[0034] In this embodiment, by providing at least one first buried cavity within the core layer and establishing a first impedance adjustment structure based on the first buried cavity, a capacitor-like structure can be constructed using multiple layers of first conductive layers and multiple layers of second conductive layers stacked alternately and at intervals along a first direction in the first impedance adjustment structure. Simultaneously, each first conductive layer is connected to its corresponding power layer, and each second conductive layer is electrically connected to its corresponding power layer. This allows for the effective increase of the equivalent capacitor in the power network by adjusting the number of first and second conductive layers within the first impedance adjustment structure, thereby increasing the loop capacitance of the power network. Furthermore, by adjusting the planar dimensions of the first buried cavity and the area of ​​the adjacent first and second conductive layers facing each other in the first direction, the loop inductance of the power network can be reduced. This not only reduces the impedance and ripple of the power network in the packaging substrate but also increases the current-carrying cross-sectional area of ​​the power network, improving the performance of the packaging substrate in terms of DC voltage drop and current density, thereby ensuring and enhancing the power integrity of the packaging substrate.

[0035] Furthermore, compared to surface-mounting capacitors on the upper and lower surfaces of the packaging substrate or embedding capacitors in the core layer, the first impedance adjustment structure in this embodiment does not need to occupy the upper and lower surface space of the packaging substrate, nor is it subject to many limitations in the size and capacitance selection of capacitors, and can have a more flexible range of capacitance additions.

[0036] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features, objects, and advantages of this disclosure will become apparent from the specification, drawings, and claims. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the embodiments or related technologies of this disclosure will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 A cross-sectional structural diagram of a packaging substrate provided for some embodiments;

[0039] Figure 2 A cross-sectional view of another packaging substrate provided for some embodiments;

[0040] Figure 3 A cross-sectional structural schematic diagram of a semiconductor packaging structure is provided for some embodiments;

[0041] Figure 4 A schematic flowchart illustrating a method for manufacturing a packaging substrate according to some embodiments;

[0042] Figure 5 A schematic flowchart illustrating another method for manufacturing a packaging substrate provided in some embodiments;

[0043] Figure 6 A top view of a core layer is provided for some embodiments;

[0044] Figure 7 A top view schematic diagram of a structure obtained after forming through-holes and trenches in a core layer, provided for some embodiments;

[0045] Figure 8 A top view schematic diagram of a structure obtained after forming an electroplated material layer in the through-holes and trenches of the core layer, provided for some embodiments;

[0046] Figure 9 A top view schematic diagram of a structure obtained after forming a first embedded cavity and a first electroplating layer and a second electroplating layer in a core layer, provided for some embodiments;

[0047] Figure 10 A top view schematic diagram of a structure obtained after forming a disk-in-hole in the core layer, provided for some embodiments;

[0048] Figure 11A cross-sectional schematic diagram of a structure obtained after forming a first power layer and a second power layer and providing an auxiliary support structure, provided for some embodiments;

[0049] Figure 12 A schematic cross-sectional view of a structure obtained after forming a first insulating dielectric layer in a first embedded cavity, provided for some embodiments;

[0050] Figure 13 A cross-sectional schematic diagram of a structure obtained after forming a first and second conductive layer in a first embedded cavity, provided for some embodiments;

[0051] Figure 14 A schematic cross-sectional view of a structure obtained after forming a second insulating dielectric layer in a first embedded cavity, provided for some embodiments;

[0052] Figure 15 A cross-sectional schematic diagram of a structure obtained after forming a first conductive layer in a first embedded cavity, as provided in some embodiments;

[0053] Figure 16 A schematic cross-sectional view of a structure obtained after forming a third insulating dielectric layer in a first embedded cavity, provided for some embodiments;

[0054] Figure 17 A cross-sectional schematic diagram of a structure obtained after forming a second conductive layer in a first embedded cavity, as provided in some embodiments;

[0055] Figure 18 A cross-sectional schematic diagram of a structure obtained after forming multiple layers of a first conductive layer, multiple layers of a second conductive layer and multiple layers of insulating dielectric layer in a first embedded cavity, provided for some embodiments;

[0056] Figure 19 A schematic cross-sectional view of the structure obtained after forming the first electrode plate is provided for some embodiments;

[0057] Figure 20 A cross-sectional schematic diagram of the structure obtained by removing the auxiliary support structure and flipping it upside down, as provided in some embodiments;

[0058] Figure 21 A schematic cross-sectional view of a structure obtained after etching back the insulating dielectric layer to form a second electrode accommodating opening, as provided in some embodiments;

[0059] Figure 22 A schematic cross-sectional view of the structure obtained after forming the second electrode plate, provided for some embodiments;

[0060] Figure 23 A schematic flowchart illustrating another method for manufacturing a packaging substrate provided in some embodiments;

[0061] Figure 24 A schematic flowchart illustrating another method for manufacturing a packaging substrate provided in some embodiments;

[0062] Figure 25 A cross-sectional schematic diagram of a structure obtained after patterning a first power layer and a second power layer, provided for some embodiments;

[0063] Figure 26 A cross-sectional schematic diagram of a structure obtained after forming the first layer of isolation material in a redistribution structure, provided for some embodiments;

[0064] Figure 27 A cross-sectional schematic diagram of a structure obtained after a patterned isolation material layer is provided for some embodiments;

[0065] Figure 28 A schematic cross-sectional view of a structure obtained after forming the first conductive material layer in a redistribution structure, provided for some embodiments;

[0066] Figure 29 This is a cross-sectional schematic diagram of a structure obtained after a patterned conductive material layer is provided for some embodiments.

[0067] Explanation of reference numerals in the attached figures:

[0068] 10 - Core layer, 20 - First power layer, 30 - Second power layer, 40 - First impedance adjustment structure, 401 - First conductive layer, 402 - Second conductive layer, 403 - Insulating dielectric layer, 404 - First electroplated layer, 405 - Second electroplated layer, 406 - First electrode plate, 407 - Second electrode plate, 50 - Through-hole, 501 - Electroplated sidewall, 502 - Filler layer, 60 - Redeploy structure, 610 - Insulation material layer 601 - Isolation pattern layer, 620 - Conductive material layer, 602 - Conductive pattern layer, 603 - First pad, 604 - Second pad, 605 - Third pad, 70 - Chip, 701 - Copper pillar, 702 - Micro-bump solder ball, 80 - Printed circuit board, 801 - Solder ball, 90 - Surface mount device, H - Through hole, G - Through slot, 110 - Electroplated material layer, 120 - Auxiliary support structure, Q - First embedded cavity, K - Opening. Detailed Implementation

[0069] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this disclosure.

[0070] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0071] It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0072] It should be understood that when one element is considered to be "connected" to another element, it can be directly connected to the other element or connected to the other element through an intermediary element. Furthermore, in the following embodiments, "connection" should be understood as "electrical connection," "communication connection," etc., if there is a transmission of electrical signals or data between the connected objects.

[0073] It should be understood that the singular forms of “a,” “an,” and “the” can also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0074] Currently, the power integrity of a packaging substrate is mainly reflected in two indicators: DC drop and AC ripple. That is, it can ensure that the voltage drop and ripple of the substrate power network fluctuate within an allowable range within a limited space. Among them, DC drop is a DC indicator and AC ripple is an AC indicator.

[0075] For example, the impedance of the power distribution network (PDN) in the package substrate is related to both the aforementioned DC voltage drop and AC ripple. Maintaining the impedance of the power network in the package substrate within a preset range ensures that the DC voltage drop and AC ripple do not exceed the limits. Since the impedance of a power network refers to the frequency domain impedance of its individual power networks, the impedance of a power network is directly proportional to the loop inductance (the equivalent inductance of the entire loop formed by connecting a power network, a capacitor, and a ground network) and inversely proportional to the loop capacitance (the equivalent capacitance of the entire loop formed by connecting a power network, a capacitor, and a ground network). Therefore, to achieve a smaller impedance range for the power network, it is necessary to reduce the loop inductance of each power network and increase the loop capacitance of each power network.

[0076] Based on this, the present disclosure provides a packaging substrate and its manufacturing method, as well as a semiconductor packaging structure, which can flexibly and effectively increase the loop capacitance of the power network and reduce the loop inductance of the power network, thereby reducing the impedance of the power network in the packaging substrate and ensuring and improving the power integrity of the packaging substrate.

[0077] Please see Figure 1 The packaging substrate provided in this embodiment includes: a core layer 10, a first power layer 20, a second power layer 30, and at least one first impedance adjustment structure 40.

[0078] The core layer 10 has at least one first embedding cavity. The core layer 10 is, for example, a BT resin layer. BT resin is a thermosetting resin formed by adding epoxy resin, polyphenylene ether resin (PPE) or allyl compounds as modifying components, with bismaleimide (BMI) and triazine as the main resin components. The size and number of the first embedding cavities can be selected and set according to the requirements.

[0079] The first power layer 20 and the second power layer 30 are respectively disposed on the upper and lower sides of the core layer 10. The first power layer 20 and the second power layer 30 are, for example, patterned conductive copper layers.

[0080] The first impedance adjustment structure 40 is disposed within the first embedded cavity and includes multiple layers of first conductive layers 401 and multiple layers of second conductive layers 402 that are alternately and spaced apart along a first direction (e.g., the Z direction) perpendicular to the core layer 10. Any adjacent first conductive layers 401 and second conductive layers 402 are insulated from each other, for example, by an insulating dielectric layer 403 filled within the first embedded cavity. Specifically, an insulating dielectric layer 403 is filled between each pair of adjacent first conductive layers 401 and second conductive layers 402.

[0081] Optionally, the multilayer first conductive layer 401 is electrically connected to at least one of the first power layer 20 and the second power layer 30, and the multilayer second conductive layer 402 is electrically connected to at least one of the first power layer 20 and the second power layer 30.

[0082] It is understood that the first power layer 20 and the second power layer 30 are used to construct the power network and can be patterned into multiple independent conductive patterns. Therefore, each first conductive layer 401 in the first impedance adjustment structure 40 can be correspondingly connected to the corresponding conductive pattern of at least one of the first power layer 20 and the second power layer 30, and each second conductive layer 402 in the first impedance adjustment structure 40 can be correspondingly connected to the corresponding conductive pattern of at least one of the first power layer 20 and the second power layer 30. The specific connection relationship is not limited in the embodiments of this disclosure, and the corresponding connection can be achieved by matching the design of the power network.

[0083] In this embodiment of the disclosure, by providing at least one first buried cavity in the core layer 10 and providing a first impedance adjustment structure 40 based on the first buried cavity, a capacitor-like structure can be constructed by multiple layers of first conductive layers 401 and multiple layers of second conductive layers 402 stacked alternately and at intervals along a first direction (e.g., the Z direction) in the first impedance adjustment structure 40. At the same time, the connection between each first conductive layer 401 and the corresponding power layer is realized, and the electrical connection between each second conductive layer 402 and the corresponding power layer is realized. In this way, by adjusting the number of the first conductive layer 401 and the second conductive layer 402 within the first impedance adjustment structure 40, the equivalent capacitor in the power network can be effectively increased, thereby correspondingly increasing the loop capacitance of the power network. At the same time, by adjusting the planar size of the first buried cavity and the size of the area of ​​the adjacent first conductive layer 401 and the second conductive layer 402 facing each other in the first direction, the loop inductance of the power network can be correspondingly reduced. This not only reduces the impedance of the power network in the packaging substrate and reduces the ripple of the power network, but also increases the current-carrying cross-sectional area of ​​the power network, thereby improving the performance of the packaging substrate in terms of DC voltage drop and current density of the power network, and thus ensuring and improving the power integrity of the packaging substrate.

[0084] It is understood that in some embodiments of related technologies, the packaging substrate uses a core layer as an intermediate layer and a core layer as a supporting structure for film layer stacking. Capacitors are mainly surface-mounted on the top and bottom surfaces of the packaging substrate. However, with the increasing integration density of chips (DIEs) and the growing area occupied by chips and interconnects, and considering the compatibility of production line testing fixtures, the space available for surface-mounting capacitors on the top and bottom surfaces of the packaging substrate is severely limited, resulting in a very limited number of capacitors that can be surface-mounted. Furthermore, many product applications require increasingly thinner packaging substrates. If capacitors are to be embedded in the core layer of the packaging substrate, the thickness of the core layer will greatly limit the placement space and selection range of capacitors, and must meet the process requirements of the filling dielectric and heat dissipation materials. On the other hand, if the core layer has a large thickness, it is also easy to waste space in the core layer due to the embedding of capacitors.

[0085] Therefore, compared to the above-mentioned surface-mount capacitors on the upper and lower surfaces of the packaging substrate or the embedding capacitors in the core layer, the first impedance adjustment structure 40 in this embodiment does not need to occupy the upper and lower surface space of the packaging substrate. Different capacitance values ​​can be flexibly constructed by adjusting the planar area of ​​the first conductive layer 401 and the second conductive layer 402, the filling thickness of the insulating dielectric layer 403, and the material type of the insulating dielectric layer 403. This avoids the many limitations on the package size and capacitance value selection caused by embedding capacitors, and allows for a more flexible range of capacitance value additions.

[0086] Please refer to some embodiments disclosed herein. Figure 1 The first impedance adjustment structure 40 further includes: a first electroplated layer 404 located on a first sidewall of the first embedded cavity, and a second electroplated layer 405 located on a second sidewall of the first embedded cavity; wherein the first sidewall and the second sidewall are opposite each other in a second direction (e.g., the X direction) parallel to the core layer. The first electroplated layer 404 is electrically connected to each of the first conductive layers 401, and the end of the first conductive layer 401 away from the first electroplated layer 404 is spaced apart from the second electroplated layer 405 in the second direction (e.g., the X direction). The second electroplated layer 405 is electrically connected to each of the second conductive layers 402, and the end of the second conductive layer 402 away from the second electroplated layer 405 is spaced apart from the first electroplated layer 404 in the second direction (e.g., the X direction).

[0087] In this embodiment, the first conductive layer 401 and the second conductive layer 402 are arranged in parallel and intersecting directions. The first conductive layer 401 is connected by a first electroplated layer 404 disposed on the first sidewall of the first embedding cavity, and the second conductive layer 402 is connected by a second electroplated layer 405 disposed on the second sidewall of the first embedding cavity. This facilitates the lead-out connection of each first conductive layer 401 and each second conductive layer 402, and simplifies the process.

[0088] Optionally, such as Figure 1 As shown, the first electroplated layer 404 and the second electroplated layer 405 extend along a first direction (e.g., the Z direction). The top surface of the first electroplated layer 404 and the top surface of the second electroplated layer 405 are respectively in contact with the first power layer 20. The bottom surface of the first electroplated layer 404 and the bottom surface of the second electroplated layer 405 are respectively in contact with the second power layer 30.

[0089] Please refer to some embodiments disclosed herein. Figure 1 The first impedance adjustment structure 40 further includes: a first electrode plate 406 located on the same layer as the first power layer 20 and electrically connected to the first power layer 20, and a second electrode plate 407 located on the same layer as the second power layer 30 and electrically connected to the second power layer 30.

[0090] Optionally, the orthographic projection of the first electrode 406 and the second electrode 407 along a first direction (e.g., the Z direction) coincides with the orthographic projection of the first conductive layer 401 along the first direction (e.g., the Z direction).

[0091] Optionally, the orthographic projection of the first electrode 406 and the second electrode 407 along the first direction (e.g., the Z direction) coincides with the orthographic projection of the second conductive layer 402 along the first direction (e.g., the Z direction).

[0092] In some embodiments of this disclosure, the first electrode 406 has the same film thickness as the first power layer 20. The second electrode 407 has the same film thickness as the second power layer 30. That is, the surface of the first electrode 406 facing away from the core layer 10 is flush with the surface of the first power layer 20 facing away from the core layer 10, and the surface of the second electrode 407 facing away from the core layer 10 is flush with the surface of the second power layer 30 facing away from the core layer 10. This facilitates the subsequent stacking or lamination of other thin films on the first power layer 20 and the second power layer 30 to prepare other functional layers, such as redistribution structures.

[0093] In some embodiments of this disclosure, please refer to Figure 2 The packaging substrate further includes a redistribution structure 60 disposed on the side of the first power layer 20 away from the core layer 10 and / or disposed on the side of the second power layer 30 away from the core layer 10.

[0094] Figure 2 The diagram illustrates this by taking the first power layer 20 and the second power layer 30, both of which have rewiring structures 60 on the side opposite to the core layer 10, as an example.

[0095] Optionally, the rewiring structure 60 includes multiple layers of isolation pattern layer 601 and multiple layers of conductive pattern layer 602 alternately stacked along a first direction (e.g., the Z direction); wherein each conductive pattern layer 602 is electrically connected in sequence according to a preset connection relationship.

[0096] Optionally, the rewiring structure 60 located on the side of the first power layer 20 away from the core layer 10 and on the side of the second power layer 30 away from the core layer 10 have the same number of isolation pattern layers 601 and the same number of conductive pattern layers 602.

[0097] Optionally, the isolation pattern layer 601 includes, but is not limited to, a patterned electronic-grade resin base film, such as an ABF (Ajinomoto Build-up Film) pattern layer.

[0098] Optionally, the conductive pattern layer 602 includes, but is not limited to, a copper pattern layer.

[0099] In some embodiments of this disclosure, the redistribution structure 60 includes at least one second buried cavity. The packaging substrate further includes a second impedance adjustment structure disposed within the second buried cavity. The second impedance adjustment structure includes multiple layers of third conductive layers and multiple layers of fourth conductive layers stacked alternately and at intervals along a first direction (e.g., the Z direction) perpendicular to the core layer 10, wherein any adjacent third conductive layers and fourth conductive layers are insulated from each other. The multiple layers of third conductive layers and multiple layers of fourth conductive layers are electrically connected to adjacent power layers, respectively.

[0100] Optionally, the second embedded cavity can be formed within the target layer isolation pattern layer 601. Compared to the first impedance adjustment structure 40, the second impedance adjustment structure is independently fabricated within the second embedded cavity of the target layer isolation pattern layer 601, requiring more precise electroplating and dielectric filling processes to achieve a more closely spaced intersecting parallel plate metal electroplating planar structure, even if the spacing between adjacent third and fourth conductive layers is smaller.

[0101] For example, the target layer isolation pattern layer 601 is one or more isolation pattern layers 601.

[0102] For example, the different isolation pattern layers 601 have different thicknesses. The target isolation pattern layer 601 is the isolation pattern layer 601 with the largest thickness or a thickness greater than a target threshold among all isolation pattern layers.

[0103] It is understood that the second impedance adjustment structure is similar in structure and function to the first impedance adjustment structure 40; that is, the specific limitations of the second impedance adjustment structure can be found in the limitations of the first impedance adjustment structure 40 described above. Furthermore, the second impedance adjustment structure can achieve the same or similar technical effects as the first impedance adjustment structure 40. Further details are omitted here.

[0104] Based on the same inventive concept, this disclosure also provides a semiconductor packaging structure, including a packaging substrate as described in some of the preceding embodiments. The solution provided by this semiconductor packaging structure is similar to the implementation described in the packaging substrate above; therefore, the specific limitations of this semiconductor packaging structure can be found in the limitations of the packaging substrate described above, and will not be repeated here.

[0105] In some embodiments of this disclosure, please refer to Figure 3 The semiconductor packaging structure also includes a chip 70 packaged on one side of the packaging substrate.

[0106] In some examples disclosed herein, chip 70 has conductive portions. For example... Figure 3 As shown, the conductive portion is located on the side of the chip 70 closest to the package substrate, and includes, for example, a copper pillar 701. The copper pillar 701 can be electrically connected to the corresponding pad or circuit via microbump solder balls 702. The microbump solder balls 702 include, but are not limited to, solder balls.

[0107] Optionally, the orthographic projection of the first impedance adjustment structure 40 along the first direction (e.g., the Z direction) overlaps with the orthographic projection of the conductive portion along the first direction (e.g., the Z direction).

[0108] Optionally, the distance between the orthographic projection of the first impedance adjustment structure 40 along the first direction (e.g., the Z direction) and the orthographic projection of the conductive part along the first direction (e.g., the Z direction) in the direction parallel to the core layer 10 is less than the target threshold.

[0109] In this embodiment of the present disclosure, a first impedance adjustment structure 40 is provided below the orthographic projection of the conductive portion of the chip 70 along a first direction (e.g., the Z direction) or in the surrounding area of ​​the orthographic projection. This facilitates the improvement of the power integrity of the packaging substrate by bringing the distance between the first impedance adjustment structure 40 and the conductive portion of the chip 70 closer together. At the same time, it can also have a better decoupling effect on the power noise within the chip 70.

[0110] Please refer to some embodiments disclosed herein. Figure 3 The semiconductor packaging structure also includes a printed circuit board (PCB) 80 packaged on the side of the packaging substrate opposite to the chip 70. That is, the chip 70 and the printed circuit board 80 can be packaged on the upper and lower sides of the packaging substrate, respectively.

[0111] Optionally, the printed circuit board 80 is packaged on the package substrate by solder balls 801. Solder balls 801 include, but are not limited to, solder balls.

[0112] Please refer to some embodiments disclosed herein. Figure 3The semiconductor packaging structure also includes a surface-mount device 90 located on the same side as the chip 70 and packaged on the packaging substrate.

[0113] Optionally, the surface-mount device 90 includes, but is not limited to, surface-mount capacitors. The surface-mount device 90 can be surface-mounted onto the package substrate using surface mount technology (SMT).

[0114] Optionally, such as Figure 3 As shown, the redistribution structure 60 of the packaging substrate has multiple pads on its surface, which are matched with different electrical functions. The multiple pads include, for example, a first pad 603 for connecting the chip 70, a second pad 604 for connecting the printed circuit board 80, and a third pad 605 for connecting the surface mount device 90.

[0115] It is worth mentioning that, in some embodiments of this disclosure, the number of core layers 10 in the packaging substrate can be multiple. Accordingly, a first impedance adjustment structure 40 can be respectively provided in each of the multiple core layers 10.

[0116] In some embodiments of this disclosure, the encapsulation substrate includes a glass core substrate, that is, the core layer 10 is a glass substrate. After a first embedded cavity is formed in the core layer 10, the first impedance adjustment structure 40 can be embedded in the first embedded cavity.

[0117] In other embodiments of this disclosure, the core layer 10 is an interposer or a middleware layer.

[0118] In some embodiments of this disclosure, the packaging substrate is a single-sided stacked coreless substrate, that is, the core layer 10 can be located on the top layer of the packaging substrate. Accordingly, the chip 70 and the first impedance adjustment structure 40 can both be embedded inside the core layer 10.

[0119] Based on the same inventive concept, this disclosure also provides a method for manufacturing a packaging substrate, used to manufacture the packaging substrate as described in any of the foregoing embodiments. The solution provided by this method for manufacturing the packaging substrate is similar to the implementation scheme described in the above-described packaging substrates; therefore, the specific limitations of the relevant structures in this method for manufacturing the packaging substrate can be found in the limitations of the packaging substrate described above, and will not be repeated here.

[0120] Please see Figure 4 The manufacturing method of the packaging substrate may include the following steps S100~S300.

[0121] S100, prepare the core layer, and form at least one first embedded cavity in the core layer.

[0122] S200, a first impedance adjustment structure is formed in the first embedded cavity; the first impedance adjustment structure includes multiple layers of first conductive layers and multiple layers of second conductive layers that are alternately and spaced apart along a first direction perpendicular to the core layer, and any adjacent first conductive layers and second conductive layers are insulated from each other.

[0123] S300, a first power layer and a second power layer are formed on the upper and lower sides of the core layer, respectively, such that multiple first conductive layers are electrically connected to at least one of the first power layer and the second power layer, and multiple second conductive layers are electrically connected to at least one of the first power layer and the second power layer.

[0124] In some embodiments of this disclosure, the first impedance adjustment structure further includes a first electroplated layer electrically connected to each of the first conductive layers and a second electroplated layer electrically connected to each of the second conductive layers. Accordingly, please refer to... Figure 5 The formation of a first impedance adjustment structure in the first embedded cavity in step S200 may include the following steps S210 and S220.

[0125] S210, a first electroplated layer is formed on the first sidewall of the first embedded cavity, and a second electroplated layer is formed on the second sidewall of the first embedded cavity; the first sidewall and the second sidewall are opposite to each other in a second direction parallel to the core layer.

[0126] S220, multiple layers of insulating dielectric layer and multiple layers of conductive dielectric layer are alternately stacked in the first embedded cavity, such that the conductive dielectric layer electrically connected to the first electroplated layer and spaced apart from the second electroplated layer constitutes the first conductive layer, and the conductive dielectric layer electrically connected to the second electroplated layer and spaced apart from the first electroplated layer constitutes the second conductive layer.

[0127] It is worth mentioning that in some embodiments disclosed herein, please continue to refer to... Figure 5 Step S300 includes step S310: forming a first power layer and a second power layer on the upper and lower sides of the core layer, respectively. Here, the first power layer and the second power layer are initial power material layers, i.e., they have not yet been patterned. Accordingly, the first power layer and the second power layer are formed after the formation of the first electroplated layer on the first sidewall of the first embedded cavity and the formation of the second electroplated layer on the second sidewall of the first embedded cavity, and before the alternating stacking of multiple insulating dielectric layers and multiple conductive dielectric layers within the first embedded cavity. That is, step S310 can be performed after step S210 and before step S220. In this way, the first power layer will cover the top surface of the first electroplated layer and the top surface of the second electroplated layer, and the second power layer will cover the bottom surface of the first electroplated layer and the bottom surface of the second electroplated layer.

[0128] In some embodiments of this disclosure, the first impedance adjustment structure further includes: a first electrode plate located on the same layer as the first power layer and electrically connected thereto, and a second electrode plate located on the same layer as the second power layer and electrically connected thereto. Please continue reading. Figure 5 After step S220, in which multiple layers of insulating dielectric layer and multiple layers of conductive dielectric layer are alternately stacked in the first buried cavity, step S200 forms a first impedance adjustment structure in the first buried cavity, and may also include the following steps S230 and S240.

[0129] S230, a first electrode plate is formed on the side of the core layer where the first power layer is located, and the first electrode plate is electrically connected to the first power layer.

[0130] S240, a second electrode plate is formed on the side of the core layer where the second power layer is located, and the second electrode plate is electrically connected to the second power layer.

[0131] Optionally, the orthographic projection of the first electrode plate and the second electrode plate along the first direction coincides with the orthographic projection of the first conductive layer along the first direction.

[0132] Optionally, the orthographic projection of the first electrode and the second electrode along the first direction coincides with the orthographic projection of the second conductive layer along the first direction.

[0133] To more clearly illustrate the manufacturing method of the packaging substrate provided in the embodiments of this disclosure, the following is combined with... Figures 6-22 right Figure 5 The manufacturing method shown is illustrated by way of example.

[0134] In steps S100 and S210, as Figures 6-10 As shown, a core layer 10 is fabricated, and at least one first embedded cavity Q is formed within the core layer 10. A first electroplated layer 404 is formed on the first sidewall of the first embedded cavity Q, and a second electroplated layer 405 is formed on the second sidewall of the first embedded cavity Q; the first sidewall and the second sidewall are opposite each other in a second direction (e.g., the X direction) parallel to the core layer 10.

[0135] For example, such as Figure 6 As shown, a substrate for the core layer 10 is provided, which is cut to the size of the packaging substrate and then surface-treated. Figure 7 As shown, the core layer 10 is drilled according to the design requirements to form through holes H and through slots G; wherein, through holes H and through slots G penetrate the core layer 10 along the first direction (i.e. the thickness direction of the core layer 10), and through slots G can be used to construct the first embedded cavity Q, for example, by excavating two adjacent through slots G to form the first embedded cavity Q.

[0136] For example, such as Figure 8 As shown, an electroplating process is performed on the inner walls of the through hole H and the through groove G to form an electroplated material layer 110.

[0137] In some examples, the first embedded cavity Q is formed by drilling through two adjacent through slots G. The through slot G is, for example, a rectangular mechanical through-hole, with its four corners chamfered and a chamfer radius, for example, >0.5 mm. After forming an electroplated material layer 110 on the inner wall of the two adjacent through slots G, as... Figure 9 As shown, the material in the area between the two adjacent through slots G of the core layer 10 is removed by drilling, so that the two adjacent through slots G are connected to form the first embedded cavity Q. And: the electroplated material layer on the left side wall of the left through slot G can be retained as the first electroplated layer 404, and the electroplated material layer on the right side wall of the right through slot G can be retained as the second electroplated layer 405; or, the electroplated material layer on the right side wall of the right through slot G can be retained as the first electroplated layer 404, and the electroplated material layer on the left side wall of the left through slot G can be retained as the second electroplated layer 405.

[0138] For example, such as Figure 10 As shown, after forming the first embedded cavity Q, the drilling debris is cleaned, and then a resin plugging electroplating filling process is performed on the through hole H to obtain a plate over filled via (POFV) 50. The plate over filled via 50 includes: an electroplated sidewall 501 composed of an electroplated material layer 110 retained in the through hole H, and a filling layer 502 covering the electroplated sidewall 501 and filling the through hole H.

[0139] In step S310, please refer to Figure 11 The first power layer 20 and the second power layer 30 are formed on the upper and lower sides of the core layer 10, respectively.

[0140] For example, the first power layer 20 and the second power layer 30 are the copper layers on the upper and lower sides of the core layer 10, respectively.

[0141] For example, such as Figure 11 As shown, an auxiliary support structure 120 is provided, and the surface of the area of ​​the auxiliary support structure 120 facing the first embedded cavity Q is subjected to surface treatment such as grinding. Then, the auxiliary support structure 120 is placed below the second power layer 30 for load-bearing support.

[0142] In step S220, please refer to Figures 12-18 Multiple insulating dielectric layers 403 and multiple conductive dielectric layers are alternately stacked in the first embedded cavity Q, such that the conductive dielectric layer electrically connected to the first electroplated layer 404 and spaced apart from the second electroplated layer 405 constitutes the first conductive layer 401, and the conductive dielectric layer electrically connected to the second electroplated layer 405 and spaced apart from the first electroplated layer 404 constitutes the second conductive layer 402.

[0143] Here, the placement of the packaging substrate is matched, and the top and bottom surfaces and left and right sidewalls of the packaging substrate can be interchanged. Figures 12-19Taking the example of a first power layer 20 located on the upper surface of the packaging substrate, a second power layer 30 located on the lower surface of the packaging substrate, a first electroplated layer 404 located on the right side wall of the first buried cavity Q, and a second electroplated layer 405 located on the left side wall of the first buried cavity Q, the packaging substrate is supported on the auxiliary support structure 120.

[0144] For example, such as Figure 12 As shown, a first insulating dielectric layer 403 is formed on the surface of the auxiliary support structure 120 exposed within the first embedded cavity Q. Then, the first insulating dielectric layer 403 undergoes surface treatment, allowing a thin, uniform copper layer to be deposited on its surface. This can be achieved by chemically plating copper to form a copper seed layer, ensuring smooth electroplating on the insulating dielectric layer 403 to form the corresponding conductive layer. Afterwards, as... Figure 13 As shown, a copper layer is electroplated on the insulating dielectric layer 403, for example forming a first second conductive layer 402. This second conductive layer 402 is connected to the sidewall of the second electroplated layer 405 and has a gap between it and the sidewall of the first electroplated layer 404. Figure 14 As shown, the insulating dielectric layer 403 continues to be filled, and a copper seed layer can be formed on the insulating dielectric layer 403. Figure 14 (Not shown in the image). For example... Figure 15 As shown, a copper layer is electroplated on the insulating dielectric layer 403, for example forming a first conductive layer 401. This first conductive layer 401 is connected to the sidewall of the first electroplated layer 404 and has a gap between it and the sidewall of the second electroplated layer 405. Figure 16 As shown, the insulating dielectric layer 403 continues to be filled, and a copper seed layer can be formed on the insulating dielectric layer 403. Figure 16 (Not shown in the image). For example... Figure 17 As shown, a copper layer is electroplated on the insulating dielectric layer 403, forming, for example, a second conductive layer 402. This second conductive layer 402 is connected to the sidewall of the second electroplated layer 405 and has a gap between it and the sidewall of the first electroplated layer 404. Thus, as... Figure 18 As shown, the process of repeatedly filling the insulating dielectric layer 403 and electroplating the conductive layer can be stopped after the surface of the top insulating dielectric layer 403 is flush with the upper surface of the core layer 10 (located in the same plane).

[0145] Optionally, each first conductive layer 401 is electrically connected to the power supply voltage network in the first power supply layer 20 and the second power supply layer 30 through a first electroplating layer 404; each second conductive layer 402 is electrically connected to the ground voltage network in the first power supply layer 20 and the second power supply layer 30 through a second electroplating layer 405.

[0146] In step S230, please refer to Figure 19A first electrode plate 406 is formed on the side of the core layer 10 where the first power layer 20 is located, and the first electrode plate 406 is electrically connected to the first power layer 20.

[0147] For example, the insulating dielectric layer 403 exposed in the first buried cavity Q can be surface treated first, for example, by chemically plating copper to form a copper seed layer, and then electroplating to form the first electrode plate 406. The first electrode plate 406 is, for example, an electroplated copper layer.

[0148] Optionally, the first electrode 406 is electrically connected to the power supply voltage network in the first power supply layer 20.

[0149] Optionally, the film thickness of the first electrode plate 406 is the same as the film thickness of the first power layer 20, that is, the upper surface of the first electrode plate 406 is flush with the upper surface of the first power layer 20 (located in the same plane).

[0150] Optionally, the orthographic projection of the first electrode plate 406 along a first direction (e.g., the Z direction) coincides with the orthographic projection of the first conductive layer 401 along a first direction (e.g., the Z direction). Accordingly, after the first electrode plate 406 is formed, the space between the outer sidewall of the first electrode plate 406 and the first power layer 20 can be filled with an insulating dielectric layer 403.

[0151] In step S240, please refer to Figures 20-22 A second electrode plate 407 is formed on the side of the core layer 10 where the second power layer 30 is located, and the second electrode plate 407 is electrically connected to the second power layer 30.

[0152] For example, such as Figure 20 As shown, the auxiliary support structure 120 is removed, and then the packaging substrate is flipped so that the second power layer 30 is located on the upper side of the packaging substrate. The exposed upper surface of the first insulating dielectric layer 403 is then ground to ensure that the upper surface of the insulating dielectric layer 403 is flush with the upper surface of the second power layer 30 (located in the same plane). Figure 21 As shown, the insulating dielectric layer 403 is etched back to form an opening K. The bottom surface of the opening K is, for example, flush with the top surface of the core layer 10, and the opening K is used to accommodate the second electrode plate 407. Figure 22 As shown, the insulating dielectric layer 403 exposed by the opening K can first undergo surface treatment, for example, by chemically plating copper to form a copper seed layer, and then electroplating to form the second electrode plate 407. The second electrode plate 407 is, for example, an electroplated copper layer.

[0153] Optionally, the second electrode 407 is electrically connected to the power supply voltage network in the second power supply layer 30.

[0154] Optionally, the film thickness of the second electrode plate 407 is the same as the film thickness of the second power layer 30, that is, the upper surface of the second electrode plate 407 is flush with the upper surface of the second power layer 30 (located in the same plane).

[0155] Optionally, the orthographic projection of the second electrode plate 407 along the first direction (e.g., the Z direction) coincides with the orthographic projection of the first conductive layer 401 along the first direction (e.g., the Z direction). Accordingly, after the second electrode plate 407 is formed, the space between the outer sidewall of the second electrode plate 407 and the second power layer 30 can be filled with an insulating dielectric layer 403.

[0156] It is worth mentioning that, in some embodiments of this disclosure, please refer to Figure 23 The manufacturing method of the packaging substrate may also include the following steps S320 and S400.

[0157] S320, respectively pattern the first power layer and the second power layer.

[0158] S400 forms a rewiring structure on the side of the first power layer away from the core layer and / or on the side of the second power layer away from the core layer.

[0159] In some embodiments of this disclosure, please refer to Figure 24 The manufacturing method of the packaging substrate may also include the following steps S500 and S600.

[0160] S500, at least one second embedded cavity is formed in the rewiring structure.

[0161] S600, a second impedance adjustment structure is formed in the second embedded cavity; the second impedance adjustment structure includes multiple layers of third conductive layers and multiple layers of fourth conductive layers stacked alternately and at intervals along the first direction, and any adjacent third conductive layers and fourth conductive layers are insulated from each other; the multiple layers of third conductive layers and multiple layers of fourth conductive layers are electrically connected to adjacent power supply layers respectively.

[0162] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0163] To more clearly illustrate the manufacturing method of the packaging substrate provided in the embodiments of this disclosure, the following is combined with... Figures 25-29 and Figure 2 right Figure 23 Steps S320 and S400 in the manufacturing method shown are illustrated by way of example.

[0164] In step S320, please refer to Figure 25 The first power layer 20 and the second power layer 30 are patterned respectively.

[0165] For example, dry films are formed on the surfaces of the first power layer 20 and the second power layer 30, respectively. Then, the dry films are exposed and developed, so that the patterned dry films can be used as masks to pattern the corresponding power layers.

[0166] In step S400, please refer to Figures 26-29 and Figure 2 A rewiring structure 60 is formed on the side of the first power layer 20 away from the core layer 10 and / or on the side of the second power layer 30 away from the core layer 10.

[0167] Figures 26-29 The diagram illustrates an example where both the first power layer 20 and the second power layer 30 have a redistribution structure 60 formed on the side opposite to the core layer 10. The redistribution structure 60 is, for example, composed of alternating layers of isolation pattern layers 601 and multiple layers of conductive pattern layers 602. The isolation pattern layer 601 is, for example, an ABF (Ajinomoto Build-up Film) pattern layer, and the conductive pattern layer 602 is, for example, a copper pattern layer.

[0168] For example, such as Figure 26 As shown, insulating material layers 610 are laminated onto the surfaces of the first power layer 20 and the second power layer 30, respectively. Figure 27 As shown, the patterned isolation material layer 610 forms an isolation pattern layer 601. Optionally, laser holes can be formed in the isolation material layer 610 by laser engraving to form the isolation pattern layer 601.

[0169] After that, as Figure 28 As shown, a conductive material layer 620 can be deposited and / or electroplated on the surface of the isolation pattern layer 601 (including within the laser aperture). Figure 29As shown, a conductive material layer 620 is patterned to form a conductive pattern layer 602. Optionally, the conductive material layer 620 may be, for example, an electroplated copper layer. In some examples, a copper seed layer may be formed by chemically plating copper on the surface of the isolation pattern layer 601 (including inside the laser hole), followed by electroplating to form the conductive material layer 620, and then patterning the conductive material layer 620; or, in other examples, the copper seed layer may be patterned first to form the initial pattern outline of the conductive pattern layer 602 after the copper seed layer is formed, and then copper material may be electroplated to the target thickness to obtain the conductive pattern layer 602.

[0170] For example, the patterned conductive material layer 620 or the patterned copper seed layer can be manifested as: forming a dry film on the material surface, and then exposing and developing the dry film, so that the patterned dry film can be used as a mask to pattern the corresponding material.

[0171] It should be added that after the conductive pattern layer 602 is formed, a stripping process and a rapid etching process (including but not limited to a cleaning process) can be performed to ensure the removal of excess adhesive film and copper shavings.

[0172] Based on this, to meet the requirements, multiple layers can be added, that is, the aforementioned fabrication processes of the isolation pattern layer 601 and conductive pattern layer 602 can be repeated to alternately stack the isolation pattern layer 601 and conductive pattern layer 602 to the target number of layers, thereby obtaining, as Figure 2 The redistribution structure 60 of the packaging substrate is shown. Furthermore, before each lamination of the isolation material layer 610, the surface of the conductive pattern layer 602 needs to be roughened to ensure that the isolation material layer 610 can be better laminated and connected with the conductive pattern layer 602 during the lamination process, which helps to improve the reliability of the redistribution structure 60 and the packaging substrate.

[0173] It is understood that in S500 and S600, the formation of the second buried cavity in the redistribution structure and the formation of the second impedance adjustment structure can be made by referring to the formation of the first buried cavity in the core layer and the formation of the first impedance adjustment structure in some of the aforementioned embodiments, and will not be elaborated here.

[0174] Optionally, the second embedded cavity can be formed within the target layer isolation pattern layer 601. Compared to the first impedance adjustment structure 40, the second impedance adjustment structure is independently fabricated within the second embedded cavity of the target layer isolation pattern layer 601, requiring more precise electroplating and dielectric filling processes to achieve a more closely spaced intersecting parallel plate metal electroplating planar structure, even if the spacing between adjacent third and fourth conductive layers is smaller.

[0175] For example, the target layer isolation pattern layer 601 is one or more isolation pattern layers 601.

[0176] For example, the different isolation pattern layers 601 have different thicknesses. The target isolation pattern layer 601 is the isolation pattern layer 601 with the largest thickness or a thickness greater than a target threshold among all isolation pattern layers.

[0177] It is worth mentioning that, please combine Figure 3 It is understood that after the above-mentioned packaging substrate is formed, solder mask opening can be performed at the location where the solder pads need to be set in the redistribution structure 60 to expose the solder pads. The solder pads can also be surface treated to protect and reinforce them, so as to avoid oxidation or damage due to stress.

[0178] For example, the plurality of pads may include: a first pad 603 for connecting the chip 70, a second pad 604 for connecting the printed circuit board 80, and a third pad 605 for connecting the surface mount device 90. Optionally, the second pad 604 and the first pad 603 are respectively disposed on the upper and lower sides of the package substrate, and the first pad 603 and the third pad 605 are disposed on the same side of the package substrate.

[0179] Accordingly, in some examples, microbump solder balls 702 can be provided on the first pad 603, and the conductive part of the chip 70 (e.g., copper pillar 701) can be electrically connected to the first pad 603 through the microbump solder balls 702 to achieve the packaging and testing of the chip 70 on the packaging substrate.

[0180] In some examples, solder balls 801 may be provided on the printed circuit board 80, and the second pad 604 may be electrically connected to the printed circuit board 80 via the solder balls 801. The solder balls 801 include, but are not limited to, solder balls.

[0181] In some examples, surface mount devices 90 can be connected to the third pad 605 via surface mount technology (SMT). Surface mount devices 90 include, but are not limited to, surface mount capacitors.

[0182] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this disclosure.

[0183] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent disclosure. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the protection scope of this disclosure. Therefore, the protection scope of this disclosure should be determined by the appended claims.

Claims

1. A package substrate, characterized by, The package substrate comprises: a core layer provided with at least one first embedded cavity; a first power supply layer and a second power supply layer arranged on the upper and lower sides of the core layer respectively; at least one first impedance adjustment structure arranged in the first embedded cavity, comprising a plurality of first conductive layers and a plurality of second conductive layers alternately and spaced stacked along a first direction perpendicular to the core layer, and any adjacent first conductive layer and second conductive layer are insulated; wherein the plurality of first conductive layers are electrically connected to at least one of the first power supply layer and the second power supply layer, and the plurality of second conductive layers are electrically connected to at least one of the first power supply layer and the second power supply layer.

2. The package substrate of claim 1, wherein The first impedance adjustment structure further comprises a first electroplated layer located on a first side wall of the first embedded cavity, and a second electroplated layer located on a second side wall of the first embedded cavity; wherein the first side wall and the second side wall are opposite in a second direction parallel to the core layer; the first electroplated layer is electrically connected to each of the first conductive layers, and the end of the first conductive layer away from the first electroplated layer has a spacing with the second electroplated layer in the second direction; the second electroplated layer is electrically connected to each of the second conductive layers, and the end of the second conductive layer away from the second electroplated layer has a spacing with the first electroplated layer in the second direction.

3. The package substrate of claim 2, wherein The first electroplated layer and the second electroplated layer extend along the first direction; the top surface of the first electroplated layer and the top surface of the second electroplated layer are respectively in contact with the first power supply layer; the bottom surface of the first electroplated layer and the bottom surface of the second electroplated layer are respectively in contact with the second power supply layer.

4. The package substrate of claim 1, wherein The first impedance adjustment structure further comprises a first electrode plate located in the same layer as the first power supply layer and electrically connected to the first power supply layer, and a second electrode plate located in the same layer as the second power supply layer and electrically connected to the second power supply layer; wherein the first electrode plate and the second electrode plate are projected along the first direction and coincide with the first conductive layer projected along the first direction; or, the first electrode plate and the second electrode plate are projected along the first direction and coincide with the second conductive layer projected along the first direction.

5. The package substrate according to claim 4, wherein: the first electrode plate has the same film layer thickness as the first power supply layer; the second electrode plate has the same film layer thickness as the second power supply layer.

6. The package substrate according to any one of claims 1 to 5, wherein Further comprising: a redistribution structure arranged on the side of the first power supply layer away from the core layer and / or arranged on the side of the second power supply layer away from the core layer.

7. The package substrate of claim 6, wherein, The redistribution structure is provided with at least one second embedded cavity; the package substrate further comprises a second impedance adjustment structure arranged in the second embedded cavity; the second impedance adjustment structure comprises a plurality of third conductive layers and a plurality of fourth conductive layers alternately and spaced stacked along a first direction perpendicular to the core layer, and any adjacent third conductive layer and fourth conductive layer are insulated; the plurality of third conductive layers and the plurality of fourth conductive layers are respectively electrically connected to adjacent power supply layers.

8. A method of manufacturing a package substrate, characterized by, ​ forming at least one first embedded cavity in the core layer; forming a first impedance adjusting structure in the first embedded cavity; the first impedance adjusting structure comprises a plurality of first conductive layers and a plurality of second conductive layers which are alternately and spacedly stacked along a first direction perpendicular to the core layer, and any adjacent first conductive layer and second conductive layer are insulated; forming a first power supply layer and a second power supply layer on the upper and lower sides of the core layer respectively, so that the plurality of first conductive layers are electrically connected to at least one of the first power supply layer and the second power supply layer, and the plurality of second conductive layers are electrically connected to at least one of the first power supply layer and the second power supply layer.

9. The method of manufacturing a package substrate according to claim 8, wherein The first impedance adjusting structure further comprises a first plating layer electrically connected to each of the first conductive layers and a second plating layer electrically connected to each of the second conductive layers; The forming of the first impedance adjusting structure in the first embedded cavity comprises: forming a first plating layer on a first sidewall of the first embedded cavity and forming a second plating layer on a second sidewall of the first embedded cavity; the first sidewall and the second sidewall are opposite in a second direction parallel to the core layer; alternately stacking a plurality of insulating medium layers and a plurality of conductive medium layers in the first embedded cavity, and making the conductive medium layers electrically connected to the first plating layer and spaced from the second plating layer constitute the first conductive layers, and making the conductive medium layers electrically connected to the second plating layer and spaced from the first plating layer constitute the second conductive layers.

10. The method of manufacturing a package substrate according to claim 9, wherein The first power supply layer and the second power supply layer are formed after the forming of the first plating layer on the first sidewall of the first embedded cavity and the forming of the second plating layer on the second sidewall of the first embedded cavity, and before the alternately stacking of the plurality of insulating medium layers and the plurality of conductive medium layers in the first embedded cavity; The first power supply layer further covers the top surface of the first plating layer and the top surface of the second plating layer; and the second power supply layer further covers the bottom surface of the first plating layer and the bottom surface of the second plating layer.

11. The method of manufacturing a package substrate according to claim 8, wherein The first impedance adjusting structure further comprises a first electrode plate located in the same layer as the first power supply layer and electrically connected thereto, and a second electrode plate located in the same layer as the second power supply layer and electrically connected thereto; after the alternately stacking of the plurality of insulating medium layers and the plurality of conductive medium layers in the first embedded cavity, the forming of the first impedance adjusting structure in the first embedded cavity further comprises: forming the first electrode plate on the side of the core layer provided with the first power supply layer and electrically connecting the first electrode plate and the first power supply layer; forming the second electrode plate on the side of the core layer provided with the second power supply layer and electrically connecting the second electrode plate and the second power supply layer; The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively.

12. The method of manufacturing a package substrate according to any one of claims 8 to 11, wherein The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. The first electrode plate and the second electrode plate are located in the same layer as the first conductive layers and the second conductive layers respectively. A redistribution structure is formed on the side of the first power supply layer away from the core layer and / or on the side of the second power supply layer away from the core layer.

13. The method of manufacturing a package substrate according to claim 12, wherein Further comprising: At least one second buried cavity is formed in the redistribution structure; A second impedance adjustment structure is formed in the second buried cavity; the second impedance adjustment structure comprises a plurality of third conductive layers and a plurality of fourth conductive layers alternately and spaced stacked along the first direction, and any adjacent third conductive layer and fourth conductive layer are insulated; the plurality of third conductive layers and the plurality of fourth conductive layers are electrically connected to adjacent power supply layers respectively.

14. A semiconductor package structure, comprising: Comprising: The package substrate as claimed in any one of claims 1 to 7, and a chip and a printed circuit board respectively packaged on the upper and lower sides of the package substrate.

15. The semiconductor package structure of claim 14, wherein, The chip has a conductive part; wherein, The first impedance adjustment structure along the first direction is overlapped with the first direction projection of the conductive part; Or, the first impedance adjustment structure along the first direction is overlapped with the first direction projection of the conductive part in the direction parallel to the core layer, and the interval is less than a target threshold.

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