Three-dimensional field effect transistors with gate cuts to enhance carrier mobility and related methods of manufacture

Abstract

A gate cut-out extending through a gate adjacent to a channel region of a 3D FET causes the gate to apply a first force and a second force on the channel region in directions orthogonal to each other to improve carrier mobility, thereby increasing drive strength. The gate cut may include gate cut walls to cause the gate to apply a first force on the channel region in a first direction. The gate cut may include a gate cut wedge to cause the gate to apply a second force on the channel region in a first direction and a third force on the channel region in a second direction to further improve carrier mobility. The 3D FET may be a P-type or an N-type, and the 3D FET may be a FinFET or a GAA FET.

Description

[0001] Priority application

[0002] This application claims priority to U.S. Patent Application Serial No. 18 / 336,269, filed June 16, 2023, entitled “THREE-DIMENSIONAL (3D) FIELDEFFECT TRANSISTORS (FETS) WITH GATE CUTS TO ENHANCE CARRIER MOBILITY ANDRELATED FABRICATION METHODS”, the entire contents of which are incorporated herein by reference. Background Technology

[0003] I. Technical Field

[0004] The technology disclosed herein relates generally to transistors in integrated circuits, and more specifically to three-dimensional transistors.

[0005] II. Background Technology

[0006] The current in the channel region of a field-effect transistor (FET) is controlled by a gate voltage applied to a gate adjacent to the channel region. When the gate is adjacent to the surface of the channel region, the gate voltage has the effect of turning on or off the thin conductive channel layer beneath the surface for the flow of majority carriers (i.e., electrons and holes). In a planar FET, the conductive channel is formed in one surface of a semiconductor substrate. To increase the total cross-sectional area of ​​the channel region to increase the drive strength, fin-type FETs (FinFETs) and gate-all-around (GAA) FETs have been developed. In both FinFETs and GAA FETs, the channel region is induced in multiple faces of a plate of doped semiconductor material. The plate includes two planes and two edges between the main planes. The direction of current flow is orthogonal to the cross-section of the plate. The ability to apply a gate voltage to the two planar surfaces makes it possible to turn the current channel on or off on both sides of the plate, essentially doubling the drive strength relative to a planar FET. Additionally, FinFETs and GAA FETs (both three-dimensional (3D) FETs) can include multiple plates to further increase the drive strength. It has been found that applying forces (e.g., stress and strain) to the crystal structure of a semiconductor substrate in the channel region of a FET can improve carrier mobility. However, applying such stress to the substrate of a 3D FET is difficult. Summary of the Invention

[0007] The aspects disclosed in the detailed description include three-dimensional (3D) field-effect transistors (FETs) with gate notches to enhance carrier mobility. Related methods for fabricating 3D FETs including gate notches to enhance carrier mobility are also disclosed. Although the semiconductor plates (e.g., fins) in a fin-type FET (FinFET) and the semiconductor plates (e.g., nanosheets) in a gate-all-around (GAA) FET are oriented along different planes of the crystal structure of the semiconductor wafer, applying a force in the channel region in the same direction relative to the surface of such semiconductor plates can improve carrier mobility in both types of 3D FETs. In the exemplary 3D FETs disclosed herein, a gate notch is provided in the gate adjacent to the channel region so that a first force is applied to the channel region of the semiconductor plate in a first direction and a second force is applied to the channel region of the semiconductor plate in a second direction orthogonal to the first direction to improve carrier mobility, thereby increasing the drive strength of the 3D FET. The first and second forces complement each other to enhance carrier mobility to obtain a drive strength greater than that achievable by either force alone. For example, the gate notch may include a gate notch wall of a first gate notch material to apply a first force to the channel region of the semiconductor substrate in a first direction. In a further example, the gate notch may also include a gate notch wedge to further apply the first force to the channel region of the semiconductor substrate in the first direction and to apply a second force to the channel region of the semiconductor substrate in a second direction, thereby further improving carrier mobility. In some examples, the 3D FET may be a P-type FET or an N-type FET, and the 3D FET may be one of a FinFET or a GAA FET. In some examples, the 3D complementary metal-oxide-semiconductor (CMOS) FET may include an NFET and a PFET, each including a gate notch to improve drive strength.

[0008] In this regard, in one aspect, a 3D FET structure is disclosed. The 3D FET structure includes at least one semiconductor plate, each semiconductor plate including a channel region configured to conduct current in a first direction. The 3D FET structure further includes: a gate extending in a second direction orthogonal to the first direction, the gate including a gate material disposed on at least one semiconductor plate in the channel region; and a gate cutout extending in the second direction through the gate material adjacent to the channel region of the at least one semiconductor plate, wherein the gate cutout is configured to apply a first force to the channel region of the at least one semiconductor plate in the second direction and a second force to the channel region of the at least one semiconductor plate in a third direction orthogonal to the second direction.

[0009] In another aspect, a method for fabricating a 3D FET structure is disclosed. The method includes forming at least one semiconductor plate, each semiconductor plate including a channel region configured to conduct current in a first direction. The method further includes forming a gate extending in a second direction orthogonal to the first direction, the gate including gate material disposed on at least one semiconductor plate in the channel region. The method further includes forming a gate notch extending in the second direction through the gate material adjacent to the channel region of the at least one semiconductor plate, wherein the gate notch is configured to apply a first force to the channel region of the at least one semiconductor plate in the second direction and a second force to the channel region of the at least one semiconductor plate in a third direction orthogonal to the second direction.

[0010] In another aspect, a complementary metal-oxide-semiconductor (CMOS) circuit structure is disclosed. The CMOS circuit structure includes: at least one first semiconductor plate, each first semiconductor plate including a first type dopant; a first channel region configured to conduct a first current in a first direction; a first source / drain region located on a first side of the first channel region; and a second source / drain region located on a second side of the first channel region. The CMOS circuit structure further includes: a first gate extending in a second direction orthogonal to the first direction, the first gate including gate material disposed on each of the at least one first semiconductor plate in the first channel region. The CMOS circuit structure also includes: a first gate notch extending in the second direction through the first gate adjacent to the first channel region of the at least one first semiconductor plate. The CMOS circuit structure further includes: at least one second semiconductor plate, each second semiconductor plate including a second type dopant; a second channel region configured to conduct a second current in a first direction; a third source / drain region located on a first side of the second channel region; and a fourth source / drain region located on a second side of the second channel region. The CMOS circuit structure further includes a second gate and a second gate notch, the second gate extending in a second direction and including gate material on each of at least one second semiconductor plate disposed in a second channel region, the second gate notch extending in the second direction through a second gate adjacent to the second channel region of at least one second semiconductor plate, wherein the first gate notch is configured to apply a first force to the first channel region of at least one first semiconductor plate in the second direction and a second force to the first channel region of at least one first semiconductor plate in a third direction orthogonal to the second direction, and the second gate notch is configured to apply a third force to the second channel region of at least one second semiconductor plate in the second direction and a fourth force to the second channel region of at least one second semiconductor plate in a third direction. Attached Figure Description

[0011] Figure 1 This is an example of a three-dimensional (3D) fin field-effect transistor (FET) (FinFET) structure and an axis indicating the direction of the force relative to the surface of the semiconductor plate (fin) to improve carrier mobility;

[0012] Figure 2 This is an example of a 3D gate all around (GAA) FET structure and an axis indicating the direction of the force relative to the surface of the semiconductor plate (nanosheet) to improve carrier mobility;

[0013] Figure 3It is a top view of a 3D complementary metal-oxide-semiconductor (MOS) (CMOS) FinFET circuit structure, including exemplary gate cutouts formed in the gate adjacent to the semiconductor plate (e.g., fin) to apply force to the gate so that the gate applies force to the channel region in two (2) different directions.

[0014] Figure 4 These are cross-sectional side views of an NMOS FinFET and a PMOS FinFET, each including a gate notch, the gate notch including a gate notch wall and a gate notch wedge, so that the gate applies forces to the fins in a first direction and a second direction.

[0015] Figure 5 It is a top view of a CMOS GAA FET structure that includes NMOS nanosheet stacks and PMOS nanosheet stacks, as well as gate notches to improve carrier mobility;

[0016] Figure 6 This is a cross-sectional side view of a first example of a CMOS circuit including an NMOS GAA FET and a PMOS GAA FET, each comprising two nanosheet stacks and a gate notch, wherein the gate notch includes a gate notch wall and a gate notch wedge to apply forces to the nanosheets in a first direction and a second direction.

[0017] Figure 7 This is a cross-sectional side view of a second example of a CMOS circuit including an NMOS GAA FET and a PMOS GAA FET, each comprising two nanosheet stacks and a gate notch, wherein the gate notch includes a gate notch wall and a gate notch wedge to apply forces to the nanosheets in a first direction and a second direction.

[0018] Figure 8 This illustrates the fabrication of a 3D FET (including) comprising a gate notch formed adjacent to a semiconductor substrate (e.g., a nanosheet) to apply forces to the channel region in both directions to improve carrier mobility. Figures 3 to 7 A flowchart of a method (either PFET or NFET);

[0019] Figures 9A to 9D and Figures 10A to 10D This includes gate cutouts in the gate adjacent to the semiconductor plate (e.g., fins and nanosheets) to apply forces to the channel region in both directions to improve carrier mobility, and according to Figures 11A to 11D Exemplary manufacturing stages during the fabrication of 3D FETs (FinFET and GAA FET, respectively) in an exemplary manufacturing process;

[0020] Figures 11A to 11D This illustrates the fabrication of 3D FETs (including but not limited to) that include gate notches to improve carrier mobility. Figures 3 to 7 A flowchart of another exemplary manufacturing process for a 3D FET (as shown in the figure) is as follows: Figures 9A to 10D exemplified;

[0021] Figure 12 This is a block diagram of an exemplary wireless communication device including a radio frequency (RF) component that may include a 3D FET, the 3D FET including a gate cutout in a gate formed adjacent to a semiconductor plate (e.g., a nanosheet) to apply forces to the channel region in two directions to improve carrier mobility and increase drive strength, including but not limited to... Figures 3 to 7 3D FET in, and according to, but not limited to Figure 8 and Figures 11A to 11D Any of the exemplary manufacturing processes for manufacturing such 3D FETs; and

[0022] Figure 13 This is a block diagram of an exemplary processor-based system that may include a 3D dual complementary circuit structure, including a 3D FET. The 3D FET includes a gate cutout in a gate adjacent to a channel region, such that the gate applies forces to a semiconductor substrate in two directions to improve carrier mobility and increase drive strength, including but not limited to... Figures 3 to 7 3D FET in, and according to, but not limited to Figure 8 and Figures 11A to 11D Any of the exemplary manufacturing processes used to manufacture such 3D FETs. Detailed Implementation

[0023] Several exemplary aspects of this disclosure are described with reference to the accompanying drawings. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0024] The aspects disclosed in the detailed description include three-dimensional (3D) field-effect transistors (FETs) with gate notches to enhance carrier mobility. Related methods for fabricating 3D FETs including gate notches to enhance carrier mobility are also disclosed. Although the semiconductor plates (e.g., fins) in a fin-type FET (FinFET) and the semiconductor plates (e.g., nanosheets) in a gate-all-around (GAA) FET are oriented along different planes of the crystal structure of the semiconductor wafer, applying a force in the channel region in the same direction relative to the surface of such plates can improve carrier mobility in both types of 3D FETs. In the exemplary 3D FETs disclosed herein, a gate notch in the gate adjacent to the channel region includes a gate notch wall and a gate notch wedge to apply a first force in a first direction to the channel region of the semiconductor plate and a second force in a second direction orthogonal to the first direction to the channel region of the semiconductor plate to improve carrier mobility, thereby increasing the drive strength of the 3D FET. The first and second forces are applied orthogonally and complementary to each other to enhance carrier mobility, thereby achieving a drive strength greater than that achievable by either force alone. For example, the gate notch may include a gate notch wall of a first gate notch material such that the gate applies the first force to the channel region of the semiconductor substrate in a first direction. In a further example, the gate notch may also include a gate notch wedge to apply the first force to the channel region of the semiconductor substrate in the first direction and to apply a second force to the channel region of the semiconductor substrate in a second direction, further improving carrier mobility. In some examples, the 3D FET may be a P-type FET or an N-type FET, and the 3D FET may be one of a FinFET or a GAA FET. In some examples, the 3D complementary metal-oxide-semiconductor (CMOS) FET may include an NFET and a PFET, each including a gate notch to improve drive strength.

[0025] exist Figure 3 Before discussing examples of 3D FETs that include gate notches to apply forces to the gate so that complementary forces are applied to the channel region in two (2) different directions orthogonal to each other, we should first relate to Figure 1 and Figure 2 Examples of 3D FETs that do not include gate cutouts formed in the gate adjacent to the semiconductor plate are discussed below.

[0026] In this regard, Figure 1This is an example of a three-dimensional (3D) fin field-effect transistor (FET) structure 100 including semiconductor plates or fins 102A and 102B (collectively referred to as "fin 102") formed from a semiconductor wafer or substrate 104. The 3D FET structure 100 also includes an insulating layer or shallow trench isolation (STI) layer 106 and a gate 108 formed above the fin 102. The gate 108 is formed of a gate material 110 (e.g., polysilicon) disposed on the first surfaces 112A, 114A and the second surfaces 112B, 114B of the fin 102. Figure 1 This includes spatial X, Y, and Z axes, similar to those in a Cartesian coordinate system, to identify spatial orientation. See the accompanying figures (including...) Figure 1 In the example in ), the plane including the X-axis and Y-axis is parallel to the substrate. Figure 1 It also includes axes x1, y1, and z1, which indicate the longitudinal, transverse, and orthogonal directions relative to the first surfaces 112A and 114A and the second surfaces 112B and 114B of the fin 102, respectively. As shown here, since surface 112A is orthogonal to the substrate 104, the spatial Y and Z axes are opposite to the y1 and z1 axes.

[0027] Fins 102 (e.g., semiconductor plate 102) are formed from a semiconductor substrate 104 having a crystal structure 116 in a subtractive process. In some examples, the semiconductor substrate 104 is a slice or wafer of silicon crystal grown with a predetermined crystal orientation. In this respect, the flat surfaces 112A, 114A, 112B, and 114B of the fins 102 correspond to planes in the crystal structure 116 having a Miller index (110). The direction of current through the fins 102 (which is in the x1-axis direction or the longitudinal direction) has <110> The Miller index. The gate 108 extends above the channel regions 118A and 118B of the fin 102 in the z1 axis direction orthogonal to the surfaces 112A, 114A, 112B and 114B of the fin 102. It extends orthogonally to the current direction across the channel regions 118A and 118B in the y1 axis direction or lateral direction.

[0028] Figure 2 This is an example of another 3D FET structure 200, which includes structures also formed from a semiconductor wafer or substrate 204 and having... Figure 1 The 3D FET structure 200 comprises a gate-all-around (GAA) FET with the same crystal structure as the semiconductor plate or nanosheets 202A to 202C (collectively referred to as "nanosheet 202"). The 3D FET structure 200 also includes an STI layer 206 and a gate 208 formed above the nanosheet 202. The gate 208 is formed of a gate material 210 disposed on the first surfaces 212A, 214A, 216A and the second surfaces 212B, 214B, 216B of the nanosheet 202. Figure 2This includes spatial axes X, Y, and Z, and also axes x2, y2, and z2 that respectively indicate the longitudinal, lateral, and orthogonal directions relative to each of surfaces 212A to 216A and 212B to 216B. Here, since surface 212A is parallel to substrate 204, the Y and Z axes are the same as the y2 and z2 axes, respectively. In the remaining figures herein, only spatial axes X, Y, and Z are shown in each example. The orientation of stress relative to the surfaces of the semiconductor plate in the remaining examples can be referred to back to... Figure 1 and Figure 2 Sure.

[0029] Nanosheets 202 are formed from semiconductor substrates 204 using a subtractive process. The direction of current flowing through the nanosheets 202 is either the x2-axis direction or the longitudinal direction, exhibiting [variable characteristics]. <100> The Miller index, which corresponds to Figure 1 The x1 axis direction in the fin 102. However, the first surfaces 212A to 216A and the second surfaces 212B to 216B correspond to a plane with a Miller index of (100). As a reminder, surfaces 112A, 114A, 112B, and 114B of the fin 102 have a Miller index of (110). Therefore, Figure 2 The z2 axis, orthogonal to the first plane 212A to 216A and the second plane 212B to 216B, corresponds to Figure 1 The y1 axis in the middle, and the y2 axis extending across the channel region 218 corresponds to Figure 1 The z1 axis in the equation.

[0030] It has been determined that applying forces in certain directions to the crystal structure of a semiconductor plate in the channel region can improve carrier mobility through the channel region. Additionally, this improvement applies to both N-type metal-oxide-semiconductor (MOS) and P-type MOS devices, where N-type and P-type refer to semiconductor materials that, due to doping with trivalent or pentavalent dopants, have electrons or holes as majority carriers, respectively. While P-type semiconductor plates benefit from compressive forces in one direction, N-type semiconductor plates benefit from tensile forces in that direction, and vice versa.

[0031] although Figure 1 The first surfaces 112A and 112B and the second surfaces 114A and 114B of the fin 102 have the same characteristics as those in the fin 102. Figure 2Different crystal orientations of the nanosheet 202 faces 212A to 216A and 212B to 216B have been found to improve carrier mobility relative to the faces of fin 102 and nanosheet 202, thus increasing device performance. As shown in Table A below, for example, tensile forces in the lateral direction across the first faces 112A and 112B (orthogonal to the current flow direction in the y1 direction) improve carrier mobility in both P-type and N-type silicon fin 102, and tensile forces in the lateral direction across faces 212A to 216A (orthogonal to the y2 direction) also improve carrier mobility in nanosheet 202 (both P-type and N-type). Table A also shows the difference in the type of orthogonal force (i.e., compression or stretching) in the z1 / z2 direction between NMOS and PMOS.

[0032] <![CDATA[ axis ]]> <![CDATA[ NMOS ]]> <![CDATA[ PMOS ]]> <![CDATA[ Vertical ]]> x1 / x2 stretching compression <![CDATA[ Horizontal ]]> y1 / y2 stretching stretching <![CDATA[ orthogonal ]]> z1 / z2 compression stretching

[0033] Table A

[0034] Figure 3 This is a top view of a 3D complementary MOS (CMOS) FinFET structure 300 (FinFET structure 300) including N-type MOS (NMOS) FinFET (NFET) and P-type MOS (PMOS) FinFET (PFET). The FinFET structure 300 is disposed on an integrated circuit (IC) chip 301 and includes a gate 302 and fins 304P(0) to 304P(1) and 304N(0) to 304N(1). In operation, the current I... 300 Fins (e.g., semiconductor plates) 304P(0) to 304P(1) and 304N(0) to 304N(1) flow longitudinally in a first horizontal direction (X-axis direction). Gate 302 extends across fins 304P(0) to 304P(1) and 304N(0) to 304N(1) in a second horizontal direction (Y-axis direction). Gate 302 may be coupled to a metal interconnect layer (not shown) in a third vertical direction (Z-axis direction) via via 305. Dummy gates 306L and 306R extending across fins 304P(0) to 304P(1) and 304N(0) to 304N(1) are electrically inactive.

[0035] The CMOS FinFET structure 300 includes an exemplary gate cutout 308P adjacent to fins 304P(0) to 304P(1) (also referred to as semiconductor plates 304P(0) to 304P(1)) and a gate cutout 308N adjacent to fins 304N(0) to 304N(1). Figure 4 As shown in the cross-sectional view, gate notches 308P and 308N are formed in the gate 302 to include gate notch walls and gate notch wedges that apply force to the gate 302 (see...). Figure 4The gate 302 applies forces to the channel regions 310P and 310N in a first direction and a second direction orthogonal to the first direction to improve the carrier mobility in the fins 304P(0) to 304P(1) and 304N(0) to 304N(1). A gate notch 308P is formed from gate notch material 312P inserted into a slice 314P formed in the gate 302, and a gate notch 308N is formed from gate notch material 312N inserted into a slice 314P in the gate 302. As explained in more detail below, the gate notch materials 312P and 312N each provide one of a tensile force and a compressive force to the gate 302 in a second (Y-axis) direction. The forces applied to the gate 302 by the gate notches 308P and 308N are transferred to the channel regions 310P and 310N. That is, the gate 302 is formed of a gate material 316 (e.g., polysilicon) that does not deform under the force applied by the gate notches 308P and 308N, so as to absorb all the force elastically. More specifically, due to the rigidity of the gate material 316, in response to the force applied at the gate notch 308P, for example, the gate material 316 will provide stress on the channel regions 310P of the fins 304P(0) to 304P(1). Such a force may be either compressive or tensile. In this way, the gate notches 308P and 308N allow the gate 302 to apply forces to the fins 304P(0) to 304P(1) and 304N(0) to 304N(1), respectively. In other words, gate cutouts 308P and 308N can be considered as indirectly applying force to fins 304P(0) to 304P(1) and 304N(0) to 304N(1). Given... Figure 4 More readily understood, the gate notches disclosed herein (such as gate notches 308P and 308N) include features that allow complementary forces to be applied to the fins in two mutually orthogonal directions.

[0036] Figure 4 This is a cross-sectional side view of a CMOS FinFET structure 400 including an NMOS FinFET 401N and a PMOS FinFET 401P. The CMOS FinFET structure 400 may include... Figure 3 The CMOS FinFET structure 300 is described. The NMOS FinFET 401N and PMOS FinFET 401P include semiconductor plates (fins) 402N(1) to 402N(4) and 404P(1) to 402P(4) extending vertically (in the Z-axis direction) from the substrate 404. The fins 402N(1) to 402N(4) and 404P(1) to 402P(4) may be collectively referred to as fins 402N and 402P, respectively. The current I in the fins 402N and 402P... 400In the first direction (X-axis direction), an insulating layer 406 formed of, for example, shallow trench isolation (STI) material 408 (not shown) is disposed on a substrate 404 and covers the non-functional portions 410 of the fins 402N and 402P, which are characteristic of the substrate 404. A gate 412 is disposed above the fins 402N and 402P in the channel regions 414N and 414P. The channel regions 414N and 414P are the regions of the fins 402N and 402P below the gate 412, wherein the gate 412 is disposed on a semiconductor plate (fin) and wherein a voltage applied to the gate 412 can induce a conductive channel below the surface of the semiconductor plate. In the channel regions 414N and 414P, each of the fins 402N includes a first surface 416A opposite to a second surface 416B, and each of the fins 402P includes a first surface 418A opposite to a second surface 418B. Gate 412 is formed of gate material 420 and disposed on the first surface 416A and the second surface 416B of fin 402N and on the first surface 418A and the second surface 418B of fin 402P. Fins 402N and 402P are separated from gate 412 by dielectric layer 422 and work function metal layer 424. The work function metal layer 424 on fin 402N may be different from the work function metal layer 424 on fin 402P.

[0037] To improve carrier mobility in channel regions 414N and 414P (which increases performance, e.g., drive strength), NMOS FinFET 401N and PMOS FinFET 401P respectively include exemplary gate notches 426N and 426P. Gate notches 426N and 426P extend through gate material 420 adjacent to channel regions 414N and 414P of fins 402N and 402P in a second direction (Y-axis direction). Gate notches 426N and 426P allow gate 412 to apply force to channel regions 414N and 414P in the second direction. Specifically, gate notches 426N and 426P include gate notch walls 428N and 428P to apply force FN in the second direction (Y-axis direction), respectively. WL and FP WL Force is applied to gate 412, which in turn applies force to channel regions 414N and 414P. Gate cutouts 426N and 426P also include gate cutout wedges 430N and 430P to distribute force FN. WG and FP WG The force is applied indirectly (via gate 412) to channel regions 414N and 414P, and includes components in a second direction (Y-axis direction) and also in a third direction (Z-axis direction).

[0038] exist Figure 4In this embodiment, a gate notch 426N is disposed in the gate material 420 between fins 402N(2) and fins 402N(3) in a second direction. As further explained below, after a portion or slice 432 of the gate 412 is removed (e.g., by trench etching), the gate material 420 is replaced by a gate notch wall 428N, which may include a first gate notch material 434C that applies a compressive (pushing) force to the gate material 420, or a second gate notch material 434T that applies a tensile (pulling) force to the gate material 420. The gate notch wall 428N extends in a plane P1 orthogonal to the second direction and contacts an insulating layer 406 between the gate 412 and the substrate 404. In this example, the gate notch wall 428N includes a gate notch material 434C as determined by the direction of the force to be applied and the type of MOS material of the NMOS FinFET 401N. As previously mentioned, the gate notch wall 428N applies a force FN in a second direction (Y-axis) orthogonal to the gate notch wall 428N. WL Force FN WL It is also orthogonal (or substantially orthogonal) to planes 416A and 416B, which correspond to Figure 1 The z1 axis direction. Referring back to Table A, in response to the compressive forces orthogonal to surfaces 416A and 416B, the carrier mobility in the NMOS semiconductor board is improved. Therefore, in this example, gate cut material 434C is used in the gate cut wall 428N to reduce the force FN. WL Provides compression force.

[0039] The gate cut-out material 434C is selected from materials known to expand after formation (e.g., after cooling) (e.g., silicon nitride (SiN)). Therefore, the gate cut-out material 434C applies a force orthogonal to the sides S1 / S2 (e.g., pushed into the sides) of the portion or slice 432 removed from the gate 412. In response, the rigid structure of the gate 412 transfers this force in a second direction orthogonal to the surfaces 416A and 416B of the fin 402N. In this way, the gate cut-out wall 428N improves the carrier (electron) mobility in the NMOS semiconductor plate 402N.

[0040] Gate notch 426P includes a gate notch wall 428P corresponding to gate notch wall 428N and is located at the same position relative to fin 402P as gate notch 426N relative to fin 402N. Depending on the magnitude of the force desired for gate notches 426N and 426P, they can be of the same thickness (in the second direction) or different thicknesses. However, unlike gate notch material 434C, gate notch material 434T is used in gate notch wall 428P because it contracts upon cooling, causing it to be pulled inward rather than pushed outward in the direction orthogonal to the sides S1 / S2 of gate 412P. This pulling applies a tensile force to gate 412 in the second direction, which is transferred to the channel region 414P, improving carrier (hole) mobility in PMOS semiconductor plate 402P.

[0041] Continue to refer to Figure 4 In the NMOS FinFET 401N, after removing a portion of the gate notch wall 428N or slice 432 in which the gate 412 may be formed, a void 436 can be formed in the insulating layer 406. In one example, a chemical etchant selectively applied to the insulating material can be introduced into the slice 432. Here, the gate notch wedge 430N is grown as a crystal structure having a first surface 438L and a second surface 438R. The gate notch wedge 430N can be formed from the gate notch material 434C (or a similar material) that forms the gate notch wall 428N to resist force FN WG Applying a compressive force, or using a gate cutout material 434T (or a similar material) to distribute the force FN. WG A tensile force is applied. The force FN applied by the first surface 438L is tensile. WG Includes components in the second direction (Y-axis) and the third direction (Z-axis).

[0042] Figure 4 The second direction in corresponds to Figure 2 The z2 axis direction and Figure 1 The second direction is along the z1 axis, and is orthogonal to surfaces 416A and 416B of fin 402N. The force FN WG A force FN is applied in the second direction to the gate notch wall 428N. WL Therefore, the first force applied by the gate cutout 426N in the second direction includes a first portion in the second direction (i.e., force FN). WL ) and the second part in the second direction (i.e., force FN) WG (the amount). Figure 4 The second force (i.e., force FN) is applied in the third direction by the gate cutout 426N. WG The components in the third direction) respectively correspond to Figure 1and Figure 2 The cross surfaces 416A and 416B are orthogonal to the y1 and y2 axes in the current flow direction (X-axis direction). The vertical force component (third direction) of the gate cutout wedge 430N on the gate 412 generates a tensile force (e.g., pull-up) in the third direction on the fin 402N. Force FN WG The two components (directions) improve carrier mobility in fin 402N.

[0043] In the PMOS FinFET 401P, the force FP WL It is orthogonal to planes 418A and 418B (e.g., in...). Figure 1 A tensile force in the z1-axis direction (i.e., the second direction) is applied to improve carrier mobility in fin 402P. Therefore, the gate cut-out wall 428P is formed of gate cut-out material 434T. Referring again to Table A, both NMOS and PMOS semiconductor plates respond to lateral tensile forces (e.g., in the z1-axis direction) to improve carrier mobility in fin 402P. Figure 1 The gate cut-out wedge 430P provides improved carrier mobility in the y1-axis direction (as shown in the diagram), and this lateral tensile force can be provided by the gate cut-out wedge 430P. Therefore, the gate cut-out wedge 430P in the gate cut-out 426P is formed of a first gate cut-out material 434C. In this case, the gate cut-out wall 428P and the gate cut-out wedge 430P are formed of different materials, such that the gate cut-out wall 428P applies a tensile force in the second direction, while the force FP applied by the gate cut-out wedge 430P... WG The component in the second direction is compressive. In this respect, the force FP... WG Some of the forces FP of the gate notch wall 428P can be offset in the second direction. WL Although the gate notch wedge 430P can reduce the beneficial force provided by the gate notch wall 428P in the second direction, given the tensile force FP indirectly applied to the fin 402P in the third direction (laterally) by the gate notch wedge 430P via the gate 412, WG The improvement in carrier mobility provided by the component is a satisfactory trade-off.

[0044] Figure 5 This is a top view of a CMOS gate-all-around (GAA) FET structure 500 (GAA FET structure 500) including an NFET 502N and a PFET 502P. The GAA FET structure 500 is included in an IC chip 501 and includes a gate 504, a nanosheet 506N in the NFET 502N, and a nanosheet 506P in the PFET 502P. In operation, the current I... 500Nanosheets (e.g., semiconductor plates) 506P and 506N flow longitudinally in a first horizontal direction (X-axis direction). A gate 504 extends across nanosheets 506N and 506P in a second horizontal direction (Y-axis direction). The gate 504 may be coupled to a metal interconnect (not shown) in a third vertical direction (Z-axis direction) via a via 508. The GAA FET structure 500 also includes dummy gates 510L and 510R, which may be electrically inactive.

[0045] The GAA FET structure 500 also includes a gate cutout 512N in the gate 504 adjacent to the channel region 514N of the nanosheet 506N and a gate cutout 512P in the gate 504 adjacent to the channel region 514P of the nanosheet 506P. (See reference...) Figure 6 In more detail, gate cutouts 512N and 512P apply force in the second direction (Y-axis direction) to improve carrier mobility in both NMOS and PMOS semiconductor plates.

[0046] Figure 6 Yes, it can include Figure 5 A cross-sectional side view of a first example of a CMOS GAA FET structure (GAA FET structure 600) of the GAA FET structure 500. The GAA FET structure 600 includes a GAA NFET 602N and a GAA PFET 602P having vertically stacked nanosheets 604N(1) to 604N(6) and 604P(1) to 604P(6), respectively. The nanosheets 604N(1) to 604N(6) and 604P(1) to 604P(6) may be collectively referred to as nanosheets 604N and 604P, respectively. Figure 6 The cross-sectional side view is a cross-section along the gate 606 in a second direction (Y-axis direction) and a third direction (Z-axis direction), the gate extending through the channel regions 608N of nanosheets 604N(1) to 604N(6) and the channel regions 608P of nanosheets 604P(1) to 604P(6). The gate 606 includes a gate material 607. A voltage applied to the gate 606 can induce a conductive channel in faces 610A and 610B of nanosheet 604N, and alternatively, a conductive channel can be induced in faces 612A and 612B of nanosheet 604P.

[0047] The GAA FET structure 600 includes a gate cutout 614N disposed between nanosheets 604N(1) to 604N(3) and nanosheets 604N(4) to 604N(6), and a gate cutout 614P disposed between nanosheets 604P(1) to 604P(3) and nanosheets 604P(4) to 604P(6). The gate cutout 614N includes a gate cutout wall 616N, which causes the gate 606 to apply force FN in a second direction (Y-axis).WL Applied to gate 606, the second direction is transverse to or across current I. 600 direction ( Figure 2 (y2 axis in the table). As indicated in Table A, tensile force in the lateral direction provides a beneficial improvement to carrier mobility in an NMOS semiconductor plate, regardless of whether the NMOS semiconductor plate is a fin or a nanosheet. Therefore, the gate cut-out wall 616N is formed of gate cut-out material 618T to apply force FN in the second direction (Y-axis direction). WL A tensile force is applied so that the gate 606 applies force to the nanosheet 604P in the channel region 608N. The gate cut-out material 618T may be a stretching oxide (e.g., SiO2) or another material that shrinks in size after cooling following deposition. The gate cut-out material 618T applies a tensile or pulling force to the gate 606, which in turn applies a tensile or pulling force in a second direction (laterally), thereby causing corresponding forces on the nanosheets 604N(1) to 604N(3) and 604N(4) to 604N(6).

[0048] A GAA FET structure 600 is formed on a substrate 620 and includes an insulating layer (e.g., an STI layer) 622 between the substrate 620 and nanosheets 604N and 604P. The gate notch 614N also includes a gate notch wedge 624N disposed in the insulating layer 622 between the gate notch wall 616N and the substrate 620. The gate notch wedge 624N includes faces 626L and 626R, each providing upward force components in a second direction and a third direction. As mentioned in Table A, the beneficial force directions orthogonal to faces 610A and 610B in the NMOS semiconductor plate are compressive. Therefore, the gate notch wedge 624N is formed using a gate notch material 618C to apply an upward (vertical) force. Although the gate cut wedge 624N formed of the gate cut material 618C also has a compressive component in the second direction, which is opposite to the beneficial tensile force provided by the gate cut wall 616N, this can be considered a satisfactory trade-off given the benefits provided by the compressive force orthogonal to surfaces 610A and 610B in the third direction. In this respect, the gate cut material 618T in the gate cut wedge 624N is configured to apply a first force component in the second direction and a second force component in the third direction, both of which are compressive forces.

[0049] As mentioned in Table A, the tensile force in the second direction (transverse to nanosheets 604N and 604P) is beneficial to both the NMOS and PMOS semiconductor substrates. Therefore, the gate notch 614P includes a gate notch wall 616P also formed of gate notch material 618T to absorb the force FP in the second direction. WLA tensile force is applied. Compared to the gate cutout wedge 624N that provides compressive force on the nanosheet 604N in a third-order direction, the gate cutout wedge 624P of the gate cutout 614P is formed of gate cutout material 618T to apply force FP in a third-order direction orthogonal to the faces 612A and 612B of the nanosheet 604P. WG A tensile force is applied. The gate cut-out wedge 624P includes surfaces 628L and 628R that have components in a third direction and also in a second direction. Here, surfaces 628L and 628R assist the gate cut-out wall 628P in providing a tensile force in the second direction.

[0050] Figure 7 This is a cross-sectional side view of a second example of a CMOS GAA FET circuit structure 700 (GAA FET structure 700) including NMOS nanosheets 702N(1) to 702N(6) (nanosheet 702N) and PMOS nanosheets 702P(1) to 702P(6) (nanosheet 702P). The GAA FET structure 700 includes a gate 704 disposed above the channel regions 706N and 706P of the nanosheets 702N and 702P. A gate notch 708N is disposed between the NMOS nanosheets 702N(1) to 702N(3) and the nanosheets 702N(4) to 702N(6) to apply forces in a second direction and a third direction upward to improve carrier mobility. Except for the gate notch 708N, the GAA FET structure 700 is similar to Figure 6 The GAA FET structure in this model is the same as that in the 600 series. (Similar to...) Figure 6 The gate cut wall 616N is formed of gate cut material 618T to distribute force FN in the second direction. WL The gate cutout 614N and gate cutout 708N, which are subjected to tensile force, also include a force FN selected to apply force in a second direction. WL A gate cut-out wall 710N is formed from a gate cut-out material 712T (or a similar material) to which a tensile force is applied. However, unlike the gate cut-out wedge 624N formed from a gate cut-out material 618C to provide a compressive force, the gate cut-out wedge 714N is formed from the gate material 712T to apply a force FN having a tensile component in both the second and third directions. WG The tensile force in the second direction contributes to the force FN applied in the second direction by the gate cutout wall 710N. WL The component of the tensile force applied upwards by a third party to the NMOS nanosheet 702N is... Figure 6 The forces acting on the NMOS nanosheet 604N in the third direction are opposite. In some examples, the forces from the gate cut-out wedge 714N are opposite. Figure 7 The third-party upward tensile force component can provide more than Figure 6The upward component applied further improves carrier mobility. In some examples, the upward tensile force FN applied by the third party... WG It can provide a higher ratio to nanosheets 702N(1) to 702N(6). Figure 6 The compressive force FN in WG Further improvements.

[0051] Figure 8 This illustrates the fabrication of a 3D FET structure including a gate notch formed adjacent to a semiconductor substrate to allow the gate to apply forces to the channel region to improve carrier mobility. Figures 3 to 7 A flowchart of method 800 (which describes a FET structure in the diagram). The method includes forming at least one semiconductor plate 402N, 604N, each semiconductor plate including: a channel region 414N, 608N configured to conduct current in a first direction (X-axis direction); and a first surface 416A, 610A and a second surface 416B, 610B (frame 802) opposite to each other; and forming gates 412, 606 extending in a second direction (Y-axis direction) orthogonal to the first direction, the gates 412, 606 including at least one of the semiconductor plates 402N, 604N disposed in the channel regions 414N, 608N. Gate materials 420 and 607 (box 804) on first surfaces 416A, 610A and second surfaces 416B, 610B; and gate cutouts 426N and 614N (box 806) formed in the gate materials 420 and 607 extending in a second direction through the channel regions 414N and 608N adjacent to at least one semiconductor plate 402N and 604N, wherein the gate cutouts 426N and 614N are configured to cause the gates 412 and 606 to apply a first force in the second direction to the channel regions 414N and 608N of at least one semiconductor plate 402N and 604N.

[0052] Figures 9A to 9D It includes a gate cutout in the gate and adjacent to a semiconductor plate (e.g., a fin) to apply a force that improves carrier mobility. Figure 3 and Figure 4 The CMOS FinFET structure in, and according to Figures 11A to 11D The exemplary manufacturing stage during 3D FinFET manufacturing is shown in the flowchart of the exemplary manufacturing process 1100. Figures 10A to 10D In GAA FET (including Figures 5 to 7 In the GAA FET structure, a gate notch is fabricated adjacent to the gate to improve carrier mobility in the corresponding manufacturing stage, and can also be based on... Figures 11A to 11D The manufacturing process is carried out in 1100.

[0053] Figure 9AThis is a cross-sectional side view of a FinFET structure 900 in a first manufacturing stage 900A in the channel region 902 of a semiconductor plate (fin) 904 formed on a substrate 906. The channel region 902 is configured to conduct current in the fin 904 in a first direction. The FinFET structure 900 includes an insulating layer 908 formed on the substrate 906, a dielectric layer 910 formed on the fin 904, and a work function layer 912 formed on the dielectric layer 910. The FinFET structure 900 also includes a gate 914 disposed in the channel region 902 above the semiconductor plate 904 in a second direction. The gate 914 is also disposed on the insulating layer 908. Figures 9B to 9D The FinFET structure in the 900 is still in use. Figure 9A The features shown are marked as the same.

[0054] Figure 10A This is a cross-sectional side view of a GAA FET structure 1000 in the first manufacturing stage 1000A of a semiconductor plate (nanosheet) 1004 formed on a substrate 1006, in the channel region 1002. The channel region 1002 is configured to conduct current in the nanosheet 1004 in a first direction. The GAA FET structure 1000 includes an insulating layer 1008 disposed on the substrate 1006, a dielectric layer 1010 formed on the nanosheet 1004, and a work function layer 1012 formed on the dielectric layer 1010. The GAA FET structure 1000 also includes a gate 1014 disposed in the channel region 1002 above the semiconductor plate 1004 in a second direction. The gate 1014 is also formed on the insulating layer 1008. Figures 10B to 10D The features of the GAA FET structure 1000 shown in Figure 10 are also marked as the same.

[0055] like Figure 11A As shown, it forms as Figure 9A and Figure 10A The gate cutouts 915 and 1015 shown (see) Figure 9C / Figure 9D and Figure 10C / Figure 10D The method includes step 1100A of forming slices 916 and 1016 through gates 914 and 1014 and through insulating layers 908 and 1008 adjacent to channel regions 902 and 1002 of semiconductor substrates 904 and 1004. Masks 918 and 1018 may be used on gates 914 and 1014 to determine the location of slices 916 and 1016. In some examples, optional extensions 920 and 1020 of slices 916 and 1016 may extend into substrates 906 and 1006. Slices 916 and 1016 extend along a plane P1 orthogonal to a second direction. Figure 9A and Figure 10A It also shows that it can be based on Figure 11A The method described above includes optional extensions 920 and 1020 of slices 916 and 1016. Slices 916 and 1016 extend on a plane P1 orthogonal to the second direction.

[0056] Figure 9B and Figure 10B Examples based on Figure 11B The method illustrated includes a second manufacturing stage 900B and 1000B for the FinFET structure 900 and GAA FET structure 1000. The method also includes forming gaps 922 and 1022 in the insulating layers 908 and 1008 that are wider in a second direction than the slices 916 and 1016 in the gates 914 and 1014.

[0057] Figure 9C and Figure 10C Examples based on Figure 11C The method illustrated includes third manufacturing stages 900C and 1000C of the FinFET structure 900 and GAA FET structure 1000. The method further includes forming gate notches 915, 1015 in voids 922, 1022 and in slices 916, 1016. Forming the gate notches includes forming gate notch wedges 924, 1024 comprising first gate notch materials 926, 1026 in voids 922, 1022. In cases where slices 916, 1016 include extensions 920, 1020, the extensions 920, 1020 are also filled with the first gate notch materials 926, 1026.

[0058] Figure 9D and Figure 10D Examples based on Figure 11D The methods illustrated herein represent the fourth manufacturing stages 900D and 1000D of the FinFET structure 900 and GAA FET structure 1000. The method of forming gate notches 915, 1015 includes forming gate notch walls 928, 1028 comprising second gate notch materials 930, 1030 in slices 916, 1016. In some examples, the first gate notch materials 926, 1026 are the same as the second gate notch materials 930, 1030.

[0059] Electronic devices including 3D FETs can be provided in or integrated into any processor-based device, wherein the 3D FET includes Figures 3 to 7The gate notch in the gate adjacent to the channel region, according to any aspect disclosed herein, allows the gate to apply forces to the semiconductor plate to improve carrier mobility and increase drive strength. Examples, not limited to, include: set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, Session Initiation Protocol (SIP) phones, tablet computers, phablets, servers, computers, portable computers, mobile computing devices, laptop computers, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multirotor aircraft.

[0060] In this regard, Figure 12 This block diagram illustrates an exemplary wireless communication device 1200 including radio frequency (RF) components formed from one or more ICs 1202, wherein any of the ICs 1202 may include an integrated circuit including a 3D FET, the 3D FET including Figures 3 to 7 The gate notch in the gate adjacent to the channel region, according to any aspect disclosed herein, allows the gate to apply forces to the semiconductor plate to improve carrier mobility and increase drive strength. Wireless communication device 1200 may include or be provided as an example of any of the aforementioned devices. Figure 12 As shown, the wireless communication device 1200 includes a transceiver 1204 and a data processor 1206. The data processor 1206 may include memory for storing data and program code. The transceiver 1204 includes a transmitter 1208 and a receiver 1210 supporting bidirectional communication. Generally, the wireless communication device 1200 may include any number of transmitters 1208 and / or receivers 1210 for any number of communication systems and frequency bands. All or part of the transceiver 1204 may be implemented on one or more analog ICs, RF ICs (RFICs), mixed-signal ICs, etc.

[0061] The transmitter 1208 or receiver 1210 can be implemented using a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal undergoes multi-stage frequency conversion between RF and baseband, for example, from RF to intermediate frequency (IF) in one stage and then from IF to baseband in another stage. In a direct conversion architecture, the signal is converted between RF and baseband in a single stage. Superheterodyne and direct conversion architectures can use different circuit blocks and / or have different requirements. Figure 12 In the wireless communication device 1200, the transmitter 1208 and the receiver 1210 are implemented using a direct frequency conversion architecture.

[0062] In the transmission path, data processor 1206 processes the data to be transmitted and provides I and Q analog output signals to transmitter 1208. In the exemplary wireless communication device 1200, data processor 1206 includes digital-to-analog converters (DACs) 1212(1) and 1212(2) to convert digital signals generated by data processor 1206 into I and Q analog output signals (e.g., I and Q output currents) for further processing.

[0063] Within transmitter 1208, low-pass filters 1214(1) and 1214(2) filter the I and Q analog output signals, respectively, to remove unwanted signals caused by the previous digital-to-analog conversion. Amplifiers (AMPs) 1216(1) and 1216(2) amplify the signals from low-pass filters 1214(1) and 1214(2), respectively, and provide I and Q baseband signals. Upconverter 1218 upconverts the I and Q baseband signals using the I and Q TX LO signals from transmit (TX) local oscillator (LO) signal generator 1222 via mixers 1220(1) and 1220(2) to provide upconverted signal 1224. Filter 1226 filters the upconverted signal 1224 to remove unwanted signals caused by upconversion and noise in the receive band. Power amplifier (PA) 1228 amplifies the upconverted signal 1224 from filter 1226 to obtain the desired output power level and provide the transmit RF signal. The RF signal is routed through the duplexer or switch 1230 and transmitted via the antenna 1232.

[0064] In the receiving path, antenna 1232 receives signals transmitted by the base station and provides the received RF signal, which is routed through duplexer or switch 1230 and provided to low-noise amplifier (LNA) 1234. Duplexer or switch 1230 is designed to operate using a specific receive (RX) to TX duplexer frequency separation, such that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 1234 and filtered by filter 1236 to obtain the desired RF input signal. Downconversion mixers 1238(1) and 1238(2) mix the output of filter 1236 with the I and Q RX LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 1240 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMPs 1242(1) and 1242(2) and further filtered by low-pass filters 1244(1) and 1244(2) to obtain I and Q analog input signals, which are provided to data processor 1206. In this example, data processor 1206 includes analog-to-digital converters (ADCs) 1246(1) and 1246(2) to convert the analog input signals into digital signals to be further processed by data processor 1206.

[0065] exist Figure 12 In the wireless communication device 1200, a TX LO signal generator 1222 generates I and Q TXLO signals for up-conversion, while an RX LO signal generator 1240 generates I and Q RX LO signals for down-conversion. Each LO signal is a periodic signal with a specific base frequency. A TX phase-locked loop (PLL) circuit 1248 receives timing information from a data processor 1206 and generates control signals for adjusting the frequency and / or phase of the TX LO signals from the TX LO signal generator 1222. Similarly, an RXILL circuit 1250 receives timing information from a data processor 1206 and generates control signals for adjusting the frequency and / or phase of the RX LO signals from the RX LO signal generator 1240.

[0066] Figure 13 A block diagram illustrating an example of a processor-based system 1300, which may employ components such as... Figures 3 to 7The integrated circuit of the 3D FET in the process includes a gate cutout in the gate adjacent to the channel region to apply force to the semiconductor plate to improve carrier mobility and increase drive strength. In this example, the processor-based system 1300 includes one or more central processing units (CPUs) 1302, which may also be referred to as CPUs or processor cores, each CPU or processor core including one or more processors 1304. The CPU 1302 may have a cache memory 1306 coupled to the processor 1304 for fast access to temporarily stored data. The CPU 1302 is coupled to a system bus 1308 and may interactively couple to master and slave devices included in the processor-based system 1300. As is well known, the CPU 1302 communicates with these other devices by exchanging address, control, and data information on the system bus 1308. For example, the CPU 1302 may communicate a bus transaction request to a memory controller 1310, which is an example of a slave device. Although in Figure 13 Not illustrated, but multiple system buses 1308 may be provided, each of which constitutes a different texture.

[0067] Other master and slave devices can be connected to system bus 1308. For example... Figure 13 As illustrated, by way of example, these devices may include a memory system 1312 (which includes a memory controller 1310 and one or more memory arrays 1314), one or more input devices 1316, one or more output devices 1318, one or more network interface devices 1320, and one or more display controllers 1322. Input devices 1316 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. Output devices 1318 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. Network interface devices 1320 may be any device configured to allow data exchange to and from network 1324. Network 1324 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), Bluetooth, etc. ™ Networks and the Internet. The network interface device 1320 can be configured to support any type of communication protocol desired.

[0068] CPU 1302 can also be configured to access display controller 1322 via system bus 1308 to control information transmitted to one or more displays 1326. Display controller 1322 transmits information to be displayed to displays 1326 via one or more video processors 1328, which process the information to be displayed into a format suitable for displays 1326. Displays 1326 may include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, or light-emitting diode (LED) displays.

[0069] Those skilled in the art will further understand that the various exemplary logic blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein can be implemented as electronic hardware, instructions stored in memory, or in another computer-readable medium, wherein any such instructions are executed by a processor or other processing device or a combination of both. As an example, the devices and components described herein can be used in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any desired information. To clearly illustrate this interchangeability, the functionality of the various exemplary components, blocks, modules, circuits, and steps has been generally described above. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be construed as departing from the scope of this disclosure.

[0070] The various exemplary logic blocks, modules, and circuits described in conjunction with the aspects disclosed herein may be implemented or executed using a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic unit, discrete hardware component, or any combination thereof, designed to perform the functions described herein. The processor may be a microprocessor, but in alternative embodiments, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors cooperating with a DSP core, or any other such configuration).

[0071] The aspects disclosed herein can be embodied in hardware and instructions stored in the hardware, and can reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Alternatively, the storage medium may be integral with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and storage medium may reside as discrete components in a remote station, base station, or server.

[0072] It should also be noted that the operational steps described in any of the exemplary aspects of this document are described for the purpose of providing examples and discussion. The described operations may be performed in many different orders other than the order illustrated. Furthermore, the operations described in a single operational step may actually be performed in multiple different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It will be understood that, as will be apparent to those skilled in the art, many different modifications may be made to the operational steps illustrated in the flowcharts. Those skilled in the art will also understand that various techniques and methods can be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0073] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0074] Specific implementation examples are described in the following numbered clauses:

[0075] 1. A three-dimensional (3D) field-effect transistor (FET) structure, said three-dimensional (3D) field-effect transistor (FET) structure comprising:

[0076] At least one semiconductor plate, each semiconductor plate including a channel region configured to conduct current in a first direction;

[0077] A gate extending in a second direction orthogonal to the first direction, the gate comprising a gate material disposed on the at least one semiconductor plate in the channel region; and

[0078] A gate cutout extending in the second direction through the gate material adjacent to the channel region of the at least one semiconductor plate;

[0079] The gate cutout is configured such that the gate applies a first force to the channel region of the at least one semiconductor plate in the second direction and applies a second force to the channel region of the at least one semiconductor plate in a third direction orthogonal to the second direction.

[0080] 2. The 3D FET structure according to Clause 1, wherein the gate notch includes a gate notch wall configured to allow the gate to apply the first force in the second direction as a first portion.

[0081] 3. The 3D FET structure according to Clause 2, wherein the gate cut-out further comprises a gate cut-out wedge configured to cause the gate to apply a second portion of the first force to the channel region of the at least one semiconductor plate in the second direction, and to cause the gate to apply the second force to the channel region of the at least one semiconductor plate in the third direction.

[0082] 4. The 3D FET structure according to Clause 3, wherein the gate cut-out wall includes a first gate cut-out material, the first gate cut-out material being configured to apply a first force, including a compressive force, to the gate in the first portion.

[0083] 5. The 3D FET structure according to Clause 4, wherein the gate cut-out wedge includes a second gate cut-out material configured to apply the first force to the gate in a second portion and to each of the second force including a compressive force.

[0084] 6. The 3D FET structure according to Clause 5, wherein:

[0085] The gate notch wall comprises silicon nitride (SiN); and

[0086] The gate notch wedge includes SiN.

[0087] 7. The 3D FET structure according to Clause 4, wherein the gate cut-out wedge includes a second gate cut-out material configured to apply the first force to the gate in a second portion and to each of the second force including a tensile force.

[0088] 8. The 3D FET structure according to Clause 7, wherein:

[0089] The gate notch wall comprises silicon nitride (SiN); and

[0090] The gate cut-out wedge includes silicon dioxide (SiO2).

[0091] 9. The 3D FET structure according to Clause 3, wherein the gate cut-out wall includes a first gate cut-out material configured to apply a first portion of a first force including a tensile force to the gate.

[0092] 10. The 3D FET structure according to Clause 9, wherein the gate cut-out wedge includes a second gate cut-out material configured to apply the first force to the gate in a second portion and to each of the second force including a tensile force.

[0093] 11. The 3D FET structure according to Clause 10, wherein:

[0094] The gate notch wall comprises silicon dioxide (SiO2); and

[0095] The gate notch wedge includes SiO2.

[0096] 12. The 3D FET structure according to Clause 9, wherein the gate cut-out wedge includes a second gate cut-out material configured to apply the first force to the gate in a second portion and to each of the second force including a compressive force.

[0097] 13. The 3D FET structure according to Clause 12, wherein:

[0098] The gate notch wall comprises silicon dioxide (SiO2); and

[0099] The gate notch wedge includes silicon nitride (SiN).

[0100] 14. The 3D FET structure according to any one of clauses 3 to 13, wherein the 3D FET structure further comprises:

[0101] Substrate; and

[0102] An insulating layer disposed between the gate and the substrate in the third-party orientation;

[0103] The gate cutout wedge is disposed in the insulating layer between the gate cutout wall and the substrate.

[0104] 15. The 3D FET structure according to Clause 14, wherein:

[0105] The gate notch wedge includes a gate notch material having a first surface; and

[0106] The force applied by the first surface of the gate cut-out wedge includes components in the second direction and in the third direction.

[0107] 16. The 3D FET structure according to Clause 15, wherein the gate cutout material is in contact with the insulating layer between the gate and the substrate.

[0108] 17. The 3D FET structure according to any one of Clauses 1 to 16, wherein the gate material is disposed between the gate cutout and the at least one semiconductor plate.

[0109] 18. The 3D FET structure according to any one of clauses 1 to 17, wherein:

[0110] The 3D FET structure includes a FinFET; and

[0111] The at least one semiconductor plate includes at least one fin.

[0112] 19. The 3D FET structure according to any one of clauses 1 to 17, wherein:

[0113] The 3D FET structure includes a gate-all-around (GAA) field-effect transistor (FET); and

[0114] The at least one semiconductor plate includes at least one nanosheet.

[0115] 20. The 3D FET structure according to any one of Clauses 1 to 19, wherein the 3D FET structure is integrated into a device selected from the group consisting of: set-top boxes; entertainment units; navigation devices; communication devices; fixed location data units; mobile location data units; global positioning system (GPS) devices; mobile phones; cellular phones; smartphones; session initiation protocol (SIP) phones; tablet computers; tablet phones; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants (PDAs); monitors; computer monitors; televisions; tuners; radios; satellite radios; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; unmanned aerial vehicles; and multirotor aircraft.

[0116] 21. A method for manufacturing a three-dimensional (3D) field-effect transistor (FET) structure, the method comprising:

[0117] At least one semiconductor plate is formed, each semiconductor plate including a channel region configured to conduct current in a first direction;

[0118] A gate is formed, the gate extending in a second direction orthogonal to the first direction, the gate comprising a gate material disposed on the at least one semiconductor plate in the channel region; and

[0119] A gate cutout is formed, the gate cutout extending in the second direction through the gate material adjacent to the channel region of the at least one semiconductor plate;

[0120] The gate cutout is configured such that the gate applies a first force to the channel region of the at least one semiconductor plate in the second direction and applies a second force to the channel region of the at least one semiconductor plate in a third direction orthogonal to the second direction.

[0121] 22. The method according to Clause 21, wherein:

[0122] Forming the at least one semiconductor plate further includes:

[0123] A first semiconductor plate is formed on a substrate; and

[0124] An insulating layer is disposed on the substrate; and

[0125] Forming the gate also includes forming the gate on the insulating layer.

[0126] 23. The method according to Clause 22, further comprising:

[0127] A slice is formed through the gate and the insulating layer to the substrate adjacent to the channel region of the at least one semiconductor plate;

[0128] A gap wider than the slice is formed in the insulating layer in the second direction; and

[0129] The gate cutout is formed in the gap and in the slice.

[0130] 24. The method described according to Clause 23, wherein:

[0131] Forming the slice further includes forming the slice extending along a plane orthogonal to the second direction; and

[0132] Forming the gate cutout in the gap and in the slice also includes:

[0133] A gate cut-wedge comprising a first gate cut-out material is formed in the gap; and

[0134] A gate cut wall comprising a second gate cut material is formed in the slice on the gate cut wedge.

[0135] 25. A complementary metal-oxide-semiconductor (CMOS) circuit structure, the complementary metal-oxide-semiconductor (CMOS) circuit structure comprising:

[0136] At least one first semiconductor board, each first semiconductor board comprising:

[0137] Type I dopant;

[0138] A first channel region, the first channel region being configured to conduct a first current in a first direction;

[0139] The first source / drain region is located on the first side of the first channel region; and

[0140] The second source / drain region is located on the second side of the first channel region;

[0141] A first gate extends in a second direction orthogonal to the first direction, and the first gate includes gate material disposed on each of the at least one first semiconductor plate in the first channel region;

[0142] A first gate cutout extends in the second direction through the first gate adjacent to the first channel region of the at least one first semiconductor plate;

[0143] At least one second semiconductor board, each second semiconductor board comprising:

[0144] Type II dopant;

[0145] A second channel region, the second channel region being configured to conduct a second current in the first direction;

[0146] The third source / drain region is located on the first side of the second channel region; and

[0147] A fourth source / drain region, wherein the fourth source / drain region is located on the second side of the second channel region;

[0148] A second gate, the second gate extending in the second direction and including the gate material disposed on each of the at least one second semiconductor plate in the second channel region; and

[0149] A second gate cutout extends in the second direction through the second gate adjacent to the second channel region of the at least one second semiconductor plate.

[0150] in:

[0151] The first gate notch is configured such that the first gate applies a first force to the first channel region of the at least one first semiconductor plate in the second direction and applies a second force to the first channel region of the at least one first semiconductor plate in a third direction orthogonal to the second direction; and

[0152] The second gate notch is configured to apply a third force to the second channel region of the at least one second semiconductor plate in the second direction and a fourth force to the second channel region of the at least one second semiconductor plate in the third direction.

[0153] 26. The CMOS circuit structure according to Clause 25, wherein:

[0154] The at least one first semiconductor plate includes a first fin and a second fin doped with the first type of dopant and separated from each other in the second direction; and

[0155] The at least one second semiconductor plate includes a third fin and a fourth fin doped with a second type of dopant that is different from the first type of dopant, the third fin and the fourth fin being separated from each other in the second direction;

[0156] in:

[0157] The first gate cut includes a first gate cut wall disposed between the first fin and the second fin, and the second gate cut includes a second gate cut wall disposed between the third fin and the fourth fin;

[0158] The first gate notch wall includes a first gate notch material;

[0159] The second gate notch wall includes a second gate notch material; and

[0160] The first gate cut material is different from the second gate cut material.

[0161] 27. The CMOS circuit structure according to Clause 26, further comprising:

[0162] Substrate; and

[0163] An insulating layer is disposed, in the third-party direction, between the first gate and the substrate and between the second gate and the substrate;

[0164] in:

[0165] The first gate notch further includes a first gate notch wedge disposed in the insulating layer between the first gate notch wall and the substrate;

[0166] The second gate notch further includes a second gate notch wedge disposed in the insulating layer between the second gate notch wall and the substrate; and

[0167] The first gate cut wedge and the second gate cut wedge include the first gate cut material.

[0168] 28. The CMOS circuit structure according to Clause 25, wherein:

[0169] The at least one first semiconductor plate comprises a first nanosheet stack and a second nanosheet stack separated from each other in the second direction; and

[0170] The at least one second semiconductor plate includes a third nanosheet stack and a fourth nanosheet stack separated from each other in the second direction;

[0171] in:

[0172] The first gate cut includes a first gate cut wall disposed between the first nanosheet stack and the second nanosheet stack, and the second gate cut includes a second gate cut wall disposed between the third nanosheet stack and the fourth nanosheet stack;

[0173] The first gate notch wall includes a first gate notch material;

[0174] The second gate notch wall includes a second gate notch material; and

[0175] The first gate cut material is the same as the second gate cut material.

[0176] 29. The CMOS circuit structure according to Clause 28, further comprising:

[0177] Substrate; and

[0178] An insulating layer is disposed, in the third-party direction, between the first gate and the substrate and between the second gate and the substrate;

[0179] in:

[0180] The first gate notch further includes a first gate notch wedge disposed in the insulating layer between the first gate notch wall and the substrate;

[0181] The second gate notch further includes a second gate notch wedge disposed in the insulating layer between the second gate notch wall and the substrate;

[0182] The first gate cut wedge includes the first gate cut material;

[0183] The second gate cut-out wedge includes a third gate cut-out material; and

[0184] The first gate cut material is different from the third gate cut material.

[0185] 30. The CMOS circuit structure according to Clause 28, further comprising:

[0186] Substrate; and

[0187] An insulating layer is disposed, in the third-party direction, between the first gate and the substrate and between the second gate and the substrate;

[0188] in:

[0189] The first gate notch further includes a first gate notch wedge disposed in the insulating layer between the first gate notch wall and the substrate;

[0190] The second gate notch further includes a second gate notch wedge disposed in the insulating layer between the second gate notch wall and the substrate;

[0191] The first gate notch wedge and the material including the first gate notch; and

[0192] The second gate cut wedge includes the second gate cut material.

Claims

1. A three-dimensional (3D) field effect transistor (FET) structure, the three-dimensional (3D) field effect transistor (FET) structure comprising: at least one semiconductor plate, each semiconductor plate including a channel region configured to conduct electrical current in a first direction; a gate extending in a second direction orthogonal to the first direction, the gate including a gate material disposed on the at least one semiconductor plate in the channel region; and a gate cut extending in the second direction through the gate material adjacent to the channel region of the at least one semiconductor plate; wherein the gate cut is configured to cause the gate to exert a first force on the channel region of the at least one semiconductor plate in the second direction and a second force on the channel region of the at least one semiconductor plate in a third direction orthogonal to the second direction.

2. The 3D FET structure of claim 1, wherein the gate cut includes a gate cut wall configured to cause the gate to exert a first portion of the first force in the second direction.

3. The 3D FET structure of claim 2, wherein the gate cut further includes a gate cut wedge configured to cause the gate to exert a second portion of the first force on the channel region of the at least one semiconductor plate in the second direction and the second force on the channel region of the at least one semiconductor plate in the third direction.

4. The 3D FET structure of claim 3, wherein the gate cut wall includes a first gate cut material configured to cause the gate to exert the first portion of the first force including a compressive force.

5. The 3D FET structure of claim 4, wherein the gate cut wedge includes a second gate cut material configured to cause the gate to exert each of the second portion of the first force and the second force including a compressive force.

6. The 3D FET structure of claim 5, wherein: the gate cut wall includes silicon nitride (SiN); and the gate cut wedge includes SiN.

7. The 3D FET structure of claim 4, wherein the gate cut wedge includes a second gate cut material configured to cause the gate to exert each of the second portion of the first force and the second force including a tensile force.

8. The 3D FET structure of claim 7, wherein: the gate cut wall includes silicon nitride (SiN); and the gate cut wedge includes silicon dioxide (SiO2).

9. The 3D FET structure of claim 3, wherein the gate cut wall includes a first gate cut material configured to cause the gate to exert the first portion of the first force including a tensile force. ​ 10. The 3D FET structure of claim 9, wherein the gate cut wedge comprises a second gate cut material configured to cause each of the second portion of the first force and the second force comprising a tensile force to be exerted by the gate.

11. The 3D FET structure of claim 10, wherein: the gate cut wall comprises silicon dioxide (Si02); and the gate cut wedge comprises Si02.

12. The 3D FET structure of claim 9, wherein the gate cut wedge comprises a second gate cut material configured to cause each of the second portion of the first force and the second force comprising a compressive force to be exerted by the gate.

13. The 3D FET structure of claim 12, wherein: the gate cut wall comprises silicon dioxide (Si02); and the gate cut wedge comprises silicon nitride (SiN).

14. The 3D FET structure of claim 3, further comprising: a substrate; and an insulating layer disposed between the gate and the substrate in the third direction; wherein the gate cut wedge is disposed in the insulating layer between the gate cut wall and the substrate.

15. The 3D FET structure of claim 14, wherein: the gate cut wedge comprises a gate cut material having a first surface; and a force exerted by the first surface of the gate cut wedge comprises a component in the second direction and in the third direction.

16. The 3D FET structure of claim 15, wherein the gate cut material is in contact with the insulating layer between the gate and the substrate.

17. The 3D FET structure of claim 1, wherein the gate material is disposed between the gate cut and the at least one semiconductor plate.

18. The 3D FET structure of claim 1, wherein: the 3D FET structure comprises a fin field effect transistor (FinFET); and the at least one semiconductor plate comprises at least one fin.

19. The 3D FET structure of claim 1, wherein: the 3D FET structure comprises a gate all around (GAA) field effect transistor (FET); and the at least one semiconductor plate comprises at least one nanosheet.

20. The 3D FET structure of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computer; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a transportation component; avionics systems; a drone; and a multicopter.

21. A method of fabricating a three-dimensional (3D) field effect transistor (FET) structure, the method comprising: forming at least one semiconductor plate, each semiconductor plate including a channel region configured to conduct electrical current in a first direction; forming a gate, the gate extending in a second direction orthogonal to the first direction, the gate including a gate material disposed on the at least one semiconductor plate in the channel region; and forming a gate cutout, the gate cutout extending in the second direction through the gate material adjacent the channel region of the at least one semiconductor plate; wherein the gate cutout is configured to cause the gate to exert a first force on the channel region of the at least one semiconductor plate in the second direction and a second force on the channel region of the at least one semiconductor plate in a third direction orthogonal to the second direction.

22. The method of claim 21, wherein: forming the at least one semiconductor plate further comprises: forming a first semiconductor plate on a substrate; and disposing an insulating layer on the substrate; and forming the gate further comprises forming the gate on the insulating layer.

23. The method of claim 22, the method further comprising: forming a slice through the gate and the insulating layer to the substrate adjacent the channel region of the at least one semiconductor plate; forming a void in the insulating layer wider than the slice in the second direction; and forming the gate cutout in the void and in the slice.

24. The method of claim 23, wherein: forming the slice further comprises forming the slice extending along a plane orthogonal to the second direction; and forming the gate cutout in the void and in the slice further comprises: forming a gate cutout wedge comprising a first gate cutout material in the void; and forming a gate cutout wall comprising a second gate cutout material in the slice on the gate cutout wedge. ​ 25. A complementary metal-oxide-semiconductor (CMOS) circuit structure, the complementary metal-oxide-semiconductor (CMOS) circuit structure comprising: at least one first semiconductor plate, each first semiconductor plate comprising: a first-type dopant; a first channel region configured to conduct a first current in a first direction; a first source / drain region on a first side of the first channel region; and a second source / drain region on a second side of the first channel region; a first gate extending in a second direction orthogonal to the first direction, the first gate comprising a gate material disposed on each of the at least one first semiconductor plate in the first channel region; a first gate cut extending in the second direction through the first gate adjacent to the first channel region of the at least one first semiconductor plate; at least one second semiconductor plate, each second semiconductor plate comprising: a second-type dopant; a second channel region configured to conduct a second current in the first direction; a third source / drain region on a first side of the second channel region; and a fourth source / drain region on a second side of the second channel region; a second gate extending in the second direction and comprising the gate material disposed on each of the at least one second semiconductor plate in the second channel region; and a second gate cut extending in the second direction through the second gate adjacent to the second channel region of the at least one second semiconductor plate, wherein: the first gate cut is configured to cause the first gate to exert a first force on the first channel region of the at least one first semiconductor plate in the second direction and a second force on the first channel region of the at least one first semiconductor plate in a third direction orthogonal to the second direction; and the second gate cut is configured to cause the second gate to exert a third force on the second channel region of the at least one second semiconductor plate in the second direction and a fourth force on the second channel region of the at least one second semiconductor plate in the third direction.

26. The CMOS circuit structure of claim 25, wherein: the at least one first semiconductor plate comprises a first fin and a second fin doped with the first-type dopant and separated from one another in the second direction; and the at least one second semiconductor plate comprises a third fin and a fourth fin doped with the second-type dopant different from the first-type dopant, the third fin and the fourth fin separated from one another in the second direction; wherein: the first gate cutout includes a first gate cutout wall disposed between the first fin and the second fin, and the second gate cutout includes a second gate cutout wall disposed between the third fin and the fourth fin; the first gate cutout wall includes a first gate cutout material; the second gate cutout wall includes a second gate cutout material; and the first gate cutout material is different than the second gate cutout material.

27. The CMOS circuit structure of claim 26, further comprising: a substrate; and an insulating layer disposed between the first gate and the substrate and between the second gate and the substrate in the third direction; wherein: the first gate cutout further includes a first gate cutout wedge in the insulating layer disposed between the first gate cutout wall and the substrate; the second gate cutout further includes a second gate cutout wedge in the insulating layer disposed between the second gate cutout wall and the substrate; and the first gate cutout wedge and the second gate cutout wedge include the first gate cutout material.

28. The CMOS circuit structure of claim 25, wherein: the at least one first semiconductor plate includes a first nanoplate stack and a second nanoplate stack separated from one another in the second direction; and the at least one second semiconductor plate includes a third nanoplate stack and a fourth nanoplate stack separated from one another in the second direction; wherein: the first gate cutout includes a first gate cutout wall disposed between the first nanoplate stack and the second nanoplate stack, and the second gate cutout includes a second gate cutout wall disposed between the third nanoplate stack and the fourth nanoplate stack; the first gate cutout wall includes a first gate cutout material; the second gate cutout wall includes a second gate cutout material; and the first gate cutout material is the same as the second gate cutout material.

29. The CMOS circuit structure of claim 28, further comprising: a substrate; and an insulating layer disposed between the first gate and the substrate and between the second gate and the substrate in the third direction; wherein: the first gate cutout further includes a first gate cutout wedge in the insulating layer disposed between the first gate cutout wall and the substrate; the second gate cutout further includes a second gate cutout wedge in the insulating layer disposed between the second gate cutout wall and the substrate; the first gate cutout wedge includes the first gate cutout material; the second gate cutout wedge includes a third gate cutout material; and the first gate cutout material is different than the third gate cutout material.

30. The CMOS circuit structure of claim 28, further comprising: a substrate; and an insulating layer disposed between the first gate and the substrate and between the second gate and the substrate in the third direction; wherein: The first gate cut further includes a first gate cut wedge disposed in the insulating layer between the first gate cut wall and the substrate; The second gate cut further includes a second gate cut wedge disposed in the insulating layer between the second gate cut wall and the substrate; The first gate cut wedge comprises the first gate cut material; and The second gate cut wedge comprises the second gate cut material.

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