High-speed data communication method and system based on synchronous triggering and parallel transmission

Abstract

This invention relates to the field of embedded system technology, providing a high-speed data communication method and system based on synchronous triggering and parallel transmission. The method includes: configuring a master timer, multiple slave timers, and a corresponding number of DMA channels in an MCU, and setting up a data buffer for each DMA channel; configuring the master timer to generate a synchronous trigger signal for the target sampling rate, driving all slave timers to generate synchronous update events with sequentially delayed phases as parallel DMA trigger signals; using these signals to control each DMA channel to transmit external device data alternately and in parallel to the corresponding area of ​​the buffer; and finally, reassembling the data from multiple areas according to the phase order of the update events to restore the complete sampling sequence. This invention overcomes the rate bottleneck of a single DMA channel, utilizing the aggregated bandwidth of multiple DMA channels to achieve high sampling rate data acquisition far exceeding the limit of a single DMA channel under limited hardware resources, effectively improving the system's data throughput.

Description

Technical Field

[0001] This invention relates to embedded systems, particularly to the fields of digital signal processing, high-speed data acquisition, and industrial control, and especially to a high-speed data communication method and system based on synchronous triggering and parallel transmission. Background Technology

[0002] In modern embedded systems, especially in signal processing, high-speed data acquisition, and industrial control, MCUs need to frequently and rapidly read data from external analog-to-digital converters (ADCs) or other parallel interface devices. Traditional reading methods typically use a single timer (TIM) to generate the sampling clock, coupled with a single DMA channel to move data from peripherals (such as the data register of a parallel ADC) to memory. This approach offers a simple system architecture, but its maximum sustainable sampling rate is limited by the highest operating frequency of the single DMA channel. For example, the theoretical maximum transmission frequency of a single DMA channel in the AT32F403A series MCU with a clock frequency of 240MHz is approximately 27MHz. When applications require higher sampling rates (e.g., 48MHz), this traditional single-timer-single-DMA architecture becomes a performance bottleneck and cannot meet the demands. While using a higher-level MCU with stronger DMA performance is one solution, it significantly increases system costs. Therefore, how to break through the performance limit of a single DMA channel and achieve higher data throughput with limited hardware resources has become a pressing technical problem. Summary of the Invention

[0003] To address the shortcomings of the existing technologies, this invention provides a high-speed data communication method and system based on synchronous triggering and parallel transmission. This method can decompose a single high-speed data stream into multiple parallel data streams for processing, thereby breaking through the rate bottleneck of a single DMA channel. By utilizing the aggregated bandwidth of multiple DMA channels, it ultimately achieves high sampling rate data reading and reconstruction that far exceeds the limit of a single DMA channel.

[0004] In a first aspect, the high-speed data communication method based on synchronous triggering and parallel transmission provided by the present invention includes:

[0005] In a microcontroller unit (MCU), a master timer, multiple slave timers, and multiple direct memory access (DMA) channels corresponding to the number of slave timers are configured. In the MCU memory, a data buffer corresponding to each DMA channel is set. Each data buffer corresponds to an independent storage area, and each storage area corresponds to the destination address of a DMA channel.

[0006] The master timer is configured to generate a synchronous trigger signal for the target sampling rate, and all slave timers are configured to generate multiple synchronous update events with sequentially delayed phases based on the synchronous trigger signal, serving as multiple parallel DMA trigger signals; using the DMA trigger signals, the corresponding DMA channels are controlled to transfer data from external devices to their respective corresponding storage areas in the data buffer in parallel and alternately.

[0007] Based on the phase delay order of the timer update events, the data stored in the multiple storage areas are time-series reassembled to restore the complete sampling sequence defined by the target sampling rate.

[0008] Secondly, the present invention provides a high-speed data communication system based on synchronous triggering and parallel transmission, wherein the high-speed data communication system based on synchronous triggering and parallel transmission uses the above-mentioned high-speed data communication method based on synchronous triggering and parallel transmission.

[0009] Compared with the prior art, the beneficial effects of this invention are as follows:

[0010] This invention provides a high-speed data communication method and system based on synchronous triggering and parallel transmission. The method includes: configuring a master timer, multiple slave timers, and multiple direct memory access (DMA) channels corresponding to the number of slave timers in a microcontroller unit (MCU); setting a data buffer corresponding to each DMA channel in the MCU memory, with each data buffer corresponding to an independent storage area, and each storage area corresponding to the destination address of a DMA channel; configuring the master timer to generate a synchronous trigger signal for a target sampling rate, and configuring all slave timers to generate multiple synchronous and sequentially phase-delayed update events based on the synchronous trigger signal, as multiple parallel DMA trigger signals; using the DMA trigger signals to control the corresponding DMA channels to transmit data from external devices in parallel and alternately to their respective corresponding storage areas in the data buffers; and performing time-series reassembly on the data stored in the multiple storage areas based on the phase delay order of the slave timer update events to reconstruct the complete sampling sequence defined by the target sampling rate. This invention configures a master timer, multiple slave timers, and multiple DMA channels, sets up logically partitioned buffers, and synchronously triggers the slave timers to generate phase delay update events based on the master timer to control the parallel and alternating transmission of data by the DMA channels. Finally, it performs timing reassembly according to the phase order, which can decompose a single high-speed data stream into multiple parallel data streams for processing. This breaks through the rate bottleneck of a single DMA channel and utilizes the aggregate bandwidth of multiple DMA channels to ultimately achieve high sampling rate data reading and reconstruction that far exceeds the limit of a single DMA channel. Attached Figure Description

[0011] The accompanying drawings are provided to further illustrate the invention and are not intended to unduly limit the scope of the invention. Specific embodiments of the invention will be described in detail below with reference to the accompanying drawings by way of example rather than limitation. The same reference numerals in the drawings designate the same or similar parts or components. It should be understood by those skilled in the art that these drawings are not necessarily drawn to scale.

[0012] Figure 1 This is a flowchart illustrating a high-speed data communication method based on synchronous triggering and parallel transmission according to an embodiment of the present invention.

[0013] Figure 2 This is a waveform diagram of the DMA trigger signals formed by four sequentially delayed phases of update events from four slave timers within the same master timer cycle, as shown in this embodiment of the invention.

[0014] Figure 3 This is a schematic diagram illustrating the state of time-series reorganization of data stored in multiple storage areas according to an embodiment of the present invention. Detailed Implementation

[0015] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0016] Example 1

[0017] See Figures 1-3 This embodiment provides a high-speed data communication method based on synchronous triggering and parallel transmission, including the following steps:

[0018] S101. Configure a master timer, multiple slave timers, and multiple direct memory access (DMA) channels corresponding to the number of slave timers in the microcontroller unit (MCU). Set a data buffer for each DMA channel in the MCU memory. Each data buffer corresponds to an independent storage area, and each storage area corresponds to the destination address of a DMA channel.

[0019] S102. Configure the master timer to generate a synchronous trigger signal for the target sampling rate, and configure all slave timers to generate multiple synchronous update events with sequentially delayed phases based on the synchronous trigger signal, as multiple parallel DMA trigger signals; use the DMA trigger signal to control the corresponding DMA channel to transfer data from the external device to their respective corresponding storage areas in the data buffer in parallel and alternately.

[0020] S103. Based on the phase delay order of the timer update events, the data stored in the multiple storage areas are time-series reassembled to restore the complete sampling sequence defined by the target sampling rate.

[0021] It should be noted that in this embodiment, hardware resource configuration can be performed in the microcontroller unit (MCU). Taking the AT32F403A MCU as an example, one master timer TMR4 and four slave timers TMR8, TMR5, TMR3, and TMR1 are configured. Simultaneously, four DMA channels are configured accordingly: DMA1 channel 3, DMA1 channel 5, DMA2 channel 1, and DMA2 channel 2. A contiguous large array is selected in the MCU's memory as a data buffer, and logically divided into four independent storage regions of equal length (segment 1 to segment 4). Each region is specifically allocated to a DMA channel as its transmission destination address. Next, timer synchronization and trigger configuration can be performed. The master timer TMR4 is configured in trigger output (TRGO) mode, its clock source is set to the system clock frequency of 240MHz, and by setting the divider to 0 (no division) and the automatic reload register (ARR) to 4, it generates a square wave signal with a frequency of 48MHz (240MHz / 5) as the synchronization trigger signal. All four slave timers (TMR8, TMR5, TMR3, TMR1) are configured as slaves, and the master timer TMR4 is selected as its trigger input (ITRx) clock source, thus achieving hardware-level synchronization between all slave timers and the master timer. Then, DMA transfer is configured. Each slave timer update event is used as a unique trigger source and associated with its corresponding DMA channel: TMR3 update events trigger DMA1 channel 3, TMR5 update events trigger DMA2 channel 2, TMR1 update events trigger DMA1 channel 5, and TMR8 update events trigger DMA2 channel 1. The source address of all DMA channels is configured to the address of the GPIO input data register connected to the external ADC data bus, and the destination address points to the four pre-allocated memory areas in the buffer. Finally, data reconstruction is performed. After sampling, the data in the four memory areas is an interleaved subsequence separated by DMA channels. Data points are extracted from each segment in chronological order and concatenated according to the triggering order of the slave timer update events (TMR3 first, then TMR5, then TMR1, and finally TMR8). Specifically, the first point of segment 1 (the first sampling point), the first point of segment 2 (the second sampling point), the first point of segment 3 (the third sampling point), and the first point of segment 4 (the fourth sampling point) are extracted sequentially. Then, the second point of segment 1 (the fifth sampling point) is extracted, and so on, until a complete sampling sequence with equal time intervals of 48MHz is finally restored.

[0022] It should be noted that in this embodiment, by configuring a master timer, multiple slave timers, and multiple DMA channels, setting up a data buffer corresponding to each DMA channel, and each data buffer corresponding to an independent storage area, and by synchronously triggering the slave timers to generate phase delay update events based on the master timer to control the parallel and alternating transmission of data by the DMA channels, and finally performing timing reassembly according to the phase order, it is possible to decompose a single high-speed data stream into multiple parallel data streams for processing, thereby breaking through the rate bottleneck of a single DMA channel, utilizing the aggregated bandwidth of multiple DMA channels, and ultimately achieving high sampling rate data reading and reconstruction that far exceeds the limit of a single DMA.

[0023] Preferably, configuring all slave timers to generate the update event includes: configuring all slave timers to use the synchronization trigger signal of the master timer as the clock source, and setting the same auto-reload value and different counter initial values ​​for each slave timer, so that all slave timers generate synchronized update events with sequentially delayed phases.

[0024] It should be noted that when configuring update events from slave timers, the specific implementation can be as follows: All slave timers (TMR8, TMR5, TMR3, TMR1) use the 48MHz synchronous trigger signal generated by the master timer TMR4 as their clock source. To achieve phase delay, all slave timers are set to the same auto-reload value (ARR = 3), enabling them to generate an update frequency of 12MHz (48MHz / 4). The key phase control is achieved by setting different initial values ​​for the counters (CNT) for each slave timer: the initial CNT value for TMR1 is set to 0, for TMR5 to 1, for TMR3 to 2, and for TMR8 to 3. In this way, within the same master timer cycle, the update events of the four slave timers will occur sequentially at 1 / 48MHz time intervals, forming four synchronous but sequentially phase-delayed DMA trigger signal streams.

[0025] It should be noted that in this embodiment, by configuring all slave timers to use the master timer's synchronization trigger signal as the clock source, and setting the same auto-reload value and different counter initial values ​​for each slave timer, it is possible to enable all slave timers to generate update events with the same frequency but sequentially delayed phases while maintaining strict synchronization.

[0026] Preferably, when controlling the parallel and alternating transmission of data from external devices, the method includes: uniquely associating the trigger source of each DMA channel with an update event of a slave timer, configuring the source address of each DMA channel as the data register address of the external device, and configuring the destination address as the corresponding storage area in the data buffer, so that during the duration of the synchronization trigger signal, each DMA channel is started sequentially to complete the parallel and alternating transmission of data from the external device.

[0027] It should be noted that the specific implementation for controlling parallel and alternating data transmission is as follows: A strict one-to-one correspondence is established between timer update events and DMA channels. The update event of TMR3 triggers DMA1 channel 3, moving data to the first segment of the buffer; the update event of TMR5 triggers DMA2 channel 2, moving data to the second segment of the buffer; the update event of TMR1 triggers DMA1 channel 5, moving data to the third segment of the buffer; and the update event of TMR8 triggers DMA2 channel 1, moving data to the fourth segment of the buffer. During the duration of the 48MHz synchronization trigger signal, these four DMA channels are started sequentially and independently, transferring the parallel data stream from the external ADC to four different areas of memory in an alternating manner, achieving parallel transmission and avoiding data overwriting.

[0028] It should be noted that in this embodiment, the trigger source of each DMA channel is uniquely associated with an update event of a slave timer, and its source / destination address is pointed to the corresponding storage area of ​​the external device data register and the buffer, respectively. This enables the independent and automated operation of multiple DMA channels, so that the continuous data stream from the external device can be automatically and orderly distributed to different storage areas in memory according to the phase relationship of the timer.

[0029] Preferably, configuring the master timer to generate a synchronous trigger signal for the target sampling rate includes: configuring the clock source of the master timer as the system clock of the MCU; controlling the frequency division and counting of the system clock by setting the frequency divider parameters and auto-reload register parameters of the master timer, so that it generates a square wave signal with a frequency equal to the target sampling rate at the trigger output terminal; the square wave signal is input to all slave timers as the synchronous trigger signal, and output to external devices through the MCU's GPIO pins as the conversion clock of the external devices, so as to ensure that the data reading timing of the MCU is synchronized with the sampling timing of the external devices.

[0030] It should be noted that the specific implementation for configuring the master timer can be as follows: The clock source for the master timer TMR4 directly uses the MCU's 240MHz system clock. By setting its prescaler (PSC) register to 0 (i.e., a division of 1, the clock frequency remains 240MHz) and setting the automatic reload register (ARR) to 4, TMR4 generates an update event every 5 clock pulses (from 0 to 4). This update event is configured as a trigger output (TRGO), thereby generating a precise 48MHz square wave signal on the TRGO pin of TMR4. This signal is sent as a synchronization trigger signal to each of the internal slave timers, and also output through a GPIO pin of the MCU (such as PA8) to the conversion clock (CLK) input of the external ADC chip, thus ensuring that the sampling and reading rhythm inside the MCU is strictly synchronized with the conversion rhythm of the external ADC.

[0031] It should be noted that in this embodiment, the master timer is configured to generate a square wave signal with a frequency equal to the target sampling rate. This signal is input to the slave timer on one hand and output to the external device on the other hand as its conversion clock. This can realize that the sampling and reading timing of the MCU and the data conversion timing of the external device originate from the same clock reference, thereby realizing hard synchronization between the MCU and the external device and fundamentally eliminating sampling timing errors or jitter that may be caused by asynchronous clock sources.

[0032] Preferably, before all slave timers generate multiple synchronous and sequentially phase-delayed update events based on the synchronous trigger signal, the process includes: configuring the master timer to trigger output mode and setting its trigger output source to update events; simultaneously, configuring each slave timer to slave mode and selecting the master timer as its trigger input source; and each synchronous trigger signal pulse generated by the master timer directly resets or starts the counters of all slave timers.

[0033] It should be noted that timer synchronization can be implemented as follows: Utilize the MCU's internal timer synchronization hardware link. Configure the master timer TMR4 in trigger output (TRGO) mode and set its TRGO signal source to update events. Simultaneously, configure each slave timer (TMR8, TMR5, TMR3, TMR1) in slave mode and select internal trigger 1 (ITR1) as its trigger input signal source (TS). This ITR1 is mapped to the master timer TMR4 internally within the MCU. Through this hardware connection, each time the master timer TMR4 generates an update event (i.e., a 48MHz pulse), it directly resets the counters of all slave timers, forcing them to restart counting from their initial values. This achieves hard synchronization of all timer counting operations, eliminating software-induced delays and jitter.

[0034] It should be noted that in this embodiment, configuring the master timer as the trigger output mode and configuring the slave timer as the slave mode and selecting the master timer as the trigger input source can realize the use of the hardware synchronization link inside the MCU to enable the update event pulse of the master timer to directly reset or start the counters of all slave timers, thereby achieving hardware-level, software-delay-free, precise synchronization of all timer counting operations and reducing timing jitter.

[0035] Preferably, the number of slave timers is N, where N is an integer greater than 1; the target sampling rate is Fs, and the frequency of update events generated by each slave timer is Fs / N; by configuring N slave timers to generate update events with sequentially delayed phases, the N corresponding DMA channels can operate in parallel at an operating frequency of Fs / N, thereby achieving a data throughput rate N times that of a single DMA channel operating frequency.

[0036] It should be noted that in this specific example, the number of timers N=4, and the target sampling rate Fs=48MHz. With the above configuration, the update event frequency generated by each timer is Fs / N=12MHz. These four phase-interleaved 12MHz DMA trigger signals enable the four DMA channels to operate in parallel at a frequency of 12MHz each. Since the theoretical limit of a single DMA channel on the AT32F403A is approximately 27MHz, traditional architectures cannot achieve 48MHz sampling. However, this method, by having four DMA channels operate alternately in parallel, increases the overall data throughput to four times the operating frequency of a single DMA channel, thus achieving the target sampling rate of 48MHz and breaking through the performance bottleneck of a single DMA channel.

[0037] It should be noted that in this embodiment, N slave timers are set, each generating an update event at a frequency of Fs / N, and their phases are sequentially delayed. This can evenly distribute the data throughput pressure of the target sampling rate Fs across the N DMA channels, so that each DMA channel only needs to work at a lower frequency of Fs / N. Finally, through the parallel cooperation of the N channels, the total system data throughput is N times that of the operation frequency of a single DMA channel.

[0038] Preferably, when setting different initial counter values ​​for each slave timer, the method includes: uniformly setting the auto-reload value of all slave timers to M-1, so that the counting period of each slave timer is M synchronous trigger signal clock cycles, and setting the initial counter values ​​of N slave timers to 0, 1, 2, ..., N-1 in sequence, where M = N, so that the update events of the N slave timers occur in the same master timer period, staggered by a time interval of one synchronous trigger signal clock cycle.

[0039] It should be noted that when setting the slave timer parameters to achieve precise phase delay, the specific implementation can be as follows: The automatic reload (ARR) value of the four slave timers (N=4) is uniformly set to 3 (i.e., M-1=3, M=4), so the counting period of each slave timer is 4 master timer clock cycles (i.e., 4 1 / 48MHz time intervals). Subsequently, the initial values ​​of the counters (CNT) of the four slave timers are set to 0, 1, 2, and 3 respectively. Since M=4 equals N=4, this ensures that the update events of the four slave timers occur sequentially within the same master timer cycle (1 / 48MHz). Specifically, TMR1 with an initial CNT value of 0 reaches the ARR first and generates an update, followed by TMR5 with an initial CNT value of 1, then TMR3 with an initial CNT value of 2, and finally TMR8 with an initial CNT value of 3. The time interval between adjacent update events is exactly 1 / 48MHz.

[0040] It should be noted that in this embodiment, the automatic reload value of all slave timers is uniformly set to M-1, and the initial values ​​of the counters of N slave timers are set to 0, 1, 2, ..., N-1 in sequence. This can enable the update events of N slave timers to occur sequentially and evenly within the same master timer cycle, with the time interval between adjacent events fixed as one clock cycle of the synchronization trigger signal, thereby generating multiple DMA trigger signals that are absolutely uniformly distributed on the time axis.

[0041] Preferably, the mapping relationship between the multiple independent storage areas of the data buffer and the DMA channels is determined according to the order in which their corresponding timer update events occur: the DMA channel with the earliest update event corresponds to the first segment of the buffer's starting address, the DMA channel with the second earliest update event corresponds to the next segment, and so on; each DMA channel uses a cyclic overwrite or incremental transmission mode within its destination address range to independently transfer data, so as to ensure that the data of multiple DMA channels will not overwrite each other during high-speed continuous transmission.

[0042] It should be noted that the specific implementation for establishing the buffer mapping relationship can be as follows: The mapping between the DMA channel and the buffer storage area is determined based on the actual occurrence order of the timer update events (TMR3 first, TMR5 second, TMR1 third, TMR8 fourth). Therefore, DMA1 channel 3, driven by the first triggered TMR3, is assigned to the first segment (0-1 / 4) of the buffer's starting address. DMA2 channel 2, driven by the second triggered TMR5, is assigned to the immediately adjacent second segment (1 / 4-2 / 4). Subsequent segments follow the same pattern. Each DMA channel is configured in circular buffer or address increment mode within its assigned destination address range, independently and continuously transmitting data. This ensures that the four data streams do not overlap during long-term, high-speed data acquisition, completely recording the interleaved sampling subsequences.

[0043] It should be noted that in this embodiment, the mapping relationship between the DMA channel and the buffer storage area is determined according to the order of occurrence of the timer update events, and each DMA channel adopts a cyclic overlay or incremental transmission mode within its address range. This can realize the establishment of an independent and ordered storage space for each interleaved sampled data subsequence in physical memory, ensuring that the data streams do not overwrite each other during continuous high-speed data transmission, and completely preserving the time sequence information of the data.

[0044] Preferably, the external device is a high-speed parallel interface analog-to-digital converter (ADC). The ADC is connected to a set of GPIO ports of the MCU. The source address of the DMA channel is configured as the input data register address of the set of GPIO ports, so that the DMA can directly capture parallel data at the GPIO ports and move it to memory without CPU intervention.

[0045] It should be noted that the external device can specifically be a high-speed parallel ADC chip, such as the 3PA1030. The parallel data output bus of this ADC is directly connected to a set of GPIO ports of the MCU (e.g., pins 0-7 of GPIOA). During DMA configuration, the source address of each DMA channel does not point to a specific peripheral's dedicated register, but is uniformly set to the address of the input data register corresponding to that set of GPIO ports (e.g., GPIOA→IDR). In this way, when the ADC conversion is complete and data appears on the GPIO pin, the DMA can directly capture this parallel data from the GPIO's input data register and, triggered by a timer, efficiently move it to the specified location in memory without any CPU intervention or copy instructions, achieving real-time, lossless acquisition of data from external devices.

[0046] It should be noted that in this embodiment, the external high-speed parallel ADC is connected to the GPIO port of the MCU, and the source address of the DMA channel is configured as the input data register address of the GPIO port. This enables the DMA controller to directly capture parallel data from the GPIO port, eliminating the CPU's involvement in data transfer. This achieves the most direct and fastest real-time acquisition of external ADC data and reduces the system CPU load.

[0047] Preferably, the timing reassembly includes: determining a fixed sequence of occurrences of the timer update events; sequentially extracting the first data point from each of the storage regions according to the fixed sequence to form the first X points of the complete sampling sequence, where X is the number of storage regions; again sequentially extracting the second data point from each of the storage regions according to the same fixed sequence to form the next X points of the complete sampling sequence; repeating this process until all data points have been extracted and spliced ​​together to reconstruct the complete sampling sequence defined by the target sampling rate.

[0048] It should be noted that the specific implementation method of the timing reassembly can be as follows: First, a fixed triggering sequence of timer update events is determined according to the hardware configuration. For example, the fixed triggering sequence is TMR3→TMR5→TMR1→TMR8. During reassembly, according to this fixed order, the first data point is extracted sequentially from segment 1 corresponding to DMA1_3 (this is the first point of the complete sequence), the first data point is extracted from segment 2 corresponding to DMA2_2 (the second point), the first data point is extracted from segment 3 corresponding to DMA1_5 (the third point), and the first data point is extracted from segment 4 corresponding to DMA2_1 (the fourth point). This constitutes the first 4 (X=4) points of the complete sampling sequence. Then, again according to the order of TMR3→TMR5→TMR1→TMR8, the second data point is extracted sequentially from the four segments to form the 5th, 6th, 7th, and 8th points of the sequence. This cyclic extraction process is repeated until all data points are processed, and the final spliced ​​sequence is the complete sampling sequence of 48MHz with equal time intervals.

[0049] It should be noted that in this embodiment, by determining a fixed sequence of update events from the timer and cyclically extracting data points from each storage area according to this sequence and splicing them together, it is possible to accurately restore the interleaved data subsequences that are collected in parallel by multiple DMA channels and stored separately in physical memory into a single data sequence that corresponds one-to-one with the original high-speed sampling in time, and with equal time intervals.

[0050] Example 2

[0051] See Figures 1-3This embodiment provides a high-speed data communication system based on synchronous triggering and parallel transmission. The high-speed data communication system based on synchronous triggering and parallel transmission uses any of the high-speed data communication methods based on synchronous triggering and parallel transmission in the above embodiments.

[0052] It should be noted that the above embodiments are merely preferred embodiments of the present invention, and the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention, and the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A high-speed data communication method based on synchronous triggering and parallel transmission, characterized in that, include: In a microcontroller unit (MCU), a master timer, multiple slave timers, and multiple direct memory access (DMA) channels corresponding to the number of slave timers are configured. In the MCU memory, a data buffer corresponding to each DMA channel is set. Each data buffer corresponds to an independent storage area, and each storage area corresponds to the destination address of a DMA channel. The master timer is configured to generate a synchronous trigger signal for the target sampling rate, and all slave timers are configured to generate multiple synchronous update events with sequentially delayed phases based on the synchronous trigger signal, serving as multiple parallel DMA trigger signals; using the DMA trigger signals, the corresponding DMA channels are controlled to transfer data from external devices to their respective corresponding storage areas in the data buffer in parallel and alternately. Based on the phase delay order of the timer update events, the data stored in the multiple storage areas are time-series reassembled to reconstruct the complete sampling sequence defined by the target sampling rate; When configuring all slave timers to generate the update event, the process includes: configuring all slave timers to use the synchronization trigger signal of the master timer as their clock source, and setting the same auto-reload value and different initial counter values ​​for each slave timer, so that all slave timers generate synchronized update events with sequentially delayed phases; The number of slave timers is N, where N is an integer greater than 1; the target sampling rate is Fs, and the frequency of update events generated by each slave timer is Fs / N; by configuring N slave timers to generate update events with sequentially delayed phases, the N corresponding DMA channels can operate in parallel at an operation frequency of Fs / N, thereby achieving a data throughput rate N times that of a single DMA channel operation frequency.

2. The method according to claim 1, characterized in that, When controlling the parallel and alternating transmission of data from external devices, the method includes: uniquely associating the trigger source of each DMA channel with an update event of a slave timer, configuring the source address of each DMA channel as the data register address of the external device, and configuring the destination address as the corresponding storage area in the data buffer, so that during the duration of the synchronization trigger signal, each DMA channel is started sequentially to complete the parallel and alternating transmission of data from the external device.

3. The method according to claim 1, characterized in that, When configuring the master timer to generate a synchronous trigger signal for the target sampling rate, the process includes: configuring the clock source of the master timer as the system clock of the MCU; controlling the frequency division and counting of the system clock by setting the frequency divider parameters and auto-reload register parameters of the master timer, so that it generates a square wave signal with a frequency equal to the target sampling rate at the trigger output terminal; the square wave signal is input to all slave timers as the synchronous trigger signal and output to external devices through the MCU's GPIO pins as the conversion clock of the external devices, so as to ensure that the data reading timing of the MCU is synchronized with the sampling timing of the external devices.

4. The method according to claim 1, characterized in that, Before all slave timers generate multiple synchronous and sequentially phase-delayed update events based on the synchronous trigger signal, the process includes: configuring the master timer to trigger output mode and setting its trigger output source to update events; simultaneously, configuring each slave timer to slave mode and selecting the master timer as its trigger input source; and each synchronous trigger signal pulse generated by the master timer directly resetting or starting the counters of all slave timers.

5. The method according to claim 1, characterized in that, When setting different initial counter values ​​for each slave timer, the following steps are taken: the auto-reload value of all slave timers is uniformly set to M-1, so that the counting period of each slave timer is M synchronous trigger signal clock cycles. The initial counter values ​​of N slave timers are set sequentially to 0, 1, 2, ..., N-1, where M = N, so that the update events of N slave timers occur sequentially at intervals of one synchronous trigger signal clock cycle within the same master timer period.

6. The method according to claim 2, characterized in that, The mapping relationship between the multiple independent storage areas of the data buffer and the DMA channels is determined according to the order in which their corresponding timer update events occur: the DMA channel with the earliest update event corresponds to the first segment of the buffer's starting address, the DMA channel with the second earliest update event corresponds to the next segment, and so on; each DMA channel uses a cyclic overwrite or incremental transmission mode within its destination address range to independently move data, ensuring that the data of multiple DMA channels will not overwrite each other during high-speed continuous transmission.

7. The method according to any one of claims 1-6, characterized in that, The external device is a high-speed parallel interface analog-to-digital converter (ADC). The ADC is connected to a set of GPIO ports of the MCU. The source address of the DMA channel is configured as the input data register address of the set of GPIO ports, so that the DMA can directly capture parallel data at the GPIO ports and move it to memory without CPU intervention.

8. A high-speed data communication system based on synchronous triggering and parallel transmission, characterized in that, The high-speed data communication system based on synchronous triggering and parallel transmission uses the high-speed data communication method based on synchronous triggering and parallel transmission as described in any one of claims 1-7.

Images