A method, system, and storage medium for placement of digital circuit pipeline registers
By optimizing the layout path of pipeline registers and avoiding embedded IP and other restricted areas, the problem of uneven pipeline register latency is solved, improving chip performance and the practicality of the layout path, and supporting more complex digital chip designs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN HONGXIN MICRO NANO TECH CO LTD
- Filing Date
- 2025-12-09
- Publication Date
- 2026-05-19
AI Technical Summary
Existing EDA tools struggle to guarantee uniform delay across register levels in automated pipelined register placement, and the actual placement path differs significantly from the ideal path, making them unsuitable for complex chip design.
By adjusting the position of pipeline registers based on the initial layout path to avoid embedded IPs, prohibited areas, high-density and congested areas, and by using Steiner tree algorithm and other optimization path planning methods, the uniform distribution of registers at each stage is ensured.
It achieves uniform delay in pipelined registers, improves the overall performance of the chip and the practicality of the layout path, and supports more complex digital chip designs.
Smart Images
Figure CN121303048B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit design automation technology, specifically to a method, system, and storage medium for placing pipeline registers in digital circuits. Background Technology
[0002] In digital chip design, pipelines are a key technology that uses staged parallel processing to improve system throughput and efficiency. The core idea is to break down a complex operation into multiple smaller, overlapping stages, similar to an assembly line in a factory. Ensuring uniform latency for registers at each stage of the pipeline has always been a challenge for the automatic placement section of EDA (Electronic Design Automation) tools.
[0003] In existing EDA tools, registers at each stage of the pipeline are treated the same as other registers in terms of connection method, which often results in uneven latency among registers at each stage of the pipeline. To solve the latency problem, users often need to manually adjust the position of each register in the EDA tool.
[0004] Existing automated placement processes for pipelined registers employ grid-based analysis, dividing the chip into grids of equal or different sizes. Path traversal is used to find the shortest path between any two ports, and the pipelined register positions are allocated based on this path. However, the main problem with this method is that the calculated shortest path is an ideal path and cannot be directly applied in practice. This is because actual placement and routing involve many constraints, such as considering embedded IP modules and user-defined restricted areas. Therefore, the actual path used differs significantly from the calculated shortest path. Summary of the Invention
[0005] To address the aforementioned issues of uneven delay and practicality, this invention provides a layout method, system, and storage medium for pipelined registers in digital circuits. Based on different prohibited routing regions, an optimized layout path is formed by adjusting the initial layout path. The registers at each stage of each pipeline are evenly distributed along the planned optimized layout path to ensure that each stage of registers on each pipeline has a uniform delay.
[0006] According to a first aspect, this embodiment provides a layout method for a digital circuit pipelined register, including:
[0007] Obtain the initial layout path for each pipeline in the netlist;
[0008] Obtain the chip layout plan and embedded IP area from the netlist, and determine the specified prohibited areas based on the chip layout plan;
[0009] Calculate and identify high-density areas and severely congested areas in the netlist;
[0010] Based on path planning algorithms, the initial layout path is optimized to avoid embedded IP areas, designated prohibited areas, high-density areas, and severely congested areas, resulting in an optimized layout path for each pipeline.
[0011] Based on the optimized layout path, registers at each level are evenly arranged on the corresponding optimized layout path to form an optimized register pipeline.
[0012] In some embodiments, the following steps are included before obtaining the initial layout path for each pipeline in the netlist:
[0013] Traverse the circuit netlist to find all the registers. Registers with connections form multiple pipelines.
[0014] Search the circuit netlist to identify all pipelines;
[0015] For each pipeline, based on the connection relationship between the start and end positions of the pipeline, the initial layout path of the current pipeline is constructed through a path planning algorithm.
[0016] In practice, the calculation of the avoidance area includes the designated prohibited area, high-density area, and severely congested area. The path planning algorithm is Steiner tree algorithm, minimum spanning tree algorithm, or A* heuristic search algorithm.
[0017] In some embodiments, the step of forming the optimized layout path for each pipeline includes:
[0018] Construct the Steiner tree for the pipeline from the start register to the end register;
[0019] Determine whether the Steiner tree crosses the embedded IP region or calculate the avoidance region;
[0020] If so, flip the branches of the Steiner tree that overlap with the embedded IP region or the computation avoidance region, so that the Steiner tree avoids the IP region and the computation avoidance region, forming an optimized Steiner tree;
[0021] Based on this optimized Steiner tree, an optimized layout path is determined from the starting position to the ending position, and the corresponding pipeline registers at each stage are evenly distributed on the optimized layout path.
[0022] In this optimized register pipeline, a set of registers are connected end to end. No other type of device, except for buffers and inverters, can be placed between registers. The relationship between registers in the preceding and following stages is either one-to-one or one-to-many.
[0023] In some embodiments, when the relationship between registers at different stages is one-to-many, that is, when the register at the previous stage drives multiple registers, the following steps are included:
[0024] First process one pipeline that passes through the one-to-many relational register;
[0025] The process involves selecting the next pipeline from the one-to-many relation register for computation until the optimized layout path calculation for all pipelines in the one-to-many relation register is completed.
[0026] In some embodiments, the layout method of the digital circuit pipeline register further includes:
[0027] When multiple registers exist, calculations are performed sequentially according to the order of the last register level from smallest to largest.
[0028] In some embodiments, the following steps are repeated in the path planning algorithm calculation for each pipeline:
[0029] Determine if the device in the start register of the drive pipeline is a driver. If it is, move the start register closer to the driver; otherwise, leave the start register in its original position. Drivers include embedded IPs, latches, or devices that lock positions.
[0030] Determine whether the last stage register in the pipeline drives a driver. If it does, move the last stage register near the driver. If not, leave the last stage register in its original position. Drivers include embedded IP, latches, or devices that lock positions.
[0031] According to a second aspect, this embodiment provides a pipelined register layout system, including a processor and a memory, wherein the memory stores instructions and the processor calls instructions to cause the processor to execute the digital circuit pipelined register layout method of any embodiment of the first aspect.
[0032] According to a third aspect, this embodiment provides a computer-readable storage medium storing a computer program that can be executed by a processor to implement the layout method of digital circuit pipeline registers of any embodiment of the first aspect.
[0033] The layout method, system, and storage medium of the digital circuit pipeline register according to the above embodiments have the following beneficial effects:
[0034] On the pre-generated initial layout path, based on embedded IP regions, specified prohibited regions, and calculated high-density and severely congested regions, the initial layout path is modified and adjusted to form an optimized layout path. The registers at each stage of each pipeline are evenly distributed along the planned optimized layout path. This path planning is highly practical and ensures uniform delay for registers at each stage of each pipeline. In this embodiment, when planning the optimized layout path for each pipeline, information such as chip layout planning, timing constraints, and potential future routing congestion is fully considered. Applying the optimized layout path results in higher stability, ensuring that registers at each stage of the pipeline will not be moved during subsequent automatic placement by the EDA tool due to layout planning considerations or prohibited routing. Furthermore, it improves the overall chip performance, including timing convergence, routing smoothness, circuit stability, and yield.
[0035] Furthermore, the digital circuit pipeline register placement method, system, and storage medium of the above embodiments support pipeline optimization placement path calculation from one port to multiple ports, which can support more complex digital chip designs. Attached Figure Description
[0036] Figure 1 This is a main flowchart of a layout method for a digital circuit pipeline register in one embodiment;
[0037] Figure 2 for Figure 1 The flowchart for generating the initial layout path is shown below;
[0038] Figure 3 This is a flowchart illustrating the generation of an optimized path in one embodiment.
[0039] Figure 4 This is a schematic diagram of the path calculation process for each pipeline in one embodiment.
[0040] Figure 5 An example diagram showing the optimized layout path formation of the Steiner tree for a pipeline in one embodiment;
[0041] Figure 6 This is a schematic diagram of the hardware structure of a pipelined register layout system in one embodiment. Detailed Implementation
[0042] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of this application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to this application are not shown or described in the specification. This is to avoid obscuring the core parts of this application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.
[0043] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.
[0044] The serial numbers assigned to components in this document, such as "first" and "second," are used solely to distinguish the described objects and have no sequential or technical meaning. "Multiple" means two or more. Unless otherwise specified, "connection" or "linkage" in this application includes both direct and indirect connections (linkages).
[0045] Please refer to Figure 1 The digital circuit pipeline register placement method in one embodiment of the present invention is implemented on an EDA tool, including pipeline identification and automatic pipeline placement. During the automatic placement process, all pipelines in the netlist are identified and the pipeline paths are optimized and corrected. Then, the registers at each stage of each pipeline are evenly distributed along the optimized path to ensure that the registers at each stage of each pipeline have uniform delay.
[0046] In pipeline identification, the initial layout paths for all pipelines in the computation netlist are quickly laid out by initially identifying the pipelines. In this embodiment, a pipeline is defined as a group of registers connected end-to-end, and no devices other than buffers and inverters can exist between the registers. The digital circuit pipeline register layout method in this embodiment supports pipeline computation from one port to multiple ports. The relationship between registers must be one-to-one or one-to-many, meaning that a register cannot be driven by multiple registers simultaneously.
[0047] In automated placement of a pipeline, for each pipeline, based on the connection relationship between the start and end registers, and referring to chip layout planning, timing constraints, and potential future routing directions, an initial placement path is constructed and then optimized to form an optimized placement path. Registers at each level are then evenly distributed along this optimized placement path. By optimizing the path positions of registers at each level on the pipeline during the automated placement process using EDA tools, uniform delays for registers at each level on each pipeline are ensured.
[0048] Please refer to Figure 1 as well as Figure 2 The layout method of the digital circuit pipeline register in one embodiment of the present invention mainly includes steps S101-150, which are described in detail below. Steps S101-S103 pertain to pipeline identification. Steps S110-150 pertain to the automatic layout of the pipeline.
[0049] Please refer to Figure 2 The following are the steps of the initial layout path:
[0050] Step S101: Traverse the components in the circuit netlist, find all registers, and connect related registers to form multiple pipelines. Before path optimization begins, the algorithm in this embodiment relies on EDA tools to pre-complete the rapid placement and calculation of all components.
[0051] Step S102: Search the circuit netlist to identify all pipelines. In this embodiment, a pipeline is defined as a group of registers connected end-to-end. No devices other than buffers and inverters can exist between registers. The relationship between registers must be one-to-one or one-to-many; that is, a register cannot be driven by multiple registers simultaneously.
[0052] Step S103: For each pipeline, based on the connection relationship between the start and end positions of the pipeline, the initial layout path of the current pipeline is constructed by a path planning algorithm. The calculation of the initial layout path involves the use of weights based on factors such as timing and estimated detour congestion.
[0053] like Figure 1 As shown, after calculating the initial layout path, the following are the main steps for path optimization calculation.
[0054] Step S110: Obtain the initial layout path for each pipeline in the netlist.
[0055] Step S120: Obtain the chip layout plan and embedded IP area of the netlist, and determine the specified prohibited area according to the chip layout plan.
[0056] Step S130: Calculate and determine the high-density regions and severely congested regions of the netlist. The high-density regions are calculated by dividing the sum of the device areas within the mesh by the mesh area. The severely congested regions are calculated by dividing the expected number of routing traces within the mesh by the estimated number of routing traces that can be routed within the mesh. Further pipelined placement in embedded IP regions, designated prohibited regions, high-density regions, and severely congested regions may result in registers in these regions being moved during subsequent EDA tool optimization, or registers not being optimized due to oversight. An unreasonable register placement will affect the overall chip performance, including timing convergence, routing smoothness, circuit stability, and yield.
[0057] Step S140: Based on the path planning algorithm, the initial layout path is optimized to avoid embedded IP areas, specified prohibited areas, high-density areas and severely congested areas, forming an optimized layout path for each pipeline.
[0058] The optimized layout path of the pipeline avoids these areas. On the one hand, it prevents the registers on the pipeline from being removed during subsequent EDA tool optimization, thus improving computational efficiency. On the other hand, the even distribution of registers based on the optimized layout path can not only enable the pipeline to obtain uniform delay, but also improve the overall chip performance, including timing convergence, smooth routing, and more stable circuits.
[0059] Step S150: Based on the optimized layout path, evenly distribute the registers at each level on the corresponding optimized layout path to form an optimized register pipeline. Evenly distributing the registers at each level ensures that each level of register has a uniform delay on each pipeline.
[0060] exist Figure 1 as well as Figure 2 In the illustrated embodiment, the path planning algorithm can employ the Steiner tree algorithm, the minimum spanning tree algorithm, or the A* heuristic search algorithm. To clearly describe the subsequent methods, the designated prohibited region, high-density region, and severely congested region in the above steps are collectively referred to as the computational avoidance region. This computational avoidance region includes, but is not limited to, the designated prohibited region, high-density region, and severely congested region.
[0061] The path planning algorithms for the initial layout path and the optimized layout path are illustrated using the Steiner tree algorithm. The optimization and correction process for other path planning algorithms is the same.
[0062] Please refer to Figure 3 In this embodiment, the step of forming the optimized layout path for each pipeline using the Steiner tree algorithm includes:
[0063] Step S200: Construct the Steiner tree of the pipeline from the start register to the end register; for example, using the shortest right-angled Steiner tree with the shortest bus length, connect all the pins of the pipeline with horizontal and vertical lines, and the right-angled Steiner tree can be obtained from the start register to the end register by connecting through any intermediate point.
[0064] Step S240: Segment the Steiner tree for subsequent determination of whether the current segment overlaps with the prohibited wiring area.
[0065] Step S241: Determine whether each segment of the Steiner tree crosses the embedded IP region or calculate the avoidance region;
[0066] Step S242: If both are not true, the Steiner tree path remains unchanged.
[0067] Step S243: If applicable, determine the short and long segments of adjacent segments in the overlap between the Steiner tree and the prohibited wiring region;
[0068] Step S245: When avoiding prohibited wiring areas, flip the short segments of the Steiner tree that overlap with the embedded IP area or the calculated avoidance area, and adjust the length of the long segments accordingly to make the Steiner tree avoid the embedded IP area or the calculated avoidance area, thus forming an optimized Steiner tree. Please refer to... Figure 5 The purple path represents the initial layout path of the register pipeline from the starting register B to the ending register C, including the first segment A1, the second segment A2, the third segment A3, and the fourth segment A4. The first pink box 30 is designated as the embedded IP module, and the second pink box 40 is designated as the routing congestion area. When avoiding the embedded IP area or calculating the avoidance area, if the first pink box 30 overlaps with the longer first segment A1 and the shorter second segment A2, the length of the longer first segment is adjusted accordingly until the first segment A1 no longer overlaps with the first pink box 30 while maintaining a set distance. Then, based on the contraction point of the first segment A1, the overlapping second segment A2 is flipped entirely, and the revised new path is the green first new path A12. For example, the second pink box 40 overlaps with the longer third segment A3 and the shorter fourth segment A4. Adjust the length of the longer third segment until the third segment A3 no longer overlaps with the second pink box 40 and maintains the set distance. Then, based on the contraction point of the third segment A3, flip the overlapping fourth segment A4 as a whole and connect the end register C with the smallest straight line. Adjust the revised new path to the second new green path A34.
[0069] The optimized layout path consists of both purple and green paths.
[0070] Step S246: Based on the optimized Steiner tree, determine the optimized layout path from the start position to the end position, and evenly distribute the corresponding pipeline registers at each level on the optimized layout path. Evenly distributing the registers at each level can ensure that the registers at each level on each pipeline have uniform delay.
[0071] Similarly, the register pipeline with optimized layout path is a set of registers connected end to end. There cannot be any other type of device between registers except for buffers and inverters. The relationship between registers before and after the stage is one-to-one or one-to-many.
[0072] Please refer to Figure 4 In this embodiment, the relationship between the registers before and after the registers adopts a one-to-many relationship, which requires processing pipeline optimization layout path calculation from one port to multiple ports to support more complex digital chip designs.
[0073] For example, when the path planning algorithm uses the Steiner tree algorithm, the relationship between the registers before and after the registers is one-to-many, that is, the register before the register drives multiple registers. First, one pipeline that passes through the one-to-many relationship registers is processed, and then the next pipeline is selected from the one-to-many relationship registers for calculation and processing until the optimized layout path calculation of all pipelines in the one-to-many relationship registers is completed.
[0074] In the path planning algorithm calculation for each pipeline, the following steps are repeated:
[0075] Step S200: Construct the Steiner tree of the pipeline from the start register to the end register.
[0076] Perform the first step of judgment:
[0077] Step S210: Determine whether the device in the starting register of the drive pipeline is a driver, wherein the driver includes embedded IP, latch, or device that locks the position.
[0078] Step S211: If so, place the first register, i.e. the start register, near the driver.
[0079] Step S212: If not, the position of the start register remains unchanged.
[0080] Proceed to the second step of the judgment:
[0081] Step S220: Determine whether the last stage register in the pipeline is driven by a driver, wherein the driver includes embedded IP, latch, or a device that locks the position.
[0082] Step S221: If so, place the end register near the driver.
[0083] Step S222: If not, the position of the end register remains unchanged.
[0084] Proceed to the third step of the judgment:
[0085] Step S230: Determine whether the relationship between the registers before and after is a one-to-many relationship.
[0086] Step S235: If not, optimize the current Steiner tree path.
[0087] Step S231: If so, process and calculate the pipeline in the one-to-many relation register in ascending order of the last level register level.
[0088] Step S232: First process one of the pipelines that passes through the one-to-many relation register.
[0089] Step S233: Select the next pipeline to calculate and process until the optimized layout path calculation of all pipelines in the one-to-many relation register is completed.
[0090] When multiple registers exist, they are processed sequentially in ascending order of their last-level register order. For example, if register D1 drives register D2, register D2 drives register D3, register D3 drives register D4, and register D2 also drives register D5, then registers D4 and D5 are both last-level registers. D4 has a level of 4, and D5 has a level of 3. The priority processing path is: register D1 -> register D2 -> register D5. Then, with D2's position fixed, registers D2 -> D3 -> D4 are processed.
[0091] like Figure 6 As shown, the pipelined register layout system 500 includes a central processing unit (CPU) 501, which can perform various appropriate actions and processes based on computer program instructions stored in read-only memory 502 (ROM) or loaded from storage units into random access memory 503 (RAM). The RAM can also store various programs and data required for device operation. The CPU, ROM, and RAM are interconnected via a bus. An input / output (I / O) interface 505 is also connected to the bus.
[0092] Multiple components in the device are connected to the I / O interface, including: input unit 506, such as a keyboard, mouse, etc.; output unit 507, such as various types of displays, speakers, etc.; storage unit 508, such as a disk, optical disk, etc.; and communication unit 509, such as a network card, modem, wireless transceiver, etc. The communication unit 509 allows the device to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.
[0093] The processing unit executes the various methods and processes described above, such as the series of method steps S101 to S246. For example, in some embodiments, method steps S110 to S150 may be implemented as a computer software program tangibly contained in a machine-readable medium, such as a storage unit. In some embodiments, part or all of the computer program may be loaded and / or installed on the device via ROM and / or a communication unit. When the computer program is loaded into RAM and executed by the CPU, one or more steps of the method steps S101 to S246 described above may be performed. Alternatively, in other embodiments, the CPU may be configured to execute method steps S101 to S246 by any other suitable means (e.g., by means of firmware).
[0094] Those skilled in the art will understand that all or part of the functions of the various methods in the above embodiments can be implemented by hardware or by computer programs. When all or part of the functions in the above embodiments are implemented by computer programs, the program can be stored in a computer-readable storage medium, which may include: read-only memory, random access memory, disk, optical disk, hard disk, etc., and the program is executed by a computer to achieve the above functions. For example, the program can be stored in the memory of a device, and when the program in the memory is executed by the processor, all or part of the above functions can be achieved. In addition, when all or part of the functions in the above embodiments are implemented by computer programs, the program can also be stored in a server, another computer, disk, optical disk, flash drive, or external hard drive, etc., and can be downloaded or copied to the memory of a local device, or the system of the local device can be updated. When the program in the memory is executed by the processor, all or part of the functions in the above embodiments can be achieved.
[0095] The above examples illustrate the present invention only to aid in understanding it and are not intended to limit the scope of the invention. Those skilled in the art can make various simple deductions, modifications, or substitutions based on the principles of this invention.
Claims
1. A layout method for pipelined registers in digital circuits, characterized in that, include: Obtain the initial layout path for each pipeline in the netlist; Obtain the chip layout plan and embedded IP area of the netlist, and determine the specified prohibited area based on the chip layout plan; The high-density regions and severely congested regions of the netlist are calculated and determined. Based on the path planning algorithm, the initial layout path avoids the embedded IP area, the specified prohibited area, the high-density area and the severely congested area, and optimizes and adjusts the initial layout path to form the optimized layout path of each pipeline. as well as Based on the optimized layout path, registers at each level are evenly arranged on the corresponding optimized layout path to form an optimized register pipeline.
2. The layout method for digital circuit pipelined registers as described in claim 1, characterized in that, Before obtaining the initial layout path for each pipeline in the netlist, the following steps are also included: Traverse the circuit netlist to find all the registers. Registers with connections form multiple pipelines. Search the circuit netlist to identify all pipelines; For each pipeline, based on the connection relationship between the start and end positions of the pipeline, the initial layout path of the current pipeline is constructed using the path planning algorithm.
3. The layout method for digital circuit pipelined registers as described in claim 2, characterized in that, The calculation avoidance area includes the specified prohibited area, high-density area and severely congested area, and the path planning algorithm is Steiner tree algorithm, minimum spanning tree algorithm or A* heuristic search algorithm.
4. The layout method for digital circuit pipelined registers as described in claim 3, characterized in that, The steps for forming the optimized layout path for each pipeline include: Construct the Steiner tree for the pipeline from the start register to the end register; Determine whether the Steiner tree crosses the embedded IP region or calculates the avoidance region; If so, flip the branches of the Steiner tree that overlap with the embedded IP region or the computation avoidance region, so that the Steiner tree avoids the IP region and the computation avoidance region, forming an optimized Steiner tree; Based on the optimized Steiner tree, the optimized layout path is determined based on the starting position to the ending position, and the corresponding pipeline registers at each stage are evenly distributed on the optimized layout path.
5. The layout method for digital circuit pipelined registers as described in claim 4, characterized in that, The optimized register pipeline is a set of registers connected end to end. No other type of device, except for buffers and inverters, is allowed between the registers. The relationship between the registers is either one-to-one or one-to-many.
6. The layout method for digital circuit pipelined registers as described in claim 5, characterized in that, When the relationship between the registers at different levels is one-to-many, that is, when the register at the previous level drives multiple registers, the following steps are included: First, process one of the pipelines that passes through the one-to-many relation register; The next pipeline is selected from the one-to-many relationship register for computation and processing until the optimized layout path calculation for all pipelines in the one-to-many relationship register is completed.
7. The layout method for digital circuit pipelined registers as described in claim 6, characterized in that, Also includes: When multiple registers exist, calculations are performed sequentially according to the order of the last register level from smallest to largest.
8. The layout method for digital circuit pipelined registers as described in claim 5, characterized in that, In the path planning algorithm calculation for each pipeline, the following steps are repeated: Determine whether the device in the starting register of the driving pipeline is a driver. If it is, place the starting register near the driver. If not, the position of the starting register remains unchanged. The driver includes an embedded IP, a latch, or a device that locks the position. as well as Determine whether the last stage register in the pipeline drives a driver. If it does, place the last stage register near the driver. If not, keep the position of the last stage register unchanged. The driver includes embedded IP, latches, or devices that lock positions.
9. A layout system for pipelined registers, characterized in that, It includes a processor and a memory, the memory storing instructions, and the processor calling the instructions to cause the processor to execute the layout method of the digital circuit pipeline register as described in any one of claims 1-8.
10. A computer-readable storage medium, characterized in that, The storage medium stores a computer program that can be executed by a processor to implement the layout method of the digital circuit pipeline register as described in any one of claims 1 to 8.