Chip layout positioning method, positioning system, chip testing system and electronic equipment

Abstract

The application discloses a chip layout positioning method, a positioning system, a chip test system and electronic equipment, and relates to the technical field of chip layout positioning. The method comprises the following steps: obtaining a conversion relationship between a first coordinate system and a second coordinate system, generating a simulated photograph of a chip according to the conversion relationship; and determining the position of a target region in a layout design file according to the conversion relationship after the target region is determined in a target actual local photo of the chip. The application can greatly simplify the operation process, save time and labor cost, and has wider applicability and adaptability. The positioning accuracy and stability are improved, and the problem that the manual mapping process is time-consuming and labor-intensive and the difficulty increases exponentially with the increase of the complexity of the chip is effectively solved.

Description

Technical Field

[0001] This invention relates to the field of chip layout positioning technology, and in particular to a chip layout positioning method, positioning system, chip testing system, and electronic device. Background Technology

[0002] The creation of a chip involves design, manufacturing, and testing, corresponding to the design, manufacturing, and packaging / testing sectors of the integrated circuit industry chain, respectively. Figure 1 As shown.

[0003] Chip testing is a crucial step in ensuring chip quality and performance. It detects defects that may occur during the chip's design and manufacturing process. Chip testing is mainly divided into physical testing and electrical performance testing. Physical testing can be further divided into pre-packaging chip surface defect detection and post-packaging package defect detection, such as... Figure 2 As shown.

[0004] In physical testing, optical microscopes are used to magnify chip details and observe the microstructure of the chip surface, revealing defects in key details. A single magnified chip can generate thousands of images. With the increasing precision of optical microscopes, the number of images generated from a single chip photograph has multiplied. However, viewing a magnified image alone is insufficient to accurately and intuitively identify which part of the chip it represents, let alone pinpoint a defect within the image to its exact location. In other words, the difficulty of subsequently locating defects (i.e., certain pixels in an image) within the overall chip design layout increases continuously with the precision of microscopes. Traditional methods for locating defects include three specific methods:

[0005] The first method is manual visual inspection, but it has been gradually phased out due to its low efficiency, poor accuracy, and high cost. The second method uses image stitching technology to stitch together all the microscope photographs end-to-end to form a complete chip image, thus presenting the overall distribution of defective pixels on the chip. The third method uses positioning-assisted hardware to directly calculate the positional relationship between each pixel in the image and the layout image during the imaging process. Its implementation generally involves the following steps: First, prepare a photograph B of the layout design file A in advance: for simple designs, the image may be directly exported from the design software; for complex designs, the chip unpacking, delamination, and imaging processes are required to generate the final layout photograph containing module distribution information. Then, use hardware technology to establish the coordinate correspondence between the layout design photograph B and the actual photograph C; calculate the positional coordinates of a pixel in photograph C on the layout design photograph B; finally, manually determine the correspondence between the layout design photograph B and the layout design file A.

[0006] However, whether using image stitching or hardware technology to assist in positioning, existing technical solutions all have the following drawbacks to varying degrees:

[0007] 1) Existing technical solutions require users to prepare layout images in advance and export them from the chip design environment by means of screenshots or format conversion. If it is a substrate layer, it may be necessary to perform sample processing such as unpacking, de-layering, and taking pictures of the chip, which is a relatively complex and tedious process.

[0008] 2) Existing technical solutions that rely on hardware technology require customized positioning adjustment devices, processors, and other equipment, resulting in high costs for iterative optimization;

[0009] 3) Similarly, hardware-based technical solutions have poor scalability. They may not be applicable to unknown layout optimizations and cannot be extended to photos taken by other microscopes.

[0010] 4) If image stitching technology is used, it depends on the accuracy of the stitching technology and requires high image quality. Vertical stitching errors will affect horizontal stitching, and stitching errors will accumulate continuously.

[0011] 5) Existing solutions cannot achieve end-to-end pixel positioning. Hardware-assisted positioning technology can only locate points on the image to the layout image provided by the user in the first step. That is, it cannot directly show the location of defects in the layout design file. It is necessary to manually map the layout image (the image file B provided by the user at the beginning) to the layout design file A. This process is time-consuming and labor-intensive. Due to manual visual inspection, the accuracy is poor and the efficiency is low. As the complexity of the chip increases, the difficulty increases exponentially. Summary of the Invention

[0012] The technical problem to be solved by this invention is to address the shortcomings of existing technologies, and specifically provides a chip layout positioning method, a positioning system, a chip testing system, and an electronic device, as detailed below:

[0013] 1) In a first aspect, the present invention provides a chip layout positioning method, the specific technical solution of which is as follows:

[0014] Obtain the transformation relationship between the first coordinate system and the second coordinate system, and generate a simulated photograph of the chip based on the transformation relationship; wherein, the first coordinate system refers to the coordinate system used in the actual photograph of the chip, the second coordinate system refers to the coordinate system used in the chip's layout design file, and the coordinate system used in the simulated photograph is the first coordinate system;

[0015] Once the target region is identified in the actual local photograph of the chip, the position of the target region in the layout design file is determined according to the transformation relationship. The actual local photograph of the chip is a photograph of the chip itself.

[0016] The beneficial effects of the chip layout positioning method provided by this invention are as follows:

[0017] Traditional methods require pre-prepared layout images, resulting in complex and cumbersome operations. This application eliminates the need for users to perform complex sample processing and image export steps. It directly generates simulated photographic images by obtaining the transformation relationship between a first coordinate system (the actual photograph coordinate system) and a second coordinate system (the layout design file coordinate system). This avoids the tedious processes of manually unpacking, delaminating, photographing, and exporting images or converting formats from design software, greatly simplifying the operation process and saving time and labor costs. Addressing the high costs of customized equipment and iterative optimization associated with existing hardware-dependent solutions, this application does not rely on specific hardware auxiliary equipment, reducing hardware dependence. It primarily uses software algorithms or computational methods to obtain and locate coordinate system transformation relationships, reducing the need for customized position adjustment devices, processors, and other hardware, thereby significantly lowering hardware costs. During technology iteration and optimization, large-scale updates and adjustments to hardware equipment are unnecessary; only optimization and improvement of the software algorithm or computational model are required, resulting in relatively low optimization costs. This application also solves the problem of poor scalability based on hardware technology. Because it does not rely on specific hardware, it is highly scalable, better adaptable to unknown layout optimization needs, and can be flexibly applied to photographs taken with different microscopes, without hardware limitations, thus having wider applicability and adaptability. Compared to image stitching technology, which has high requirements for image quality and suffers from the problem of accumulated stitching errors, this application does not have the problem of accumulated image stitching errors. It directly determines the position of the target area in the layout design file by establishing a coordinate system transformation relationship, avoiding problems such as vertical stitching errors affecting horizontal stitching (or horizontal stitching errors affecting vertical stitching) during image stitching, thus improving the accuracy and stability of positioning, and ensuring that the final positioning result is not affected by image quality or errors in the stitching process. Addressing the problem that existing solutions cannot achieve end-to-end pixel positioning and require manual mapping between layout images and layout design files, this application achieves true end-to-end pixel positioning. Once the location of the target area in the actual photograph is determined, its accurate location in the layout design file can be obtained directly through the conversion relationship, without the need for additional manual mapping operations. This greatly improves positioning efficiency and accuracy, reduces errors and time consumption caused by manual operations, and can still efficiently and accurately determine the location of defective pixels in the layout design file even with the continuous increase in chip complexity. This effectively solves the problem that the manual mapping process in the existing technology is time-consuming and labor-intensive, and the difficulty increases exponentially with the increase of chip complexity.

[0018] Based on the above scheme, the chip layout positioning method of the present invention can be further improved as follows.

[0019] Furthermore, the transformation relationship between the first coordinate system and the second coordinate system includes: the positional relationship between the origin of the first coordinate system and the origin of the second coordinate system, as well as the rotation angle between the first coordinate system and the second coordinate system;

[0020] Obtain the transformation relationship between the first coordinate system and the second coordinate system, including:

[0021] Determine and, based on the target position of the chip's preset actual partial photograph in the layout design file, obtain the positional relationship between the origin of the first coordinate system and the origin of the second coordinate system, and obtain the rotation angle between the first coordinate system and the second coordinate system. Here, the preset actual partial photograph of the chip is the actual photograph of the chip.

[0022] The beneficial effects of adopting the above-mentioned further scheme are as follows: By accurately determining the positional relationship and rotation angle between the origins of the first and second coordinate systems, high-precision basic information is provided for coordinate system transformation, making the positioning of the actual chip photograph and the layout design file more accurate, reducing positioning errors caused by coordinate deviations, and improving overall positioning accuracy. The transformation relationship is obtained by using the positional association between the preset actual local photograph of the chip and the layout design file. The process is direct and efficient, avoiding the cumbersome steps of traditional methods, simplifying the operation process, saving time and manpower costs, and improving positioning efficiency. This method is highly flexible, does not rely on specific hardware devices, has good scalability, and can adapt to different chip design and testing needs. For complex chip layout optimization and unknown layouts, accurate coordinate transformation can also be achieved by adjusting parameters. It has strong versatility and a wide range of applications.

[0023] Furthermore, a simulated photograph of the chip is generated based on the conversion relationship, including:

[0024] Based on the positional relationship between the origins of the first coordinate system and the second coordinate system, as well as the rotation angle between the first and second coordinate systems, and in conjunction with the layout design file, a simulated photograph is generated.

[0025] The beneficial effects of adopting the above-mentioned further scheme are as follows: By combining the origin position relationship and rotation angle of the first coordinate system and the second coordinate system, and generating simulated images based on the layout design file, it has many significant advantages. First, the coordinate system used in the simulated images is consistent with the actual photos, ensuring a high degree of matching with the actual inspection scene. This allows the analysis based on the actual chip condition to accurately correspond to the simulated image, improving the accuracy and reliability of the inspection. Second, using coordinate system transformation relationships to generate simulated images eliminates the complex image stitching or cumbersome steps of hardware positioning in traditional methods, simplifying the operation process, lowering the technical threshold and cost, and improving positioning efficiency. Third, the simulated image generation process relies on precise coordinate transformation parameters, which ensures a precise correspondence between the simulated image and the layout design file, reducing errors caused by manual mapping and other steps, and helping to achieve more efficient and accurate chip defect location and detection.

[0026] Furthermore, after identifying the target region in the actual local photograph of the chip, the location of the target region in the layout design file is determined according to the transformation relationship, including:

[0027] Determine the pixel mapping relationship between each actual local photo of the chip and the simulated photograph. When the preset actual local photo and the target actual local photo are the same actual local photo, all actual local photos include the same actual local photo. When the preset actual local photo and the target actual local photo are not the same actual local photo, all actual local photos include both the preset actual local photo and the target actual local photo. Each actual local photo of the chip belongs to the actual photo of the chip.

[0028] Once the target region is identified in the actual local photograph, the position of the target region in the layout design file is determined based on the pixel mapping relationship, the positional relationship between the origin of the first coordinate system and the origin of the second coordinate system, and the rotation angle between the first coordinate system and the second coordinate system.

[0029] The beneficial effects of adopting the above-mentioned further scheme are as follows: By determining the pixel mapping relationship between each actual local photograph of the chip and the simulated photograph, and combining the origin position relationship and rotation angle of the first coordinate system and the second coordinate system, a precise positional transformation from the actual photograph to the layout design file can be achieved. This process ensures the accurate positioning of the target area in the layout design file, avoiding positional deviations caused by manual mapping or image stitching errors in traditional methods, thereby improving the accuracy and reliability of detection. When the preset actual local photograph and the target actual local photograph are the same actual local photograph, all actual local photographs include this same actual local photograph; when they are not the same actual local photograph, all actual local photographs include both the preset actual local photograph and the target actual local photograph. This design allows each actual local photograph to establish a mapping relationship with the simulated photograph, ensuring the comprehensiveness and systematic nature of the entire chip detection process, without missing any critical areas. Once the target area is determined in the target actual local photograph, the position of the target area in the layout design file can be quickly determined based on the established pixel mapping relationship and coordinate system transformation relationship, without the need for complex secondary transformations or manual intervention, greatly improving detection efficiency and automation. Whether targeting the same or different actual local images, it can achieve precise positioning through a unified mapping and transformation mechanism, making it suitable for chip inspection tasks of varying complexity. It can effectively address the increasingly complex challenges of chip design, providing strong technical support for chip inspection and defect analysis, and exhibiting excellent flexibility and adaptability.

[0030] 2) In a second aspect, the present invention also provides a chip layout positioning system, the specific technical solution of which is as follows:

[0031] It includes a module for determining the conversion relationship, a photo generation module, and a positioning module;

[0032] The transformation relationship determination module is used to: obtain the transformation relationship between the first coordinate system and the second coordinate system;

[0033] The photo generation module is used to: generate simulated photographs of the chip based on the conversion relationship;

[0034] Wherein, the first coordinate system refers to the coordinate system used in the actual photograph of the chip, the second coordinate system refers to the coordinate system used in the chip's layout design file, and the coordinate system used in the simulated photograph is the first coordinate system;

[0035] The positioning module is used to: determine the position of the target area in the layout design file according to the transformation relationship after the target area is determined in the actual local photograph of the chip. The actual local photograph of the chip is the actual photograph of the chip.

[0036] Based on the above solution, the chip layout positioning system of the present invention can be further improved as follows.

[0037] Furthermore, the transformation relationship between the first coordinate system and the second coordinate system includes: the positional relationship between the origin of the first coordinate system and the origin of the second coordinate system, as well as the rotation angle between the first coordinate system and the second coordinate system. The transformation relationship determination module is specifically used for:

[0038] Determine and, based on the target position of the chip's preset actual partial photograph in the layout design file, obtain the positional relationship between the origin of the first coordinate system and the origin of the second coordinate system, and obtain the rotation angle between the first coordinate system and the second coordinate system. Here, the preset actual partial photograph of the chip is the actual photograph of the chip.

[0039] Furthermore, the photo generation module is specifically used to generate simulated photographs based on the positional relationship between the origin of the first coordinate system and the origin of the second coordinate system, as well as the rotation angle between the first and second coordinate systems, and in conjunction with the layout design file.

[0040] Furthermore, the positioning module is specifically used for:

[0041] Determine the pixel mapping relationship between each actual local photo of the chip and the simulated photograph. When the preset actual local photo and the target actual local photo are the same actual local photo, all actual local photos include the same actual local photo. When the preset actual local photo and the target actual local photo are not the same actual local photo, all actual local photos include both the preset actual local photo and the target actual local photo. Each actual local photo of the chip belongs to the actual photo of the chip.

[0042] Once the target region is identified in the actual local photograph, the position of the target region in the layout design file is determined based on the pixel mapping relationship, the positional relationship between the origin of the first coordinate system and the origin of the second coordinate system, and the rotation angle between the first coordinate system and the second coordinate system.

[0043] 3) In a third aspect, the present invention also provides an electronic device, the electronic device including a processor coupled to a memory, the memory storing at least one computer program, the at least one computer program being loaded and executed by the processor to enable the electronic device to implement any of the above-mentioned chip layout positioning methods.

[0044] 4) In a fourth aspect, the present invention also provides a chip testing system, including any of the chip layout positioning systems described above.

[0045] It should be noted that the beneficial effects of the technical solutions of the second to fourth aspects of the present invention and their corresponding possible implementations can be found in the above description of the technical effects of the first aspect and its corresponding possible implementations, and will not be repeated here. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments of the present invention will be briefly introduced below:

[0047] Figure 1 This is a schematic diagram of the chip fabrication process;

[0048] Figure 2 This is a schematic diagram of the chip testing process;

[0049] Figure 3 This is a schematic flowchart of a chip layout positioning method according to an embodiment of the present invention;

[0050] Figure 4 This is a schematic diagram of a chip layout positioning system according to an embodiment of the present invention;

[0051] Figure 5 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0052] The principles and features of the present invention are described below. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention.

[0053] The technical solution of the present invention and how the technical solution of the present invention solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of the present invention will now be described with reference to the accompanying drawings.

[0054] like Figure 3 As shown, a chip layout positioning method according to an embodiment of the present invention includes the following steps:

[0055] S1. Obtain the transformation relationship between the first coordinate system and the second coordinate system, and generate a simulated photograph of the chip based on the transformation relationship; wherein, the first coordinate system refers to the coordinate system used in the actual photograph of the chip, the second coordinate system refers to the coordinate system used in the chip's layout design file, and the coordinate system used in the simulated photograph is the first coordinate system;

[0056] The transformation relationship between the first coordinate system and the second coordinate system includes: the positional relationship between the origin of the first coordinate system (taken as the starting point of the first photograph taken by the microscope) and the origin of the second coordinate system (taken as the (0,0) coordinate in the layout design file), that is, the coordinates of the origin of the first coordinate system in the second coordinate system, denoted as ( The process of obtaining the transformation relationship between the first and second coordinate systems in S1 includes: ...and the rotation angle between the first and second coordinate systems.

[0057] S10. Determine and, based on the target position of the preset actual partial photograph of the chip in the layout design file, obtain the positional relationship between the origin of the first coordinate system and the origin of the second coordinate system, and obtain the rotation angle between the first coordinate system and the second coordinate system, wherein the preset actual partial photograph of the chip is the actual photograph of the chip.

[0058] In the process of taking actual photos of the chip using an optical microscope, the lens or base is moved horizontally and vertically. Therefore, the chip's placement cannot be guaranteed to be 100% aligned with the direction of the optical microscope, and there may be slight rotation. In addition, the optical microscope may also be offset due to slight shaking during the moving and shooting process. The higher the magnification of the optical microscope, the greater the error caused by this shaking. Therefore, it is necessary to obtain the positional relationship between the origin of the first coordinate system and the origin of the second coordinate system, as well as the rotation angle between the first coordinate system and the second coordinate system.

[0059] The specific implementation process for determining the target location of the preset actual local image of the chip in the layout design file is as follows:

[0060] S100: Read the chip layout design file and obtain the specified position of the preset actual local photo in the layout design file. The specified position can be provided by the user. The specified position of the preset actual local photo in the layout design file can be an approximate position. The specified position of the preset actual local photo can be the position of the target point of the preset actual local photo. The target point can be the center point or any corner point, which can be set according to the actual situation. The specified position is represented by coordinates in the second coordinate system.

[0061] S101. Obtain the target location, specifically:

[0062] Image recognition technology is used to identify the potential locations (i.e., recognition positions) of a pre-defined local photograph within a layout design file. Due to the complexity of the layout design file and the potential presence of similar patterns, image recognition technology may identify multiple recognition positions. To address this issue and accurately determine the target position, the distance between each recognition position and its corresponding designated position needs to be calculated. Euclidean distance or other suitable distance metrics can be used to quantify the difference between each recognition position and the designated position. Then, by setting a reasonable distance threshold, recognition positions within the threshold range are filtered out. The setting of the distance threshold must comprehensively consider factors such as the precision requirements of chip manufacturing, the complexity of the layout design, and the characteristics of the actual local photograph, to ensure that the selected target positions meet practical needs while minimizing false positives and false negatives. Finally, after comparing the distances of all recognition positions with the designated position and filtering based on the distance threshold, a unique and accurate target position is determined. This lays a solid foundation for accurately obtaining the transformation relationship between the first and second coordinate systems, ensuring the accuracy and reliability of the entire chip-based simulated image generation process. At least one actual local photograph is required. The more actual local photographs are required, the more accurate the calculation of the transformation relationship between the first coordinate system and the second coordinate system will be.

[0063] For example, given four pre-set partial photographs, the process for determining the target location is as follows:

[0064] Four preset local images, captured using an optical microscope, are roughly distributed around the four corners of the chip, though not necessarily strictly at the edges. Their placement prioritizes subsequent computational transformations. Simultaneously, the approximate coordinates of these four images within the layout design file are obtained for rough positioning, initially defining the area of ​​each image within the file. Image recognition technology is then used to analyze the layout design file in depth, identifying the recognition positions of each preset local image. However, due to the complexity of the layout, each image may have multiple recognition positions. For each image, the distances between its numerous recognition positions and the pre-obtained approximate coordinates are calculated, using geometric methods such as Euclidean distance for precise quantification. Then, based on a set distance threshold, these distances are filtered, with recognition positions within the threshold range identified as target positions. The determination of the distance threshold fully considers factors such as chip precision, design complexity, and image characteristics to ensure the accuracy and reliability of the filtering results. From rough positioning to precise selection, the exact target positions of these four preset actual partial photos in the layout design file are finally determined. These target positions will provide key data support for the subsequent accurate calculation of the transformation relationship between the first coordinate system and the second coordinate system, thereby ensuring the accuracy and reliability of the chip simulated photographs, realizing high-precision simulation of the chip shooting angle, and laying a solid foundation for chip testing, analysis and other related processes.

[0065] Specifically, based on the target position of the actual local photograph of the chip in the layout design file, the positional relationship between the origin of the first coordinate system and the origin of the second coordinate system is obtained. The specific implementation process is as follows: (There is a scaling ratio between the photograph and the layout).

[0066] 1) When only one preset local photograph is available, this photograph is located at the starting position of the optical microscope image, i.e., the upper left corner of the chip. The upper left corner of the chip is assumed to be the origin of the first coordinate system, and the layout design file also defaults to the upper left corner as the origin of the second coordinate system. Then, template matching is performed between the preset local photograph and the layout design file. Specifically, the preset local photograph is used as a template, and an image processing algorithm is used to search for a matching region in the layout design file. The template matching result is the target position of the preset local photograph in the layout design file, with a focus on obtaining the coordinates of its center point within the layout design file. Simultaneously, the coordinates of the center point of the preset local photograph itself in its own coordinate system (the first coordinate system) are determined. Since the photograph is located at the upper left corner of the chip and this is the default origin, the coordinates of its center point in its own coordinate system can usually be predetermined or calculated using simple geometric relationships. Finally, compare the coordinates of the preset center point of the actual partial photograph in the coordinate system of the layout design file (second coordinate system) with its own coordinate system (first coordinate system). The difference between the two reflects the positional deviation of the origin of the first coordinate system from the origin of the second coordinate system along the corresponding coordinate axis. For example, if the preset center point coordinates of the actual partial photograph in the first coordinate system are: The coordinates of the object in the second coordinate system obtained through template matching are: Then, the positional deviation of the origin of the first coordinate system relative to the origin of the second coordinate system along the x-axis is: The positional deviation along the y-axis is: This calculation determines the positional relationship between the origins of the two coordinate systems, providing a crucial coordinate transformation basis for subsequent chip-simulated image generation and related analysis. Indicates the magnification of an optical microscope.

[0067] 2) When at least two preset actual local images are available, a template matching operation is performed on each preset actual local image. Each preset actual local image is used as a template and searched within the layout design file to obtain the matching position (target position) of each preset actual local image within the layout design file. Specifically, image processing algorithms, such as squared difference matching and normalized cross-correlation matching, are used to calculate the similarity between the preset actual local image and each region in the layout design file, thereby finding the optimal matching position and obtaining the center point coordinates (coordinates in the second coordinate system) of each preset actual local image in the layout design file. Simultaneously, the center point coordinates of each preset actual local image in its own first coordinate system are determined. Since the positions of these preset actual local images are pre-defined and their approximate positions on the chip are known (e.g., distributed at the four corners or edges of the chip), their center point coordinates in the first coordinate system can be obtained through geometric relationships or pre-annotated information. The positional deviation between each pair of corresponding points (i.e., the center point coordinates of the same preset actual local image in the two coordinate systems) is calculated. For each preset local photograph, the positional deviation of that point in the x-axis and y-axis directions is obtained by subtracting its center point coordinates in the first coordinate system from its center point coordinates in the second coordinate system. For example, for the first... The coordinates of the center point of a preset actual partial photograph in the first coordinate system are: The coordinates of the center point in the second coordinate system are The positional deviation is Then, the positional deviations of all preset actual partial photographs are averaged. The components of all positional deviations along the x-axis and y-axis are summed, and then divided by the number of preset actual partial photographs to obtain the average positional deviation. This average positional deviation reflects the positional relationship between the origin of the first coordinate system and the origin of the second coordinate system. For example, if there are n preset actual partial photographs, the average positional deviation... for:

[0068]

[0069]

[0070] Finally, based on this average positional deviation, the position of the origin of the first coordinate system relative to the origin of the second coordinate system can be determined. For example, if the average positional deviation is: This indicates that the origin of the first coordinate system is located in the second coordinate system. This method integrates information from multiple pre-set local photographs, improving the accuracy and reliability of determining the positional relationship of the coordinate system origin. It provides crucial foundational data support for subsequent generation of simulated chip images and related analysis.

[0071] For example, when there are four preset actual local photos, template matching is performed on each preset actual local photo. Each preset actual local photo is used as a template to search for matching regions within the layout design file. Using image processing algorithms (such as squared difference matching, normalized cross-correlation matching, etc.), the similarity between the preset actual local photos and each region of the layout design file is calculated to find the optimal matching position. The center point coordinates (second coordinate system coordinates) of each preset actual local photo in the layout design file are obtained. Simultaneously, the center point coordinates of each preset actual local photo in the first coordinate system are determined. The positions of these photos are pre-defined, and their approximate positions on the chip are known (e.g., distributed at the four corners or edges of the chip). Their center point coordinates in the first coordinate system can be obtained through geometric relationships or pre-annotated information. The positional deviation of each pair of corresponding points (i.e., the center point coordinates of the same preset actual local photo in the two coordinate systems) is calculated. For the i-th preset actual local photo, its center point coordinates in the second coordinate system are subtracted from its center point coordinates in the first coordinate system to obtain the positional deviation of that point in the x-axis and y-axis directions. If there are four preset actual local photos, the average positional deviation is calculated. The calculation is as follows:

[0072]

[0073]

[0074] Average position deviation This reflects the positional relationship between the origins of the first and second coordinate systems. If the average positional deviation is... Then the position of the origin of the first coordinate system in the second coordinate system is This approach, which integrates information from four pre-set local photographs, improves the accuracy of determining the positional relationship of the coordinate system origin, providing crucial foundational data support for subsequent chip-simulated image generation and related analysis.

[0075] Specifically, based on the target position of the preset actual local photograph of the chip in the layout design file, the rotation angle between the first coordinate system and the second coordinate system is obtained, which is achieved in the following way:

[0076] 1) The first method:

[0077] ① The target position of each preset actual partial photograph in the layout design file is determined by template matching technology, and the coordinates of its center point in the second coordinate system are obtained. At the same time, determine the coordinates of the center point of these preset actual partial photographs in the first coordinate system. These coordinates are the basis for subsequent calculations of the rotation angle.

[0078] ② For each preset actual partial photograph, construct two vectors. Specifically, the vector in the first coordinate system is... , Vector in the second coordinate system , These vectors all represent the center point position of the preset actual local photo.

[0079] ③ Calculate the rotation angle of each corresponding point pair (two vectors corresponding to the same preset local photo) using the formula for the angle between vectors. :

[0080]

[0081] in, Representation: Vector sum vector dot product, and They are vectors and The length of the module.

[0082] ④ Calculated rotation angle The value can be positive or negative, and positive or negative values ​​are used to indicate the direction of rotation. Generally, a positive value indicates counter-clockwise rotation, and a negative value indicates clockwise rotation. The definition of the rotation direction can be adjusted according to the specific application requirements.

[0083] It should be noted that since there may be multiple preset actual local photos, each corresponding point pair may have a calculated rotation angle. To improve the accuracy and robustness of the calculation, all calculated rotation angles can be truncated and averaged. The specific steps are as follows:

[0084] Collect the rotation angles of all corresponding point pairs: Remove rotation angles with large deviations and calculate the average value of the remaining rotation angles. As the final rotation angle:

[0085]

[0086] in, Represents: the total number of all corresponding point pairs after truncation. .

[0087] In addition to calculating the rotation angle, it is also necessary to consider the positional relationship between the origins of the first and second coordinate systems, which were determined earlier, to ensure that the final coordinate transformation relationship is accurate.

[0088] 2) The second method:

[0089] The rotation angle between the first and second coordinate systems can also be obtained by rotating the template, which can be achieved in the following way:

[0090] ① Determine the target position of each preset actual partial photograph in the layout design file using existing template matching technology, and obtain its center point coordinates in the second coordinate system. At the same time, determine the coordinates of the center point of these preset actual partial photographs in the first coordinate system. Record the template matching score for this instance. These coordinate and fractional information forms the basis for subsequent calculations of the rotation angle.

[0091] ② For each preset actual local photo, perform multiple rotation template matching using the binary rotation template matching method until the difference between the template matching scores before and after rotation is less than the threshold. Then, stop rotating the template matching. The rotation angle at this point is recorded as the rotation angle obtained from the preset actual local photo. .

[0092] ③ Rotation angle obtained through rotation matching The value can be positive or negative, and positive or negative values ​​are used to indicate the direction of rotation. Generally, a positive value indicates counter-clockwise rotation, and a negative value indicates clockwise rotation. The definition of the rotation direction can be adjusted according to the specific application requirements.

[0093] It should be noted that since there may be multiple preset actual local photos, each preset actual local photo will be matched with a rotation angle. To improve the accuracy and robustness of the calculation, all calculated rotation angles can be truncated and averaged. The specific steps are as follows:

[0094] Collect the rotation angles of all corresponding point pairs: (To distinguish this from the rotation angle obtained by the first method, the superscript 't' indicates the rotation angle obtained by the second method.) Remove rotation angles with large deviations and calculate the average of the remaining rotation angles. As the final rotation angle:

[0095]

[0096] In addition to calculating the rotation angle, it is also necessary to consider the positional relationship between the origins of the first and second coordinate systems, which were determined earlier, to ensure that the final coordinate transformation relationship is accurate.

[0097] 3) The third method:

[0098] Furthermore, the rotation angle between the first and second coordinate systems can be calculated by combining the two methods described above. Specifically, the average value of the rotation angles calculated using the first method and the average value of the average values ​​of the rotation angles calculated using the first method are taken as the final rotation angle.

[0099] By following the steps described above, the rotation angle between the first and second coordinate systems can be accurately obtained. Combined with the positional deviation, a precise transformation between the two coordinate systems can be achieved. This process not only improves the accuracy of coordinate transformation but also provides crucial foundational data support for subsequent chip simulation image generation and related analysis.

[0100] In S1, a simulated photograph of the chip is generated based on the conversion relationship, including:

[0101] S11. Based on the positional relationship between the origin of the first coordinate system and the origin of the second coordinate system, as well as the rotation angle between the first coordinate system and the second coordinate system, and in conjunction with the layout design file, generate a simulated photograph. The simulated photograph can be a complete image of the simulated chip, or multiple images of the simulated chip after it has been divided into blocks. Whether to divide it into blocks and the number of blocks are determined by factors such as the size of the layout file.

[0102] S110. Divide the layout design file into blocks and encode them:

[0103] As the number of components in a layout design file increases, directly processing the entire file leads to an exponential increase in the computational complexity of calculating the distances and positions between components. To reduce computational complexity and improve processing efficiency, the layout design file is first divided into blocks for encoding. The specific implementation is as follows:

[0104] ① Establish a region in a second coordinate system that includes all images in the first coordinate system. Specifically:

[0105] Rotation angle (The final rotation angle mentioned above) and positional deviation (i.e.) and Together, they form a complete transformation relationship between the first and second coordinate systems. The calculated rotation angles are then used. and positional deviation (i.e. and The magnification (scale) of the optical microscope can transform the range in the first coordinate system to the range in the second coordinate system. The transformation relationship of the vertices in this range is expressed by the following transformation formula:

[0106]

[0107]

[0108] in, These are coordinates in the first coordinate system. These are the coordinates in the transformed second coordinate system. For example, if the actual area of ​​a local photograph taken by a microscope is a rectangle, then the final result will be the four vertices of the actual photograph area in the second coordinate system: This range of coordinates will be used in subsequent processes.

[0109] ② Divide the aforementioned coordinate range (the area in the layout design file) into multiple smaller blocks. If the coordinate range is small and does not need to be divided, the entire coordinate range can be set as a unique block.

[0110] Taking row and column partitioning as an example, the following explanation is provided:

[0111] The purpose of row and column partitioning is to divide the layout design file into several rows and columns, forming a grid-like block layout. Row partitioning can be done from top to bottom or bottom to top, while column partitioning can be done from left to right or right to left. Equal spacing partitioning can be used, dividing the height and width of the layout design file into several equal parts to determine the boundary positions of rows and columns. Adaptive partitioning can also be used, dynamically adjusting the spacing of rows and columns according to the distribution of components to ensure a relatively balanced component density within each block. When determining the partition boundaries, the integrity of components must also be considered to ensure that components crossing blocks remain intact without being split. Each partitioned block is uniquely coded for subsequent identification and management. The coding can use a combination of row and column numbers, for example, the first... Line number The blocks of a column can be encoded as The component information within each block is organized and stored, recording the relative position and attributes of the components within the block. A block index is established to enable quick location and access to specific blocks and their component information, improving data processing efficiency.

[0112] When performing block-based processing, the stitching issue between blocks also needs to be considered. Since chip layout design files are usually large, the simulated images of each block need to be seamlessly stitched together after block processing. This requires reserving a certain overlap area when dividing the blocks to avoid obvious boundaries or misalignments at the stitching points.

[0113] ③Analyze the layout design file to accurately extract the coordinate information of all components in each block range on the display layer of the chip, as well as the upper and lower coverage relationship of each layer. This information is the basis for constructing the simulated photograph.

[0114] The components of a quantum chip specifically include: Marks, such as Alignment Marks, Airbridge Marks, and Test Marks. Marks are primarily used to mark the edges of the chip or as alignment references for airbridges within the chip. Because the marked feature points are obvious, actual local photographs containing the marks are generally used as preset actual local photographs. Airbridges are abundant components in superconducting quantum chips, serving to shield signals and reduce crosstalk between different coplanar waveguides. While seemingly simple in structure, they are indeed one of the key components for achieving "large-scale integration" of quantum chips and are also components that require close attention in defect detection. Accurately extracting their coordinate information helps analyze their internal structure and operating status, such as whether the airbridges are evenly and correctly distributed, and whether there are any defects. In addition, there are metal track components, pins (PADs), etc. These components are display components and will be captured and displayed in the actual local photographs. Accurately extracting the coordinates of these points is crucial for generating simulated images of the chip. Determining their coordinates helps to quickly locate the test area, improving testing efficiency and accuracy.

[0115] ④ During the generation of layout design files (such as GDS files), there may be operations that truncate components. These truncated components need to be restored to ensure the integrity and accuracy of the components, thereby reducing the impact of errors on subsequent positioning operations.

[0116] The specific process for restoring these severed components is as follows:

[0117] For each block of the layout design file, information on all components within that block is extracted, including their geometry, location, and dimensions. Simultaneously, components that may be truncated are marked. The truncated component fragments are then reconstructed and reassembled. This reconstruction step forms the basis for generating simulated images. Block-based processing further accelerates computational complexity and improves processing efficiency.

[0118] S111. Dynamically synthesize block-based simulated photographs of the chip based on the block-encoded layout file:

[0119] After completing the block encoding and preprocessing of the layout design file, a block-based simulated photograph of the chip is dynamically synthesized using the configuration parameters of the optical microscope, the block-encoded layout file, and information such as the color and brightness parameters and offset angles of each component extracted in the final photograph. The specific implementation is as follows:

[0120] ① Establish a transformation relationship to transform any point in the second coordinate system to the first coordinate system. The transformation relationship is as follows:

[0121]

[0122]

[0123] The coordinates of components in the layout design file are transformed from the second coordinate system to the first coordinate system. The `scale` parameter is used to obtain the magnification of the optical microscope. The magnification determines the degree of magnification of the chip area.

[0124] ② Process the component information within each block. For each block, determine its appearance in the simulated image by combining the component's color parameters. The color parameters need to be preset and calibrated according to the component's material, manufacturing process, and optical microscope imaging characteristics to ensure the realism and accuracy of the simulated image. All components within each block have a starting coordinate. Using the aforementioned conversion formula, the component coordinate information within the block is converted into relative coordinates in the first coordinate system (a relative coordinate relative to the starting coordinate). Then, using a polygon filling algorithm based on scan lines, a simulated image is constructed in the first coordinate system. The converted relative coordinates can then determine its corresponding position in the simulated image.

[0125] ③ Using the processed image information from each block, it is possible to dynamically synthesize a complete simulated image of the chip. Specifically, the images of each block are stitched together according to their positions on the layout to generate a complete simulated image. This process needs to consider the image size, but it is not mandatory, and subsequent positioning can also be based on block division.

[0126] Since the image generation process for all partitions is based on the layout design file and involves coordinate transformation, the compositing process ensures that the processing results of each block can be seamlessly stitched together to form a complete image. Because excessive magnification may result in excessively large image sizes, if the complete simulated image is too large, consider abandoning the merging process and storing the simulated image according to the previous partitions for later processing and use.

[0127] By following the steps above, simulated images of the chip can be generated efficiently, ensuring that they are highly consistent with actual chip photos in terms of visual effects and coordinate correspondence, thus providing strong support for chip detection, analysis, and optimization.

[0128] S2. After identifying the target region in the actual local photograph of the chip, determine the position of the target region in the layout design file according to the transformation relationship. The coordinate system used in the actual local photograph of the chip is the same as the coordinate system used in the simulated photograph.

[0129] Specifically, it includes:

[0130] S20. Determine the pixel mapping relationship between each actual local photo and the simulated photograph, wherein when the preset actual local photo and the target actual local photo are the same actual local photo, all actual local photos include the same actual local photo; when the preset actual local photo and the target actual local photo are not the same actual local photo, all actual local photos include the preset actual local photo and the target actual local photo; each actual local photo of the chip belongs to the actual photo of the chip.

[0131] S20 specifically includes:

[0132] S200. From the naming information of all actual local photographs taken by the optical microscope, combined with the trajectory relationship of the microscope's shots (i.e., the left-right and top-bottom order of the images) and information such as the step size of the microscope during its movement, an arrangement order for assisting subsequent localization is extracted. Common microscopes generally have relatively fixed movement step sizes to photograph and observe the chip, and a fixed overlapping area is maintained between two movements to ensure a complete chip scan and avoid missed images or detections. These features can be utilized to significantly narrow down the search area when calculating the image localization search area later, thereby improving localization accuracy. Specifically, based on the shooting order of the actual local photographs of the chip taken by the microscope, these actual local photographs are converted into a row and column arrangement in the second coordinate system. For example, if the optical microscope takes pictures of different areas of the chip from left to right and from top to bottom, obtaining multiple actual local photographs, then each actual local photograph can correspond to a row and column position in the second coordinate system.

[0133] S201. Perform template matching for localization on all microscope images, where the template is a simulated photograph. Since the simulated photographs cover a large area, direct template matching is computationally intensive and inefficient. Therefore, it is necessary to use the row and column numbers of each actual partial photograph to estimate the search area of ​​each actual partial photograph. Then, within the estimated search area, template matching is performed between the actual partial photograph and the simulated photograph to achieve a rough localization of the actual partial photograph. The matching results obtained through template matching determine the initial position of each actual partial photograph within the simulated photograph. For example, if an actual partial photograph corresponds to a row and column number of... Based on parameters such as the size of the simulated photograph and the step size of the optical microscope, the approximate search area of ​​the actual local photograph in the simulated photograph can be estimated. Then, template matching is performed within this area to find the best matching position, thereby determining the initial position of the microscope image in the simulated photograph.

[0134] Template matching is a method for finding and identifying smaller images within a larger image. The simulated photographs generated in the preceding steps can be considered the larger images, while the actual local photographs can be considered the smaller images. The goal of this application is to find the actual local photographs within the global simulated photograph image, thus locating each actual local photograph within the global simulated photograph image. Since the generated simulated photographs are entirely based on real-world simulations, the simulated photographs and actual local photographs have similar grayscale values ​​and high similarity, suggesting similar external conditions. Therefore, grayscale-based template matching is chosen. The template matching algorithm used is not fixed; six common algorithms exist, such as squared difference matching, correlation matching, correlation coefficient matching, and the normalized versions of the three mentioned above. The choice depends on the specific situation. For example, if contrast changes but brightness remains constant, normalized correlation matching can be used. If the lighting is complex and brightness fluctuates greatly, normalized correlation coefficient matching can be chosen, although this increases computational complexity.

[0135] S202. After S200 and S201, each microscope image will have a roughly initial positioning. To improve the accuracy of positioning, it is necessary to use the row and column relationships of the actual local photographs formed during the microscope imaging process to correct the position of each actual local photograph, so as to avoid positioning problems such as misalignment. Specifically:

[0136] ① Based on the row and column relationships, correct the initial position of each actual partial photograph in the simulated image. For example, for the actual partial photographs in the third column and fourth row, analyze the y-coordinates of their initial positions using all actual partial photographs located in the fourth row. The y-coordinates of the initial positions of actual partial photographs in the same row should fluctuate slightly according to certain rules; for example, one actual partial photograph might have a slight increase compared to the previous one, but this change should be very small. If the y-coordinates of some actual partial photographs change significantly, it may indicate a positioning error. To avoid a large positioning error in one photograph propagating to the entire row or column, the y-coordinate should consider the entire row, and the x-coordinate should consider the entire column, while extreme data should be removed during correction.

[0137] ② After comparing the errors, narrow down the scope, return to S201, and reposition and correct the photos with errors until all S201 positions are accurate.

[0138] Ultimately, all the partial photographs have accurate positions in the simulated photograph, thus establishing a pixel mapping relationship between each actual partial photograph and the simulated photograph.

[0139] Pixel mapping refers to the correspondence between each pixel in an actual local photograph and its corresponding pixel in a simulated photograph. Through the steps described above, the precise location of each actual local photograph within the simulated photograph can be determined, thus establishing a pixel coordinate correspondence table or transformation function between the two. This allows for accurate location and analysis of the content in the actual local photograph within the coordinate system of the simulated photograph, providing a foundation for applications such as chip inspection and defect analysis. For example, if the relative coordinates of a pixel in the actual local photograph are... By using pixel mapping relationships, we can find the corresponding coordinates of the pixel in the simulated photograph. ,in The starting coordinates of the actual partial photograph within the entire simulated image are determined, thereby enabling information fusion and correlation analysis.

[0140] In another feasible approach, feature points are extracted from both the actual local photograph and the layout design file. In the actual photograph, feature points can be extracted using feature detection algorithms such as Scale Invariant Feature Transform (SIFT), Speed-Up Robust Feature Transform (SURF), or Oriented Fast and Rotated BRIEF (ORB). Similarly, corresponding key feature points, which may correspond to critical structures or markers on the chip, are extracted from the layout design file. Feature matching algorithms, such as brute-force matching or a FLANN-based matcher, are used to match the feature points in the actual photograph with those in the layout design file. By setting an appropriate matching threshold, reliable matching feature point pairs are selected. These matched feature point pairs establish a geometric correspondence between the actual photograph and the layout design file. Based on the matched feature point pairs, the geometric transformation relationship between the actual photograph and the layout design file, such as affine transformation or homography transformation, is estimated. By solving the transformation matrix, the coordinates of the target area in the actual photograph can be transformed to the coordinate system of the layout design file, thereby determining the location of the target area.

[0141] Another feasible approach involves collecting a large amount of labeled actual chip photographs and corresponding layout design files, or generating them automatically. The annotations should include the location of the target region in the actual photograph and its corresponding location in the layout design file. A suitable deep learning model, such as a convolutional neural network (CNN) or a Transformer-based object detection model, is selected. The model is trained using the prepared training data, enabling it to learn the mapping relationship between the actual photographs and the layout design files, and to accurately predict the location of the target region in the layout design file. The actual local photograph of the target is then input into the trained model, which directly outputs the coordinates of the target region's location in the layout design file. However, this method has a high data collection cost; if traditional methods can already achieve high accuracy with auxiliary correction strategies, the use of deep learning methods is not recommended.

[0142] S21. After identifying the target region in the actual local photograph of the chip, determine the position of the target region in the layout design file, i.e., its coordinates in the second coordinate system, based on pixel mapping and transformation relationships. This is specifically achieved through the following formula:

[0143]

[0144]

[0145] in These are the coordinates in the first coordinate system. These are the coordinates in the second coordinate system, i.e., the specific locations in the layout design file.

[0146] The target area can be a defective area or any specified functional area, specifically:

[0147] 1) Defective Areas: During the chip manufacturing process, various defects may occur, such as surface scratches, transistor defects, short circuits, or open circuits. These defective areas are the focus of inspection. By determining their location in the layout design file, we can further analyze the type, cause, and impact of the defects, and take further remedial measures, such as removing the corresponding defective components from the layout.

[0148] 2) Functional Areas: Chips are typically divided into multiple functional areas, such as the processor core. Different functional areas require different approaches to handling defects. During testing, it may be necessary to focus on the performance and connectivity of a particular functional area. For example, detailed electrical testing and defect analysis may be performed on the processor core area.

[0149] Other potential target areas include specific test structures on the chip (for process monitoring and quality control), identification areas (containing manufacturing information and serial numbers, etc.), and high-density wiring areas (prone to signal interference and transmission problems). Depending on the testing task, the target area can be flexibly determined to enable a comprehensive and accurate evaluation and analysis of the chip.

[0150] In the above embodiments, although the steps are numbered S1, S2, etc., they are only specific embodiments given by the present invention. Those skilled in the art can adjust the execution order of S1, S2, etc. according to the actual situation, which is also within the protection scope of the present invention. It can be understood that in some embodiments, some or all of the above embodiments may be included.

[0151] like Figure 4 As shown, a chip layout positioning system 200 according to an embodiment of the present invention includes a conversion relationship determination module 201, an image generation module 202, and a positioning module 203;

[0152] The transformation relationship determination module 201 is used to: obtain the transformation relationship between the first coordinate system and the second coordinate system;

[0153] The photo generation module 202 is used to: generate simulated photographs of the chip based on the conversion relationship;

[0154] Wherein, the first coordinate system refers to the coordinate system used in the actual photograph of the chip, the second coordinate system refers to the coordinate system used in the chip's layout design file, and the coordinate system used in the simulated photograph is the first coordinate system;

[0155] The positioning module 203 is used to: determine the position of the target area in the layout design file according to the transformation relationship after the target area is determined in the actual local photograph of the chip, wherein the actual local photograph of the chip is the actual photograph of the chip.

[0156] Optionally, in the above technical solution, the transformation relationship between the first coordinate system and the second coordinate system includes: the positional relationship between the origin of the first coordinate system and the origin of the second coordinate system, and the rotation angle between the first coordinate system and the second coordinate system. The transformation relationship determination module 201 is specifically used for:

[0157] Determine and, based on the target position of the chip's preset actual partial photograph in the layout design file, obtain the positional relationship between the origin of the first coordinate system and the origin of the second coordinate system, and obtain the rotation angle between the first coordinate system and the second coordinate system. Here, the preset actual partial photograph of the chip is the actual photograph of the chip.

[0158] Optionally, in the above technical solution, the photo generation module is specifically used to: generate a simulated photograph based on the positional relationship between the origin of the first coordinate system and the origin of the second coordinate system, the rotation angle between the first coordinate system and the second coordinate system, and in conjunction with the layout design file.

[0159] Optionally, in the above technical solution, the positioning module 203 is specifically used for:

[0160] Determine the pixel mapping relationship between each actual local photo of the chip and the simulated photograph. When the preset actual local photo and the target actual local photo are the same actual local photo, all actual local photos include the same actual local photo. When the preset actual local photo and the target actual local photo are not the same actual local photo, all actual local photos include both the preset actual local photo and the target actual local photo. Each actual local photo of the chip belongs to the actual photo of the chip.

[0161] Once the target region is identified in the actual local photograph, the position of the target region in the layout design file is determined based on the pixel mapping relationship, the positional relationship between the origin of the first coordinate system and the origin of the second coordinate system, and the rotation angle between the first coordinate system and the second coordinate system.

[0162] It should be noted that the beneficial effects of the chip layout positioning system 200 provided in the above embodiments are the same as those of the chip layout positioning method described above, and will not be repeated here. Furthermore, the system provided in the above embodiments is only illustrated by the division of the above functional modules. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the system can be divided into different functional modules according to the actual situation to complete all or part of the functions described above. In addition, the system and method embodiments provided in the above embodiments belong to the same concept, and their specific implementation process is detailed in the method embodiments, and will not be repeated here.

[0163] The chip layout positioning system of the present invention can be a computer program (including program code) running on a computer device. For example, the chip layout positioning system of the present invention is an application software that can be used to execute the corresponding steps in the chip layout positioning method of the present invention.

[0164] In some embodiments, the chip layout positioning system of the present invention can be implemented in a combination of hardware and software. As an example, the chip layout positioning system of the present invention can be a processor in the form of a hardware decoding processor, which is programmed to execute the chip layout positioning method of the present invention. For example, the processor in the form of a hardware decoding processor can be one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), or other electronic components.

[0165] The modules described in the embodiments of this invention can be implemented in software or hardware. The names of the modules are not, in some cases, limiting the scope of the module itself.

[0166] An electronic device according to an embodiment of the present invention includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements any of the chip layout positioning methods described above. That is, an electronic device according to an embodiment of the present invention may include, but is not limited to: a processor and a memory; the memory is used to store the computer program; the processor is used to execute the chip layout positioning method shown in any embodiment of the present invention by calling the computer program.

[0167] In one alternative embodiment, an electronic device is provided, such as Figure 5 As shown, Figure 5 The illustrated electronic device 4000 includes a processor 4001 and a memory 4003. The processor 4001 and the memory 4003 are connected, for example, via a bus 4002. Optionally, the electronic device 4000 may further include a transceiver 4004, which can be used for data interaction between the electronic device and other electronic devices, such as sending and / or receiving data. It should be noted that in practical applications, the transceiver 4004 is not limited to one type, and the structure of the electronic device 4000 does not constitute a limitation on the embodiments of the present invention.

[0168] Processor 4001 may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this invention. Processor 4001 may also be a combination that implements computational functions, such as including one or more microprocessor combinations, a combination of a DSP and a microprocessor, etc.

[0169] Bus 4002 may include a path for transmitting information between the aforementioned components. Bus 4002 may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. Bus 4002 can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 5 The bus 4002 is represented by only one thick line, but this does not mean that there is only one bus or one type of bus.

[0170] The memory 4003 may be ROM (Read Only Memory) or other types of static storage devices capable of storing static information and instructions, RAM (Random Access Memory) or other types of dynamic storage devices capable of storing information and instructions, or EEPROM (Electrically Erasable Programmable Read Only Memory), CD-ROM (Compact Disc Read Only Memory) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited thereto.

[0171] The memory 4003 stores application code (computer program) for executing the present invention, and its execution is controlled by the processor 4001. The processor 4001 executes the application code stored in the memory 4003 to implement the content shown in the foregoing method embodiments.

[0172] Among them, electronic devices can also be terminal devices, which can be any device that can install applications, including at least one of smartphones, tablets, laptops, desktop computers, smart speakers, smartwatches, smart TVs, and smart in-vehicle devices.

[0173] It should be noted that, Figure 5 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of use of the embodiments of the present invention.

[0174] A chip testing system according to an embodiment of the present invention includes any of the chip layout positioning systems described above.

[0175] An embodiment of the present invention provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements any of the above-described chip layout positioning methods.

[0176] Alternatively, the computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CD-ROM), magnetic tape, a floppy disk, and an optical data storage device, etc.

[0177] In an exemplary embodiment, a computer program product or computer program is also provided, which includes computer instructions stored in a computer-readable storage medium. A processor of an electronic device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the electronic device to perform any of the chip layout positioning methods described above.

[0178] Computer program code for performing the operations of this invention can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0179] It should be understood that the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of methods and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0180] The computer-readable storage medium provided in this invention can be, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EEPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this invention, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0181] The aforementioned computer-readable storage medium carries one or more programs, which, when executed by the electronic device, cause the electronic device to perform the method shown in the above embodiments.

[0182] The above description is merely a preferred embodiment of the present invention and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of disclosure in this invention is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-disclosed concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this invention.

[0183] It should be noted that the terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and represent a limitation on a specific order or sequence. Where appropriate, the order of use for similar objects can be interchanged so that the embodiments of this application described herein can be implemented in an order other than that shown or described.

[0184] Those skilled in the art will recognize that this invention can be implemented as a system, method, or computer program product. Therefore, this invention can be specifically implemented in the following forms: it can be entirely hardware, entirely software (including firmware, resident software, microcode, etc.), or a combination of hardware and software, generally referred to herein as a "circuit," "module," or "system." Furthermore, in some embodiments, this invention can also be implemented as a computer program product contained in one or more computer-readable media, which includes computer-readable program code.

[0185] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A chip layout positioning method, characterized in that, include: Obtain the transformation relationship between the first coordinate system and the second coordinate system, and generate a simulated photograph of the chip based on the transformation relationship; wherein, the first coordinate system refers to the coordinate system used in the actual photograph of the chip, the second coordinate system refers to the coordinate system used in the layout design file of the chip, and the coordinate system used in the simulated photograph is the first coordinate system; Once the target region is determined in the actual partial photograph of the chip, the position of the target region in the layout design file is determined according to the transformation relationship, wherein the actual partial photograph of the chip is a photograph of the chip. Based on the conversion relationship, a simulated photograph of the chip is generated, including: Based on the positional relationship between the origin of the first coordinate system and the origin of the second coordinate system, as well as the rotation angle between the first coordinate system and the second coordinate system, and in conjunction with the layout design file, the simulated photographic image is generated. After identifying the target region in the actual local photograph of the chip, the position of the target region in the layout design file is determined according to the transformation relationship, including: The pixel mapping relationship between each actual local photograph of the chip and the simulated photograph is determined. When the preset actual local photograph and the target actual local photograph are the same actual local photograph, all actual local photographs include the same actual local photograph. When the preset actual local photograph and the target actual local photograph are not the same actual local photograph, all actual local photographs include the preset actual local photograph and the target actual local photograph. Each actual local photograph of the chip belongs to the actual photograph of the chip. Once the target region is determined in the actual partial photograph of the target, the position of the target region in the layout design file is determined based on the pixel mapping relationship, the positional relationship between the origin of the first coordinate system and the origin of the second coordinate system, and the rotation angle between the first coordinate system and the second coordinate system.

2. The chip layout positioning method according to claim 1, characterized in that, The transformation relationship between the first coordinate system and the second coordinate system includes: the positional relationship between the origin of the first coordinate system and the origin of the second coordinate system, as well as the rotation angle between the first coordinate system and the second coordinate system; Obtain the transformation relationship between the first coordinate system and the second coordinate system, including: Determine and, based on the target position of the preset actual partial photograph of the chip in the layout design file, obtain the positional relationship between the origin of the first coordinate system and the origin of the second coordinate system, and obtain the rotation angle between the first coordinate system and the second coordinate system, wherein the preset actual partial photograph of the chip is a photograph of the chip.

3. A chip layout positioning system, characterized in that, It includes a module for determining the conversion relationship, a photo generation module, and a positioning module; The transformation relationship determination module is used to: obtain the transformation relationship between the first coordinate system and the second coordinate system; The photo generation module is used to: generate a simulated photograph of the chip based on the conversion relationship; Wherein, the first coordinate system refers to the coordinate system used in the actual photograph of the chip, the second coordinate system refers to the coordinate system used in the layout design file of the chip, and the coordinate system used in the simulated photograph is the first coordinate system; The positioning module is used to: after determining the target area in the actual local photograph of the chip, determine the position of the target area in the layout design file according to the conversion relationship, wherein the actual local photograph of the chip is a photograph of the chip. The photo generation module is specifically used to: generate the simulated photograph based on the positional relationship between the origin of the first coordinate system and the origin of the second coordinate system, the rotation angle between the first coordinate system and the second coordinate system, and in conjunction with the layout design file; The positioning module is specifically used for: The pixel mapping relationship between each actual local photograph of the chip and the simulated photograph is determined. When the preset actual local photograph and the target actual local photograph are the same actual local photograph, all actual local photographs include the same actual local photograph. When the preset actual local photograph and the target actual local photograph are not the same actual local photograph, all actual local photographs include the preset actual local photograph and the target actual local photograph. Each actual local photograph of the chip belongs to the actual photograph of the chip. Once the target region is determined in the actual partial photograph of the target, the position of the target region in the layout design file is determined based on the pixel mapping relationship, the positional relationship between the origin of the first coordinate system and the origin of the second coordinate system, and the rotation angle between the first coordinate system and the second coordinate system.

4. The chip layout positioning system according to claim 3, characterized in that, The transformation relationship between the first coordinate system and the second coordinate system includes: the positional relationship between the origin of the first coordinate system and the origin of the second coordinate system, and the rotation angle between the first coordinate system and the second coordinate system. The transformation relationship determination module is specifically used for: Determine and, based on the target position of the preset actual partial photograph of the chip in the layout design file, obtain the positional relationship between the origin of the first coordinate system and the origin of the second coordinate system, and obtain the rotation angle between the first coordinate system and the second coordinate system, wherein the preset actual partial photograph of the chip is a photograph of the chip.

5. An electronic device, characterized in that, The device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement a chip layout positioning method according to any one of claims 1 to 2.

6. A chip testing system, characterized in that, Includes a chip layout positioning system as described in any one of claims 3 to 4.

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