Digital eye pattern test method, apparatus, device, and storage medium

Abstract

The application discloses a digital eye diagram test method, device, equipment and storage medium, and relates to the technical field of testing. The digital eye diagram test method comprises the following steps: acquiring bus data of a bus corresponding to a to-be-tested memory particle in real time through a capture IC to obtain data signals of multiple channels; generating a digital eye diagram based on the data signals, and acquiring an eye width and an eye height corresponding to the digital eye diagram; if the eye width is smaller than a preset eye width or the eye height is smaller than a preset eye height, adjusting register parameters of multiple registers in a memory corresponding memory controller based on the eye width and the eye height, acquiring bus data through the capture IC to obtain data signals of multiple channels, generating a digital eye diagram according to the data signals of the multiple channels, and automatically adjusting the parameters of the registers according to the eye width and the eye height corresponding to the digital eye diagram to increase the eye height and the eye width of the digital eye diagram, so that the whole process from eye diagram measurement to register adjustment is automatically realized, and the memory test efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of testing technology, and in particular to a digital eye diagram testing method, apparatus, device, and storage medium. Background Technology

[0002] With the development of DDR (Double Data Rate) memory technology to the DDR5 era, its clock frequency has changed from 2400MHz to 4000MHz. As data transfer rates have significantly increased, signal integrity has become crucial. The digital eye diagram (DAD) is a key tool for evaluating signal integrity; it constructs a DAD by superimposing multiple 0s and 1s. Based on bit positions, the "eye height" and "eye width" of the diagram visually reflect the signal's noise and timing margins. To achieve optimal signal quality, the memory controller needs to be trained during system startup or operation. This involves adjusting a series of physical layer parameters (such as timing offset, voltage reference VREF, and on-chip resistor ODT) to optimize signal quality, followed by memory stress testing to verify the appropriateness of these parameter settings.

[0003] Currently, the mainstream methods for signal integrity analysis and training optimization of the DDR5 bus include oscilloscope-based eye diagram analysis and logic analyzer-based methods. In the oscilloscope-based method, a high-speed oscilloscope is connected to the DDR5 bus via differential probes or an interposer to directly capture analog signals and plot eye diagrams. Based on the quality of the eye diagram, the register parameters in the memory controller are manually adjusted, undergoing multiple rounds of "test-adjust-verify" cycles until the optimal settings are found. However, the oscilloscope requires a physical connection to the differential probe, a complex process prone to introducing measurement errors. Manually performing multiple rounds of stress testing and register adjustments is extremely time-consuming and unsuitable for large-scale production or automated scenarios. This is especially true for already assembled mobile phones / laptops, which lack DDR signal measurement points. Furthermore, high-end oscilloscopes typically have a limited number of channels, making it difficult to perform parallel, synchronous eye diagram analysis on multiple DDR5 data channels simultaneously. Comprehensive testing requires multiple devices or multiple tests, resulting in very high costs. Logic analyzers, on the other hand, primarily capture digital signals for protocol analysis, but have limited capabilities for accurate eye diagram generation and analog parameter optimization. Logic analyzers primarily handle digital signals and cannot generate eye height data.

[0004] Therefore, improving memory testing efficiency is a problem that urgently needs to be solved.

[0005] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention

[0006] The main objective of this application is to provide a digital eye diagram testing method, apparatus, device, and storage medium, aiming to solve the technical problem of how to improve memory testing efficiency.

[0007] To achieve the above objectives, this application proposes a digital eye diagram testing method, wherein the memory chip under test is equipped with a capture IC, and the digital eye diagram testing method includes:

[0008] The capture IC captures the bus data of the bus corresponding to the memory chip under test in real time, and obtains data signals from multiple channels.

[0009] A digital eye diagram is generated based on the data signal, and the eye width and eye height corresponding to the digital eye diagram are obtained;

[0010] If the eye width is less than a preset eye width or the eye height is less than a preset eye height, then the register parameters of multiple registers in the memory controller corresponding to the memory are adjusted based on the eye width and eye height, and the process returns to the step of capturing the bus data of the bus corresponding to the memory chip under test in real time through the capture IC to obtain data signals of multiple channels.

[0011] In one embodiment, the capture IC includes a multi-phase clock generator, a multi-level comparator array, and a SerDes interface; the step of capturing the bus data of the bus corresponding to the memory chip under test in real time through the capture IC to obtain data signals of multiple channels includes:

[0012] By capturing the multi-phase clock generator and multi-level comparator array of the IC, the bus data is scanned in two dimensions to obtain data signals from multiple channels;

[0013] The data signal is acquired through the Serdes interface of the capture IC.

[0014] In one embodiment, the step of performing a two-dimensional scan of the bus data using a multi-phase clock generator and a multi-level comparator array of a capture IC to obtain data signals for multiple channels includes:

[0015] The multi-phase clock generator generates multiple sampling clock phases that are uniformly distributed within a unit interval, and the multi-level comparator array generates multiple reference voltages of different levels.

[0016] For each data bit in the bus data, the data bit is sampled based on the clock phase to obtain a sampled voltage, and the sampled voltage is compared with the corresponding reference voltage to obtain the digital result corresponding to each sample.

[0017] Determine the two-dimensional data matrix corresponding to each digital result, wherein the data signal includes a two-dimensional data matrix corresponding to multiple data bits in each bus data.

[0018] In one embodiment, the capture IC further includes an I2C interface, and the digital eye diagram testing method further includes:

[0019] The multi-level sampling level corresponding to the capture IC can be set through the I2C interface;

[0020] The step of generating multiple reference voltages of different levels through the multi-level comparator array includes:

[0021] The multilevel comparator array generates reference voltages corresponding to each sampling level.

[0022] In one embodiment, the step of generating a digital eye diagram based on the data signal includes:

[0023] The digital eye diagram is obtained by superimposing two-dimensional data matrices corresponding to multiple data bits.

[0024] In one embodiment, the register includes at least a DQS delay register, a drive strength register, an ODT register, and a reference voltage VREF register.

[0025] In one embodiment, the bus includes a command bus CA, a data bus DQ / DQS, and a chip select CS.

[0026] Furthermore, to achieve the above objectives, this application also proposes a digital eye diagram testing device, which includes:

[0027] The capture module is used to capture the bus data of the bus corresponding to the memory chip under test in real time through the capture IC to obtain the data signal;

[0028] A generation module is used to generate a digital eye diagram based on the data signal, and to obtain the eye width and eye height corresponding to the digital eye diagram;

[0029] The execution module is configured to, if the eye width is less than a preset eye width or the eye height is less than a preset eye height, adjust the register parameters of multiple registers in the memory controller corresponding to the memory based on the eye width and eye height, and return to the step of executing the step of capturing the bus data of the bus corresponding to the memory chip under test in real time through the capture IC to obtain the data signal.

[0030] In addition, to achieve the above objectives, this application also proposes a digital eye diagram testing device, the device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the aforementioned digital eye diagram testing method.

[0031] In addition, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps of the aforementioned digital eye diagram testing method.

[0032] One or more technical solutions proposed in this application have at least the following technical effects:

[0033] The capture IC captures bus data from the bus corresponding to the memory chip under test in real time, obtaining data signals from multiple channels. Then, a digital eye diagram is generated based on the data signals, and the eye width and eye height corresponding to the digital eye diagram are obtained. If the eye width or eye height is less than a preset eye width or eye height, the register parameters of multiple registers in the memory controller corresponding to the memory chip are adjusted based on the eye width and eye height. The process then returns to the previous step of capturing bus data from the bus corresponding to the memory chip under test in real time using the capture IC to obtain data signals from multiple channels. This process, which involves capturing bus data to obtain data signals from multiple channels, generating a digital eye diagram based on the data signals from multiple channels, and automatically adjusting register parameters based on the eye width and eye height of the digital eye diagram to increase the eye height and eye width, demonstrates that a wider eye diagram (i.e., a larger eye width) indicates a signal duty cycle closer to 50%, and a higher eye diagram (i.e., a larger eye height) indicates better signal anti-interference capability. This achieves full automation from eye diagram measurement to register adjustment, improving memory testing efficiency. Attached Figure Description

[0034] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0035] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a flowchart illustrating an embodiment of the digital eye diagram testing method of this application.

[0037] Figure 2 This is a schematic diagram of the module structure of the digital eye diagram testing device according to an embodiment of this application;

[0038] Figure 3 This is a schematic diagram of the device structure of the hardware operating environment involved in the digital eye diagram testing method in the embodiments of this application;

[0039] Figure 4 This is a schematic diagram of a digital eye diagram in one embodiment of this application;

[0040] Figure 5 This is a schematic diagram of the data signals corresponding to different reference voltages in one embodiment of this application.

[0041] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0042] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0043] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0044] The main solution of this application embodiment is: to capture the bus data of the bus corresponding to the memory chip under test in real time through the capture IC to obtain data signals of multiple channels; to generate a digital eye diagram based on the data signals and obtain the eye width and eye height corresponding to the digital eye diagram; if the eye width is less than a preset eye width or the eye height is less than a preset eye height, then to adjust the register parameters of multiple registers in the memory controller corresponding to the memory based on the eye width and eye height, and return to execute the step of capturing the bus data of the bus corresponding to the memory chip under test in real time through the capture IC to obtain data signals of multiple channels.

[0045] In this embodiment, for ease of description, the digital eye diagram testing device will be used as the execution subject for the following description.

[0046] With the development of DDR (Double Data Rate) memory technology to the DDR5 era, its clock frequency has changed from 2400MHz to 4000MHz. As data transfer rates have significantly increased, signal integrity has become crucial. The digital eye diagram (DAD) is a key tool for evaluating signal integrity; it constructs a DAD by superimposing multiple 0s and 1s. Based on bit positions, the "eye height" and "eye width" of the diagram visually reflect the signal's noise and timing margins. To achieve optimal signal quality, the memory controller needs to be trained during system startup or operation. This involves adjusting a series of physical layer parameters (such as timing offset, voltage reference VREF, and on-chip resistor ODT) to optimize signal quality, followed by memory stress testing to verify the appropriateness of these parameter settings.

[0047] Currently, the mainstream methods for signal integrity analysis and training optimization of the DDR5 bus include oscilloscope-based eye diagram analysis and logic analyzer-based methods. In the oscilloscope-based method, a high-speed oscilloscope is connected to the DDR5 bus via differential probes or an interposer to directly capture analog signals and plot eye diagrams. Based on the quality of the eye diagram, the register parameters in the memory controller are manually adjusted, undergoing multiple rounds of "test-adjust-verify" cycles until the optimal settings are found. However, the oscilloscope requires a physical connection to the differential probe, a complex process prone to introducing measurement errors. Manually performing multiple rounds of stress testing and register adjustments is extremely time-consuming and unsuitable for large-scale production or automated scenarios. This is especially true for already assembled mobile phones / laptops, which lack DDR signal measurement points. Furthermore, high-end oscilloscopes typically have a limited number of channels, making it difficult to perform parallel, synchronous eye diagram analysis on multiple DDR5 data channels simultaneously. Comprehensive testing requires multiple devices or multiple tests, resulting in very high costs. Logic analyzers, on the other hand, primarily capture digital signals for protocol analysis, but have limited capabilities for accurate eye diagram generation and analog parameter optimization. Logic analyzers primarily handle digital signals and cannot generate eye height data.

[0048] Therefore, improving memory testing efficiency is a problem that urgently needs to be solved.

[0049] This application provides a solution that captures bus data from multiple channels using an IC, generates a digital eye diagram based on the data signals from these channels, and automatically adjusts the register parameters according to the eye width and eye height of the digital eye diagram to increase the eye height and eye width. A wider eye diagram indicates a signal duty cycle closer to 50%, and a higher eye diagram indicates better signal anti-interference capability. This achieves full automation from eye diagram measurement to register adjustment, improving memory testing efficiency.

[0050] It should be noted that the executing entity in this embodiment can be a computing service device with data processing, network communication, and program execution functions, such as a tablet computer, personal computer, or mobile phone, or an electronic device or digital eye diagram testing device capable of performing the above functions. The following description uses a digital eye diagram testing device as an example to illustrate this embodiment and the subsequent embodiments.

[0051] Based on this, embodiments of this application provide a digital eye diagram testing method, referring to... Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the digital eye diagram testing method of this application.

[0052] In this embodiment, the memory chip under test is equipped with a capture IC. The capture IC is used to capture the bus data of the bus corresponding to the memory chip under test. The bus includes the command bus CA, the data bus DQ / DQS, and the chip select CS.

[0053] The registers in the memory controller include at least the DQS delay register, drive strength register, ODT register, and reference voltage VREF register.

[0054] The digital eye diagram testing method includes steps S110~S130:

[0055] Step S110: The capture IC captures the bus data of the bus corresponding to the memory chip under test in real time to obtain data signals of multiple channels;

[0056] In this embodiment of the application, when testing the memory chip under test, the bus data corresponding to the memory chip under test is captured in real time by a capture IC to obtain data signals from multiple channels. The capture IC includes a multi-phase clock generator, a multi-level comparator array, and a SerDes interface. The capture IC performs a two-dimensional scan of the bus data using the sampling clock phase generated by the multi-phase clock generator and the sampling voltage generated by the multi-level comparator array to obtain data signals from multiple channels. Further, in a feasible implementation, the capture IC includes a multi-phase clock generator, a multi-level comparator array, and a SerDes interface. Step S110 may include steps A110~A120:

[0057] Step A110: By using the multi-phase clock generator and multi-level comparator array of the capture IC, the bus data is scanned in two dimensions to obtain data signals from multiple channels;

[0058] Step A120: Obtain the data signal through the Serdes interface of the capture IC.

[0059] It should be noted that the multi-phase clock generator is used to generate multiple sampling clock phases that are evenly distributed within a unit interval. For example, the multi-phase clock generator can generate 32 sampling clock phases that are evenly distributed within a unit interval. The multi-level comparator array is used to generate multiple reference voltages of different levels. For example, the multi-level comparator array can generate 32 reference voltages of different levels.

[0060] In this embodiment, the capture IC performs a two-dimensional scan of the bus data using the sampling clock phase generated by the multi-phase clock generator and the sampling voltage generated by the multi-level comparator array to obtain data signals from multiple channels. The data signals are obtained through the Serdes interface of the capture IC. For example, when the digital eye diagram test device is a host computer, the FPGA obtains the data signals captured by the capture IC through the Serdes interface and uploads the obtained data signals to the host computer.

[0061] Furthermore, in another feasible implementation, step A110 may include steps A111 to A113:

[0062] Step A111: The multi-phase clock generator generates multiple sampling clock phases that are uniformly distributed within a unit interval, and the multi-level comparator array generates multiple reference voltages of different levels.

[0063] Step A112: For each data bit in the bus data, the data bit is sampled based on the clock phase to obtain the sampled voltage, and the sampled voltage is compared with the corresponding reference voltage to obtain the digital result corresponding to each sample.

[0064] Step A113: Determine the two-dimensional data matrix corresponding to each digital result, wherein the data signal includes a two-dimensional data matrix corresponding to multiple data bits in each bus data.

[0065] In this embodiment of the application, a multi-phase clock generator can generate multiple sampling clock phases that are uniformly distributed within a unit interval. For example, a multi-phase clock generator can generate 32 sampling clock phases that are uniformly distributed within a unit interval. A multi-level comparator array can generate multiple reference voltages of different levels. For example, a multi-level comparator array can generate 32 reference voltages of different levels. The sampling clock phases and reference voltages can be generated before testing the memory chip under test, or during testing the memory chip under test.

[0066] After sampling the clock phase and reference voltage, the capture IC performs a two-dimensional scan of the bus data using the sampling clock phase and sampling voltage to obtain data signals from multiple channels. For each data bit in the bus data, the data bit is sampled based on the clock phase to obtain a sampling voltage. The sampling voltage is then compared with the corresponding reference voltage to obtain the digital result corresponding to each sampling, and the two-dimensional data matrix corresponding to each digital result is determined. That is, a two-dimensional data matrix is ​​obtained based on the digital result of each data bit. Specifically, for each data bit, each comparison of the "sampling voltage - reference voltage" combination yields a 1-bit digital result (0 or 1). For example, the digital result is 1 when the sampling voltage is greater than or equal to the reference voltage, and 0 when the sampling voltage is less than or equal to the reference voltage. By using multiple reference voltages and sampling voltages, a two-dimensional data matrix formed by multiple sets of digital results can be obtained. For example, by using 32 reference voltages of different levels and 32 sampling clock phases evenly distributed within a unit interval, a 32 (phase) * 32 (voltage) two-dimensional data matrix can be obtained. In this two-dimensional data matrix, the distribution of logic '0' and logic '1' will form a pattern. Ideally, the center region of the matrix is ​​'0' (representing the center of the eye diagram, where the signal is stable), and the outer region is '1'.

[0067] Furthermore, in another feasible implementation, the capture IC also includes an I2C interface, and the digital eye diagram testing method further includes:

[0068] Step A114: Set the multi-level sampling level corresponding to the capture IC through the I2C interface;

[0069] Step A111 includes:

[0070] Step A1111: The reference voltage corresponding to each sampling level is generated by the multi-level comparator array.

[0071] In this embodiment, the capture IC communicates with the FPGA via an I2C interface. The host computer sends multi-level sampling levels to the FPGA, and the FPGA sends multi-level sampling levels to the capture IC via the I2C interface. The capture IC receives multi-level sampling levels through the I2C interface. During the digital eye diagram test, the capture IC generates reference voltages corresponding to each sampling level through a multi-level comparator array. For example, the multi-level comparator array generates 32 different reference voltages based on 32 sampling levels.

[0072] Step S120: Generate a digital eye diagram based on the data signal, and obtain the eye width and eye height corresponding to the digital eye diagram;

[0073] In this embodiment, after acquiring the data signal, a digital eye diagram is generated based on the data signal. Specifically, a data eye diagram can be obtained by superimposing a two-dimensional data matrix of multiple data bits. Furthermore, in another feasible implementation, step S120 may include step S121:

[0074] Step S121: Superimpose the two-dimensional data matrices corresponding to multiple data bits to obtain the digital eye diagram.

[0075] In this embodiment, the capture IC uploads data signals to the FPGA via the SerDes interface. The FPGA then uploads the data signals to the host computer via PCIe. The host computer superimposes the two-dimensional data matrices corresponding to multiple data bits in the data signals to obtain the digital eye diagram. For example, 1024 or more 32x32 two-dimensional data matrices are superimposed to synthesize a complete digital eye diagram. After obtaining the digital eye diagram, the eye height and eye width can be accurately calculated by analyzing the matrix obtained by superimposing multiple two-dimensional data matrices. The eye height is the voltage range corresponding to the height of the vertical continuous '0' (or continuous '1') region at the center optimal sampling phase, and the eye width is the time range corresponding to the width of the horizontal continuous '0' (or continuous '1') region at the center reference voltage level. Thus, the eye width and eye height corresponding to the digital eye diagram are obtained.

[0076] The specific process of generating a digital eye diagram based on data signals is as follows: Figure 4 as well as Figure 5 As shown, Figure 4 In the diagram, red indicates invalid data and green indicates valid data. For example, if the data to be read is 0, but the actual data read is 1, then the read data is invalid.

[0077] Figure 5 This section describes the scenarios where data is read using different reference voltages, vref. When the read data is less than vref, the read data is 0; when the read data is greater than or equal to vref, the read data is 1. Figure 5 In (1), all the data read is 0, and therefore the corresponding eye width is 0; Figure 5 All the data read in (4) are 1, and therefore the corresponding eye width is also 0; Figure 5 In (2) of the data read, the number of 1s is less than the number of 0s, and the corresponding eye width depends on the number of 1s read; Figure 5 In (3) of the data read, the number of 1s is the same as the number of 0s, and the corresponding eye width is the maximum value. The specific eye width is determined according to the number of reference voltages / phases.

[0078] All valid phase data (0s and 1s) read are superimposed to form a digital eye diagram, for example, such as... Figure 4 As shown, the digital eye diagram formed by superimposing the valid data corresponding to vref1-0 and vref1-1 is called eye diagram vref1; the digital eye diagram formed by superimposing the valid data corresponding to vref2-0 and vref2-1 is called eye diagram vref2; the clock cycle is 32 phases, with 0 and 1 each occupying 16 phases.

[0079] like Figure 4 As shown, the DDR5 signal reference voltage range can be 0.9~1.4V. If the step size is set to 0.1V, there are 6 vrefs. The digital eye diagram formed by the 6 vrefs includes eye diagram superposition vref1, eye diagram superposition vref2, eye diagram superposition vref3, eye diagram superposition vref4, eye diagram superposition vref5, and eye diagram superposition vref6. Then, based on the digital eye diagram formed by the 6 vrefs, the corresponding eye width and eye height are calculated, resulting in an eye width of 9 and an eye height of 6. Among them, the optimal vref is vref4, which corresponds to an eye width of 9 and a signal duty cycle of 9 / 32 = 28.1%.

[0080] Step S130: If the eye width is less than a preset eye width or the eye height is less than a preset eye height, then adjust the register parameters of multiple registers in the memory controller corresponding to the memory based on the eye width and eye height, and return to the step of capturing the bus data of the bus corresponding to the memory chip under test in real time through the capture IC to obtain data signals of multiple channels.

[0081] In this embodiment, after obtaining the eye width and eye height corresponding to the digital eye diagram, the preset eye width and preset eye height of engineering practice are obtained, and then it is determined whether the eye width is less than the preset eye width and whether the eye height is less than the preset eye height. If the eye width is greater than or equal to the preset eye width and the eye height is greater than or equal to the preset eye height, then the data eye diagram is determined to be the final data eye diagram.

[0082] If the eye width is less than a preset eye width or the eye height is less than a preset eye height, the register parameters of multiple registers in the memory controller corresponding to the memory are adjusted based on the eye width and eye height. Specifically, the host computer reports the calculated eye height and eye width to the application CPU corresponding to the memory via a Socket communication interface. The driver software or firmware algorithm in the application CPU adjusts the relevant registers of the memory controller based on the eye height and eye width. These registers include at least a DQS delay register, a drive strength register, an ODT register, and a reference voltage VREF register. The eye width of the data eye diagram can be adjusted by adjusting the parameters of the DQS delay register, the eye height of the data eye diagram can be adjusted by adjusting the parameters of the VREF register, and the eye height of the data eye diagram can be adjusted by adjusting the parameters of the ODT register. Afterward, the process returns to the step of capturing the bus data of the bus corresponding to the memory chip under test in real time through the capture IC to obtain data signals from multiple channels, so as to realize fully automatic closed-loop training of the digital eye diagram, ensuring that the eye height and eye width are not less than the eye width and eye height based on engineering practice.

[0083] This application embodiment can simultaneously support parallel eye diagram capture and analysis of up to 32 or more DDR5 data channels. Compared with expensive multi-channel oscilloscopes, it has significant advantages in terms of channel quantity and testing efficiency, making it particularly suitable for rapid testing by SOC chip manufacturers. Furthermore, it achieves full automation from eye diagram measurement to register adjustment, requiring no manual intervention, greatly shortening system training and debugging time, and improving production efficiency and consistency.

[0084] This application uses high-resolution two-dimensional scanning to accurately reconstruct digital eye diagrams and extract key parameters. It can monitor signal quality in real time and dynamically adjust parameters when the system environment changes (such as temperature drift) to always keep the system's digital eye diagram in the best state.

[0085] This embodiment provides a digital eye diagram testing method. The method involves capturing bus data from the bus corresponding to the memory chip under test in real time using a capture IC to obtain data signals from multiple channels. A digital eye diagram is then generated based on these data signals, and the eye width and eye height corresponding to the digital eye diagram are obtained. If the eye width or eye height is less than a preset eye width or eye height, the register parameters of multiple registers in the memory controller corresponding to the memory chip are adjusted based on the eye width and eye height. The method then returns to the previous step of capturing bus data from the bus corresponding to the memory chip under test in real time using the capture IC to obtain data signals from multiple channels. By capturing bus data using the capture IC to obtain data signals from multiple channels, generating a digital eye diagram based on these signals, and automatically adjusting the register parameters according to the eye width and eye height of the digital eye diagram, the eye height and eye width of the digital eye diagram are increased. A wider eye diagram (i.e., a larger eye width) indicates a signal duty cycle closer to 50%, and a higher eye diagram (i.e., a larger eye height) indicates better signal anti-interference capability. This method achieves full automation from eye diagram measurement to register adjustment, improving memory testing efficiency.

[0086] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the digital eye diagram testing method of this application. Any simple modifications based on this technical concept are within the protection scope of this application.

[0087] This application also provides a digital eye diagram testing device; please refer to... Figure 2 The digital eye diagram testing device includes:

[0088] The capture module 10 is used to capture the bus data of the bus corresponding to the memory chip under test in real time through the capture IC to obtain the data signal;

[0089] The generation module 20 is used to generate a digital eye diagram based on the data signal, and to obtain the eye width and eye height corresponding to the digital eye diagram;

[0090] The execution module 30 is used to adjust the register parameters of multiple registers in the memory controller corresponding to the memory based on the eye width and eye height if the eye width is less than the preset eye width or the eye height is less than the preset eye height, and return to the step of capturing the bus data of the bus corresponding to the memory chip under test in real time through the capture IC to obtain the data signal.

[0091] The digital eye diagram testing device provided in this application, employing the digital eye diagram testing method described in the above embodiments, can solve the technical problem of how to improve memory testing efficiency. Compared with the prior art, the beneficial effects of the digital eye diagram testing device provided in this application are the same as those of the digital eye diagram testing method described in the above embodiments, and other technical features in the digital eye diagram testing device are the same as those disclosed in the methods of the above embodiments, and will not be repeated here.

[0092] This application provides a digital eye diagram testing device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the digital eye diagram testing method in the first embodiment described above.

[0093] The following is for reference. Figure 3 This document illustrates a structural schematic diagram of a digital eye diagram testing device suitable for implementing embodiments of this application. The digital eye diagram testing device in the embodiments of this application may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Description), PMPs (Portable Media Players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 3 The digital eye diagram testing device shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.

[0094] like Figure 3As shown, the digital eye diagram testing device may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.) that can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1003 into a random access memory (RAM) 1004. The RAM 1004 also stores various programs and data required for the operation of the digital eye diagram testing device. The processing unit 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to the I / O interface 1006: input devices 1007 including, for example, a touchscreen, touchpad, keyboard, mouse, image sensor, microphone, accelerometer, gyroscope, etc.; output devices 1008 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; storage devices 1003 including, for example, magnetic tape, hard disk, etc.; and communication devices 1009. Communication device 1009 allows the digital eye diagram testing equipment to communicate wirelessly or wiredly with other devices to exchange data. While the figure shows digital eye diagram testing equipment with various systems, it should be understood that implementation or possession of all the systems shown is not required. More or fewer systems may be implemented alternatively.

[0095] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from ROM 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0096] The digital eye diagram testing device provided in this application, employing the digital eye diagram testing method described in the above embodiments, can solve the technical problem of how to improve memory testing efficiency. Compared with the prior art, the beneficial effects of the digital eye diagram testing device provided in this application are the same as those of the digital eye diagram testing method described in the above embodiments, and other technical features of this digital eye diagram testing device are the same as those disclosed in the previous embodiment method, and will not be repeated here.

[0097] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0098] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0099] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, the computer-readable program instructions being used to execute the digital eye diagram testing method in the above embodiments.

[0100] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0101] The aforementioned computer-readable storage medium may be included in the digital eye diagram testing device; or it may exist independently and not assembled into the digital eye diagram testing device.

[0102] The aforementioned computer-readable storage medium carries one or more programs. When these programs are executed by a digital eye diagram testing device, the digital eye diagram testing device: captures bus data of the bus corresponding to the memory chip under test in real time through the capture IC, and obtains data signals of multiple channels; generates a digital eye diagram based on the data signals, and obtains the eye width and eye height corresponding to the digital eye diagram; if the eye width is less than a preset eye width or the eye height is less than a preset eye height, adjusts the register parameters of multiple registers in the memory controller corresponding to the memory based on the eye width and eye height, and returns to the step of capturing bus data of the bus corresponding to the memory chip under test in real time through the capture IC, and obtaining data signals of multiple channels.

[0103] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0104] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0105] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0106] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described digital eye diagram testing method, thereby solving the technical problem of how to improve memory testing efficiency. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the digital eye diagram testing method provided in the above embodiments, and will not be repeated here.

[0107] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the digital eye diagram testing method described above.

[0108] The computer program product provided in this application can solve the technical problem of how to improve memory testing efficiency. Compared with the prior art, the beneficial effects of the computer program product provided in this application are the same as those of the digital eye diagram testing method provided in the above embodiments, and will not be repeated here.

[0109] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A digital eye diagram testing method, characterized in that, The memory chip under test is equipped with a capture IC, and the digital eye diagram testing method includes: The capture IC captures the bus data of the bus corresponding to the memory chip under test in real time, and obtains data signals from multiple channels. A digital eye diagram is generated based on the data signal, and the eye width and eye height corresponding to the digital eye diagram are obtained; If the eye width is less than the preset eye width or the eye height is less than the preset eye height, then the register parameters of multiple registers in the memory controller corresponding to the memory are adjusted based on the eye width and eye height, and the process returns to the step of capturing the bus data of the bus corresponding to the memory chip under test in real time through the capture IC to obtain data signals of multiple channels. The capture IC includes a multi-phase clock generator, a multi-level comparator array, and a SerDes interface; the step of capturing the bus data of the bus corresponding to the memory chip under test in real time through the capture IC to obtain data signals of multiple channels includes: The multi-phase clock generator generates multiple sampling clock phases that are uniformly distributed within a unit interval, and the multi-level comparator array generates multiple reference voltages of different levels. For each data bit in the bus data, the data bit is sampled based on the clock phase to obtain a sampled voltage, and the sampled voltage is compared with the corresponding reference voltage to obtain the digital result corresponding to each sample. Determine the two-dimensional data matrix corresponding to each digital result, wherein the data signal includes a two-dimensional data matrix corresponding to multiple data bits in each bus data; The data signal is acquired through the Serdes interface of the capture IC.

2. The digital eye diagram testing method as described in claim 1, characterized in that, The capture IC also includes an I2C interface, and the digital eye diagram testing method further includes: The multi-level sampling level corresponding to the capture IC can be set through the I2C interface; The step of generating multiple reference voltages of different levels through the multi-level comparator array includes: The multilevel comparator array generates reference voltages corresponding to each sampling level.

3. The digital eye diagram testing method as described in claim 1, characterized in that, The step of generating a digital eye diagram based on the data signal includes: The digital eye diagram is obtained by superimposing two-dimensional data matrices corresponding to multiple data bits.

4. The digital eye diagram testing method as described in any one of claims 1 to 3, characterized in that, The registers include at least the DQS delay register, the drive strength register, the ODT register, and the reference voltage VREF register.

5. The digital eye diagram testing method as described in any one of claims 1 to 3, characterized in that, The bus includes a command bus (CA), a data bus (DQ / DQS), and a chip select bus (CS).

6. A digital eye diagram testing device, characterized in that, The digital eye diagram testing device includes: The capture module is used to capture the bus data of the bus corresponding to the memory chip under test in real time through the capture IC to obtain the data signal; A generation module is used to generate a digital eye diagram based on the data signal, and to obtain the eye width and eye height corresponding to the digital eye diagram; The execution module is used to adjust the register parameters of multiple registers in the memory controller corresponding to the memory based on the eye width and eye height if the eye width is less than the preset eye width or the eye height is less than the preset eye height, and return to the step of executing the step of capturing the bus data of the bus corresponding to the memory chip under test in real time through the capture IC to obtain the data signal; The capture IC includes a multi-phase clock generator, a multi-level comparator array, and a SerDes interface; the capture module is also used for: The multi-phase clock generator generates multiple sampling clock phases that are uniformly distributed within a unit interval, and the multi-level comparator array generates multiple reference voltages of different levels. For each data bit in the bus data, the data bit is sampled based on the clock phase to obtain a sampled voltage, and the sampled voltage is compared with the corresponding reference voltage to obtain the digital result corresponding to each sample. Determine the two-dimensional data matrix corresponding to each digital result, wherein the data signal includes a two-dimensional data matrix corresponding to multiple data bits in each bus data; The data signal is acquired through the Serdes interface of the capture IC.

7. A digital eye diagram testing device, characterized in that, The device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the digital eye diagram testing method as described in any one of claims 1 to 5.

8. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, it implements the steps of the digital eye diagram testing method as described in any one of claims 1 to 5.

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