Intelligent power control device and system for heat storage equipment

Abstract

The application discloses an intelligent power control device and system of a heat storage equipment, comprising: a terminal for real-time sampling of a 1.3pu / 180ms level forward overvoltage pulse at a valve string terminal of a solid heat storage unit with a time resolution of less than 50ns and outputting a digital trigger flag; a pre-charged SiC-MOSFET active clamping unit is connected across each thyristor anode-cathode to form a dynamic energy bypass; when the voltage difference of any two adjacent thyristors exceeds a set threshold, the corresponding thyristor gate reverse bias charge is increased; when the grid scheduling instruction drops to zero power working condition, the minimum electrothermal-airflow coupling state of 1% rated power and 5% rated airflow is maintained to prevent the heat of the heat storage brick from conducting reversely to the Fe-Cr-Al electrothermal strip; the 1.8kHz harmonic current presents a trap impedance of 25Ω-0.6mH-15μF and the frequency harmonic amplitude is suppressed to be lower than 1% of the rated current. The application gets rid of the limitation of traditional fixed R-C network that can only slow voltage equalization, and realizes integrated protection of 1.3pu level impact.

Description

Technical Field

[0001] This invention relates to the field of power technology, and in particular to an intelligent power control device and system for thermal storage equipment. Background Technology

[0002] Solid-state thermal energy storage units utilize off-peak electricity or surplus renewable energy to heat Fe-Cr-Al alloy heating tape embedded in Mg-Fe brick masonry to 700-800℃, and achieve decoupled heat-electricity release via variable frequency fans. This is currently the mainstream technology for clean heating and deep peak shaving in 30-50MW-class thermal power plants. Its power control core consists of a high-voltage (10kV or 35kV) valve section, a thyristor rectifier / power regulation unit, a PLC / DCS controller, and a voltage equalization-absorption network. Under abnormal grid conditions, 6-10 6500V thyristors in series within the valve section withstand transient overvoltages. Traditionally, a static RC voltage equalization network is connected in parallel across each device, with a design baseline of 1.1 pu (rated voltage) for 10 seconds. The existing static voltage equalization resistor-capacitor design is only for the 1.1 pu / 10s operating condition. It lacks both a dynamic model and a fast protection strategy for the 1.3 pu millisecond level impact, which has become a prominent bottleneck restricting the safe grid connection of large-capacity solid thermal energy storage units in high-altitude and near-end wind farms. Summary of the Invention

[0003] To address the aforementioned technical problems, this invention provides an intelligent power control device and system for thermal storage equipment.

[0004] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0005] On one hand, this invention discloses an intelligent power control device for a thermal storage device, comprising:

[0006] The high-voltage transient voltage impulse detection module is used to sample positive overvoltage pulses of 1.3 pu / 180 ms level at the valve string terminals of the solid thermal storage unit in real time with a time resolution of less than 50 ns and output a digital trigger flag.

[0007] An adaptive voltage equalization energy routing module is cascaded with the high-voltage transient voltage impulse detection module via optical fiber. It is used to connect the pre-charged SiC-MOSFET active clamping unit to the anode-cathode of each thyristor within 200ns after receiving the digital trigger flag to form a dynamic energy bypass.

[0008] The thyristor valve series voltage gradient blocking module shares the same fiber optic encoding bus with the adaptive voltage equalization energy routing module. It is used to increase the gate reverse bias charge of the corresponding thyristor to forcibly reduce its blocking impedance gradient when the voltage difference between any two adjacent thyristors exceeds a set threshold.

[0009] The negative voltage sustaining thermal backflow suppression module shares a DC control power supply with the thyristor valve series voltage gradient blocking module. It is used to maintain the minimum electrothermal-airflow coupling state of 1% rated power and 5% rated airflow when the power grid dispatch command drops to zero power, so as to prevent the heat of the heat storage brick from being reversed to the Fe-Cr-Al electric heating tape.

[0010] The high-frequency harmonic resonant damping module is connected in series between the primary side of the valve string and the secondary side of the transformer. It is used to present a notch impedance of 25Ω-0.6mH-15μF for the 1.8kHz harmonic current and suppress the amplitude of the harmonic at this frequency to 1% below the rated current.

[0011] Furthermore, the high-voltage transient voltage impulse detection module includes a 1:1000 high-frequency voltage divider directly coupled to the valve string terminals, a differential amplifier with a bandwidth of 500MHz, a 12-bit 1Gsps parallel ADC, and a real-time comparator implemented based on FPGA hardware description language. The voltage divider reduces the instantaneous voltage of the valve string terminals to ±5V and then sends it to the differential amplifier. The output of the differential amplifier is compared with a 1.3pu reference threshold set internally by the FPGA clock cycle. When three consecutive sampling points are higher than the reference threshold, the FPGA latches the overvoltage event and outputs a digital trigger flag with a fixed pulse width of 20ns on the next 50ns clock edge. The digital trigger flag is converted into an optical signal by a high-speed fiber optic differential driver and then sent to the adaptive voltage equalization energy routing module through the fiber optic cascade port to realize high-voltage transient voltage impulse detection.

[0012] Furthermore: The fiber optic receiver of the adaptive voltage equalization energy routing module converts the digital trigger flag from the high-voltage transient voltage impulse detection module to LVDS level, starts the 200ns timer in the FPGA, and simultaneously turns on the high-voltage isolated DC-DC converter to power the pre-charged 450V film capacitor to the SiC-MOSFET active clamping unit. Before the timer arrives, the FPGA has synchronously output two 12V / 10ns gate drive pulses, which are amplified by the gate isolation transformer and then simultaneously turn on the SiC-MOSFET, quickly bridging the active clamping unit between the anode and cathode of the corresponding thyristor to form a low-impedance dynamic energy bypass, thereby realizing adaptive voltage equalization energy routing.

[0013] Furthermore: The thyristor valve string voltage gradient blocking module acquires the instantaneous values ​​of the anode-cathode voltage of each thyristor in real time through the same fiber optic encoding bus. When the differential comparator inside the FPGA detects that the voltage difference between any two adjacent thyristors exceeds the set threshold, it instantly pulls down the fiber optic enable signal of the corresponding channel. The fiber optic enable signal is converted into a -20V / 50ns reverse bias pulse by the high-voltage isolated gate driver chip and injected into the gate of the corresponding thyristor, so that the gate-cathode junction instantly accumulates reverse charge, thereby forcibly reducing the blocking impedance gradient of the thyristor to achieve thyristor valve string voltage gradient blocking.

[0014] Furthermore: The negative voltage sustaining thermal backflow suppression module draws power from the DC control power supply of the thyristor valve series voltage gradient blocking module, outputs 1% of the rated current to the Fe-Cr-Al heating tape via an isolated Buck constant current source, and simultaneously drives the variable frequency fan to maintain 5% of the rated air volume through a 0-10V analog interface, so that the heat storage brick and the Fe-Cr-Al heating tape always maintain a positive heat flow, thereby achieving negative voltage sustaining thermal backflow suppression.

[0015] Furthermore, the harmonic high-frequency resonant damping module has an LCR series branch connected in series between the primary side of the valve string and the secondary side of the transformer. This branch includes a 25Ω non-inductive resistor, a 0.6mH high-frequency air-core reactor, and a 15μF polypropylene film capacitor. The LCR series branch forms a notch impedance at 1.8kHz. By real-time detection of the 1.8kHz component in the valve string output current and feedback to the FPGA phase-locked loop, the FPGA dynamically fine-tunes the capacitor switching relay to maintain the notch frequency at 1.8kHz±0.1%, thereby suppressing the 1.8kHz harmonic current amplitude to below 1% of the rated current, thus achieving harmonic high-frequency resonant damping.

[0016] On the other hand, the present invention also discloses an intelligent power control system for a thermal storage device, comprising:

[0017] The system includes an intelligent power control device for the aforementioned thermal storage equipment.

[0018] The technological advancements achieved by this invention compared to existing technologies are as follows:

[0019] This invention replaces static voltage equalization with dynamic energy routing: First, a high-voltage transient voltage impulse detection module directly captures millisecond-level overvoltages at the valve string terminals. An optical fiber triggers an adaptive voltage equalization energy routing module, which instantaneously bypasses excess charge between the anode and cathode of each thyristor, blocking voltage gradient formation. Simultaneously, a thyristor valve string voltage gradient blocking module injects gate charge in reverse, further smoothing the blocking impedance. A negative voltage sustaining thermal backflow suppression module maintains positive heat flow using minimal electrothermal-airflow coupling, completely eliminating reverse thermal conduction damage during zero-power standby. A harmonic high-frequency resonance damping module absorbs high-frequency harmonics with a single LCR notch filter branch, preventing maloperation of the protection system. Thus, this invention, for the first time in a solid-state thermal storage unit, unifies millisecond-level overvoltage, high-frequency resonance, and thermal backflow faults into a closed loop, overcoming the limitations of traditional fixed RC networks that can only achieve slow voltage equalization, and realizing rapid, reliable, and integrated protection against 1.3 pu-level impulses. Attached Figure Description

[0020] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the embodiments of the invention to explain the invention and do not constitute a limitation thereof.

[0021] In the attached diagram:

[0022] Figure 1 This is a system structure diagram of the present invention. Detailed Implementation

[0023] The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of the present invention will now be described with reference to the accompanying drawings.

[0024] Example 1

[0025] like Figure 1 As shown, the present invention discloses an intelligent power control device for a thermal storage device, comprising:

[0026] The high-voltage transient voltage impulse detection module is used to sample positive overvoltage pulses of 1.3 pu / 180 ms level at the valve string terminals of the solid thermal storage unit in real time with a time resolution of less than 50 ns and output a digital trigger flag.

[0027] An adaptive voltage equalization energy routing module is cascaded with the high-voltage transient voltage impulse detection module via optical fiber. It is used to connect the pre-charged SiC-MOSFET active clamping unit to the anode-cathode of each thyristor within 200ns after receiving the digital trigger flag to form a dynamic energy bypass.

[0028] The thyristor valve series voltage gradient blocking module shares the same fiber optic encoding bus with the adaptive voltage equalization energy routing module. It is used to increase the gate reverse bias charge of the corresponding thyristor to forcibly reduce its blocking impedance gradient when the voltage difference between any two adjacent thyristors exceeds a set threshold.

[0029] The negative voltage sustaining thermal backflow suppression module shares a DC control power supply with the thyristor valve series voltage gradient blocking module. It is used to maintain the minimum electrothermal-airflow coupling state of 1% rated power and 5% rated airflow when the power grid dispatch command drops to zero power, so as to prevent the heat of the heat storage brick from being reversed to the Fe-Cr-Al electric heating tape.

[0030] The high-frequency harmonic resonant damping module is connected in series between the primary side of the valve string and the secondary side of the transformer. It is used to present a notch impedance of 25Ω-0.6mH-15μF for the 1.8kHz harmonic current and suppress the amplitude of the harmonic at this frequency to 1% below the rated current.

[0031] Specifically, the high-voltage transient voltage impulse detection module includes:

[0032] 1:1000 high-frequency voltage divider: directly coupled to the thyristor valve string terminal, used to reduce the instantaneous voltage on the high-voltage side to ±5V range at a ratio of 1:1000, while ensuring that the bandwidth is not less than 500MHz through RC compensation;

[0033] A 500MHz bandwidth differential amplifier: connected to the low-voltage side of the voltage divider, used to suppress common-mode interference and provide drive capability to match the input of the subsequent high-speed analog-to-digital converter;

[0034] 12-bit 1Gsps parallel ADC: connected to a differential amplifier, used to quantize and sample the reduced instantaneous voltage waveform with a resolution of 1ns, and output digital data stream in the form of a parallel bus;

[0035] A real-time comparator implemented using FPGA hardware description language: connected to the parallel data output of the ADC, used to compare the sampled value with the set 1.3pu reference threshold clock cycle inside the FPGA, and to complete three-point continuous decision and event latching.

[0036] High-speed fiber differential driver and fiber cascade port: connected to the FPGA output, used to convert the digital trigger flag generated by the FPGA into an optical signal and transmit it to the subsequent adaptive voltage equalization energy routing module.

[0037] When a transient overvoltage of 1.3 pu occurs at the valve string terminals, the high-frequency voltage divider proportionally reduces the voltage while maintaining the high-frequency components of the pulse waveform, ensuring insulation safety. The differential amplifier adjusts the signal amplitude and performs common-mode rejection before driving a high-speed ADC. The ADC quantizes the input waveform point-by-point at a rate of 1 Gsps. The real-time comparator module inside the FPGA compares the input value with a preset 1.3 pu threshold in each sampling cycle. If three consecutive sampling points exceed this threshold, the overvoltage event is immediately latched. After latching, the comparator logic generates a digital trigger flag with a fixed width of 20 ns on the next 50 ns system clock edge. This flag is converted into an optical signal by a high-speed fiber differential driver and sent to the adaptive voltage equalization energy routing module through the fiber optic cascade port, enabling rapid event linkage.

[0038] At a sampling rate of 1 Gsps, the sampling resolution is 1 ns, far superior to the time resolution requirement of less than 50 ns. Three consecutive decision points result in a minimum decision time of 3 ns, enabling rapid identification of overvoltage at the leading edge of millisecond-level impulse waveforms. Once an overvoltage event is triggered, the FPGA output logic, controlled by a 20 MHz system clock, generates a standardized trigger pulse on the next 50 ns clock edge, ensuring the determinism of the module's output timing and the synchronization between valve segments.

[0039] The digital trigger flag is output at LVDS level by the FPGA, converted by a high-speed fiber optic differential driver, and then transmitted through the fiber optic link. The fiber optic cascade port allows the trigger signal to achieve distributed synchronization among multiple valve section modules, thereby ensuring that the subsequent adaptive voltage equalization energy routing module can initiate active clamping action under a unified time reference.

[0040] Specifically, the adaptive voltage equalization energy routing module includes:

[0041] Fiber optic receiver: Connected to the fiber optic cascade port of the high-voltage transient voltage surge detection module, used to convert digital trigger flags in optical signal form into LVDS level;

[0042] The FPGA's internal timing and drive logic is connected to the output of the fiber optic receiver. It is used to start a 200ns timer after receiving a digital trigger flag and output a gate drive control signal within the timing window.

[0043] High-voltage isolated DC-DC power supply: triggered and enabled by FPGA, used to provide isolated DC power to pre-charged thin-film capacitors and SiC-MOSFET active clamping units when an event occurs;

[0044] Precharged thin-film capacitor unit: Capacitance range of hundreds of μF, pre-charged to 450V to provide transient energy support during triggering;

[0045] SiC-MOSFET active clamping unit: connected across the thyristor anode-cathode, and simultaneously turned on by dual gate drive pulses to form a low-impedance bypass path;

[0046] Gate isolation transformer and push-pull gate driver: Connected to the FPGA output logic, used to isolate and amplify the FPGA's 12V / 10ns gate drive signal before applying it to the SiC-MOSFET gate.

[0047] When the fiber optic receiver receives the digital trigger flag from the high-voltage transient voltage surge detection module, it immediately converts it to LVDS level and sends it to the FPGA. The FPGA's internal timing logic latches the trigger signal while simultaneously starting a 200ns timer and executing two operations in parallel:

[0048] On the one hand, the high-voltage isolated DC-DC power supply is turned on through the control interface, so that the energy of the pre-charged 450V thin film capacitor is stably injected into the SiC-MOSFET active clamping unit;

[0049] On the other hand, before the timer arrives, the FPGA synchronously outputs two gate drive pulses with a duration of 10ns and an amplitude of 12V. After being amplified by the gate isolation transformer, these pulses are simultaneously applied to the gate of the SiC-MOSFET, enabling it to quickly and fully turn on.

[0050] When the SiC-MOSFET is turned on, the active clamping unit establishes a transient low-impedance bypass path between the anode and cathode of each thyristor, thereby quickly distributing overvoltage energy. This bypass path works together with the original static voltage equalization network to rebalance the voltage of each thyristor in the valve string, preventing individual devices from breaking down due to excessive blocking voltage.

[0051] Throughout the entire process from receiving the digital trigger flag to the completion of the active clamp unit bridging, the total delay is limited to within 200ns, and the timing relationship is as follows:

[0052] t=0ns: The fiber optic receiver receives the trigger flag and outputs an LVDS level;

[0053] t=0-20ns: The FPGA latches the trigger event and starts a 200ns timer, while simultaneously sending a start signal to the DC-DC power supply;

[0054] t=20-100ns: The DC-DC power supply provides isolated DC support voltage for the thin-film capacitor and SiC-MOSFET;

[0055] t=50-150ns: The FPGA outputs two 12V / 10ns gate drive pulses, which are amplified by the isolation transformer and then applied to the MOSFET gate to make it fully conduct;

[0056] t≤200ns: The active clamping unit realizes bridging and forms a dynamic energy bypass to complete the equalization energy routing.

[0057] This timing ensures that the valve string has a low-impedance energy bypass path before the arrival of millisecond-level overvoltage impacts caused by abnormal operating conditions on the grid side, thereby achieving rapid diversion and balancing of transient energy.

[0058] In the module, the thin-film capacitor is stably pre-charged to 450V to provide sufficient energy during the clamping process to maintain the conduction of the MOSFET and bypass the inrush current; the turn-on speed of the SiC-MOSFET is controlled on the order of 10ns, which can ensure the dynamic response of the entire module to high voltage transient impacts; the digital trigger flag and gate drive signal output by the FPGA are completely electrically isolated through optical fiber and isolation transformer, thereby ensuring the safe and reliable operation of the system under high voltage environment.

[0059] Specifically, the thyristor valve series voltage gradient blocking module includes:

[0060] Fiber optic coded bus interface: Shared with the adaptive voltage equalization energy routing module, used to receive the digital instantaneous value of the anode-cathode voltage of each thyristor in real time, and send the locked-in command encoded to the corresponding valve section;

[0061] FPGA internal differential comparator array: connected to the fiber optic interface, used to perform real-time differential calculation of the anode-cathode voltage values ​​of any two adjacent thyristors and compare them with the set voltage gradient threshold.

[0062] Fiber optic enable control unit: connected to the FPGA output, used to immediately pull down the fiber optic enable signal of the corresponding channel when the detected voltage difference exceeds the threshold;

[0063] High-voltage isolated gate driver chip: connected to the fiber optic enable signal, used to convert it into a -20V / 50ns reverse bias pulse;

[0064] Gate injection network: Connected to the high-voltage isolated gate driver chip, it is used to rapidly inject reverse bias pulses into the gate-cathode junction of the corresponding thyristor.

[0065] During normal operation of the unit, the fiber optic coded bus interface continuously acquires the instantaneous voltage values ​​of the anode-cathode of each thyristor in the valve string and transmits them to the FPGA as a high-speed data stream. The FPGA's internal differential comparator array performs real-time comparisons of the voltage differences between adjacent devices clock cycles. When the voltage difference between any two adjacent thyristors exceeds a set threshold, the corresponding channel immediately triggers a latching action: the FPGA output signal is quickly pulled low via the fiber optic enable control unit, triggering the high-voltage isolated gate driver chip to operate. This chip generates a reverse bias pulse with an amplitude of -20V within 50ns and injects it into the gate-cathode junction of the target thyristor through the gate injection network. Under the action of the reverse bias pulse, the thyristor gate junction instantly accumulates additional reverse charge, reducing its blocking impedance gradient. This forces the anode-cathode voltage of the thyristor to drop and redistribute to other devices in the valve string, achieving rapid voltage gradient balancing.

[0066] The timing of actions in this module has strict real-time requirements:

[0067] t=0ns: The FPGA differential comparator detects that the voltage difference between adjacent thyristors exceeds the set threshold.

[0068] t=0-10ns: The FPGA outputs a control signal and pulls down the enable signal of the corresponding fiber optic channel;

[0069] t=10-40ns: The high-voltage isolated gate driver chip converts this signal into a reverse bias pulse with an amplitude of -20V and a pulse width of 50ns;

[0070] t=40-50ns: The gate injection network completes energy coupling, and reverse charge is injected into the gate-cathode junction;

[0071] t≤50ns: The thyristor blocking impedance decreases rapidly, and the anode-cathode voltage gradient is suppressed.

[0072] The entire response time is controlled within 50ns, enabling dynamic equalization of valve string voltage before millisecond-level grid impacts occur.

[0073] The voltage difference threshold can be set through FPGA internal register programming, and can be dynamically adjusted according to altitude, ambient temperature, and thyristor device parameters; the standard is -20V amplitude and 50ns width. In practical applications, the reverse bias pulse parameters can be adjusted by the internal charge pump of the driver chip and the external capacitor to ensure sufficient reverse charge injection; the fiber optic coded bus carries both voltage data and transmits latching commands, and uses redundant coding and CRC check to prevent false triggering; under the action of this module, the voltage gradient between any two adjacent thyristors in the valve string is always suppressed within the set range, effectively preventing individual devices from breaking down prematurely due to uneven voltage distribution.

[0074] Based on the above structure and principle, the thyristor valve string voltage gradient blocking module can achieve nanosecond-level response to the voltage difference of the thyristor valve string with the support of high-speed voltage monitoring and optical fiber synchronous transmission. It can also force the blocking characteristics of a single tube through reverse bias pulse technology, thereby ensuring the safe and reliable operation of the entire valve section under abnormal impact conditions.

[0075] Specifically, the negative voltage sustaining thermal backflow suppression module includes:

[0076] DC power supply interface: Shares the same DC control power supply with the thyristor valve series voltage gradient blocking module to ensure power supply stability and system simplification;

[0077] Isolated Buck constant current source: It consists of a high-frequency isolation transformer, a synchronous rectifier and a digitally controlled PWM modulator, and is used to output a stable 1% rated current to the Fe-Cr-Al heating tape.

[0078] Variable frequency fan drive interface: Provides a standard 0-10V analog signal for adjusting the speed of the variable frequency fan to maintain 5% of the rated air volume;

[0079] FPGA coordination control logic: connected to the DC power supply interface and the fan drive interface, it manages the current output and air volume adjustment in real time to realize the dynamic coupling of electrothermal-airflow.

[0080] Heat flow status monitoring unit: Composed of thermocouple array and flow sensor, it collects the surface temperature of Fe-Cr-Al electric heating tape and the airflow velocity in the duct in real time and feeds it back to FPGA control logic.

[0081] When the grid dispatch command reduces the unit's output power to zero, if the current and airflow are completely disconnected, the high-temperature heat inside the thermal storage brick will be conducted in the reverse direction to the Fe-Cr-Al heating tape due to the temperature gradient, leading to localized overheating and material fatigue. To prevent this problem, the negative voltage sustaining type thermal backflow suppression module achieves the following functions through a minimum energy sustaining mechanism:

[0082] 1. Constant current maintenance: The isolated Buck constant current source obtains energy from the DC power supply and continuously outputs DC current equivalent to 1% of the rated value to the Fe-Cr-Al heating tape, forming a weak but stable positive Joule heating;

[0083] 2. Minimum airflow guarantee: At the same time, a control signal is sent to the variable frequency fan through the 0-10V analog interface to fix its speed at 5% of the rated value, ensuring that the airflow continues to flow through the heat storage brick channel;

[0084] 3. Maintaining positive heat flow: Under the combined effect of continuous heating of the electric heating tape and airflow pumping, the heat between the heat storage brick and the electric heating tape is always maintained in a positive direction, fundamentally suppressing heat backflow.

[0085] The action sequence of this module includes:

[0086] t=0ms: The dispatch center issues a zero-power command, and the unit's rectifier-power regulation unit completely shuts down;

[0087] t=0-5ms: The FPGA coordination control logic receives the instruction and immediately activates the isolated Buck constant current source and fan drive interface;

[0088] t=5-20ms: The constant current source begins to output 1% of the rated current, while the fan accelerates to 5% of the rated air volume;

[0089] After t=20ms: the electrothermal-airflow coupling state remains stable, the positive heat flow continues, and high-temperature backflow is avoided.

[0090] In practical applications, the isolated Buck constant current source ensures that the output current error does not exceed ±0.2% through current sampling resistor and PI digital loop adjustment. The 0-10V analog interface corresponds to the 0-100% speed range of the frequency converter fan, and this module maintains a fixed output of 0.5V control level to achieve 5% of the rated airflow. In maintenance mode, the surface temperature of the Fe-Cr-Al heating tape remains in the 50-70℃ positive overheat range, which, compared to the 700-800℃ main temperature zone inside the heat storage brick, is sufficient to ensure that the heat flow direction is always from the heating tape to the heat storage brick. All control logic is embedded in the FPGA internal hardware circuitry to avoid software delays. Both the Buck constant current source and the fan interface are equipped with overcurrent, overvoltage, and disconnection protection to ensure that secondary faults are not caused by the maintenance strategy under abnormal conditions.

[0091] This module ensures that even when the power grid requires the unit to shut down completely, it maintains minimum power and airflow, achieving a weak coupling state between the electric heating and airflow. This guarantees that there is no reverse heat conduction between the heat storage brick and the Fe-Cr-Al electric heating tape. This measure significantly extends the life of the electric heating tape, reduces the thermal stress of the heat storage brick, and avoids the risk of device overheating and shutdown caused by heat backflow.

[0092] Specifically, the harmonic high-frequency resonant damping module includes:

[0093] LCR series branch: It consists of a 25Ω precision non-inductive resistor, a 0.6mH high-frequency air-core reactor and a 15μF polypropylene film capacitor connected in series, and the whole is connected in series between the primary side of the valve string and the secondary side of the transformer.

[0094] Current detection unit: Employs a high-bandwidth Hall current sensor or shunt sampling resistor to extract the 1.8kHz component from the valve string output current in real time;

[0095] Signal processing and phase-locked loop unit (implemented within FPGA): used to phase-lock the detected current harmonic components with a 1.8kHz reference signal and calculate the harmonic amplitude in real time;

[0096] Capacitor switching control unit: includes a high-speed relay matrix and a segmented capacitor array, controlled by FPGA to realize dynamic switching of capacitors, so as to precisely fine-tune the resonant frequency;

[0097] Heat dissipation and insulation encapsulation unit: provides forced air cooling for non-inductive resistors and air-core reactors, and the capacitors adopt metal foil winding and epoxy casting to ensure long-term operational reliability.

[0098] When the solid thermal storage unit is running, the valve string output current may contain a 1.8kHz high-frequency harmonic component. If not suppressed, this will lead to localized transformer heating, bus resonance, and system harmonic voltage distortion. The harmonic high-frequency resonance damping module forms a notch impedance characteristic at 1.8kHz through the LCR series branch.

[0099] At fundamental and other frequencies, the LCR branch exhibits high impedance, which hardly affects the normal transmission power of the system;

[0100] At the 1.8kHz harmonic frequency, due to the resonance of L and C, the capacitance and reactor reactance cancel each other out, and the overall impedance drops to a resistive value of approximately 25Ω. The harmonic current preferentially flows through this branch and is dissipated in the non-inductive resistor, thereby significantly suppressing the harmonic amplitude.

[0101] Due to the potential for capacitor temperature drift and coil inductance environmental factors to shift the resonant frequency under field operating conditions, the module incorporates an FPGA phase-locked loop tuning mechanism.

[0102] 1. The current detection unit sends the valve string output current signal to the FPGA;

[0103] 2. The FPGA's internal digital phase-locked loop extracts the 1.8kHz component and compares it with a reference. If a notch filter frequency offset is detected, an adjustment command is output.

[0104] 3. The capacitor switching control unit quickly connects or disconnects segmented capacitors (each segment with an accuracy ≤0.05μF) via a relay matrix, enabling fine-tuning of the total capacitance;

[0105] 4. The adjusted total capacitance value keeps the LCR branch resonant point within the range of 1.8kHz ± 0.1%.

[0106] The action sequence of this module is as follows:

[0107] t=0ms: The current detection unit collects the output current of the valve string in real time;

[0108] t=0-100μs: The FPGA phase-locked loop completes frequency analysis and outputs harmonic amplitude values;

[0109] t=100-500μs: If the harmonic amplitude exceeds the set threshold or the notch frequency deviates, the FPGA outputs a switching command;

[0110] t=0.5-1ms: The capacitor switching relay completes its operation, and the notch filter branch frequency is relocked to 1.8kHz;

[0111] t≥1ms: The amplitude of the 1.8kHz harmonic current is stably suppressed to less than 1% of the rated current.

[0112] By using a high-frequency harmonic resonant damping module, a selective notch is formed for the 1.8kHz harmonic without affecting the fundamental power transmission of the main circuit. The harmonic current is introduced into the low-impedance branch and dissipated, thereby ensuring the stability of the electromagnetic environment of the valve string and transformer. Combined with the FPGA dynamic tuning mechanism, this module can adapt to environmental and device parameter drift during long-term operation, continuously maintain high-precision notch characteristics, and ensure that the harmonic current amplitude is suppressed to less than 1% of the rated current.

[0113] It also includes a structural encapsulation module, used to cast the power devices, detection devices, and fiber optic distribution boards of all the above modules into a single valve section in the form of a coaxial shield, including:

[0114] Power device mounting base: including thyristors, SiC-MOSFET active clamping units, non-inductive resistors, air-core reactors and polypropylene film capacitors, which are fixed on a high thermal conductivity ceramic substrate in a partitioned arrangement.

[0115] The detection and drive unit carrier layer includes a high-frequency voltage divider, a differential amplifier, an optical fiber distribution board, and a high-voltage isolation drive chip, which are arranged in a shielded isolation cavity around the power devices.

[0116] Coaxial shield: It adopts a multi-layer metal foil-epoxy resin composite material. The inner metal foil serves as an electric field equalization shield, and the outer epoxy casting layer serves as a load-bearing and moisture-proof medium.

[0117] Fiber optic interface and DC bus: All signals are input and output through fiber optic differential interface, and all power is introduced through independent DC bus and led out with full insulation through epoxy pre-embedded pipe;

[0118] Voltage equalization electric field control unit: Capacitive voltage equalization plates and electric field buffer rings are set in the gaps and edge interfaces of valve section devices to ensure uniform local electric field distribution.

[0119] This module achieves safe and stable operation under high-voltage impact through a triple approach: insulation casting, shielding voltage equalization, and modular encapsulation.

[0120] 1. Insulation casting: All power and detection devices are integrally cast with epoxy resin to form a gapless solid insulator, avoiding partial discharge in low pressure or high humidity environments;

[0121] 2. Shielding and voltage equalization: The coaxial shielding covers each unit, and the inner metal foil is electrically connected to the valve string terminal potential, so that the external electric field is evenly distributed in the shielding and avoids individual devices bearing excessively high voltage gradients;

[0122] 3. Modular packaging: The single valve section is packaged as an integrated unit, and the optical fiber and busbar are led out through independent channels, which maintains the convenience of operation and achieves high voltage isolation.

[0123] Through structural encapsulation modules, the entire valve section is constructed as an integrated high-voltage insulation unit, which can effectively avoid electric field distortion and external insulation flashover caused by changes in air pressure. It ensures that the valve string can maintain stable voltage equalization under a high-voltage impact of 1.4 pu / 200 ms, reduces the complexity of external wiring, and allows detection and protection functions to be co-encapsulated with power devices, achieving high integration and high reliability.

[0124] Example 2

[0125] Embodiment 2 of the present invention proposes an intelligent power control system for thermal storage equipment. Since Embodiment 2 and Embodiment 1 are embodiments under the same inventive concept and have some identical structures, the structures in Embodiment 2 that are substantially the same as those in Embodiment 1 will not be described in detail. For the parts not described in detail, please refer to Embodiment 1.

[0126] Finally, it should be noted that the above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. An intelligent power control device for thermal storage equipment, characterized in that, include: The high-voltage transient voltage impulse detection module is used to sample positive overvoltage pulses of 1.3 pu / 180 ms level at the valve string terminals of the solid thermal storage unit in real time with a time resolution of less than 50 ns and output a digital trigger flag. An adaptive voltage equalization energy routing module, cascaded with the high-voltage transient voltage surge detection module via optical fiber, is used to connect a pre-charged SiC-MOSFET active clamping unit across the anode-cathode of each thyristor within 200ns after receiving the digital trigger flag to form a dynamic energy bypass, including: The fiber optic receiver converts the digital trigger flag from the high-voltage transient voltage surge detection module to LVDS level, starts a 200ns timer in the FPGA, and simultaneously turns on the high-voltage isolated DC-DC converter to power the pre-charged 450V film capacitor to the SiC-MOSFET active clamping unit. Before the timer arrives, the FPGA has synchronously output two 12V / 10ns gate drive pulses, which are amplified by the gate isolation transformer and then simultaneously turn on the SiC-MOSFET, quickly bridging the active clamping unit between the anode and cathode of the corresponding thyristor to form a low-impedance dynamic energy bypass, so as to realize adaptive voltage equalization energy routing. The thyristor valve series voltage gradient blocking module shares the same fiber optic encoding bus with the adaptive voltage equalization energy routing module. It is used to increase the reverse bias charge at the gate of the corresponding thyristor to forcibly reduce its blocking impedance gradient when the voltage difference between any two adjacent thyristors exceeds a set threshold. This includes: The instantaneous values ​​of the anode-cathode voltage of each thyristor are acquired in real time through the same fiber optic encoding bus. When the differential comparator inside the FPGA detects that the voltage difference between any two adjacent thyristors exceeds the set threshold, it pulls down the fiber optic enable signal of the corresponding channel. The fiber optic enable signal is converted into a -20V / 50ns reverse bias pulse by the high-voltage isolation gate driver chip and injected into the gate of the corresponding thyristor, so that the gate-cathode junction accumulates reverse charge instantly, thereby forcibly reducing the blocking impedance gradient of the thyristor to achieve thyristor valve series voltage gradient blocking. A negative voltage sustaining type thermal backflow suppression module, sharing a DC control power supply with the thyristor valve series voltage gradient blocking module, is used to maintain a minimum electrothermal-airflow coupling state of 1% rated power and 5% rated airflow even when the grid dispatch command drops to zero power, in order to prevent the heat from the thermal storage brick from being reverse-conducted to the Fe-Cr-Al heating tape. This module includes: Power is drawn from the DC control power supply of the thyristor valve series voltage gradient blocking module, and 1% of the rated current is output to the Fe-Cr-Al heating tape through the isolated Buck constant current source. At the same time, the variable frequency fan is driven through the 0-10V analog interface to maintain 5% of the rated air volume, so that the heat storage brick and the Fe-Cr-Al heating tape always maintain positive heat flow, so as to achieve negative voltage maintenance type heat backflow suppression. The high-frequency harmonic resonant damping module is connected in series between the primary side of the valve string and the secondary side of the transformer. It is used to present a notch impedance of 25Ω-0.6mH-15μF for the 1.8kHz harmonic current and suppress the amplitude of the harmonic current at this frequency to 1% below the rated current.

2. The intelligent power control device for the thermal storage equipment according to claim 1, characterized in that, The high-voltage transient voltage impulse detection module includes a 1:1000 high-frequency voltage divider directly coupled to the valve string terminals, a 500MHz bandwidth differential amplifier, a 12-bit, 1 GSPS parallel ADC, and a real-time comparator implemented based on FPGA hardware description language. The voltage divider reduces the instantaneous voltage of the valve string terminals to ±5V and then sends it to the differential amplifier. The output of the differential amplifier is compared with a 1.3pu reference threshold set internally by the FPGA clock cycle. When three consecutive sampling points are higher than the reference threshold, the FPGA latches the overvoltage event and outputs a digital trigger flag with a fixed pulse width of 20ns on the next 50ns clock edge. The digital trigger flag is converted into an optical signal by a high-speed fiber differential driver and then sent to the adaptive voltage equalization energy routing module through the fiber optic cascade port to realize high-voltage transient voltage impulse detection.

3. The intelligent power control device for the thermal storage equipment according to claim 2, characterized in that, The harmonic high-frequency resonant damping module has an LCR series branch connected in series between the primary side of the valve string and the secondary side of the transformer. This branch includes a 25Ω non-inductive resistor, a 0.6mH high-frequency air-core reactor, and a 15μF polypropylene film capacitor. The LCR series branch forms a notch impedance at 1.8kHz. By real-time detection of the 1.8kHz component in the valve string output current and feedback to the FPGA phase-locked loop, the FPGA dynamically adjusts the capacitor switching relay to keep the notch frequency at 1.8kHz±0.1%, thereby suppressing the amplitude of the 1.8kHz harmonic current to below 1% of the rated current, thus achieving harmonic high-frequency resonant damping.

4. An intelligent power control system for thermal storage equipment, characterized in that: The system includes an intelligent power control device for the thermal storage equipment as described in any one of claims 1-3.

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