A stable, interference-resistant, fast power-on / off RC reset circuit

Abstract

This utility model relates to the field of general circuit technology, specifically to a stable and anti-interference fast power-on / off RC reset circuit; it includes an RC reset circuit and a MOSFET interlock circuit. The RC reset circuit includes resistors R1 and R2, capacitor C, diode D1, and power supply equivalent impedance RL. The MOSFET interlock circuit includes transistors M1, M2, M3, M4, M5, and I1, where I1 is a logic gate OR gate. The RC reset circuit of this design adds a MOSFET interlock structure to the traditional circuit architecture to generate high and low levels, which are then used by logic gate circuits to generate high and low voltage signals, suppressing reset signal jitter that may be caused by power supply noise or environmental interference. At the same time, the RC reset circuit uses a MOS resistor instead of a traditional resistor and utilizes its own substrate diode as a capacitor discharge diode, which can accelerate the discharge of capacitor C. Furthermore, a resistor discharge branch connected in parallel with capacitor C is added to achieve fast reset of the RC circuit when the power supply is rapidly powered on or off.

Description

Technical Field

[0001] This utility model relates to the field of general circuit technology, and in particular to a stable and interference-resistant fast power-on / off RC reset circuit. Background Technology

[0002] As a crucial component of electronic systems, the RC reset circuit plays an irreplaceable role in ensuring stable system startup and operation. Utilizing a cleverly designed charging and discharging loop composed of a resistor (R) and a capacitor (C), it precisely controls the delay time of the reset signal, laying a solid foundation for stable system operation. During system power-up, the capacitor begins charging, and the reset signal voltage gradually rises. Until the capacitor is fully charged, the system remains in a reset state, effectively preventing erroneous operations caused by state uncertainty at the moment of power-up, ensuring the system enters the initialization phase in a stable and reliable state. When the capacitor charges to a certain threshold voltage, the reset signal becomes high, and the system smoothly ends the reset state and begins normal operation, ensuring the continuity and accuracy of system operation. When power is lost, the capacitor discharges through the resistor, the reset signal voltage gradually decreases, and the system re-enters the reset state, preventing data loss or abnormal operation during power failure and ensuring adequate preparation for the next system startup. This reset circuit based on the RC charging and discharging principle, with its simple and effective design, is widely used in various electronic devices, providing strong support for the stable operation of electronic systems.

[0003] However, some technical problems were still exposed during actual operation. First, in complex electromagnetic environments, power supply noise or environmental interference is ubiquitous. These interference factors can easily affect the RC reset circuit, causing the reset signal to jitter. Second, when the power supply voltage drops, the speed at which the capacitor discharges through the resistor depends on the parameters of the resistor and capacitor. If the capacitor discharges too slowly, the system may not be able to enter the reset state in time when the power supply drops to a certain level. Utility Model Content

[0004] The purpose of this invention is to provide a stable and interference-resistant fast power-on / off RC reset circuit, aiming to solve two problems in the prior art: first, in complex electromagnetic environments, power supply noise or environmental interference is ubiquitous, and these interference factors can easily affect the RC reset circuit, causing the reset signal to jitter; second, when the power supply voltage drops, the speed at which the capacitor discharges through the resistor depends on the parameters of the resistor and capacitor. If the capacitor discharges too slowly, the system may not be able to enter the reset state in time when the power supply drops to a certain extent.

[0005] To achieve the above objectives, this utility model employs a stable and interference-resistant fast power-on / off RC reset circuit, comprising an RC reset circuit and a MOSFET interlock circuit. The RC reset circuit includes resistors R1 and R2, capacitor C, diode D1, and power supply equivalent impedance RL. The MOSFET interlock circuit includes transistors M1, M2, M3, M4, M5, and I1, where I1 is a logic gate OR gate.

[0006] In this configuration, resistor R1 is connected in parallel with capacitor C, resistor R2 is connected in series with diode D1, the anode of diode D1 is connected to the power supply through resistor R2, the cathode of diode D1 is connected to the upper plate of capacitor C, and the equivalent impedance RL of the power supply is connected in series with resistor R1 and capacitor C.

[0007] In this configuration, the gate of transistor M1 is connected to a fixed low level, the sources of transistors M1, M3, and M4 are all grounded, the drain of transistor M1 is connected to the upper plate of capacitor C, the sources of transistors M2 and M5 are both connected to the power supply, the gate of transistor M2 is connected to the drain of transistor M3, the gate of transistor M3 is connected to the drain of transistor M2, the gate of transistor M4 is connected to the drain of transistor M2, the drain of transistor M2 is connected to one input terminal of I1, the gate of transistor M5 is connected to the drain of transistor M3, the drain of transistor M3 is connected to the other input terminal of I1, transistor M2 is connected to the upper end of resistor R1, and transistor M4 is connected to the lower end of resistor R1.

[0008] The gate voltages of transistors M2, M3, M4, and M5 are all defaulted to 0.

[0009] The width-to-length ratio (W / L) of tubes M2 and M3 is the same and inversely proportional. The multiplicity of tube M2 is 1 and that of tube M3 is 2. The width-to-length ratio (W / L) of tubes M4 and M5 is directly proportional. The multiplicity of tube M4 is 1 and that of tube M5 is 2.

[0010] This invention discloses a stable and interference-resistant fast power-on / off RC reset circuit, comprising an RC reset circuit and a MOSFET interlock circuit. The RC reset circuit includes resistors R1 and R2, capacitor C, diode D1, and power supply equivalent impedance RL. The MOSFET interlock circuit includes transistors M1, M2, M3, M4, and M5, and I1, where I1 is a logic gate OR gate. This RC reset circuit design adds a MOSFET interlock structure to the traditional circuit architecture to generate high and low levels, which are then used by logic gates to generate high and low voltage signals. This suppresses reset signal jitter that may be caused by power supply noise or environmental interference, ensuring system stability. Furthermore, the RC reset circuit uses a MOS resistor instead of a traditional resistor and utilizes its built-in substrate diode as a capacitor discharge diode to accelerate capacitor C discharge. Additionally, a resistor discharge branch connected in parallel with capacitor C is added, enabling rapid reset of the RC circuit when the power supply is rapidly powered on or off. Finally, based on these three points, the stability of the chip is greatly improved. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram illustrating the working principle of a traditional circuit.

[0013] Figure 2 This is a schematic diagram illustrating the working principle of the stable, anti-interference, and fast power-on / off RC reset circuit of this utility model.

[0014] Figure 3 This is a schematic diagram of the MOSFET interlock circuit in the stable, anti-interference, fast power-on / off RC reset circuit of this utility model.

[0015] Figure 4 This is a waveform diagram of the charging and discharging voltage of capacitor C in the stable, anti-interference, and fast power-on / off RC reset circuit of this utility model.

[0016] ①-Resistor R1, ②-Resistor R2, ③-Capacitor C, ④-Diode D1, ⑤-Equivalent impedance of power supply RL, ⑥-Transistor M1, ⑦-Transistor M2, ⑧-Transistor M3, ⑨-Transistor M4, ⑩-Transistor M5 -I1. Detailed Implementation

[0017] The embodiments of this utility model are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this utility model, and should not be construed as limiting this utility model.

[0018] Please see Figures 1 to 3 This utility model provides a stable and interference-resistant fast power-on / off RC reset circuit, including an RC reset circuit and a MOSFET interlock circuit. The RC reset circuit includes resistor R1①, resistor R2②, capacitor C③, diode D1④, and power supply equivalent impedance RL⑤. The MOSFET interlock circuit includes transistors M1⑥, M2⑦, M3⑧, M4⑨, M5⑩, and I1. The I1 It is a logic gate or gate.

[0019] In this embodiment, the circuit uses the M1 transistor ⑥ as a MOS resistor instead of a common polycrystalline resistor. Utilizing its built-in reverse substrate diode, the capacitor can be quickly discharged and reset through the diode D1④ when the power supply is off, with its gate connected to a fixed low level. When the power supply voltage is applied, the Vgs of the M1 transistor ⑥ gradually increases, and the M1 transistor ⑥ gradually turns on, causing the upper plate of the capacitor C③ to start charging, with the voltage gradually increasing from 0.

[0020] In this embodiment, the I1 It is a logic gate OR gate. When the power supply is turned on and the voltage is higher than the threshold voltage (Vth=VdsM1+VgsM2), the two input terminals are 1 and 0 respectively, and the output signal rstb is high level; conversely, when the power supply is turned off and the voltage is lower than the threshold voltage, both input terminals are 0, and the output signal rstb is low level.

[0021] In this embodiment, the added resistor R1① is connected in parallel across the capacitor C③. When the power supply voltage rises, the Vgs of the M1 transistor ⑥ continuously increases, and the output current continuously charges the capacitor C③, causing its Vds to first increase and then decrease. At this time, with the discharge branch formed by the resistor R1①, the Vds of the M1 transistor will maintain a relatively stable value after it is turned on. At this time, its Vgs increases linearly, and Vds remains basically unchanged. Therefore, the output current of the M1 transistor ⑥ increases linearly, and then the voltage on the upper plate of the capacitor C③ increases linearly with the power supply voltage. When the power supply voltage drops, the capacitor C③ discharges rapidly through the substrate diode D1④, and can also be assisted in discharging through the branch of the resistor R1①, quickly reaching the power-down reset state.

[0022] In this embodiment, please refer to Figure 4The waveform of the charging and discharging voltage of capacitor C③ shows that, since this design uses a MOS resistor, it consumes about 70mV of voltage value Vds when it is working normally. As can be seen from the curve in the figure, this circuit uses an RC reset structure to achieve rapid reset when the power supply voltage is rapidly increased or decreased.

[0023] Furthermore, the resistor R1① is connected in parallel with the capacitor C③, the resistor R2② is connected in series with the diode D1④, the anode of the diode D1④ is connected to the power supply through the resistor R2②, the cathode of the diode D1④ is connected to the upper plate of the capacitor C③, and the equivalent impedance of the power supply RL⑤ is connected in series with the resistor R1① and the capacitor C③.

[0024] Furthermore, the gate of transistor M1 (6) is connected to a fixed low level. The sources of transistors M1 (6), M3 (8), and M4 (9) are all grounded. The drain of transistor M1 (6) is connected to the upper plate of capacitor C (3). The sources of transistors M2 (7) and M5 (10) are both connected to a power supply. The gate of transistor M2 (7) is connected to the drain of transistor M3 (8), the gate of transistor M3 (8) is connected to the drain of transistor M2 (7), the gate of transistor M4 (9) is connected to the drain of transistor M2 (7), and the drain of transistor M2 (7) is connected to I1. One input terminal of the M5 transistor (10) is connected to the drain of the M3 transistor (8), and the drain of the M3 transistor (8) is connected to the I1. The other input terminal is connected to the upper end of the resistor R1① via transistor M2 ⑦ and the lower end of the resistor R1① via transistor M4 ⑨.

[0025] Furthermore, the gate voltages of transistors M2 (7), M3 (8), M4 (9), and M5 (10) are all defaulted to 0.

[0026] In this embodiment, the circuit innovatively incorporates a MOS interlocking circuit structure. The gate voltage of transistors M2 to M5 is 0 by default. As transistor M1 gradually turns on, the Vgs of transistors M2 to M5 also gradually increases and begins to slowly turn on.

[0027] Furthermore, the width-to-length ratio (W / L) of the M2 tube ⑦ and the M3 tube ⑧ is the same and inversely proportional, and the multiplicity of the M2 tube ⑦ is 1, the multiplicity of the M3 tube ⑧ is 2, the width-to-length ratio (W / L) of the M4 tube ⑨ and the M5 tube ⑩ is directly proportional, and the multiplicity of the M4 tube ⑨ is 1, the multiplicity of the M5 tube ⑩ is 2.

[0028] In this embodiment, the width-to-length ratios (W / L) of transistors M2 (⑦) and M3 (⑧) are the same and inversely proportional, and their multiplicity is 1 and 2 respectively. This configuration makes transistor M2 (⑦) easier to conduct than transistor M3 (⑧) at the same Vgs voltage. The width-to-length ratios (W / L) of transistors M4 (⑨) and M5 (⑩) are directly proportional, and their multiplicity is 1 and 2 respectively. Therefore, at the same Vgs voltage, the conduction capability of transistor M5 (⑩) is greater than that of transistor M4 (⑨). Furthermore, compared to transistor M3 (⑧), which is an inversely proportional PMOS, and transistor M5 (⑩) is a directly proportional NMOS, the conduction capability of transistor M5 (⑩) is... The force is much greater than that of the M4 transistor ⑨, ensuring that when both are turned on simultaneously, the drain output voltage of the M5 transistor ⑩ will definitely be pulled down to 0, that is, the gate voltage of the M2 transistor ⑦ and the M4 transistor ⑨ is 0. The M4 transistor ⑨ is an N-type transistor and is turned off, while the gate of the M2 transistor ⑦ is a P-type transistor. The Vgs is further increased to accelerate the conduction, and the output current is further increased, causing its drain junction voltage to surge, that is, the gate voltage of the M5 transistor ⑩ is further increased. This positive feedback effect causes the M5 transistor ⑩ to conduct further, and the drain output of the M5 transistor ⑩ is low, while the drain output of the M2 transistor ⑦ is high. When the capacitor voltage gradually rises to the turn-on voltage of the M2 transistor ⑦, the M2 transistor ⑦ quickly turns on, and the drain output voltage of the M2 transistor ⑦ rises rapidly from the initial slow increase to the highest voltage Vmax = VDD - VdsM1.

[0029] The above-disclosed embodiments are merely preferred embodiments of the present utility model and should not be construed as limiting the scope of the present utility model. Those skilled in the art can understand that implementing all or part of the above-described embodiments and making equivalent changes in accordance with the claims of the present utility model are still within the scope of the utility model.

Claims

1. A stable, anti-interference, fast power-on / off RC reset circuit, characterized in that, It includes an RC reset circuit and a MOSFET interlock circuit. The RC reset circuit includes resistors R1 and R2, capacitor C, diode D1, and power supply equivalent impedance RL. The MOSFET interlock circuit includes transistors M1, M2, M3, M4, M5, and I1, where I1 is a logic gate OR gate.

2. The stable, anti-interference, fast power-on / off RC reset circuit as described in claim 1, characterized in that, The resistor R1 is connected in parallel with the capacitor C, the resistor R2 is connected in series with the diode D1, the anode of the diode D1 is connected to the power supply through the resistor R2, and the cathode of the diode D1 is connected to the upper plate of the capacitor C. The equivalent impedance RL of the power supply is connected in series with the resistor R1 and the capacitor C.

3. The stable, anti-interference, fast power-on / off RC reset circuit as described in claim 2, characterized in that, The gate of transistor M1 is connected to a fixed low level. The sources of transistors M1, M3, and M4 are all grounded. The drain of transistor M1 is connected to the upper plate of capacitor C. The sources of transistors M2 and M5 are both connected to the power supply. The gate of transistor M2 is connected to the drain of transistor M3. The gate of transistor M3 is connected to the drain of transistor M2. The gate of transistor M4 is connected to the drain of transistor M2. The drain of transistor M2 is connected to one input terminal of I1. The gate of transistor M5 is connected to the drain of transistor M3. The drain of transistor M3 is connected to the other input terminal of I1. Transistor M2 is connected to the upper end of resistor R1. Transistor M4 is connected to the lower end of resistor R1.

4. The stable, anti-interference, fast power-on / off RC reset circuit as described in claim 3, characterized in that, The gate voltages of transistors M2, M3, M4, and M5 are all set to 0 by default.

5. The stable, anti-interference, fast power-on / off RC reset circuit as described in claim 4, characterized in that, The width-to-length ratio (W / L) of tubes M2 and M3 is the same and inversely proportional. The multiplicity of tube M2 is 1 and that of tube M3 is 2. The width-to-length ratio (W / L) of tubes M4 and M5 is directly proportional. The multiplicity of tube M4 is 1 and that of tube M5 is 2.

Images