Super junction MOSFET and manufacturing method thereof

Abstract

The application provides a super-junction MOSFET and a manufacturing method thereof, which comprises a substrate, a buffer zone, a first conductive type column, a second conductive type column, a body region, a source region, a body contact region, a gate structure, a source and a drain, wherein the buffer zone is stacked above the substrate; the first conductive type column and the second conductive type column are juxtaposed and adjacent to the upper surface of the buffer zone, and at least one regulation layer is arranged in the second conductive type column, which comprises a second conductive type doped layer and a first conductive type doped region in the second conductive type doped layer; the body region is stacked on the second conductive type column; the source region and the body contact region are adjacent and both located on the upper surface layer of the body region; the gate structure is located on the upper surface of the first conductive type column; the source covers the upper surface of the device, and the drain covers the bottom surface of the substrate. By arranging at least one regulation layer in the second conductive type column, the reverse recovery softness factor of the device is improved, and the sudden change of the output capacitance of the device is relieved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology and relates to a superjunction MOSFET and its fabrication method. Background Technology

[0002] In superjunction power MOSFETs, the longitudinal electric field is reduced due to the mutual compensation between the N-type and P-type first pillar regions within the drift region. Therefore, the doping concentration of the N-type first pillar region can be increased to reduce the on-resistance without sacrificing the breakdown voltage. For example... Figure 1 The diagram shows a cross-sectional view of a superjunction MOSFET, including a substrate 01, a buffer zone 02, a first conductivity type pillar 03, a second conductivity type pillar 04, a body region 05, a source region 06, a body contact region 07, a gate structure 08, a source 09, and a drain 010. The manufacturing process of superjunction power MOSFETs generally involves multilayer epitaxy and trench filling. Because multilayer epitaxy produces epitaxial layers with high reliability and performance, the concentration, thickness, doping dose, and doping concentration of each epitaxial layer can be independently adjusted during the manufacturing process of multilayer epitaxial superjunction MOSFETs, thereby achieving the purpose of adjusting the electrical parameters of the superjunction MOSFET. Therefore, it is widely used.

[0003] Currently, the mutual depletion between the N-type and P-type first pillar regions in a superjunction MOSFET causes a sudden change in output capacitance, resulting in excessively high dV / dt and dI / dt. These excessive dV / dt and dI / dt can easily cause oscillations in the RLC loop of the application circuit, leading to strong electromagnetic interference (EMI). To improve the sudden change in output capacitance of a superjunction MOSFET, the spacing between the N-type and P-type first pillar regions can be varied within the same chip to differentiate depletion rates. However, using different spacings for the N-type and P-type first pillar regions reduces the process window for the superjunction MOSFET's breakdown voltage, meaning its process tolerance decreases. While the process tolerance can be improved by appropriately reducing the doping concentration of the N-type and P-type first pillar regions, reducing the doping concentration of the N-type and P-type first pillar regions simultaneously increases the on-resistance. Furthermore, superjunction MOSFETs exhibit extremely low reverse recovery softness factors, meaning that significant overcharging can occur during reverse recovery, potentially causing breakdown or even burnout. While increasing the reverse recovery factor of a superjunction MOSFET can be achieved by increasing the thickness of the buffer layer, a thicker buffer layer increases the on-resistance and has limited effect on improving reverse recovery softness. More importantly, a thicker buffer layer significantly increases the manufacturing cost of superjunction MOSFETs.

[0004] Therefore, there is an urgent need for a technology that can simultaneously optimize the output capacitance and reverse recovery characteristics of superjunction MOSFETs without increasing the on-resistance of the device or reducing the process tolerance. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a superjunction MOSFET and its fabrication method, which solves the problems of reduced process tolerance and increased on-resistance caused by improving the output capacitance and reverse recovery characteristics of superjunction MOSFETs in the prior art.

[0006] To achieve the above and other related objectives, the present invention provides a superjunction MOSFET, comprising:

[0007] First conductivity type substrate;

[0008] A first conductivity type buffer is located on the upper surface of the substrate;

[0009] A first conductive type pillar is disposed on the upper surface of the buffer and extends in a direction away from the substrate, and the first conductive type pillar includes a first pillar region and a second pillar region stacked on the first pillar region.

[0010] A second conductivity type pillar is disposed on the upper surface of the buffer and located on both sides of the first pillar region. The second conductivity type pillar includes at least one control layer. The sidewall of the second conductivity type pillar is adjacent to the sidewall of the first pillar region. The upper surface of the second conductivity type pillar is flush with the upper surface of the first pillar region. The control layer includes a second conductivity type doped layer and a first conductivity type doped region located in the second conductivity type doped layer.

[0011] The second type of conductive body region is stacked on the second type of conductive pillar, and the upper surface of the body region is flush with the upper surface of the second pillar region, and the sidewall of the body region is adjacent to the sidewall of the second pillar region.

[0012] The adjacent first conductivity type source region and the second conductivity type body contact region are located on the upper surface of the body region, and the source region and the body contact region are separated from the first conductivity type pillar by a predetermined distance;

[0013] A gate structure is located above the source region, the second pillar region, and the body region between the source region and the second pillar region;

[0014] The source and drain electrodes are provided, wherein the source electrode covers the exposed surfaces of the gate structure, the body region, the source region and the body contact region, and the drain electrode covers the bottom surface of the substrate.

[0015] Optionally, the doping concentration of the substrate is higher than that of the buffer.

[0016] Optionally, the control layer is located between the top and bottom of the second conductive type pillar, and the thickness of the control layer is not greater than the thickness of the second conductive type pillar.

[0017] Optionally, the sidewall of the first conductivity type doped region is spaced apart from the sidewall of the first conductivity type pillar by a predetermined distance.

[0018] Optionally, the doping concentration of the second conductivity type doped region is higher than the doping concentration of the second conductivity type pillar outside the control layer, and the conductivity type of the second conductivity type doped region does not change after the first conductivity type doped region is completely depleted.

[0019] Optionally, the doping concentration range of the first conductivity type doped region is 1×10⁻⁶. 15 cm -3 ~5×10 16 cm -3 The doping concentration range of the second conductivity type doped region is 1×10⁻⁶. 15 cm -3 ~5×10 16 cm -3 .

[0020] Optionally, when the second conductive type pillar includes multiple control layers, the total thickness of the control layers is not greater than the thickness of the second conductive type pillar.

[0021] Optionally, two adjacent control layers can be spaced apart or adjacent to each other.

[0022] Optionally, the gate structure includes a gate dielectric layer and a gate, the gate dielectric layer enclosing the gate, and both ends of the gate extending above the source region.

[0023] This invention also provides a method for fabricating a superjunction MOSFET, comprising the following steps:

[0024] A substrate of a first conductivity type is provided, and a buffer zone of the first conductivity type is formed on the upper surface of the substrate;

[0025] A first conductive type first pillar region and a second conductive type pillar located on both sides of the first pillar region are formed on the upper surface of the buffer zone, and the sidewall of the second conductive type pillar is adjacent to the sidewall of the first pillar region. The upper surface of the first pillar region is flush with the upper surface of the second conductive type pillar. During the formation of the second conductive type pillar, at least one control layer is formed in the second conductive type pillar. The control layer includes a second conductive type doped layer and a first conductive type doped region located in the second conductive type doped layer.

[0026] A first conductive type second column region is formed on the upper surface of the first column region to form a first conductive type column, and a second conductive type body region is formed on both sides of the second column region, located on the upper surface of the second conductive type column and adjacent to the side wall of the second column region, wherein the upper surface of the body region is flush with the upper surface of the second column region;

[0027] An adjacent first conductive type source region and a second conductive type body contact region are formed in the upper surface layer of the body region, and the source region and the body contact region are spaced apart from the first conductive type pillar by a predetermined distance;

[0028] A gate structure is formed above the source region, the first conductivity type pillar, and the body region between the source region and the first conductivity type pillar, and a source electrode is formed covering the exposed surface of the gate structure, the body region, the source region, and the body contact region, and a drain electrode is formed covering the bottom surface of the substrate.

[0029] As described above, the superjunction MOSFET and its fabrication method of the present invention redesign the structure of the second conductivity type pillar by providing at least one control layer in the second conductivity type pillar. The control layer includes a second conductivity type doped layer and a first conductivity type doped region located within the second conductivity type doped layer. By controlling the doping concentration of the first conductivity type doped region and the second conductivity type doped layer, as well as the size of the first conductivity type doped region, the resistance of the second conductivity type pillar is increased, reducing the junction charge storage between the second conductivity type pillar, the first conductivity type pillar, and the buffer zone. This improves the reverse recovery softness factor of the device to prevent overcharging during reverse recovery without changing the on-resistance of the device. Furthermore, by controlling the doping concentration of the second conductivity type doped layer and the first conductivity type doped region, the depletion rate of the first conductivity type pillar is controlled to mitigate the sudden change in the output capacitance of the device, thus possessing high industrial applicability. Attached Figure Description

[0030] Figure 1 The diagram shown is a cross-sectional view of a superjunction MOSFET.

[0031] Figure 2 The diagram shown is a cross-sectional view of a superjunction MOSFET of the present invention, which has a single-layer control layer.

[0032] Figure 3 The diagram shown is a cross-sectional view of another structure of the superjunction MOSFET of the present invention, which has a single-layer control layer.

[0033] Figure 4 The diagram shown is a cross-sectional view of the superjunction MOSFET of the present invention, which has two control layers.

[0034] Figure 5 The diagram shows a cross-sectional view of the superjunction MOSFET of the present invention, which has a single-layer control layer and a first conductivity type doped region located on the lower surface of the second conductivity type doped layer.

[0035] Figure 6 The diagram shows a cross-sectional view of a superjunction MOSFET of the present invention, wherein a single-layer control layer is provided and a first conductivity type doped region is located on the sidewall surface of the second conductivity type doped layer away from the first conductivity type pillar.

[0036] Figure 7 The diagram shown is a cross-sectional view of the superjunction MOSFET of the present invention, which has two spaced control layers.

[0037] Figure 8 Displayed as Figure 5 The superjunction MOSFET shown Figure 1 The Miller capacitance variation curve of the superjunction MOSFET is shown.

[0038] Figure 9 Displayed as Figure 5 The superjunction MOSFET shown Figure 1 The reverse recovery characteristic variation curve of the superjunction MOSFET is shown.

[0039] Figure 10 The diagram shown is a process flow diagram of the fabrication method of the superjunction MOSFET of the present invention.

[0040] Component designation explanation

[0041] 01 Substrate

[0042] 02 Buffer

[0043] 03 First type of conductivity column

[0044] 04 Second type of conductive column

[0045] 05 Body Area

[0046] 06 Source Region

[0047] 07 Body Contact Area

[0048] 08 Gate Structure

[0049] 09 Source

[0050] 010 Drain

[0051] 1 Substrate

[0052] 2. Buffer

[0053] 3 First type of conductive column

[0054] 31 First column area

[0055] 32 Second column area

[0056] 4. Second type of conductive column

[0057] 41. Regulatory Layer

[0058] 411 Second conductivity type doped layer

[0059] 412 First conductivity type doped region

[0060] 5 body areas

[0061] 6 source regions

[0062] 7. Body contact area

[0063] 8-gate structure

[0064] 81 Gate dielectric layer

[0065] 82 gate

[0066] 9 Source poles

[0067] 10 Drain

[0068] A Figure 5 The Miller capacitance variation curve of the superjunction MOSFET is shown.

[0069] B Figure 1 The Miller capacitance variation curve of the superjunction MOSFE is shown.

[0070] C Figure 5 The reverse recovery characteristic variation curve of the superjunction MOSFET is shown.

[0071] D Figure 1 The reverse recovery characteristic variation curve of the superjunction MOSFET is shown. Detailed Implementation

[0072] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0073] Please see Figures 2 to 10It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0074] Example 1

[0075] This embodiment provides a superjunction MOSFET, such as Figure 2 , Figure 3 and Figure 4 The diagrams shown are cross-sectional schematic diagrams of three structures of a superjunction MOSFET with a single control layer, another structure of a superjunction MOSFET with a single control layer, and a superjunction MOSFET with two control layers. The superjunction MOSFET includes a first conductivity type substrate 1, a first conductivity type buffer zone 2, a first conductivity type pillar 3, a second conductivity type pillar 4, a second conductivity type body region 5, a first conductivity type source region 6, a second conductivity type body contact region 7, a gate structure 8, a source 9, and a drain 10. The buffer zone 2 is located on the upper surface of the substrate 1. The first conductivity type pillar 3 is disposed on the upper surface of the buffer zone 2 and extends in a direction away from the substrate 1. The first conductivity type pillar 3 includes a first pillar region 31 and a second pillar region 32 stacked on the first pillar region 31. The second conductivity type pillar 4 is disposed on the upper surface of the buffer zone 2 and located on both sides of the first pillar region 31. The second conductivity type pillar 4 includes at least one control layer 41. The sidewall of the second conductivity type pillar 4 is adjacent to the sidewall of the first pillar region 31, and the upper surface of the second conductivity type pillar 4 is flush with the upper surface of the first pillar region 31. The control layer 41 includes a second conductivity type doped layer 411 and a first conductivity type doped region 412 located in the second conductivity type doped layer 411. The body region 5 is stacked on the second conductivity type pillar 4, and the upper surface of the body region 5 is flush with the upper surface of the second pillar region 31. The sidewall of the body region 5 is adjacent to the sidewall of the second pillar region 31. The sidewall of 2 is adjacent; the source region 6 is adjacent to the body contact region 7 and both are located on the upper surface of the body region 5, the source region 6 and the body contact region 7 are spaced apart from the first conductivity type pillar 3 by a predetermined distance; the gate structure 8 is located above the source region 6, the second pillar region 32 and the body region 5 between the source region 6 and the second pillar region 32; the source electrode 9 covers the exposed surfaces of the gate structure 8, the body region 5, the source region 6 and the body contact region 7, and the drain electrode 10 covers the bottom surface of the substrate 1.

[0076] Specifically, the first conductivity type includes either N-type or P-type, the second conductivity type includes either N-type or P-type, and the first conductivity type and the second conductivity type are opposite in conductivity.

[0077] Specifically, the substrate 1 is made of silicon or other suitable semiconductor materials. In this embodiment, the substrate 1 is N-type silicon.

[0078] Specifically, the thickness of the substrate 1 can be set according to the actual situation, and is not limited here; the thickness of the buffer zone 2 can be set according to the actual situation, and is not limited here; the thickness of the first pillar region 31 can be set according to the actual situation, and is not limited here.

[0079] As an example, the doping concentration of the substrate 1 is higher than that of the buffer 2.

[0080] Specifically, the doping concentration of the first conductive type pillar 3 can be set according to the actual situation, and is not limited here. When the doping concentration of the first conductive type pillar 3 is higher than the doping concentration of the buffer 2, the on-resistance of the device is lower.

[0081] Specifically, the doping concentration of the buffer 2 is lower than that of the substrate 1 and the first conductivity type pillar 3 to improve the breakdown voltage of the device.

[0082] Specifically, the doping concentration of the second conductivity type column 4 can be selected according to the actual situation, and is not limited here.

[0083] As an example, the control layer 4 is located between the top and bottom of the second conductive type pillar 4, and the thickness of the control layer 41 is not greater than the thickness of the second conductive type pillar 4.

[0084] Specifically, provided that the thickness of the control layer 41 is not greater than the thickness of the second conductive type pillar 4, the thickness of the control layer 41 can be selected according to the actual situation, and is not limited here.

[0085] As an example, the sidewall of the first conductivity type doped region 412 is spaced at a predetermined distance from the sidewall of the first conductivity type pillar 3 to prevent changes in the on-resistance of the device.

[0086] Specifically, the distance between the sidewall of the first conductivity type doped region 412 and the sidewall of the first conductivity type pillar 3 can be set according to the actual situation, and is not limited here.

[0087] Specifically, the width of the first conductivity type doped region 412 is smaller than the width of the second conductivity type doped layer 411, so as to ensure that the device can conduct when a reverse bias voltage is applied to the device.

[0088] As an example, the doping concentration of the second conductivity type doped layer 411 is higher than the doping concentration of the second conductivity type pillar 4 outside the control layer 41, and the conductivity type of the second conductivity type doped layer 411 does not change after the first conductivity type doped region 412 is completely depleted. In this embodiment, after the first conductivity type doped region 411 is completely depleted, the equivalent doping concentration of the second conductivity type doped layer 412 is the same as the doping concentration of the second conductivity type pillar 4.

[0089] Specifically, provided that the conductivity type of the second conductivity type doped layer 411 does not change after the first conductivity type doped region 412 is completely depleted, the thickness of the first conductivity type doped region 412 can be set according to the actual situation, and is not limited here.

[0090] Specifically, such as Figure 5 and Figure 6 The figures show cross-sectional views of the first conductivity type doped region 412 located on the lower surface of the second conductivity type doped layer 411 and on the sidewall surface of the second conductivity type doped layer 411, respectively. Assuming the device can conduct in reverse and the first conductivity type doped region 412 is not adjacent to the first conductivity type pillar 3, the first conductivity type doped region 412 can be located at any position in the second conductivity type doped layer 411. For example, the first conductivity type doped region 412 can be located on the upper surface, lower surface, interior, or sidewall surface of the second conductivity type doped layer 411 away from the first conductivity type pillar 3.

[0091] Specifically, the first conductivity type doped region 412 is provided in the second conductivity type doped layer 411. Through mutual compensation between the first conductivity type doped region 412 and the second conductivity type doped layer 411, the amount of junction charge stored between the second conductivity type pillar 4 and the first conductivity type pillar 3 and the buffer 2 is reduced, thereby improving the reverse recovery softness factor of the device. In addition, the resistance of the second conductivity type doped layer 411 increases, which in turn increases the resistance of the second conductivity type pillar 4, preventing the device from overcharging during the reverse recovery process.

[0092] Specifically, by adjusting the size of the first conductivity type doped region 412 in the second conductivity type doped layer 411, the amount of junction charge stored between the second conductivity type pillar 4, the first conductivity type pillar 3, and the buffer zone 4 is adjusted, thereby adjusting the reverse recovery softness factor of the device.

[0093] Specifically, when the first conductivity type doped region 412 is completely depleted, the voltage difference between the drain 10 and the source 9 is less than 200V.

[0094] Specifically, after the first conductivity type doped region 411 is completely depleted, and the equivalent doping concentration of the second conductivity type doped layer 412 remains unchanged with the conductivity type of the second conductivity type pillar 4, the doping concentrations of the second conductivity type doped layer 411 and the first conductivity type doped region 412 are adjusted. The higher the doping concentration of the second conductivity type doped layer 411, the faster the mutual depletion rate between the second conductivity type doped layer 411 and the first conductivity type pillar 3. This adjusts the mutual depletion rate between the second conductivity type doped layer 411 and the first conductivity type pillar 3 to alleviate the sudden change in output capacitance.

[0095] As an example, the doping concentration range of the first conductivity type doped region is 1×10⁻⁶. 15 cm -3 ~5×10 16 cm -3 The doping concentration range of the second conductivity type doped region is 1×10⁻⁶. 15 cm -3 ~5×10 16 cm -3 .

[0096] As an example, when the second conductive type pillar 4 includes multiple control layers 41, the total thickness of the control layers 41 is not greater than the thickness of the second conductive type pillar 4.

[0097] Specifically, when multiple control layers 41 are provided in the second conductivity type pillar 4, the control layers 41 can better control the reverse recovery softness factor of the device, and can also better control the mutual depletion rate between the second conductivity type pillar 4 and the first conductivity type pillar 3.

[0098] As an example, such as Figure 7 The diagram shown is a cross-sectional view of the superjunction MOSFET with two spaced-apart control layers 41, where adjacent control layers 41 are spaced apart or adjacent to each other.

[0099] Specifically, the number, size, and doping concentration of the control layers 41 in two adjacent second conductivity type pillars 4 can be set according to actual conditions, and are not limited here.

[0100] Specifically, since the reverse recovery softness factor of the device and the resistance value of the second conductivity type pillar 4 are controlled by the control layer 41 located in the second conductivity type pillar 4, the doping concentration of the first conductivity type pillar 3 is not changed, so the on-resistance of the device is not changed.

[0101] As an example, the gate structure 8 includes a gate dielectric layer 81 and a gate 82, the gate dielectric layer 81 enclosing the gate 82, and the two ends of the gate 82 extending above the source region 6.

[0102] Specifically, the gate 82 is used to control the conduction and shutdown of the conductive channel in the body region 5 between the source region 6 and the second pillar region 32.

[0103] Specifically, such as Figure 8 As shown, they are respectively Figure 5 The superjunction MOSFET shown Figure 1 The Miller capacitance variation curve of the superjunction MOSFET is shown below, where, Figure 5 The substrate 1 in the superjunction MOSFET shown has a doping concentration of 5 × 10⁻⁶. 19 cm -3 The thickness is 2 μm, and the doping concentration of the buffer layer 2 is 1.5 × 10⁻⁶. 15 cm -3 The thickness is 8 μm, and the doping concentration of the second conductivity type pillar 4 is 6 × 10⁻⁶. 15 cm -3 The width is 2μm and the thickness is 35μm. The doping concentration of the first conductivity type pillar 3 is 6×10⁻⁶. 15 cm -3 The width is 2μm and the thickness is 40μm. The doping concentration of the first conductivity type doped region 412 is 7×10⁻⁶. 15 cm -3 The width is 2μm and the thickness is 5μm. The doping concentration of the second conductivity type doped layer 411 is 1×10⁻⁶. 16 cm -3 The width is 1 μm and the thickness is 1 μm. The doping concentration of the body region 5 is 1 × 10⁻⁶. 17 cm -3 The thickness is 2 μm, and the doping concentration of both the bulk contact region 7 and the source region 6 is 5 × 10⁻⁶. 19 cm -3 All layers have a thickness of 0.4 μm, and the gate dielectric layer 81 has a thickness of 100 nm. Figure 1 The superjunction MOSFET in the present invention has the same dimensions and doping concentration as the superjunction MOSFET of the present invention. With the source 9 grounded and the device turned on, as the voltage at the drain 10 gradually increases, the abrupt change in the Miller capacitance of the superjunction MOSFET of the present invention is greatly mitigated, thereby greatly mitigating the abrupt change in the output capacitance of the device.

[0104] Specifically, such as Figure 9 As shown, Figure 5The superjunction MOSFET shown Figure 1 The curves showing the reverse recovery characteristics of the superjunction MOSFET are illustrated, where the device parameters are related to... Figure 8 With the same device parameters, when the device is connected to a reverse voltage, the dI / dt of the superjunction MOSFET of the present invention is reduced and the reverse recovery softness factor is improved.

[0105] In this embodiment, the superjunction MOSFET designs the structure of the second conductivity type pillar 4 by providing at least one control layer 41 in the second conductivity type pillar 4. The control layer 41 includes a second conductivity type doped layer 411 and a first conductivity type doped region 412 located in the second conductivity type doped layer 411. The doping concentration of the second conductivity type doped layer 411 is higher than that of the second conductivity type pillar 4. By adjusting the concentrations of the second conductivity type doped layer 411 and the first conductivity type doped region 412 and the size of the first conductivity type doped region 412, the first conductivity type doped region 412 and the second conductivity type doped layer 411 compensate for each other, thereby increasing the resistance of the second conductivity type pillar 4 and reducing the junction charge storage between the second conductivity type pillar 4, the first conductivity type pillar 3 and the buffer 2. This improves the reverse recovery softness factor of the device. Furthermore, by controlling the doping concentrations of the second conductivity type doped layer 411 and the first conductivity type doped region 412, the depletion rate of the first conductivity type pillar 3 is controlled, thereby mitigating the sudden change in the output capacitance of the device. Furthermore, while the control layer 41 is provided in the second conductivity type pillar 4, the doping concentration of the first conductivity type pillar 3 does not change, and consequently the on-resistance of the device does not increase.

[0106] Example 2

[0107] This embodiment provides a method for fabricating a superjunction MOSFET, such as... Figure 10 The diagram shown is a process flow chart of the fabrication method of the superjunction MSOFET, including the following steps:

[0108] S1: Provide a substrate of a first conductivity type, and form a buffer zone of the first conductivity type on the upper surface of the substrate;

[0109] S2: A first conductive type first pillar region and a second conductive type pillar located on both sides of the first pillar region are formed on the upper surface of the buffer zone, and the sidewall of the second conductive type pillar is adjacent to the sidewall of the first pillar region. The upper surface of the first pillar region is flush with the upper surface of the second conductive type pillar. During the formation of the second conductive type pillar, at least one control layer is formed in the second conductive type pillar. The control layer includes a second conductive type doped layer and a first conductive type doped region located in the second conductive type doped layer.

[0110] S3: A first conductive type second column region is formed on the upper surface of the first column region to form a first conductive type column, and a second conductive type body region is formed on both sides of the second column region, located on the upper surface of the second conductive type column and adjacent to the side wall of the second column region, wherein the upper surface of the body region is flush with the upper surface of the second column region;

[0111] S4: A first conductive type source region and a second conductive type body contact region are formed adjacent to each other in the upper surface layer of the body region, and the source region and the body contact region are spaced apart from the first conductive type pillar by a preset distance;

[0112] S5: A gate structure is formed above the source region, the first conductivity type pillar, and the body region between the source region and the first conductivity type pillar, and a source electrode is formed covering the exposed surface of the gate structure, the body region, the source region, and the body contact region, and a drain electrode is formed covering the bottom surface of the substrate.

[0113] Perform step S1: Provide a substrate of a first conductivity type and form a buffer zone of a first conductivity type on the upper surface of the substrate.

[0114] Specifically, the thickness of the buffer can be selected according to the actual situation, and is not limited here.

[0115] Specifically, the method for forming the buffer zone includes chemical vapor deposition or other suitable methods.

[0116] Perform steps S2 and S3: A first conductive type first pillar region and a second conductive type pillar located on both sides of the first pillar region are formed on the upper surface of the buffer zone, and the sidewall of the second conductive type pillar is adjacent to the sidewall of the first pillar region. The upper surface of the first pillar region is flush with the upper surface of the second conductive type pillar. During the formation of the second conductive type pillar, at least one control layer is formed in the second conductive type pillar. The control layer includes a second conductive type doped layer and a first conductive type doped region located in the second conductive type doped layer. A first conductive type second pillar region is formed on the upper surface of the first pillar region to form the first conductive type pillar. A second conductive type body region is formed on both sides of the second pillar region, located on the upper surface of the second conductive type pillar and adjacent to the sidewall of the second pillar region. The upper surface of the body region is flush with the upper surface of the second pillar region.

[0117] Specifically, the method for forming the second conductive type pillar and the first pillar region includes forming multiple pillar region semiconductor layers stacked upwards on the upper surface of the buffer, and forming the first pillar region and the second conductive type pillar in a designated area of ​​the semiconductor layer after each pillar region semiconductor layer is formed, until the thickness of the first pillar region and the second conductive type pillar reaches a preset thickness.

[0118] Specifically, during the formation of the second conductivity type pillar, the control layer is formed at a predetermined position in the pillar semiconductor layer. That is, firstly, a second conductivity type doped layer is formed at a predetermined position in the pillar semiconductor layer, and the doping concentration of the second conductivity type doped layer is higher than the doping concentration of the second conductivity type pillar. Then, a first conductivity type doped region is formed at a predetermined position in the second conductivity type doped layer. The steps of forming the pillar semiconductor layer and forming the second conductivity type doped layer and the first conductivity type doped region in the pillar semiconductor layer are repeated until a second conductivity type doped layer and a first conductivity type doped region of a predetermined thickness are obtained to obtain the control layer.

[0119] Specifically, when the second conductive type column is provided with multiple control layers, the control layers are formed at preset positions of the second conductive type column during the formation of the second conductive type column.

[0120] Specifically, the thickness of the semiconductor layer in the pillar region can be selected according to the actual situation, and is not limited here.

[0121] Specifically, the method for forming the semiconductor layer in the pillar region includes chemical vapor deposition or other suitable methods.

[0122] Specifically, the methods for forming the second type of conductive column include ion implantation or other suitable methods.

[0123] Specifically, the method for forming the second conductivity type doped layer is ion implantation or other suitable methods; the method for forming the first conductivity type doped layer includes ion implantation or other suitable methods.

[0124] Specifically, the method for forming the first column region includes ion implantation or other suitable methods.

[0125] Specifically, after forming the first pillar region and the second conductivity type pillar, a first semiconductor layer is formed on the upper surface of the pillar region semiconductor layer, and the second pillar region is formed in the first semiconductor layer above the first pillar region to obtain the first conductivity type pillar, and the body region is formed in the first semiconductor layer above the second conductivity type pillar.

[0126] Specifically, the method for forming the first semiconductor layer includes chemical vapor deposition or other suitable methods.

[0127] Specifically, the thickness of the first semiconductor layer can be selected according to the actual situation, and is not limited here.

[0128] Specifically, the method for forming the second column region includes ion implantation or other suitable methods; the method for forming the body region includes ion implantation or other suitable methods.

[0129] Perform steps S4 and S5: Form an adjacent first conductivity type source region and a second conductivity type body contact region in the upper surface layer of the body region, and the source region and the body contact region are spaced apart from the first conductivity type pillar by a predetermined distance; form a gate structure above the source region, the first conductivity type pillar and the body region between the source region and the first conductivity type pillar, and form a source electrode covering the exposed surfaces of the gate structure, the body region, the source region and the body contact region, and form a drain electrode covering the bottom surface of the substrate.

[0130] Specifically, the methods for forming the source region include ion implantation or other suitable methods.

[0131] Specifically, the method for forming the body contact area includes ion implantation or other suitable methods.

[0132] Specifically, the size and doping concentration of the source region can be selected according to the actual situation, and are not limited here.

[0133] Specifically, the size and doping concentration of the body contact region can be selected according to the actual situation, and are not limited here.

[0134] Specifically, after forming the source region and the body contact region in the body region, a first isolation layer and a conductive material layer are sequentially formed on the upper surface of the first semiconductor layer, and the first isolation layer and the conductive material layer are etched to obtain a gate isolation layer and a gate. Then, a second isolation layer is formed on the exposed surface of the gate and the gate isolation layer to obtain a gate dielectric layer including the gate isolation layer and the second isolation layer and a gate structure including the gate dielectric layer and the gate.

[0135] Specifically, the thickness of the first insulating layer can be selected according to the actual situation, and is not limited here; the thickness of the conductive material layer can be selected according to the actual situation, and is not limited here.

[0136] Specifically, the method for forming the first isolation layer includes thermal oxidation, chemical vapor deposition, or other suitable methods.

[0137] Specifically, the material of the first insulating layer includes silicon dioxide or other suitable dielectric materials.

[0138] Specifically, the method for forming the conductive material layer includes chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0139] Specifically, the conductive material layer may be made of polycrystalline silicon or other suitable conductive materials.

[0140] Specifically, the methods for forming the second isolation layer include thermal oxidation, chemical vapor deposition, or other suitable methods.

[0141] Specifically, the material of the second isolation layer includes silicon dioxide, silicon nitride, or other suitable materials. In this embodiment, both the first and second isolation layers are made of silicon dioxide.

[0142] Specifically, the method for forming the gate isolation layer includes one of dry etching and wet etching, or other suitable methods.

[0143] Specifically, the method for forming the gate includes one of dry etching and wet etching, or other suitable methods.

[0144] Specifically, the methods for forming the source electrode include sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.

[0145] Specifically, the methods for forming the drain include sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.

[0146] The superjunction MOSFET fabrication method of this embodiment only involves forming at least one control layer in the second conductivity type pillar, and only changing the doping concentration of the second conductivity type doped layer and the position of the first conductivity type doped region in the control layer. The process of forming the first conductivity type pillar remains unchanged and will not increase the process tolerance of forming the superjunction MOSFET.

[0147] In summary, the superjunction MOSFET and its fabrication method of the present invention, by setting at least one control layer including a first conductivity type doped layer and a second conductivity type doped layer in the second conductivity type pillar, and after the second conductivity type doped layer and the first conductivity type doped layer compensate for each other, the conductivity type of the second conductivity type doped layer remains unchanged. By controlling the doping concentration of the second conductivity type doped layer and the first conductivity type doped region and the size of the first conductivity type doped region, the resistance of the second conductivity type pillar is controlled, thereby increasing the resistance of the second conductivity type pillar to prevent overcharging during reverse recovery and reducing the junction charge storage between the second conductivity type pillar, the first conductivity type pillar and the buffer zone, thereby improving the reverse recovery softness factor of the device. In addition, only the structure of the second conductivity type pillar is changed, without changing the doping concentration and structure of the first conductivity type pillar, so the on-resistance and process tolerance of the device will not increase. Furthermore, by controlling the doping concentration of the second conductivity type doped layer and the first conductivity type doped region, the depletion rate of the first conductivity type pillar is controlled, thereby mitigating the sudden change in the output capacitance of the device. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0148] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A superjunction MOSFET, characterized in that, include: First conductivity type substrate; A first conductivity type buffer is located on the upper surface of the substrate; A first conductive type pillar is disposed on the upper surface of the buffer and extends in a direction away from the substrate, and the first conductive type pillar includes a first pillar region and a second pillar region stacked on the first pillar region. A second conductivity type pillar is disposed on the upper surface of the buffer and located on both sides of the first pillar region. The second conductivity type pillar includes at least one control layer. The sidewall of the second conductivity type pillar is adjacent to the sidewall of the first pillar region. The upper surface of the second conductivity type pillar is flush with the upper surface of the first pillar region. The control layer includes a second conductivity type doped layer and a first conductivity type doped region located in the second conductivity type doped layer. The second type of conductive body region is stacked on the second type of conductive pillar, and the upper surface of the body region is flush with the upper surface of the second pillar region, and the sidewall of the body region is adjacent to the sidewall of the second pillar region. The adjacent first conductivity type source region and the second conductivity type body contact region are located on the upper surface of the body region, and the source region and the body contact region are separated from the first conductivity type pillar by a predetermined distance; A gate structure is located above the source region, the second pillar region, and the body region between the source region and the second pillar region; The source and drain electrodes are provided, wherein the source electrode covers the exposed surfaces of the gate structure, the body region, the source region and the body contact region, and the drain electrode covers the bottom surface of the substrate.

2. The superjunction MOSFET according to claim 1, characterized in that: The doping concentration of the substrate is higher than that of the buffer.

3. The superjunction MOSFET according to claim 1, characterized in that: The control layer is located between the top and bottom of the second conductive type pillar, and the thickness of the control layer is not greater than the thickness of the second conductive type pillar.

4. The superjunction MOSFET according to claim 1, characterized in that: The sidewall of the first conductivity type doped region is spaced apart from the sidewall of the first conductivity type pillar by a predetermined distance.

5. The superjunction MOSFET according to claim 1, characterized in that: The doping concentration of the second conductivity type doped layer is higher than the doping concentration of the second conductivity type pillar outside the control layer, and the conductivity type of the second conductivity type doped region does not change after the first conductivity type doped region is completely exhausted.

6. The superjunction MOSFET according to claim 1, characterized in that: The doping concentration range of the first conductivity type doped region is 1×10⁻⁶. 15 cm -3 ~5×10 16 cm -3 The doping concentration range of the second conductivity type doped region is 1×10⁻⁶. 15 cm -3 ~5×10 16 cm -3 .

7. The superjunction MOSFET according to claim 1, characterized in that: When the second conductive type column includes multiple control layers, the total thickness of the control layers is not greater than the thickness of the second conductive type column.

8. The superjunction MOSFET according to claim 7, characterized in that: The two adjacent control layers are set apart or adjacent to each other.

9. The superjunction MOSFET according to claim 1, characterized in that: The gate structure includes a gate dielectric layer and a gate, the gate dielectric layer encapsulating the gate, and both ends of the gate extending above the source region.

10. A method for fabricating a superjunction MOSFET, characterized in that, Includes the following steps: A substrate of a first conductivity type is provided, and a buffer zone of the first conductivity type is formed on the upper surface of the substrate; A first conductive type first pillar region and a second conductive type pillar located on both sides of the first pillar region are formed on the upper surface of the buffer zone, and the sidewall of the second conductive type pillar is adjacent to the sidewall of the first pillar region. The upper surface of the first pillar region is flush with the upper surface of the second conductive type pillar. During the formation of the second conductive type pillar, at least one control layer is formed in the second conductive type pillar. The control layer includes a second conductive type doped layer and a first conductive type doped region located in the second conductive type doped layer. A first conductive type second column region is formed on the upper surface of the first column region to form a first conductive type column, and a second conductive type body region is formed on both sides of the second column region, located on the upper surface of the second conductive type column and adjacent to the side wall of the second column region, wherein the upper surface of the body region is flush with the upper surface of the second column region; An adjacent first conductive type source region and a second conductive type body contact region are formed in the upper surface layer of the body region, and the source region and the body contact region are spaced apart from the first conductive type pillar by a predetermined distance; A gate structure is formed above the source region, the first conductivity type pillar, and the body region between the source region and the first conductivity type pillar, and a source electrode is formed covering the exposed surface of the gate structure, the body region, the source region, and the body contact region, and a drain electrode is formed covering the bottom surface of the substrate.

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