Sorting method and device, decoder, communication equipment and storage medium

Abstract

The invention relates to the technical field of decoding in communication, in particular to a sorting method and device, a decoder, communication equipment and a storage medium. The method is applied to a decoder, and comprises the following steps: determining a sub-path sequence corresponding to each main path according to the number M of information bits of parallel decoding and the number P of frozen bits in each decoding; p belongs to [0, M); the positive integer is a non-negative integer; determining a metric value of each sub-path in the sub-path sequence, and taking the metric value of each sub-path in the sub-path sequence as a to-be-sorted sequence; determining a sorting network according to the total amount of the metric values in the L to-be-sorted sequences, and sorting the metric values in the L to-be-sorted sequences by using the sorting network to obtain the minimum L metric values; wherein the sorting network comprises M-P sorting layers, and the sorting layers are used for sorting the measurement values and filtering half of data according to a descending order. By adopting the method provided by the invention, the time delay of metric value sorting in a multi-bit SCL decoding process can be reduced.

Description

Technical Field

[0001] This application relates to the technical field of decoding in communication, and in particular to a sorting method, apparatus, decoder, communication device and storage medium. Background Technology

[0002] In the field of communications, to achieve high throughput and low latency polar code decoding, the industry has proposed a multi-bit SCL algorithm for decoding polar codes. The essence of multi-bit SCL decoding is the alternation of SC decoding and metric sorting. The latency of SC decoding and the latency of metric sorting together constitute the latency of the multi-bit SCL algorithm. Assuming that the number of information bits that can be decoded simultaneously in parallel during multi-bit decoding is M, and the number of main paths is L, then for every M information bits decoded, the metric sorting process requires... Among the available paths, L are selected as the shortest; in the process of decoding a polar code of length N, it is necessary to perform... The ranking of secondary metrics. When L is large or When the values ​​are large, the complexity of sorting the metrics is high, resulting in a significant time delay.

[0003] Related technologies typically use algorithms such as extended punctured bitonic sorting, simplified bubble sort, and odd-even sorting to sort metrics; however, these sorting algorithms are extensions of sorting methods used in single-bit SC decoding and do not take into account the characteristics of multi-bit decoding, so their decoding latency is still relatively high.

[0004] Therefore, how to further reduce the latency of metric sorting in the multi-bit SCL decoding process is an urgent problem to be solved. Summary of the Invention

[0005] Therefore, it is necessary to provide a sorting method, apparatus, decoder, communication device, and storage medium that can reduce the delay of metric sorting in the multi-bit SCL decoding process, in order to address the above-mentioned technical problems.

[0006] In a first aspect, this application provides a sorting method applied to a decoder, the method comprising:

[0007] The sub-path sequence corresponding to each main path is determined based on the number of information bits M in parallel decoding and the number of frozen bits P in each decoding step; P∈[0,M). , The value is a non-negative integer; the frozen bit is the information bit that has a fixed path.

[0008] Determine the metric value of each sub-path in the sub-path sequence, and use the metric values ​​of each sub-path in the sub-path sequence as a sequence to be sorted;

[0009] Based on the total amount of the metrics in the L sequences to be sorted, a sorting network is determined, and the sorting network is used to sort the metrics in the L sequences to be sorted to obtain the L smallest metrics.

[0010] The sorting network includes MP sorting layers, which are used to sort each of the metrics and filter out half of the data in descending order.

[0011] In one embodiment, when P∈[0, M-1], the sorting layer of the first level is composed of several parallel first sorting modules. The first sorting module is used to sort and filter the input T elements and output the smallest T / 2 elements in an increasing sequence.

[0012] Each sorting layer after the first level is composed of a parallel second sorting module, wherein the second sorting module is used to sort a bitonic sequence of length T and finally output the smallest T / 2 elements as a bitonic sequence.

[0013] The number of second sorting modules in the second-level sorting layer is half the number of first sorting modules in the first-level sorting layer;

[0014] The number of the second sorting modules in each sorting layer after the second level is half the number of the second sorting modules in the previous level sorting layer.

[0015] In one embodiment, when P=M-1, the sorting network has only one sorting layer, and the sorting layer consists of only one second sorting module.

[0016] In one embodiment, if the number of the second sorting modules running in parallel in the sorting layer at level H is greater than or equal to 4, then the sorting layer at level H is connected to the sorting layer at the next level through a sequence conversion layer; where H ≥ 2.

[0017] The sequence conversion layer consists of multiple parallel sequence conversion modules, which are used to convert the elements of a bitonic sequence of length T / 2 into a monotonically increasing sequence output.

[0018] The number of sequence conversion modules is the same as the number of the second sorting modules in the sorting layer of level H.

[0019] In one embodiment, when the number of the second sorting modules running in parallel in the sorting layer at level H is 2, the sorting layer at level H is connected to the sorting layer at the next level through a bubble layer; H≥2;

[0020] The bubbling layer includes two parallel bubbling modules, which are used to convert a sequence of length T / 2 into a monotonically increasing sequence output.

[0021] In one embodiment, the number of the first sorting modules running in parallel is the ratio of the total number of the metrics to T, where T=16.

[0022] Secondly, this application also provides a sorting apparatus, the apparatus comprising a sequence determination module and a sorting module, wherein:

[0023] The sequence determination module is used to determine the sub-path sequence corresponding to each main path based on the number of information bits M and the number of frozen bits P; P∈[0,M). , The value is a non-negative integer; the frozen bit is the information bit that has a fixed path.

[0024] The sequence determination module is further configured to determine the metric value of each sub-path in the sub-path sequence, and use the metric values ​​of each sub-path in the sub-path sequence as a sequence to be sorted;

[0025] The sorting module is used to determine a sorting network based on the total amount of the metric values ​​in the L sequences to be sorted, and to use the sorting network to sort the metric values ​​in the L sequences to be sorted to obtain the L smallest metric values.

[0026] The sorting network includes MP sorting layers, which are used to sort each of the metrics and filter out half of the data in descending order.

[0027] Thirdly, this application also provides a decoder, which includes multiple hardware sub-units, a sorting unit, a metric determination unit, and a network determination unit, wherein:

[0028] The metric determination unit is used to determine the sub-path sequence corresponding to each main path based on the number of information bits M and the number of frozen bits P; P∈[0,M). , The value is a non-negative integer; the frozen bit is the information bit that has a fixed path.

[0029] The metric value determination unit is further configured to determine the metric value of each sub-path in the sub-path sequence, and use the metric values ​​of each sub-path in the sub-path sequence as a sequence to be sorted;

[0030] The network determining unit is used to determine the network structure table corresponding to the sorting network based on the total amount of the metrics in the L sequences to be sorted. The network structure table represents the type, quantity, and connection relationship of each hardware sub-unit constituting the sorting network.

[0031] The sorting unit is used to sort the metric values ​​in the L sequences to be sorted based on the sorting network indicated by the network structure table, so as to obtain the L smallest metric values.

[0032] The sorting network includes MP sorting layers, which are used to sort the metric values ​​based on their size and filter out the largest half.

[0033] Fourthly, this application also provides a communication device, which includes a decoder as described in the third aspect above.

[0034] Fifthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the sorting method as described in any one of the first aspects above.

[0035] Sixthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the sorting method as described in any one of the first aspects above.

[0036] In the aforementioned sorting methods, apparatus, decoders, communication devices, and storage media, since the number of information bits M and the number of main paths L in the actual decoding process are already determined, the only dynamically changing element in each parallel decoding of M information bits is the number of frozen bits P. In other words, the number of sorting layers in the sorting network is negatively correlated with the number of frozen bits P. That is, the more frozen bits, the fewer sorting layers the sorting network has, resulting in a simpler network; conversely, the fewer frozen bits, the more sorting layers the network has, leading to a more complex network. In related technologies, the structure of the sorting network remains the same regardless of the number of frozen bits. However, the sorting method provided in this application can dynamically select the corresponding sorting network based on the number of frozen bits. Therefore, when the number of frozen bits is large, a simpler sorting network with fewer sorting layers can be used to sort the metrics, thereby shortening the sorting time and reducing the latency of metric sorting. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a flowchart illustrating a sorting method in one embodiment;

[0039] Figure 2 This is a schematic diagram of the Comparison Permutation (CAS) structure in one embodiment;

[0040] Figure 3 This is a schematic diagram of the structure of the first sorting module (PMS) in one embodiment;

[0041] Figure 4 This is a schematic diagram of the structure of the second sorting module (16mux8) in one embodiment;

[0042] Figure 5 This is a schematic diagram of the sequence conversion module (Simple bitonic) in one embodiment;

[0043] Figure 6 This is a schematic diagram of the structure of a sorting network when P=0 in one embodiment;

[0044] Figure 7 This is a schematic diagram of the structure of a sorting network when P=1 in one embodiment;

[0045] Figure 8 This is a schematic diagram of the structure of a sorting network when P=2 in one embodiment;

[0046] Figure 9 This is a schematic diagram of the structure of a sorting network when P=3 in one embodiment;

[0047] Figure 10 This is a schematic diagram of the sorting device in one embodiment;

[0048] Figure 11 Here is a block diagram of the decoder in one embodiment;

[0049] Figure 12 This is an internal structural diagram of a communication device in one embodiment. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0051] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0052] The sorting method provided in this application is applied to a decoder; the decoder can be configured in a communication device to decode the polar codes received by the communication device. The communication device can be a base station or a terminal; the terminal includes various personal computers, laptops, smartphones, tablets, drones, low-altitude aircraft, IoT devices, and portable wearable devices. IoT devices can include smart speakers, smart TVs, smart air conditioners, smart in-vehicle devices, and projection devices. Portable wearable devices can include smartwatches, smart bracelets, and head-mounted devices. Head-mounted devices can be virtual reality (VR) devices, augmented reality (AR) devices, and smart glasses.

[0053] In one exemplary embodiment, such as Figure 1 As shown, a sorting method is provided, specifically including the following steps 110 to 130, wherein:

[0054] Step 110: Determine the sub-path sequence corresponding to each main path based on the number of information bits M in parallel decoding and the number of frozen bits P in each decoding step; P∈[0,M). , It is a non-negative integer; frozen bits are information bits with fixed paths.

[0055] In the embodiments of this application, the length of the received polar code is N, that is, there are N bits in the received polar code; wherein, the decoder can only perform parallel decoding on M bits at a time, where M≥2.

[0056] Furthermore, during each parallel decoding of M information bits, since the decoded value of each information bit can be either 0 or 1, where 0 represents the high-order bit and 1 represents the low-order bit, for M information bits, there are a total of There are 10 possible combinations of decoded values ​​for the M information bits. Each combination of decoded values ​​for these M information bits corresponds to a possible subpath on each main path. Therefore, for each of the L main paths, the M information bits will have 10 possible subpaths. There are L sub-paths. For L main paths, these M information bits will exist in total during the decoding process. Sub-path.

[0057] The characteristic of multi-bit SCL decoding is that the number of frozen bits is determined in real time based on a preset frozen bit map when decoding M information bits each time. The frozen bit map means that M bits are read each time according to the decoding sequence, and the bits are inverted bit by bit according to the decoded value from high to low. The number of frozen bits, in turn, determines the number of sub-paths that may be derived from each main path.

[0058] From all possible combinations of decoded values ​​corresponding to the M information bits, remove the combinations of decoded values ​​corresponding to the frozen bit diagram, and use the remaining combinations of decoded values ​​as sub-paths to be sorted; therefore, the number of sub-paths corresponding to the M information bits and P frozen bits in each main path is... .

[0059] When P=M, since each of the M information bits corresponds to a fixed decoding value, the combination of the decoding values ​​of the M information bits is fixed, meaning that there is no need to sort the subpath metrics.

[0060] Step 120: Determine the metric value of each sub-path in the sub-path sequence, and use the metric values ​​of each sub-path in the sub-path sequence as the sequence to be sorted.

[0061] In the embodiments of this application, for each sub-path, a metric value for the sub-path is determined based on the decoded values ​​of the M information bits corresponding to that sub-path; wherein, the metric value characterizes the reliability of the sub-path; the smaller the metric value, the more reliable the sub-path. Therefore, for The purpose of sorting is to select the L sub-paths with the smallest metric values. It should be noted that when decoding M information bits, the metric values ​​only need to be sorted when decoding the last information bit to select the L metric values; therefore, the intermediate decoding steps do not require monotonically sorting the L smallest numbers.

[0062] The sequence of sub-paths corresponding to each main path contains a total of The metric of each sub-path, i.e., the number of sub-paths within each sequence to be sorted. The metrics that need to be included in the sorting.

[0063] Step 130: Determine the sorting network based on the total number of metrics in the L unsorted sequences, and use the sorting network to sort the metrics in the L unsorted sequences to obtain the L smallest metrics; wherein, the sorting network includes MP sorting layers, which are used to sort each metric and filter out half of the data in descending order.

[0064] For the embodiments of this application, the total number of metrics in the L sequences to be sorted is: L, the result of the metric sorting is from The L sub-paths with the smallest metric values ​​are selected from the sorting network. The sorting network has MP sorting layers; that is, when P=0 and there are no frozen bits, the sorting network has the most sorting layers, and when P=M-1, the sorting network has the fewest sorting layers, with a minimum of 1 layer. Each sorting layer consists of at least one sorting module. Since the amount of data (number of metrics) that a sorting module can process is limited, the number of sorting modules in a sorting layer is determined by the number of metrics input to that layer.

[0065] In the above sorting method, since the number of information bits M and the number of main paths L in the actual decoding process are already determined, the only dynamically changing element in each parallel decoding of M information bits is the number of frozen bits P. In other words, the number of sorting layers in the sorting network is negatively correlated with the number of frozen bits P. That is, the more frozen bits there are, the fewer sorting layers the sorting network has, resulting in a simpler network; conversely, the fewer frozen bits there are, the more sorting layers the network has, leading to a more complex network. In related technologies, the structure of the sorting network remains the same regardless of the number of frozen bits. However, the sorting method provided in this application can dynamically select the corresponding sorting network based on the number of frozen bits. Therefore, when the number of frozen bits is large, a simpler sorting network with fewer sorting layers can be used to sort the metrics, thereby shortening the sorting time and reducing the latency of sorting the metrics.

[0066] Furthermore, the structure of the sorting network is further elaborated; each sorting layer consists of parallel, single sorting modules, which can be either first or second sorting modules; both the first and second sorting modules are built based on the basic comparison and permutation module; furthermore, the sorting network also includes a sequence transformation module. The following sections will elaborate on each module constituting the sorting network.

[0067] Reference Figure 2This is a schematic diagram of the Compare and Swap (CAS) module, which is used for ascending order sorting; that is, when a > b, the positions of a and b are swapped; when a ≤ b, the positions of a and b remain unchanged.

[0068] The first sorting module is constructed from multiple comparison-permutation (CAS) modules and is also known as the punctured PMS module. Specifically, it sorts the T elements (measures) in the input sequence of measures, filters out the largest half of the elements, and then outputs the smaller T / 2 elements in a monotonically increasing sequence. The input sequence for the first sorting module is... Its output sequence is .

[0069] like Figure 3 The diagram shows the structure of the first sorting module, which includes 10 serially arranged unit structures from 0 to 9. The second sorting module is also constructed from multiple comparison permutation (CAS) modules, and it is a unit structure within the first sorting module. The second sorting module (16mux8 module) is used to sort the elements (metrics) in a bitone sequence of length T and output the smallest T / 2 elements as a bitone sequence.

[0070] like Figure 4 The diagram shows the structure of the second sorting module, which is the fourth unit structure in the first sorting module. The input sequence for the second sorting module is... The bitonic sequence is given, and the output bitonic sequence is given. .

[0071] Furthermore, the sequence conversion module is a simple bitonic module; it is used to sort a bitonic sequence of length T / 2 and output a monotonically increasing sequence. For example... Figure 5 The diagram shown is a structural schematic of the sequence conversion module, whose input sequence is a bitonic sequence. Its output sequence is a monotonically increasing sequence. .

[0072] A monotonically increasing sequence is one in which the values ​​of the elements increase sequentially in the order they are arranged; for example, (1, 2, 3, 5, 7) is a monotonically increasing sequence. A monotonically decreasing sequence is one in which the values ​​of the elements decrease sequentially in the order they are arranged; for example, (8, 6, 4, 2, 1) is a monotonically decreasing sequence. A bitonal sequence is one in which the values ​​of the elements increase first and then decrease, or decrease first and then increase, in the order they are arranged; for example, (1, 2, 9, 5, 3) and (5, 3, 2, 8, 9) are both bitonal sequences.

[0073] Furthermore, the bubble sort module uses the bubble sort algorithm to sort a sequence of length T / 2. Convert to monotonically increasing sequence .

[0074] The above content describes the structure and function of each module constituting the sorting network; each of the above modules can be constructed by hardware or software and hardware-software structures, and this application embodiment does not impose specific limitations on them.

[0075] The following content provides a detailed explanation of the structure of sorting networks.

[0076] In one embodiment, when P∈[0, M-1], each sorting layer of the first level consists of several parallel first sorting modules, and each sorting layer after the first level consists of parallel second sorting modules. The number of second sorting modules in the second level sorting layer is half the number of first sorting modules in the first level sorting layer; the number of second sorting modules in each sorting layer after the second level is half the number of second sorting modules in the previous level sorting layer.

[0077] Since the sorting module only includes a first sorting module and a second sorting module, and the input requirement for the second sorting module is a bitonic sequence; and the first-level sorting layer is used to sort unordered metric sequences, therefore, the first-level sorting layer can only consist of the first sorting module. Furthermore, since the first sorting module outputs an increasing sequence of length T / 2, and the second sorting module requires a bitonic sequence of length T as input, the two monotonically increasing sequences of length T / 2 output from the first sorting modules in the first-level sorting layer are grouped together. Simultaneously, one of the monotonically increasing sequences of length T / 2 is inverted to obtain a monotonically decreasing sequence of length T / 2. Further, the monotonically increasing and decreasing sequences, both of length T / 2, are concatenated to obtain a bitonic sequence of length T. This bitonic sequence can then be used as the input to one of the second sorting modules in the second-level sorting layer.

[0078] It should be noted that when both the first and second sorting modules are hardware structures, it is not necessary to process the monotonically increasing sequence output by the first sorting module separately to obtain a monotonically decreasing sequence; instead, the output interface of one of the first sorting modules can be connected to the input interface of the second sorting module, and the output interface of the other first sorting module can be connected to the input interface of the second sorting module in reverse, so that the input of the second sorting module is a bitone sequence.

[0079] When P=M-1, the sorting network has only one sorting layer, and the sorting layer consists of only one second sorting module. When P=M-1, it is effectively equivalent to having only one information bit on each main path with a total of 2L possible sub-paths, meaning the number of metrics to be sorted is 2L. Since each sorting layer is used to filter out the larger half of the metrics, for a set of 2L metrics, only one sorting layer is needed to obtain the required L smallest metrics.

[0080] In one embodiment, when the network structure has many sorting layers, such as three or more, the second and third level sorting layers are both composed of second sorting modules. However, since the output of the second sorting module is a monotonic sequence of length T / 2, the output of the second sorting module in the previous level sorting layer cannot be directly used as the input of the second sorting module in the next level sorting layer. In this embodiment, a sequence conversion layer is introduced to convert the bitonic sequence output by the second sorting module in the previous level sorting layer into a monotonically increasing sequence before using it as the input of the second sorting module in the next level sorting layer.

[0081] Furthermore, if the number of parallel second sorting modules in the H-th sorting layer is greater than or equal to 4, then the H-th sorting layer is connected to the next level sorting layer through a sequence transformation layer; where H≥2; the sequence transformation layer consists of multiple parallel sequence transformation modules, which are used to convert the elements of a bitonic sequence of length T / 2 into a monotonically increasing sequence output. The number of sequence transformation modules is the same as the number of second sorting modules in the H-th sorting layer.

[0082] Specifically, the number of parallel second sorting modules in the sequence conversion layer is equal to the number of parallel sequence conversion modules in the sorting layer above the sequence conversion layer. In other words, there is a one-to-one correspondence between the sequence conversion modules in the sequence conversion layer and the second sorting modules in the sorting layer above.

[0083] Furthermore, when the number of parallel second sorting modules in the H-level sorting layer is 2, a bubble layer connects the H-level sorting layer to the next level sorting layer. The bubble layer includes two parallel bubble modules, which are used to convert a sequence of length T / 2 into a monotonically increasing sequence output.

[0084] Specifically, when a sorting layer consists of only two parallel second sorting modules, the next level of sorting layer is the last layer of the sorting network, which consists of only one second sorting module. In other words, the function of the bubble layer is the same as that of the sequence transformation layer: to transform the bitonic sequence output by the previous level of sorting layer into a monotonically increasing sequence, which is then used as the output of the next level of sorting layer. The difference is that the bubble layer connects only the last level of the sorting network to the previous level, while the sequence transformation layer connects other levels of sorting layers.

[0085] It is important to emphasize that, for the sequence conversion layer, since each sequence conversion module outputs a monotonically increasing sequence of length T / 2, the two sequence conversion modules in this layer correspond to a second sorting module in the next level sorting layer. Furthermore, the output interface of one sequence conversion module is directly connected to the input port of the corresponding first sorting module, while the output interface of the other sequence conversion module is connected in reverse to the input port of the corresponding first sorting module. This results in one sequence conversion module outputting a monotonically increasing sequence and the other outputting a monotonically decreasing sequence, thus forming a bitonal sequence that is output to the corresponding second sorting module.

[0086] In a typical decoding scenario, the number of information bits decoded in each parallel session is set to M=4, the number of main paths is set to 8, and the input data volume of the first sorting module is T=16. According to the protocol, the type of the frozen bit map is set to: 0000, 0001, 0011, 0101, 0111, 1111.

[0087] The following sections will explain the structure of the sorting network for the cases where P=0, 1, 2, 3, and 4.

[0088] When the number of frozen bits P=0, the sorting network has a structure of 4 (M) sorting layers, such as... Figure 6 As shown: Each main path Pathi (i=0, 1, ... 7) splits into 16 sub-path metric values ​​after 4 bits of information to be decoded, that is, 16 metric values ​​corresponding to the decoding values ​​from 0000 to 1111; the number of metric values ​​that need to be sorted is 16*8=128.

[0089] Stage 1 is the first-level sorting layer: the first-level sorting layer consists of 128 / 16=8 parallel first sorting modules (Pruned PMS modules); the input of each first sorting module is 16 metrics corresponding to each main path, and the output is a monotonically increasing sequence. In the first-level sorting layer, the monotonically increasing sequence of length 8 output by the i-th (i is an even number, i≤6) first sorting module and the monotonically decreasing sequence output by the (i+1)-th first sorting module together form a new bitonical sequence of length 16, which is input to the second-level sorting layer of Stage 2.

[0090] The second-level sorting layer consists of four parallel second-level sorting modules (16mux8 modules), each outputting a bitonic sequence of length 8. Further, the second-level sorting layer in Stage 2 is connected to the third-level sorting layer in Stage 3 via a sequence transformation layer. This layer consists of four parallel sequence transformation (Simplebitonic) modules. Each module corresponds one-to-one with a second-level sorting module in the previous level, converting the bitonic sequence of length 8 into a monotonically increasing sequence of length 8, and outputting it to the third-level sorting layer of Stage 3.

[0091] The third-level sorting layer consists of two parallel second sorting modules. The input of each second sorting module is a new bitone sequence of length 16 formed by the monotonically increasing sequence of length 8 input from one sequence conversion module in the sequence conversion layer and the monotonically decreasing sequence of length 8 output from the other sequence conversion module. Then the second sorting module outputs the bitone sequence of length 8 to the fourth-level sorting layer of Stage 4.

[0092] The fourth-level sorting layer is connected to the third-level sorting layer by a bubble layer, which consists of two bubble modules. The input of each bubble module is a bitonic sequence of length 8, which is the output of the second sorting module in the previous-level sorting layer. The output of the bubble module is a monotonically increasing sequence of length 8, which is then passed to the fourth-level sorting layer of Stage 4.

[0093] The fourth-level sorting layer consists of only one second sorting module. The input to this second sorting module is a sequence of length 8, output by the two bubble modules in the bubble layer. One bubble module's output is directly connected to the second sorting module's input, providing a monotonically increasing sequence. The other bubble module's output is connected in reverse, providing a monotonically decreasing sequence. This results in the second sorting module receiving a complete bitoneic sequence of length 16 as its input. The output of the second sorting module is a monotone sequence of length 8, which is the final output of the sorting network.

[0094] When the number of frozen bits P=0, the four sorting layers of the sorting network correspond to four stages, namely Stage1, Stage2, Stage3 and Stage4. The sorting layer of each stage is used to filter out the larger half of the input metrics and pass the smaller half of the metrics to the next stage. Finally, the 8 smallest metrics among all 128 input metrics are obtained, which are the metrics corresponding to the bitonic sequence 8 output by Stage4.

[0095] When the number of frozen bits P=1, the structure of the sorting network is 3 (4-1) sorting layers, such as Figure 7 As shown: Each main path Pathi (i=0, 1, ... 7) takes the metric value corresponding to the 8 decoded values ​​0000, 0010, 0100, 0110, 1000, 1010, 1100, and 1110; that is, each main path has 8 metric values ​​that need to be sorted, and there are a total of 64 metric values ​​that need to be sorted for the 8 main paths.

[0096] Stage 1 is the first-level sorting layer: the first-level sorting layer consists of 64 / 16=4 parallel first sorting modules (Pruned PMS modules); the input of each first sorting module is 8 metrics corresponding to each main path Path, and the output is a monotonically increasing sequence. The 8 metrics of Pathi (i is an even number, i≤6) and Pathi+1 in Stage 1 are injected into one first sorting module (Pruned PMS); the monotonically increasing sequence of length 8 output by the first sorting module is sent to the second-level sorting layer of Stage 2.

[0097] The second-level sorting layer consists of two parallel second sorting modules (16mux8 modules); the two first sorting modules output monotonically increasing and monotonically decreasing sequences of length 8 to a second sorting module, respectively, so that the input of the second sorting module is a bitonal sequence of length 16; each second sorting module outputs a bitonal sequence of length 8.

[0098] Furthermore, the second-level sorting layer of Stage 2 and the third-level sorting layer of Stage 3 are connected via a bubble layer; the third-level sorting layer consists of only one second sorting module. The bubble layer comprises two parallel bubble modules, whose outputs, respectively, form a bitonal sequence input in the third-level sorting layer of Stage 3 in a monotonically increasing and monotonically decreasing form. The second sorting module in the third-level sorting layer outputs a bitonal sequence of length 8, thereby selecting the 8 smallest measures from all 64 input measures.

[0099] When the number of frozen bits P=2, there are two forms of frozen bitmaps. When the frozen bitmap is 0011, each path takes the metric value corresponding to the four decoded values ​​0000, 0100, 1000, and 1100. When the frozen bitmap is 0101, each path takes the metric value corresponding to the four decoded values ​​0000, 0010, 1000, and 1010. That is, each main path corresponds to 4 possible sub-paths; that is, each main path corresponds to 4 metric values. There are a total of 4*8=32 metric values ​​that need to be sorted for 8 main paths.

[0100] The structure of a sorting network is as follows Figure 8 As shown: the number of sorting layers is 4-2=2, and the number of first sorting modules in the first-level sorting layer is 32 / 16=2. The 16 metrics of the main path Path0~3 in Stage1 are input into one first sorting module of the first-level sorting layer, and the 16 values ​​of the main path Path4~7 are input into another first sorting module; each first sorting module outputs a monotonic sequence of length 8 to the second-level sorting layer of Stage2.

[0101] The second-level sorting layer consists of only one second sorting module (16mux8 module); one first sorting module is directly connected to the second sorting module, and another first sorting module is directly connected to the second sorting module; thus, a monotonically increasing sequence of length 8 and a monotonically decreasing sequence are combined to form a new bitoneic sequence of length 16, which is input to the second sorting module. The second sorting module outputs a bitoneic sequence of length 8, which is the 8 smallest measures among the 32 input measures.

[0102] When the number of frozen bits P=3, the number of sorting layers in the sorting network is 4-3=1; each main path takes the metric value corresponding to the two decoded values ​​0000 and 1000; that is, each main path has 2 metric values, and there are a total of 16 metric values ​​for sorting the 8 main paths.

[0103] The structure of a sorting network is as follows Figure 9As shown: The first-level sorting layer includes one second sorting module (16mux8 module); before the sorting layer, there is a bubble layer consisting of two parallel bubble modules; specifically, the 8 values ​​corresponding to the main path Path0~3 are input into one bubble module, and the 8 metrics corresponding to Path4~7 are input into another bubble module; each bubble module outputs a monotonically increasing sequence of length 8. Furthermore, one bubble module is connected in reverse to the second sorting module, inputting a monotonically decreasing sequence of length 8; the other bubble module is connected in forward to the second sorting module, inputting a monotonically increasing sequence of length 8; thus, the input to the second sorting module is a bitonically increasing sequence of length 16, and the output is a bitonically increasing sequence of length 8, which are the 8 smallest metrics among the 16 input metrics.

[0104] When the number of frozen bits P=4, each path outputs the metric value corresponding to the decoded value 0000. Taking the typical number of decoding paths L=8 as an example, each main path Pathi (i=0, 1, ..., 7) corresponds to only 1 sub-path, with a total of 8 sub-paths. There is no need to sort the metric values ​​to determine the path.

[0105] The above example illustrates the structure of the sorting network when the number of information bits in each parallel decoding is M=4, the number of main paths is 8, and the input data of the first sorting module is 16, with the frozen bits ranging from 0 to 4.

[0106] It should be noted that when the number of information bits in each parallel decoding is M=2, the number of main paths is 8, and the input data of the first sorting module is 16, the structure of the sorting network corresponding to the freezing bit being 0 is as described above. Figure 8 This refers to the structure of the sorting network when M=4 and P=2. When M=8, and the number of main paths and the input data of the first sorting modulus are 16, the structure of the sorting network corresponding to different values ​​of the number of frozen bits can be derived based on the above rules and examples, and will not be elaborated here.

[0107] It should be noted that, in the actual decoding process, the number of information bits M and the number of main paths L in parallel decoding are already determined; and each module of each sorting network is composed of corresponding hardware sub-units, including the hardware sub-units corresponding to the first sorting module, the hardware sub-units corresponding to the sequence conversion module, and the hardware sub-units corresponding to the bubble module.

[0108] The structure of the sorting network corresponding to each value of P can be pre-constructed as a network structure table. The network structure table represents the type, quantity, and connection relationship of each hardware sub-unit constituting the sorting network. During each decoding, when determining the number of frozen bits P, the corresponding network structure table is determined according to P, and the corresponding hardware sub-unit is called to sort the metric value according to the structure of the sorting network indicated by the network structure table.

[0109] Furthermore, from the structure of each sorting network when P is different, it can be determined that when M and L are both fixed, the structure of the sorting network is most complex when P=0 and simplest when P=M-1. Moreover, the hardware of the hardware sub-units set in the decoder is fixed, and each time the relevant hardware sub-units are called according to the determined network structure table corresponding to P. In other words, these hardware sub-units can be reused. Since it is not necessary to set up a separate hardware structure for each sorting network, this also greatly reduces the complexity of the decoder.

[0110] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0111] Based on the same inventive concept, this application also provides a sorting apparatus for implementing the sorting method described above. The solution provided by this apparatus is similar to the implementation described in the above method; therefore, the specific limitations in one or more sorting apparatus embodiments provided below can be found in the limitations of the sorting method described above, and will not be repeated here.

[0112] In one exemplary embodiment, such as Figure 10 As shown, a sorting device 100 is provided, which includes a sequence determination module 101 and a sorting module 102, wherein:

[0113] Sequence determination module 101 is used to determine the sub-path sequence corresponding to each main path based on the number of information bits M and the number of frozen bits P; P∈[0,M). , The bits are non-negative integers; frozen bits are information bits with fixed paths.

[0114] The sequence determination module 101 is also used to determine the metric value of each sub-path in the sub-path sequence, and to use the metric value of each sub-path in the sub-path sequence as a sequence to be sorted;

[0115] The sorting module 102 is used to determine the sorting network based on the total number of metrics in the L sequences to be sorted, and to use the sorting network to sort the metrics in the L sequences to obtain the L smallest metrics. The sorting network includes MP sorting layers, which are used to sort each metric and filter out half of the data in descending order.

[0116] In the aforementioned sorting device, since the number of information bits M and the number of main paths L in parallel decoding are already determined during the actual decoding process, the only dynamically changing element in each parallel decoding of M information bits is the number of frozen bits P. In other words, the number of sorting layers in the sorting network is negatively correlated with the number of frozen bits P. That is, the more frozen bits there are, the fewer sorting layers the sorting network has, resulting in a simpler network; conversely, the fewer frozen bits there are, the more sorting layers the network has, leading to a more complex network. In related technologies, the structure of the sorting network remains the same regardless of the number of frozen bits. However, the sorting method provided in this application can dynamically select the corresponding sorting network based on the number of frozen bits. Therefore, when the number of frozen bits is large, a simpler sorting network with fewer sorting layers can be used to sort the metrics, thereby shortening the sorting time and reducing the latency of sorting the metrics.

[0117] In one embodiment, when P∈[0, M-1], the first-level sorting layer is composed of several parallel first sorting modules. The first sorting module is used to sort and filter the input T elements and output the smallest T / 2 elements in an increasing sequence.

[0118] Each sorting layer after the first level consists of a parallel second sorting module, which sorts a bitonic sequence of length T and finally outputs the smallest T / 2 elements as a bitonic sequence.

[0119] The number of second sorting modules in the second-level sorting layer is half that of the number of first sorting modules in the first-level sorting layer.

[0120] The number of second sorting modules in each sorting layer after the second level is half the number of second sorting modules in the previous level sorting layer.

[0121] In one embodiment, when P=M-1, the sorting network has only one sorting layer, and the sorting layer consists of only one second sorting module.

[0122] In one embodiment, if the number of parallel second sorting modules in the H-th sorting layer is greater than or equal to 4, then the H-th sorting layer is connected to the next level sorting layer through a sequence conversion layer; where H≥2.

[0123] The sequence transformation layer consists of multiple parallel sequence transformation modules. Each sequence transformation module is used to transform the elements of a bitonic sequence of length T / 2 into a monotonically increasing sequence output.

[0124] The number of sequence transformation modules is the same as the number of second sorting modules in the H-level sorting layer.

[0125] In one embodiment, when the number of parallel second sorting modules in the H-th sorting layer is 2, the sorting layer in the H-th level is connected to the next level sorting layer through a bubble layer; H≥2;

[0126] The bubbling layer includes two parallel bubbling modules, which are used to convert a sequence of length T / 2 into a monotonically increasing sequence output.

[0127] In one embodiment, the number of parallel first sorting modules is the ratio of the total number of metrics to T, where T=16.

[0128] Each module in the sorting device 100 described above can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0129] In one exemplary embodiment, refer to Figure 11 A decoder is provided, which includes multiple hardware subunits, a sorting unit, a metric determination unit, and a network determination unit, wherein:

[0130] The metric determination unit is used to determine the sub-path sequence corresponding to each main path based on the number of information bits M and the number of frozen bits P; P∈[0,M). , The bits are non-negative integers; frozen bits are information bits with fixed paths.

[0131] The metric determination unit is also used to determine the metric value of each sub-path in the sub-path sequence, and to use the metric values ​​of each sub-path in the sub-path sequence as a sequence to be sorted.

[0132] The network determination unit is used to determine the network structure table corresponding to the sorting network based on the total number of metrics in the L sequences to be sorted. The network structure table represents the type, quantity, and connection relationship of each hardware sub-unit constituting the sorting network.

[0133] The sorting unit is used to sort the metrics in L sequences to be sorted based on the sorting network indicated by the network structure table, and to obtain the L smallest metrics.

[0134] The sorting network includes MP sorting layers, which sort the metrics based on their magnitude and filter out the largest half. The limitations on the decoder in the above sorting method embodiments also apply to the embodiments provided in this application, and will not be repeated here.

[0135] Furthermore, in an exemplary embodiment, a communication device is provided, which includes at least the decoder provided in the decoder embodiment described above. The communication device can be a terminal or a base station, as long as it is a device that uses the decoder disclosed in the decoder embodiment described above; for example, a terminal side of the 5G NR Physical Downlink Control Channel (PDCCH), a terminal side of the Physical Broadcast Channel (PBCH), a base station side of the Physical Uplink Control Channel (PUCCH), etc.

[0136] The internal structure diagram of the communication equipment can be as follows Figure 12As shown, the communication device includes a processor, memory, decoder, input / output interface, communication interface, display unit, and input device. The processor, memory, and input / output interface are connected via a system bus; the decoder, communication interface, display unit, and input device are also connected to the system bus via the input / output interface. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The input / output interface is used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, Near Field Communication (NFC), or other technologies. The decoder can be used to execute the steps of any of the sorting methods provided in the above-described sorting method embodiments. The display unit is used to form a visually visible image and can be a display screen, projection device, or virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the communication device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the communication device, or external keyboards, touchpads, or mice, etc.

[0137] Those skilled in the art will understand that Figure 11 and Figure 12 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the decoder and communication device to which the present application is applied. Specific decoders and communication devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0138] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps of any of the methods described in the above-described sorting method embodiments.

[0139] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps of any of the methods described in the sorting method embodiments above.

[0140] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0141] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0142] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0143] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A sorting method, characterized in that, The method is applied to a decoder, and the method includes: The sub-path sequence corresponding to each main path is determined based on the number of information bits M in parallel decoding and the number of frozen bits P in each decoding step; P∈[0,M). , The value is a non-negative integer; the frozen bit is the information bit that has a fixed path. Determine the metric value of each sub-path in the sub-path sequence, and use the metric values ​​of each sub-path in the sub-path sequence as a sequence to be sorted; Based on the total amount of the metrics in the L sequences to be sorted, a sorting network is determined, and the sorting network is used to sort the metrics in the L sequences to be sorted to obtain the L smallest metrics. The sorting network includes MP sorting layers, which are used to sort each of the metrics and filter out half of the data in descending order.

2. The method according to claim 1, characterized in that, When P∈[0, M-1], the sorting layer of the first level is composed of several parallel first sorting modules. The first sorting module is used to sort and filter the input T elements and output the smallest T / 2 elements in an increasing sequence. Each sorting layer after the first level is composed of a parallel second sorting module, wherein the second sorting module is used to sort a bitonic sequence of length T and finally output the smallest T / 2 elements as a bitonic sequence. The number of second sorting modules in the second-level sorting layer is half the number of first sorting modules in the first-level sorting layer; The number of the second sorting modules in each sorting layer after the second level is half the number of the second sorting modules in the previous level sorting layer.

3. The method according to claim 2, characterized in that, When P=M-1, the sorting network has only one sorting layer, and the sorting layer consists of only one second sorting module.

4. The method according to claim 2, characterized in that, If the number of parallel second sorting modules in the sorting layer at level H is greater than or equal to 4, then the sorting layer at level H and the sorting layer at the next level are connected through a sequence conversion layer; where H≥2; The sequence conversion layer consists of multiple parallel sequence conversion modules, which are used to convert the elements of a bitonic sequence of length T / 2 into a monotonically increasing sequence output. The number of sequence conversion modules is the same as the number of the second sorting modules in the sorting layer of level H.

5. The method according to claim 3, characterized in that, When the number of parallel second sorting modules in the sorting layer at level H is 2, the sorting layer at level H is connected to the sorting layer at the next level through a bubble layer; H≥2; The bubbling layer includes two parallel bubbling modules, which are used to convert a sequence of length T / 2 into a monotonically increasing sequence output.

6. The method according to any one of claims 2-5, characterized in that, The number of the first sorting modules running in parallel is the ratio of the total number of the metrics to T, where T=16.

7. A sorting device, characterized in that, The device includes a sequence determination module and a sorting module, wherein: The sequence determination module is used to determine the sub-path sequence corresponding to each main path based on the number of information bits M and the number of frozen bits P; P∈[0,M). , The value is a non-negative integer; the frozen bit is the information bit that has a fixed path. The sequence determination module is further configured to determine the metric value of each sub-path in the sub-path sequence, and use the metric values ​​of each sub-path in the sub-path sequence as a sequence to be sorted; The sorting module is used to determine a sorting network based on the total amount of the metric values ​​in the L sequences to be sorted, and to use the sorting network to sort the metric values ​​in the L sequences to be sorted to obtain the L smallest metric values. The sorting network includes MP sorting layers, which are used to sort each of the metrics and filter out half of the data in descending order.

8. A decoder, characterized in that, The decoder includes multiple hardware sub-units, a sorting unit, a metric determination unit, and a network determination unit, wherein: The metric determination unit is used to determine the sub-path sequence corresponding to each main path based on the number of information bits M and the number of frozen bits P; P∈[0,M). , The value is a non-negative integer; the frozen bit is the information bit that has a fixed path. The metric value determination unit is further configured to determine the metric value of each sub-path in the sub-path sequence, and use the metric values ​​of each sub-path in the sub-path sequence as a sequence to be sorted; The network determining unit is used to determine the network structure table corresponding to the sorting network based on the total amount of the metrics in the L sequences to be sorted. The network structure table represents the type, quantity, and connection relationship of each hardware sub-unit constituting the sorting network. The sorting unit is used to sort the metric values ​​in the L sequences to be sorted based on the sorting network indicated by the network structure table, so as to obtain the L smallest metric values. The sorting network includes MP sorting layers, which are used to sort the metric values ​​based on their size and filter out the largest half.

9. A communication device, characterized in that, The device includes the decoder as described in claim 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

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