High-resolution tdc system based on complementary blind mechanism and time interval measurement method
By employing a dual-chip system architecture and modulo operation fusion technology, the contradiction between resolution, bandwidth, and cost in existing TDC systems has been resolved, achieving high-precision and high-throughput time interval measurement while reducing hardware costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HEFEI LIANGXIN TECH CO LTD
- Filing Date
- 2025-10-13
- Publication Date
- 2026-05-22
AI Technical Summary
Existing TDC systems struggle to simultaneously achieve high resolution, high data bandwidth, high integration, and reasonable cost, limiting their widespread adoption in applications such as quantum communication.
The system adopts a dual-chip system architecture. The first processing chip uses an FPGA chip for high-speed coarse-grained sampling, while the second processing chip uses an ASIC chip dedicated to time measurement tasks for precise blind filling. The measurement results of the two are fused by modulo operation to achieve high-precision time interval measurement.
It achieves high-resolution (1~2ps) time interval measurement, improves data bandwidth and reduces system cost, while maintaining high performance and economy.
Smart Images
Figure CN121325545B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to TDC systems, and more specifically to a high-resolution TDC system based on a blind spot compensation mechanism and a time interval measurement method. Background Technology
[0002] Time control units (TDCs) are indispensable core components in the field of high-precision time interval measurement, and their performance directly determines the time synchronization effect of quantum communication systems. Currently, mainstream solutions mainly fall into two categories: FPGA-based TDCs and dedicated ASIC-based TDCs, each with its own distinct advantages and bottlenecks.
[0003] FPGA-based time-of-conversion (TDC) solutions are widely used, typically employing dedicated carry chains or register-based sampling circuits within the chip to construct delay lines or perform time-of-conversion sampling. They offer advantages such as high data throughput and ease of integration, and are commonly used to build System-on-Chip (SoC). However, due to limitations in manufacturing processes, cell delays, and wiring delays, they suffer from instability, calibration difficulties, and high logic resource requirements. Their resolution is typically limited to the tens to hundreds of picosecond range, failing to meet the urgent need for picosecond-level accuracy in applications such as quantum communication. To improve resolution, existing technologies employ multi-channel SerDes (Multi-Gigabit Serializer / Deserializer) interleaved sampling, but this method significantly increases hardware resource overhead and system cost.
[0004] On the other hand, while dedicated ASIC-based TDCs can achieve high single-scan measurement resolution (up to 1-2 ps), they face inherent problems such as high cost and severely limited output bandwidth. The extremely high design and fabrication costs of such chips limit their application in large-scale or cost-sensitive scenarios. Furthermore, their measurement mechanism results in a long dead time, and the use of low-speed serial interfaces (such as SPI) for data transmission severely limits system data throughput, making them unsuitable for continuous acquisition of high-speed, high-frequency signals.
[0005] In summary, no high-performance TDC solution has yet emerged in the current technology that can simultaneously achieve high resolution, high data bandwidth, high integration, and reasonable cost. This has become a key bottleneck restricting the development of many cutting-edge technologies. Summary of the Invention
[0006] (a) Technical problems to be solved
[0007] In view of the above-mentioned shortcomings of the existing technology, the present invention provides a high-resolution TDC system and time interval measurement method based on the blind spot compensation mechanism, which can effectively overcome the shortcomings of the existing technology in that it does not have a high-performance TDC solution that simultaneously takes into account high resolution, high data bandwidth, high integration and reasonable cost.
[0008] (II) Technical Solution
[0009] To achieve the above objectives, the present invention provides the following technical solution:
[0010] A high-resolution TDC system based on a blind spot compensation mechanism includes a signal input interface and a first processing chip and a second processing chip connected in parallel to the signal input interface.
[0011] The signal input interface receives the start and stop signals of the time interval to be measured, and synchronously distributes the analog signal to be measured to the first processing chip and the second processing chip.
[0012] The first processing chip, as the main processing channel, is responsible for high-speed coarse-grained sampling of the analog signal under test, determining the blind zone location of the time interval, providing coarse delay measurement values, and calculating with the fine time measurement values sent by the second processing chip to obtain high-precision time interval measurement results.
[0013] The second processing chip, as an auxiliary processing channel, is responsible for precisely filling the blind spots determined by the first processing chip, performing fine-grained sampling of the analog signal under test, accurately measuring high-resolution fine time measurements within the blind spots, and sending them to the first processing chip.
[0014] Preferably, the first processing chip includes a SerDes unit, a data processing logic unit, and an output unit connected in sequence;
[0015] The SerDes unit performs high-speed coarse-grained sampling of the analog signal under test, determines the location of the dead zone where the time interval is located, and provides coarse delay measurement values, i.e., coarse delay information;
[0016] The data processing logic unit receives the coarse delay measurement value sent by the SerDes unit and the fine time measurement value sent by the second processing chip. It extracts the fine time residual in the blind zone by performing a modulo operation on the fine time measurement value and fuses it with the coarse delay measurement value to obtain a high-precision time interval measurement result.
[0017] The output unit receives the time interval measurement results sent by the data processing logic unit and outputs them.
[0018] Among them, fine time residuals represent fine time located within the blind zone.
[0019] Preferably, the first processing chip is an FPGA chip, which leverages its advantages of high precision and high data throughput. The SerDes unit, data processing logic unit, and output unit are connected sequentially through the FPGA's internal high-speed bus.
[0020] The SerDes unit has a first resolution of 100~1000ps, and the output unit is an external interface or internal memory.
[0021] Preferably, the second processing chip adopts an ASIC chip specifically designed for time measurement tasks, providing fine time measurement capabilities. The second processing chip can accurately measure high-resolution fine time measurement values within the blind zone, and detect high-precision fine delay information with low power consumption.
[0022] The second processing chip has a higher resolution than the first resolution, which is 1~10ps.
[0023] The time interval measurement method based on the blind spot mechanism includes the following steps:
[0024] S1, Signal input interface receives the analog signal to be tested;
[0025] S2, the signal input interface synchronously distributes the analog signal to be tested to the first processing chip and the second processing chip, triggering the two chips to perform time interval measurements in parallel and independently;
[0026] S3. The first processing chip performs high-speed coarse-grained sampling of the analog signal under test through the SerDes unit to determine the location of the blind zone where the time interval is located, and sends the coarse delay measurement value T (coarse delay) reflecting the blind zone number to the data processing logic unit.
[0027] S4. The second processing chip performs precise blind filling for the blind zone determined by the SerDes unit, performs fine-grained sampling of the analog signal under test, accurately measures the high-resolution fine time measurement value T (fine time) within the blind zone, and sends it to the data processing logic unit.
[0028] S5. The data processing logic unit of the first processing chip receives the coarse delay measurement value T and the fine time measurement value T, and extracts the fine time residual T in the blind zone by performing a modulo operation on the fine time measurement value T.
[0029] S6. The data processing logic unit performs fusion calculation on the fine time residual T and the coarse delay measurement value T to obtain a high-precision time interval measurement result T, and sends it to the output unit.
[0030] S7. The output unit of the first processing chip outputs the time interval measurement result T(result);
[0031] The coarse delay measurement T is an integer multiple of the first resolution d1 of the SerDes unit, and the fine time measurement T is an integer multiple of the second resolution d2 of the second processing chip.
[0032] Preferably, the data processing logic unit of the first processing chip in S5 receives the coarse delay measurement value T and the fine time measurement value T, and extracts the fine time residual T within the dead zone by performing a modulo operation on the fine time measurement value T, including:
[0033] The fine time measurement value T is moduloed using the following formula to extract the fine time residual T (fine delay) within the blind zone:
[0034] T(fine delay)=T(fine time)%d1;
[0035] Here, % represents the modulo operation.
[0036] Preferably, the data processing logic unit in S6 performs a fusion calculation on the fine time residual T and the coarse delay measurement T to obtain a high-precision time interval measurement result T, and sends it to the output unit, including:
[0037] The fine time residual T and the coarse delay measurement T are fused together using the following formula to obtain the high-precision time interval measurement result T(result):
[0038] T(result)=T(coarse delay)+T(fine delay).
[0039] (III) Beneficial Effects
[0040] Compared with the prior art, the high-resolution TDC system and time interval measurement method based on the blind spot compensation mechanism provided by the present invention have the following advantages:
[0041] 1) High-resolution data acquisition is achieved, and the resolution of the final time interval measurement result can reach the level of a dedicated TDC chip (e.g., 1~2ps). At the same time, the overall measurement accuracy benefits from the high precision characteristics of the FPGA chip and the high resolution capability of the dedicated ASIC chip, achieving a balance between high precision and high resolution.
[0042] 2) High-bandwidth data acquisition is achieved. Since the FPGA chip serves as the main processing channel, it ensures high data throughput. The dedicated ASIC chip only needs to provide relevant fine delay information, which significantly reduces the amount of data. Through optimization processing such as modulo operation, the overall output bandwidth of the system is much higher than that of the solution that uses a dedicated ASIC chip alone.
[0043] 3) While maintaining high performance, the system cost is significantly reduced. There is no need to use resource-intensive solutions such as multi-channel FPGA interleaved sampling to improve resolution. Only one dedicated ASIC chip needs to be added, which greatly saves hardware costs and power consumption and improves the economy and feasibility of the solution. Attached Figure Description
[0044] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.
[0045] Figure 1 This is a schematic diagram of the system of the present invention;
[0046] Figure 2 This is a schematic diagram of the process of the present invention. Detailed Implementation
[0047] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.
[0048] The following describes the specific functional modules of the high-resolution TDC system based on the blind spot compensation mechanism provided by this invention, using concrete examples (such as...). Figure 1 As shown in the figure, and in terms of technical effects, the system functional module includes a signal input interface, and a first processing chip and a second processing chip connected in parallel to the signal input interface;
[0049] The signal input interface receives the start and stop signals of the time interval to be measured, and synchronously distributes the analog signal to be measured to the first processing chip and the second processing chip.
[0050] The first processing chip, as the main processing channel, is responsible for high-speed coarse-grained sampling of the analog signal under test, determining the blind zone location of the time interval, providing coarse delay measurement values, and calculating with the fine time measurement values sent by the second processing chip to obtain high-precision time interval measurement results.
[0051] The second processing chip, as an auxiliary processing channel, is responsible for precisely filling the blind spots determined by the first processing chip, performing fine-grained sampling of the analog signal under test, accurately measuring high-resolution fine time measurements within the blind spots, and sending them to the first processing chip.
[0052] I. First Processing Chip
[0053] The first processing chip includes a SerDes unit, a data processing logic unit, and an output unit connected in sequence.
[0054] The SerDes unit performs high-speed coarse-grained sampling of the analog signal under test, determines the location of the dead zone where the time interval is located, and provides coarse delay measurement values, i.e., coarse delay information;
[0055] The data processing logic unit receives the coarse delay measurement value sent by the SerDes unit and the fine time measurement value sent by the second processing chip. It extracts the fine time residual in the blind zone by performing a modulo operation on the fine time measurement value and fuses it with the coarse delay measurement value to obtain a high-precision time interval measurement result.
[0056] The output unit receives the time interval measurement results sent by the data processing logic unit and outputs them.
[0057] Among them, fine time residuals represent fine time located within the blind zone.
[0058] In the technical solution of this application, the first processing chip adopts an FPGA chip, which leverages its advantages of high precision and high data throughput. The SerDes unit, data processing logic unit, and output unit are connected sequentially through the high-speed bus inside the FPGA.
[0059] The SerDes unit has a first resolution of 100~1000ps, which can be 200ps in the technical solution of this application. The output unit is an external interface or an internal memory.
[0060] II. Second Processing Chip
[0061] The second processing chip uses an ASIC chip specifically designed for time measurement tasks, providing fine time measurement capabilities. The second processing chip can accurately measure high-resolution fine time measurement values within the blind zone, and detect high-precision fine delay information with low power consumption.
[0062] The second processing chip has a second resolution that is higher than the first resolution. The second resolution is 1~10ps, and 1ps can be used in the technical solution of this application.
[0063] The above technical solution creatively proposes a dual-chip system processing architecture to address the difficulty of balancing high resolution, high data bandwidth, and reasonable cost in existing technologies. The first processing chip serves as the main processing channel, responsible for measuring coarse delay values and determining the blind zone number. The second processing chip serves as the auxiliary processing channel, responsible for precisely filling in the blind zones and accurately measuring high-resolution fine time measurements within them. Specifically, the first processing chip uses an FPGA chip, leveraging its high precision and high data throughput capabilities; the second processing chip uses an ASIC chip specifically optimized for time measurement tasks, providing fine time measurement capabilities. The two chips complement each other in terms of functionality and performance.
[0064] To address the issue of low output bandwidth in the second processing chip, this invention optimizes its output data content by omitting high-order bits and retaining only the low-order bits containing precise delay information. The omitted high-order bits represent coarse delay information, which is synchronously provided by the first processing chip, which has high data throughput capabilities, and is paired with the data. This significantly reduces the amount of data transmitted between the second and first processing chips, fundamentally overcoming the communication bandwidth bottleneck and enabling the system to maintain ultra-high resolution while achieving high data throughput.
[0065] Based on the aforementioned high-resolution TDC system based on a blind spot compensation mechanism, this application also discloses a time interval measurement method based on a blind spot compensation mechanism, such as... Figure 2 As shown, it includes the following steps:
[0066] S1, Signal input interface receives the analog signal to be tested;
[0067] S2, the signal input interface synchronously distributes the analog signal to be tested to the first processing chip and the second processing chip, triggering the two chips to perform time interval measurements in parallel and independently;
[0068] S3. The first processing chip performs high-speed coarse-grained sampling of the analog signal under test through the SerDes unit to determine the location of the blind zone where the time interval is located, and sends the coarse delay measurement value T (coarse delay) reflecting the blind zone number to the data processing logic unit.
[0069] S4. The second processing chip performs precise blind filling for the blind zone determined by the SerDes unit, performs fine-grained sampling of the analog signal under test, accurately measures the high-resolution fine time measurement value T (fine time) within the blind zone, and sends it to the data processing logic unit.
[0070] S5. The data processing logic unit of the first processing chip receives the coarse delay measurement value T and the fine time measurement value T, and extracts the fine time residual T in the blind zone by performing a modulo operation on the fine time measurement value T.
[0071] S6. The data processing logic unit performs fusion calculation on the fine time residual T and the coarse delay measurement value T to obtain a high-precision time interval measurement result T, and sends it to the output unit.
[0072] S7. The output unit of the first processing chip outputs the time interval measurement result T(result);
[0073] The coarse delay measurement T is an integer multiple of the first resolution d1 of the SerDes unit, and the fine time measurement T is an integer multiple of the second resolution d2 of the second processing chip.
[0074] Specifically, the data processing logic unit of the first processing chip in S5 receives the coarse delay measurement value T and the fine time measurement value T, and extracts the fine time residual T within the dead zone by performing a modulo operation on the fine time measurement value T, including:
[0075] The fine time measurement value T is moduloed using the following formula to extract the fine time residual T (fine delay) within the blind zone:
[0076] T(fine delay)=T(fine time)%d1;
[0077] Here, % represents the modulo operation.
[0078] Specifically, the data processing logic unit in S6 performs a fusion calculation on the fine time residual T and the coarse delay measurement T to obtain a high-precision time interval measurement result T, which is then sent to the output unit, including:
[0079] The fine time residual T and the coarse delay measurement T are fused together using the following formula to obtain the high-precision time interval measurement result T(result):
[0080] T(result)=T(coarse delay)+T(fine delay).
[0081] The aforementioned technical solution enables a high-bandwidth FPGA chip and an ultra-high-resolution dedicated ASIC chip to measure the same analog signal under test in parallel and independently. It also introduces "modulo operation" as a key data processing algorithm for the first time, accurately extracting the fine time residual relative to the FPGA sampling period from the fine time measurement value obtained by the dedicated ASIC chip. This effectively solves the alignment and fusion problem of two different resolution data sets, which are then fused with the coarse delay measurement value from the FPGA. This solution breaks through the traditional single-chip TDC technical route, effectively solving the problem of balancing high resolution, high data bandwidth, high integration, and reasonable cost. It replaces the traditional hardware resource stacking solution, achieving a leapfrog improvement in TDC system performance.
[0082] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A time interval measurement method based on a blind spot compensation mechanism, executed by a high-resolution TDC system based on the blind spot compensation mechanism, the system comprising a signal input interface, and a first processing chip and a second processing chip connected in parallel to the signal input interface, characterized in that: The method includes the following steps: S1, Signal input interface receives the analog signal to be tested; S2, the signal input interface synchronously distributes the analog signal to be tested to the first processing chip and the second processing chip, triggering the two chips to perform time interval measurements in parallel and independently; S3. The first processing chip performs high-speed coarse-grained sampling of the analog signal under test through the SerDes unit, determines the location of the blind zone where the time interval is located, and sends the coarse delay measurement value T (coarsedelay) reflecting the blind zone number to the data processing logic unit. S4. The second processing chip performs precise blind filling for the blind zone determined by the SerDes unit, performs fine-grained sampling of the analog signal under test, accurately measures the high-resolution fine time measurement value T (fine time) within the blind zone, and sends it to the data processing logic unit. S5. The data processing logic unit of the first processing chip receives the coarse delay measurement value T and the fine time measurement value T, and extracts the fine time residual T within the dead zone by performing a modulo operation on the fine time measurement value T, including: The fine time measurement value T is moduloed using the following formula to extract the fine time residual T (fine delay) within the blind zone: T(fine delay)=T(fine time)%d1; Where % represents the modulo operation; S6. The data processing logic unit fuses the fine time residual T (fine delay) and the coarse delay measurement value T (coarse delay elay) to obtain a high-precision time interval measurement result T (result), and sends it to the output unit, including: The fine time residual T and the coarse delay measurement T are fused together using the following formula to obtain the high-precision time interval measurement result T(result): T(result)=T(coarse delay)+T(fine delay); S7. The output unit of the first processing chip outputs the time interval measurement result T(result); The coarse delay measurement T is an integer multiple of the first resolution d1 of the SerDes unit, and the fine time measurement T is an integer multiple of the second resolution d2 of the second processing chip.
2. A high-resolution TDC system based on a blind spot compensation mechanism, used to execute the time interval measurement method based on a blind spot compensation mechanism as described in claim 1, characterized in that: It includes a signal input interface, and a first processing chip and a second processing chip connected in parallel to the signal input interface; The signal input interface receives the start and stop signals of the time interval to be measured, and synchronously distributes the analog signal to be measured to the first processing chip and the second processing chip. The first processing chip, as the main processing channel, is responsible for high-speed coarse-grained sampling of the analog signal under test, determining the blind zone location of the time interval, providing coarse delay measurement values, and calculating with the fine time measurement values sent by the second processing chip to obtain high-precision time interval measurement results. The second processing chip, as an auxiliary processing channel, is responsible for precisely filling the blind spots determined by the first processing chip, performing fine-grained sampling of the analog signal under test, accurately measuring high-resolution fine time measurements within the blind spots, and sending them to the first processing chip.
3. The high-resolution TDC system based on the blind spot compensation mechanism according to claim 2, characterized in that: The first processing chip includes a SerDes unit, a data processing logic unit, and an output unit connected in sequence. The SerDes unit performs high-speed coarse-grained sampling of the analog signal under test, determines the location of the dead zone where the time interval is located, and provides coarse delay measurement values, i.e., coarse delay information; The data processing logic unit receives the coarse delay measurement value sent by the SerDes unit and the fine time measurement value sent by the second processing chip. It extracts the fine time residual in the blind zone by performing a modulo operation on the fine time measurement value and fuses it with the coarse delay measurement value to obtain a high-precision time interval measurement result. The output unit receives the time interval measurement results sent by the data processing logic unit and outputs them. Among them, fine time residuals represent fine time located within the blind zone.
4. The high-resolution TDC system based on the blind spot compensation mechanism according to claim 3, characterized in that: The first processing chip uses an FPGA chip, leveraging its advantages of high precision and high data throughput. The SerDes unit, data processing logic unit, and output unit are connected sequentially through the FPGA's internal high-speed bus. The SerDes unit has a first resolution of 100~1000ps, and the output unit is an external interface or internal memory.
5. The high-resolution TDC system based on the blind spot compensation mechanism according to claim 4, characterized in that: The second processing chip uses an ASIC chip specifically designed for time measurement tasks, providing fine time measurement capabilities. The second processing chip can accurately measure high-resolution fine time measurement values within the blind zone, and detect high-precision fine delay information with low power consumption. The second processing chip has a higher resolution than the first resolution, which is 1~10ps.