Logic operation method and device based on ferroelectric transistor and electronic equipment

Abstract

The application relates to the technical field of semiconductors, and provides a logic operation method and device based on a ferroelectric transistor and electronic equipment, the logic operation method based on the ferroelectric transistor comprises the following steps: obtaining an operation instruction to be executed, the operation instruction comprising input variables and the type of the logic operation to be executed; determining an assignment relationship between the input variables and logic variables of a target logic gate according to the working principle of the target logic gate and the type of the logic operation to be executed, wherein the target logic gate comprises at least one ferroelectric transistor; assigning the values of the input variables to the logic variables according to the assignment relationship; controlling the ferroelectric transistor to execute the logic operation according to the logic variables, and storing the result of the logic operation in situ by using the polarization state of the ferroelectric transistor. The method realizes the integration of storage and calculation based on the Boolean logic gate of the ferroelectric transistor, breaks through the limitations of the storage wall and the power consumption wall, and improves the flexibility of the Boolean logic gate of the ferroelectric transistor when performing the logic operation.

Description

Technical Field

[0001] This invention relates to the field of computer science and technology, and in particular to a logic operation method, apparatus and electronic device based on ferroelectric transistors. Background Technology

[0002] The development of data-intensive applications such as the Internet of Things, big data, and artificial intelligence has brought about enormous demands for computing power and storage. Because the computing and storage units of von Neumann architecture computers are separate, frequent memory accesses lead to severe latency and power consumption, forming the von Neumann bottleneck and limiting system computing power and energy efficiency. To address this issue, various new devices and architectures have been explored. One highly promising approach is in-memory computing technology, which directly utilizes memory for data processing or computation, fundamentally avoiding frequent access between computing and storage. To fully realize the potential of in-memory computing, multi-functional modules need to be implemented in each processing unit at the device level, enabling parallel execution of various computing tasks. Reconfigurable in-memory computing devices can store information and switch functions according to external operating instructions and scenario requirements, exhibiting low latency and low power consumption. They are the cornerstone of building a parallel computing paradigm at the hardware level and are of great significance for breaking through the "memory wall."

[0003] The application of novel non-volatile memories in overcoming the von Neumann bottleneck and realizing in-memory computing has received widespread research and attention. Among them, ferroelectric transistors, as three-terminal devices, have the structural advantage of integrating storage and logic functions, and have the characteristics of being fast, low-power, and non-volatile, showing great application potential in future in-memory computing chips.

[0004] However, most current in-memory computing devices based on ferroelectric transistors can only perform a fixed and limited number of operations, which limits the chip's functional flexibility. They are only suitable for edge AI scenarios where functional flexibility is not a primary concern and low power consumption is paramount, rather than cloud AI scenarios that demand high computing power, energy efficiency, and flexibility simultaneously. With the continuous emergence of high-precision, large-scale AI models, the computing power required for training and inference in cloud AI scenarios such as data centers is increasing daily. Therefore, exploring methods to simultaneously improve the energy efficiency and flexibility of chips is of great value. Summary of the Invention

[0005] This invention provides a logic operation method, apparatus, and electronic device based on ferroelectric transistors to solve the problem of separation between storage units and computing units in von Neumann computers, thereby overcoming the limitations of the memory wall and power consumption wall, reducing computing latency and power consumption, and further improving the richness and flexibility of logic functions to meet the high requirements of application scenarios for computing power, energy efficiency, and flexibility.

[0006] This invention provides a logic operation method based on ferroelectric transistors, comprising: acquiring an operation instruction to be executed, wherein the operation instruction includes input variables and the type of logic operation to be executed; determining the assignment relationship between the input variables and the logic variables of the target logic gate according to the working principle of the target logic gate and the type of logic operation to be executed, wherein the target logic gate includes at least one ferroelectric transistor, the logic variables include the initial threshold voltage state of the ferroelectric transistor and the voltage at the input terminal of the ferroelectric transistor, the voltage at the input terminal including the gate voltage and source voltage or the gate voltage and drain voltage; assigning the value of the input variable to the logic variable according to the assignment relationship; controlling the ferroelectric transistor to perform the logic operation according to the logic variable, and storing the result of the logic operation in situ using the polarization state of the ferroelectric transistor.

[0007] According to the present invention, a logic operation method based on ferroelectric transistors is characterized in that determining the assignment relationship between the input variable and the logic variable of the target logic gate based on the working principle of the target logic gate and the type of the logic operation to be performed includes: determining the assignment relationship between the input variable and the logic variable according to a pre-established assignment relationship table associated with the target logic gate, wherein the assignment relationship table records the assignment relationship between the input variable and the logic variable corresponding to each logic operation type covered by the target logic gate.

[0008] According to the present invention, a logic operation method based on ferroelectric transistors is characterized in that the target logic gate includes a first logic gate composed of an N-type ferroelectric transistor, and the logic operation types covered by the first logic gate include operations with output of 0, operations with output of 1, NOT operations, OR operations, AND operations, NAND operations, NOR operations, inverse implication operations, implication operations, non-implication operations, and inverse non-implication operations.

[0009] According to the present invention, a logic operation method based on ferroelectric transistors is characterized in that the first logic gate further includes a depletion-type N-type field-effect transistor or a resistor located in the saturation region, wherein the gate and source of the N-type ferroelectric transistor in the first logic gate are the input terminals, and the drain of the N-type ferroelectric transistor is connected to a resistor or the gate of the depletion-type N-type transistor as the read terminal.

[0010] According to the present invention, a logic operation method based on ferroelectric transistors is characterized in that the target logic gate includes a second logic gate composed of two N-type ferroelectric transistors, wherein the gate and source of the two N-type ferroelectric transistors in the second logic gate are the input terminals, the drains of the two N-type ferroelectric transistors are connected as the read terminals, and the logic operation types covered by the second logic gate include XOR operation and NAND operation.

[0011] According to the present invention, a logic operation method based on ferroelectric transistors is characterized in that the second logic gate further includes a load resistor, the gates and sources of the two N-type ferroelectric transistors in the second logic gate are the input terminals, and the drains of the two N-type ferroelectric transistors are connected to one end of the resistor as the read terminal.

[0012] According to the present invention, a logic operation method based on ferroelectric transistors is characterized in that, after obtaining the operation instruction to be executed for the target logic gate, the method further includes: selecting a logic gate from candidate logic gates whose covered logic operation type includes the type of the logic operation to be executed as the target logic gate.

[0013] The present invention also provides a logic operation device based on a ferroelectric transistor, comprising: an acquisition module configured to acquire an operation instruction to be executed, wherein the operation instruction includes input variables and a type of logic operation to be executed; a determination module configured to determine the assignment relationship between the input variables and the logic variables based on the relationship between the logic variables of a target logic gate and the type of the logic operation to be executed, wherein the target logic gate includes at least one ferroelectric transistor, the logic variables include the initial threshold voltage state of the ferroelectric transistor and the voltage at the input terminal of the ferroelectric transistor, and the voltage at the input terminal includes the gate voltage and the source voltage or the gate voltage and the drain voltage; an assignment module configured to assign the value of the input variable to the logic variable according to the assignment relationship; and an operation module configured to control the ferroelectric transistor to perform a logic operation according to the logic variable, and to store the result of the logic operation in situ using the polarization state of the ferroelectric transistor.

[0014] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the logic operation method based on ferroelectric transistors as described above.

[0015] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the logic operation method based on ferroelectric transistors as described above.

[0016] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the logic operation method based on ferroelectric transistors as described above.

[0017] The present invention provides a logic operation method, apparatus, and electronic device based on ferroelectric transistors. According to the working principle of the target logic gate and the type of logic operation to be performed, the assignment relationship between the input variable and the logic variable of the target logic gate is determined. The value of the input variable is assigned to the logic variable according to the assignment relationship. Then, the ferroelectric transistor is controlled to perform logic operation according to the logic variable, and the result of the logic operation is stored in place by utilizing the polarization state of the ferroelectric transistor, thus realizing a more flexible logic operation process. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0019] Figure 1 This is one of the flowcharts illustrating the logic operation method based on ferroelectric transistors provided by the present invention.

[0020] Figure 2 This is one of the circuit diagrams of Boolean logic gates based on ferroelectric transistors provided by the present invention.

[0021] Figure 3 This is the second circuit diagram of the Boolean logic gate based on ferroelectric transistors provided by the present invention.

[0022] Figure 4 This is the third circuit diagram of the Boolean logic gate based on ferroelectric transistors provided by this invention.

[0023] Figure 5 This is the fourth circuit diagram of the Boolean logic gate based on ferroelectric transistors provided by this invention.

[0024] Figure 6 This is the fifth circuit diagram of the Boolean logic gate based on ferroelectric transistors provided by the present invention.

[0025] Figure 7 This is a schematic diagram of the structure of the logic operation device based on ferroelectric transistors provided by the present invention.

[0026] Figure 8 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0028] The following is combined with Figures 1-8 The present invention describes a logic operation method, apparatus, and electronic device based on ferroelectric transistors.

[0029] Figure 1 This is one of the flowcharts illustrating the logic operation method based on ferroelectric transistors provided in this embodiment of the invention, such as... Figure 1 As shown, the method includes:

[0030] Step 101: Obtain the operation instructions to be executed.

[0031] In this embodiment, the operation instruction includes input variables and the type of logical operation to be performed. The input variables are the objects of the logical operation. The types of logical operations can include operations that output 0, operations that output 1, NOT, OR, AND, NAND, NOR, RIMP, IMP, NIMP, RNIMP, XOR, and XNOR.

[0032] Step 102: Based on the working principle of the target logic gate and the type of logic operation to be performed, determine the assignment relationship between the input variables and the logic variables of the target logic gate.

[0033] In this embodiment, the target logic gate includes at least one ferroelectric transistor. The logic variables include the initial threshold voltage state of the ferroelectric transistor and the voltage at the input terminal of the ferroelectric transistor. The voltage at the input terminal includes the gate voltage and source voltage or the gate voltage and drain voltage. Based on the working principle of the target logic gate, the polarization state of the ferroelectric transistor under different logic variables can be deduced, thereby determining the assignment relationship between the input variables and the logic variables of the target logic gate when performing different logic operations.

[0034] The ferroelectric materials for ferroelectric transistors can be: SBT, PZT, PTO, PMN-PT and other ferroelectric perovskite oxides; , - Two-dimensional ferroelectric materials; Ferroelectric III-V nitrides such as N and hafnium oxide-based ferroelectric materials (whose doping elements include, but are not limited to, Zr, Si, La, Y, Gd, Al, etc.).

[0035] In terms of specific device structure, ferroelectric transistors can be metal-ferroelectric material-semiconductor structure transistors (MFS-FET), metal-ferroelectric material-gate oxide-semiconductor structure transistors (MFIS-FET), or metal-ferroelectric material-metal-gate oxide-semiconductor structure transistors (MFMIS-FET).

[0036] Ferroelectric transistors can be of various types, including metal-oxide-semiconductor field-effect transistors (MOSFETs), junctionless transistors, thin-film transistors (TFTs), two-dimensional transistors, nanowire transistors, fin field-effect transistors (FinFETs), or gate-all-around field-effect transistors (GAA FETs).

[0037] The gate-source or gate-drain voltage of a ferroelectric transistor can reverse the polarization of the ferroelectric layer, thus affecting its threshold voltage. Furthermore, due to the non-volatility of ferroelectric polarization, the threshold voltage state of a ferroelectric transistor can be maintained after power is turned off. Applying a negative voltage to the source or drain and a positive voltage to the gate both result in a low threshold voltage state with high channel conductivity; conversely, applying a positive voltage to the source or drain and a negative voltage to the gate both result in a high threshold voltage state with low channel conductivity. When the same voltage is applied to both the gate and source, the threshold voltage state of the ferroelectric transistor remains unchanged.

[0038] Based on the above principles, the ferroelectric transistor can first be initialized by applying a positive or negative voltage pulse to the gate, placing it in a low or high threshold voltage state, corresponding to logic variable I=1 or 0. Next, a programming operation is performed by simultaneously applying voltage pulses to the gate (A) and source (B) of the ferroelectric transistor. A positive pulse corresponds to logic "1", and a negative pulse corresponds to logic "0". Thus, depending on the logic variables I, A, and B, the ferroelectric transistor will be in different threshold voltage states. For example, when I=1, only when a negative pulse is applied to the gate and a positive pulse to the source can the polarization flip, placing the ferroelectric transistor in a high threshold voltage state; otherwise, the ferroelectric polarization does not flip, and the ferroelectric transistor remains in a low threshold voltage state. In this way, the ferroelectric transistor can complete the logic operation in two steps and store the result in place in the ferroelectric polarization, exhibiting in-memory computing characteristics without requiring additional storage units or data transfer to storage units. When the operation result needs to be read, only the operating voltage needs to be applied, and the channel conductance of the ferroelectric transistor can be read. Furthermore, by assigning different values ​​to the logic variables (I, A, B), different Boolean logic operations can be performed between the input variables p and q, thus exhibiting reconfigurability. It is important to note that, depending on the performance of the ferroelectric transistor, the pulse forms corresponding to logic variables A and B are different; for example, logic "1" and "0" can represent a positive pulse and zero voltage, respectively. In addition to the gate and source voltages serving as logic variables A and B, the gate and drain voltages can also be used as A and B, respectively.

[0039] Step 103: Assign the values ​​of the input variables to the logical variables according to the assignment relationship.

[0040] In this embodiment, the values ​​of input variables can be assigned to logical variables according to the assignment relationship. For example, I is assigned the value 1, p is assigned the value of A, and q is assigned the value of B.

[0041] Step 104: Control the ferroelectric transistor to perform logical operations according to the logical variables, and use the polarization state of the ferroelectric transistor to store the results of the logical operations in situ.

[0042] Specifically, a positive or negative voltage pulse is applied to the gate to set the initial threshold voltage state of the ferroelectric transistor according to the initial state (1 or 0) of the desired logic variable I. Simultaneously, voltage pulses are applied to the gate and source of the ferroelectric transistor; these pulses represent logic variables A and B. A positive pulse typically represents logic "1," while a negative pulse or zero voltage represents logic "0." The threshold voltage state of the ferroelectric transistor changes according to the input logic variables A and B, and the initialization state I, thereby implementing different Boolean logic operations. The polarization state of the ferroelectric transistor is non-volatile, so once set, it retains its state even when power is off. This polarization state directly corresponds to the result of the logic operation, achieving in-situ storage.

[0043] Furthermore, when it is necessary to read the result of the operation, by applying the operating voltage and measuring the channel conductance of the ferroelectric transistor or the voltage at the read terminal, it is possible to determine whether the threshold voltage state of the ferroelectric transistor is high or low, thereby reading the result of the logic operation (0 or 1).

[0044] The present invention provides a logic operation method based on ferroelectric transistors, which implements a reconfigurable Boolean logic gate based on ferroelectric transistors. It utilizes ferroelectric transistors to realize various Boolean logic functions and in-situ storage of operation results. This logic gate has the characteristics of in-memory computing and can be reconfigured between different functions, providing a new solution for realizing an in-memory computing chip with low power consumption, simple circuit and rich functions.

[0045] In some optional implementations, the assignment relationship between input variables and logical variables of the target logic gate is determined based on the working principle of the target logic gate and the type of logical operation to be performed. This includes: determining the assignment relationship between input variables and logical variables based on a pre-established assignment relationship table associated with the target logic gate. The assignment relationship table records the assignment relationship between input variables and logical variables corresponding to each type of logical operation covered by the target logic gate. The assignment relationship table can be established through principle analysis or comparison of operation results. Based on the pre-established assignment relationship table, the assignment relationship can be determined more quickly, further improving the efficiency of the operation.

[0046] In some alternative implementations, the target logic gate includes a first logic gate consisting of an N-type ferroelectric transistor. The logic operation types covered by the first logic gate include operations with an output of 0, operations with an output of 1, NOT, OR, AND, NAND, NOR, inverse implication, implication, non-implication, and inverse non-implication.

[0047] like Figure 2 As shown: This logic gate consists of only one N-type ferroelectric transistor (201). The gate (210) and source (220) of the ferroelectric transistor (201) serve as input terminals, and the input voltage signals represent logic variables A and B, respectively. The drain (230) serves as the read terminal, and the read current represents the operation result Y.

[0048] The logical operation process includes two steps:

[0049] (1) Initialization: Apply a positive or negative pulse to the gate (210) of the ferroelectric transistor (201), the source (220) voltage is 0 V, the drain (230) voltage is 0 V or floating, so that the ferroelectric transistor (201) is in a low threshold or high threshold voltage state, and the corresponding initialization logic variable I=1 or 0.

[0050] (2) Programming: Simultaneously apply voltage pulses corresponding to logic variables A and B to the gate (210) and source (220) of the ferroelectric transistor (201), while the drain (230) is left floating. Logic "1" corresponds to a positive pulse, and logic "0" corresponds to a negative pulse or zero voltage. Thus, when AB=10, the ferroelectric transistor (201) is in a low threshold voltage state; when AB=01, the ferroelectric transistor (201) is in a high threshold voltage state; and when AB=00 or 11, the threshold voltage of the ferroelectric transistor (201) remains in its initial state. In this way, the final threshold voltage state of the ferroelectric transistor (201) is determined by I, A, and B, and it has non-volatile characteristics.

[0051] Therefore, after the above two steps, the logical operation is completed and the result is stored in place in the computing unit, i.e., the ferroelectric transistor (201), realizing in-memory computing. When it is necessary to read the result, it is only necessary to apply the operating voltage to the drain (230). V d The gate (210) and source (220) voltages were 0 V, and the source-drain current was measured. I d That's it. When the ferroelectric transistor (201) is in a high threshold voltage state, the current is read. I d Small, when it is in a low threshold voltage state I d Since it is large, the result of the operation can be read as 0 or 1.

[0052] Furthermore, by assigning values ​​to the three logic variables I, A, and B, a single ferroelectric transistor can implement 14 different Boolean logic functions and store the results in place. For example, when (I, A, B) is assigned the value (1, p', q), a NAND operation can be performed between inputs p and q; when (I, A, B) is assigned the value (0, p', q), a NOR operation can be performed between inputs p and q. The variable assignments corresponding to the 14 logic functions are shown in Table 1, where p' represents the negation of p, and q' represents the negation of q.

[0053] Table 1 Figure 2 The table showing the assignment relationships between logic gates

[0054]

[0055] In some alternative implementations, the first logic gate also includes a depletion-type N-type field-effect transistor or resistor located in the saturation region. The gate and source of the N-type ferroelectric transistor in the first logic gate are the input terminals, and the drain of the N-type ferroelectric transistor is connected to a resistor or the gate of the depletion-type N-type transistor as the read terminal.

[0056] like Figure 3As shown, the logic gate includes an N-type ferroelectric transistor (301) and a resistor (302). The gate (310) and source (320) of the ferroelectric transistor (301) are the input terminals, and the input voltage signals represent logic variables A and B. The common terminal (330) of the ferroelectric transistor (301) and the resistor (302) is the read terminal, and its voltage level represents the read result 1 or 0. The other end (340) of the resistor (302) is either floating or connected to a voltage. V dd .

[0057] The operation process also includes two steps: initialization and programming. When reading, a voltage is connected to the other end (340) of the resistor (302). V dd Simultaneously, the voltage at the common terminal (330) of the ferroelectric transistor (301) was tested when the gate (310) and source (320) voltages were 0 V. V out The value of represents whether the result of the operation is 1 or 0.

[0058] like Figure 4 As shown, the logic gate includes an N-type ferroelectric transistor (401) and a depletion-type N-type field-effect transistor (402) located in the saturation region. The gate of the depletion-type N-type transistor (402) is connected to the source and to the drain (420) of the ferroelectric transistor (401). The drain (430) is either floating or has an applied operating voltage. V dd Thus, the depletion-type N-type transistor (402) is in the saturation region, and the channel resistance remains unchanged. The gate (410) and source (440) of the ferroelectric transistor (401) are the input terminals, and the input voltage signal represents the logic variables A and B. The common terminal (420) of the ferroelectric transistor (401) and the depletion-type N-type transistor (402) is the read terminal, and its voltage level represents the read result 1 or 0.

[0059] The logic operation process includes two steps: (1) Initialization: Apply a positive or negative pulse to the gate (410) of the ferroelectric transistor (401), the source (440) voltage is 0 V, and the other terminals are floating, so that the ferroelectric transistor (401) is in a low threshold or high threshold voltage state, and the corresponding logic variable I is initialized to 1 or 0.

[0060] (2) Programming: Simultaneously, voltage pulses corresponding to logic variables A and B are applied to the gate (410) and source (440) of the ferroelectric transistor (401), while the other terminals are left floating. Logic "1" corresponds to a positive pulse, and logic "0" corresponds to a negative pulse or zero voltage. Thus, when AB=10, the ferroelectric transistor (401) is in a low threshold voltage state; when AB=01, the ferroelectric transistor (401) is in a high threshold voltage state; and when AB=00 or 11, the threshold voltage of the ferroelectric transistor (401) remains in its initial state. In this way, the final threshold voltage state of the ferroelectric transistor (401) is determined by I, A, and B. The logic operation is completed and the result is stored in the ferroelectric transistor (401) in place, realizing in-memory computing. When reading the operation result, a voltage is applied to the drain (430) of the depletion-type N-type transistor (402). V dd The gate (410) and source (440) voltages are 0 V, and the voltage at the common terminal (420) is measured. V out That is, when the ferroelectric transistor (401) is in the high threshold voltage state, its channel resistance is large and the voltage division is high, so the output is high and the corresponding operation result is 1; when it is in the low threshold voltage state, the channel resistance is small and the output is low and the corresponding operation result is 0.

[0061] The variable assignments for the 14 logic functions of the logic gate, which includes a depletion-type N-type field-effect transistor or resistor located in the saturation region, are shown in Table 2.

[0062] Table 2 Figure 3 and Figure 4 The table showing the assignment relationships between logic gates.

[0063]

[0064] In some alternative implementations, the target logic gate includes a second logic gate composed of two N-type ferroelectric transistors. The gate and source of the two N-type ferroelectric transistors are the input terminals, and the drains of the two N-type ferroelectric transistors are connected as the read terminals. The logic operation types covered by the second logic gate include XOR operation and NAND operation.

[0065] See Figure 5 The logic gate consists of two N-type ferroelectric transistors (501) and (502). The input voltage signals of the gate (510) and source (520) of the ferroelectric transistor (501) represent logic variables A1 and B1, and the input voltage signals of the gate (540) and source (550) of the ferroelectric transistor (502) represent logic variables A2 and B2. The initial states of the ferroelectric transistors (501) and (502) are I1 and I2, respectively. Their drains (530) are connected and serve as read terminals. The read current represents the operation result Y.

[0066] The calculation process also includes two steps:

[0067] (1) Initialization: Apply positive or negative pulses to the gates (510) and (540) of the two ferroelectric transistors (501) and (502), the source voltages (520) and (550) are 0 V, the common drain voltage (530) is 0 V or floating, and initialize the two ferroelectric transistors (501) and (502), corresponding to the logic variables I1 and I2.

[0068] (2) Programming: Simultaneously apply voltage pulses corresponding to logic variables A1 and B1 to the gate (510) and source (520) of ferroelectric transistor (501), and apply voltage pulses corresponding to logic variables A2 and B2 to the gate (540) and source (550) of ferroelectric transistor (502). At the same time, the common drain (530) is floating or the voltage is 0 V. In this way, the logic operation is completed and the result is stored in the logic unit. When reading, set the voltages of the gates (510) and (540) and sources (520) and (550) of the two ferroelectric transistors (501) and (502) to 0 V, apply the reading voltage to the drain (530) and test the current. The magnitude of the current indicates that the result Y of the logic operation is 1 or 0.

[0069] By assigning different inputs to six logical variables (I1, A1, B1, I2, A2, B2), XNOR or XOR operations can be performed between p and q, and the results are stored in place in the computing unit, as shown in Table 3.

[0070] Table 3 Figure 5 The table showing the assignment relationships between logic gates.

[0071]

[0072] In some alternative implementations, the second logic gate also includes a load resistor, with the gates and sources of the two N-type ferroelectric transistors in the second logic gate serving as input terminals, and the drains of the two N-type ferroelectric transistors connected to one end of the resistor as read terminals.

[0073] This implementation proposes a reconfigurable in-memory Boolean logic gate based on two ferroelectric transistors, capable of performing XNOR and XOR functions. The unit structure is as follows: Figure 6As shown: This logic gate consists of two N-type ferroelectric transistors (601) and (602) and a load resistor (603). The input voltage signals at the gate (610) and source (620) of ferroelectric transistor (601) represent logic variables A1 and B1, and the input voltage signals at the gate (640) and source (650) of ferroelectric transistor (602) represent logic variables A2 and B2. The initial states of ferroelectric transistors (601) and (602) are I1 and I2, respectively. Their drains are connected to one end of resistor (603) and serve as the read terminal (630). The other end (660) of resistor (603) is either floating or connected to the operating voltage. V dd The voltage reading represents the calculation result Y.

[0074] The calculation process includes two steps:

[0075] (1) Initialization: Apply positive or negative pulses to the gates (610) and (640) of the two ferroelectric transistors (601) and (602), the source voltages (620) and (650) are 0 V, and the other terminals are floating, to initialize the two ferroelectric transistors (601) and (602), and the corresponding logic variables I1 and I2.

[0076] (2) Programming: Simultaneously apply voltage pulses corresponding to logic variables A1 and B1 to the gate (610) and source (620) of ferroelectric transistor (601), and apply voltage pulses corresponding to logic variables A2 and B2 to the gate (340) and source (650) of ferroelectric transistor (602). Leave other terminals floating to complete the logic operation and store the result in place. When reading, set the voltages of the gates (610) and (640) and sources (620) and (650) of the two ferroelectric transistors (601) and (602) to 0 V. Apply the reading voltage to the other end (660) of resistor (603) and test the voltage at the reading terminal (630). The voltage magnitude indicates that the result Y of the logic operation is 1 or 0.

[0077] By assigning different inputs to six logical variables (I1, A1, B1, I2, A2, B2), XNOR or XOR operations can be performed between p and q, and the results are stored in place in the computing unit, as shown in Table 4.

[0078] Table 4 Figure 6 The table showing the assignment relationships between logic gates.

[0079]

[0080] In some optional implementations, after obtaining the arithmetic instructions to be executed for the target logic gate, the method further includes: selecting a logic gate from candidate logic gates whose covered logic operation types include the type of logic operation to be executed as the target logic gate. Candidate logic gates may include logic gates composed of a single ferroelectric transistor and logic gates composed of two ferroelectric transistors. Using the initial threshold voltage state of the ferroelectric transistor and the gate and source voltages (or gate and drain voltages) as logic variables I, A, and B respectively, and the final threshold voltage state or channel conductance of the ferroelectric transistor as the output Y, a single ferroelectric transistor can implement all 14 Boolean logic functions (excluding XNOR and XOR) and store the operation results in place between inputs p and q; furthermore, two ferroelectric transistors can implement XNOR and XOR functions. By changing the assignment of the logic variables, the reconfigurability between the arithmetic functions can be achieved.

[0081] This invention utilizes the logic functions and non-volatile storage characteristics of ferroelectric transistors to realize reconfigurable in-memory Boolean logic gates. Without altering the cell structure, all 16 Boolean logic operations can be performed simply by assigning values ​​to logic variables. Furthermore, the operation results can be stored in-situ within the logic cell, eliminating the need for additional storage units or data movement. This invention combines the low power consumption of in-memory computing technology with the high functional richness of reconfigurable technology, achieving a wealth of logic functions with a minimal number of devices and avoiding data movement, thus offering multiple advantages in terms of structure, area, and performance.

[0082] Figure 7 A schematic diagram of the structure of a logic operation device based on ferroelectric transistors provided in the embodiments of this application is shown below. Figure 7 As shown, the specific components include: an acquisition module 701, configured to acquire an operation instruction to be executed, wherein the operation instruction includes input variables and the type of the logical operation to be executed; a determination module 702, configured to determine the assignment relationship between the input variables and the logical variables based on the relationship between the logical variables of the target logic gate and the type of the logical operation to be executed, wherein the target logic gate includes at least one ferroelectric transistor, the logical variables include the initial threshold voltage state of the ferroelectric transistor and the voltage at the input terminal of the ferroelectric transistor, and the voltage at the input terminal includes the gate voltage and the source voltage or the gate voltage and the drain voltage; an assignment module 703, configured to assign the value of the input variable to the logical variable according to the assignment relationship; and an operation module 704, configured to control the ferroelectric transistor to perform the logical operation according to the logical variable, and to store the result of the logical operation in situ using the polarization state of the ferroelectric transistor.

[0083] In some optional implementations, the determining module 702 is further configured to: determine the assignment relationship between input variables and logical variables based on a pre-established assignment relationship table associated with the target logic gate, wherein the assignment relationship table records the assignment relationship between input variables and logical variables corresponding to each logical operation type covered by the target logic gate.

[0084] In some alternative implementations, the target logic gate includes a first logic gate consisting of an N-type ferroelectric transistor. The logic operation types covered by the first logic gate include operations with an output of 0, operations with an output of 1, NOT, OR, AND, NAND, NOR, inverse implication, implication, non-implication, and inverse non-implication.

[0085] In some alternative implementations, the first logic gate also includes a depletion-type N-type field-effect transistor or resistor located in the saturation region. The gate and source of the N-type ferroelectric transistor in the first logic gate are the input terminals, and the drain of the N-type ferroelectric transistor is connected to a resistor or the gate of the depletion-type N-type transistor as the read terminal.

[0086] In some alternative implementations, the target logic gate includes a second logic gate composed of two N-type ferroelectric transistors. The gate and source of the two N-type ferroelectric transistors are the input terminals, and the drains of the two N-type ferroelectric transistors are connected as the read terminals. The logic operation types covered by the second logic gate include XOR operation and NAND operation.

[0087] In some alternative implementations, the second logic gate also includes a load resistor, with the gates and sources of the two N-type ferroelectric transistors in the second logic gate serving as input terminals, and the drains of the two N-type ferroelectric transistors connected to one end of the resistor as read terminals.

[0088] In some alternative implementations, the apparatus further includes a selection module configured to select, from candidate logic gates, a logic gate whose covered logic operation type includes the type of logic operation to be performed as the target logic gate.

[0089] In this embodiment, the specific processing of the acquisition module 701, calculation module 702, assignment module 703, and operation module 704 of the logic operation device based on ferroelectric transistors can be referred to Figure 1 The corresponding steps are 101, 102, 103 and 104 in the embodiment.

[0090] The logic operation device based on ferroelectric transistors provided by this invention improves the flexibility of in-memory Boolean logic gates based on ferroelectric transistors in performing logic operations.

[0091] Figure 8 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 8As shown, the electronic device may include a processor 810, a communications interface 820, a memory 830, and a communication bus 840. The processor 810, communications interface 820, and memory 830 communicate with each other via the communication bus 840. The processor 810 can call logic instructions from the memory 830 to execute a logic operation method based on ferroelectric transistors. This method includes: obtaining the operation instruction to be executed, wherein the operation instruction includes input variables and the type of logic operation to be executed; determining the assignment relationship between the input variables and the logic variables of the target logic gate according to the working principle of the target logic gate and the type of logic operation to be executed, wherein the target logic gate includes at least one ferroelectric transistor, and the logic variables include the initial threshold voltage state of the ferroelectric transistor and the voltage at the input terminal of the ferroelectric transistor, the voltage at the input terminal including the gate voltage and source voltage or the gate voltage and drain voltage; assigning the values ​​of the input variables to the logic variables according to the assignment relationship; controlling the ferroelectric transistor to execute the logic operation according to the logic variables, and storing the result of the logic operation in situ using the polarization state of the ferroelectric transistor.

[0092] Furthermore, the logical instructions in the aforementioned memory 830 can be implemented as software functional modules and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, essentially, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0093] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the logic operation method based on ferroelectric transistors provided by the above methods. The method includes: obtaining an operation instruction to be executed, wherein the operation instruction includes input variables and the type of logic operation to be executed; determining the assignment relationship between the input variables and the logic variables of the target logic gate according to the working principle of the target logic gate and the type of logic operation to be executed, wherein the target logic gate includes at least one ferroelectric transistor, the logic variables include the initial threshold voltage state of the ferroelectric transistor and the voltage at the input terminal of the ferroelectric transistor, and the voltage at the input terminal includes the gate voltage and the source voltage or the gate voltage and the drain voltage; assigning the value of the input variable to the logic variable according to the assignment relationship; controlling the ferroelectric transistor to perform the logic operation according to the logic variable, and storing the result of the logic operation in situ using the polarization state of the ferroelectric transistor.

[0094] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon. When executed by a processor, the computer program implements the logic operation method based on ferroelectric transistors provided by the above methods. The method includes: obtaining an operation instruction to be executed, wherein the operation instruction includes input variables and the type of logic operation to be executed; determining the assignment relationship between the input variables and the logic variables of the target logic gate according to the working principle of the target logic gate and the type of logic operation to be executed, wherein the target logic gate includes at least one ferroelectric transistor, the logic variables include the initial threshold voltage state of the ferroelectric transistor and the voltage at the input terminal of the ferroelectric transistor, and the voltage at the input terminal includes the gate voltage and the source voltage or the gate voltage and the drain voltage; assigning the value of the input variable to the logic variable according to the assignment relationship; controlling the ferroelectric transistor to perform the logic operation according to the logic variable, and storing the result of the logic operation in situ using the polarization state of the ferroelectric transistor.

[0095] The device embodiments described above are merely illustrative. The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0096] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0097] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A logic operation method based on ferroelectric transistors, characterized in that, include: Obtain the operation instruction to be executed, wherein the operation instruction includes input variables and the type of logical operation to be executed; Based on the working principle of the target logic gate and the type of logic operation to be executed, the assignment relationship between the input variable and the logic variable of the target logic gate is determined. The target logic gate includes at least one ferroelectric transistor, and the logic variable includes the initial threshold voltage state of the ferroelectric transistor and the voltage at the input terminal of the ferroelectric transistor. The voltage at the input terminal includes the gate voltage and the source voltage or the gate voltage and the drain voltage. The values ​​of the input variables are assigned to the logical variables according to the assignment relationship; The ferroelectric transistor is controlled to perform logical operations according to the logical variables, and the results of the logical operations are stored in situ using the polarization state of the ferroelectric transistor.

2. The logic operation method based on ferroelectric transistors according to claim 1, characterized in that, The step of determining the assignment relationship between the input variable and the logical variable of the target logic gate based on the working principle of the target logic gate and the type of the logical operation to be performed includes: Based on the pre-established assignment relationship table associated with the target logic gate, the assignment relationship between the input variable and the logic variable is determined, wherein the assignment relationship table records the assignment relationship between the input variable and the logic variable corresponding to each logic operation type covered by the target logic gate.

3. The logic operation method based on ferroelectric transistors according to claim 2, characterized in that, The target logic gate includes a first logic gate composed of an N-type ferroelectric transistor. The logic operation types covered by the first logic gate include operations with an output of 0, operations with an output of 1, NOT operations, OR operations, AND operations, NAND operations, NOR operations, inverse implication operations, implication operations, non-implication operations, and inverse non-implication operations.

4. The logic operation method based on ferroelectric transistors according to claim 3, characterized in that, The first logic gate further includes a depletion-type N-type field-effect transistor or resistor located in the saturation region. The gate and source of the N-type ferroelectric transistor in the first logic gate are the input terminals, and the drain of the N-type ferroelectric transistor is connected to a resistor or the gate of the depletion-type N-type transistor as the read terminal.

5. The logic operation method based on ferroelectric transistors according to claim 2, characterized in that, The target logic gate includes a second logic gate composed of two N-type ferroelectric transistors. The gate and source of the two N-type ferroelectric transistors are the input terminals, and the drains of the two N-type ferroelectric transistors are connected as the read terminals. The logic operation types covered by the second logic gate include XOR operation and NAND operation.

6. The logic operation method based on ferroelectric transistors according to claim 5, characterized in that, The second logic gate also includes a load resistor. The gates and sources of the two N-type ferroelectric transistors in the second logic gate are the input terminals, and the drains of the two N-type ferroelectric transistors are connected to one end of the resistor as the read terminal.

7. The logic operation method based on ferroelectric transistors according to claim 1, characterized in that, After obtaining the arithmetic instructions to be executed for the target logic gate, the method further includes: Select a logic gate from the candidate logic gates whose covered logic operation types include the type of the logic operation to be performed as the target logic gate.

8. A logic operation device based on ferroelectric transistors, characterized in that, include: The acquisition module is configured to acquire the operation instructions to be executed, wherein the operation instructions include input variables and the type of the logical operation to be executed; The determination module is configured to determine the assignment relationship between the input variable and the logic variable based on the relationship between the logic variables of the target logic gate and the type of the logic operation to be performed. The target logic gate includes at least one ferroelectric transistor, and the logic variable includes the initial threshold voltage state of the ferroelectric transistor and the voltage at the input terminal of the ferroelectric transistor. The voltage at the input terminal includes the gate voltage and the source voltage or the gate voltage and the drain voltage. The assignment module is configured to assign the value of the input variable to the logical variable according to the assignment relationship; The arithmetic module is configured to control the ferroelectric transistor to perform logical operations according to the logical variables, and to store the results of the logical operations in situ using the polarization state of the ferroelectric transistor.

9. An electronic device, characterized in that, The system includes a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that the processor, when executing the program, implements the logic operation method based on ferroelectric transistors as described in any one of claims 1 to 7.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the logic operation method based on ferroelectric transistors as described in any one of claims 1 to 7.

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