Wiring method and device of high-speed bus and computer equipment

Abstract

The invention relates to a wiring method and device of a high-speed bus and computer equipment. The method is applied to an automatic design process of the PCB, and comprises the following steps: determining a wiring layer structure matrix, a via hole matrix and a rule matrix of each signal network of the PCB to be designed; determining wiring layer constraint information based on the wiring layer structure matrix; based on the via hole matrix, determining via hole constraint information; determining dynamic rule information based on the rule matrix; determining a cost function based on the wiring layer constraint information, the via hole constraint information and the dynamic rule information; performing path optimization on the cost function by using an A star algorithm to obtain the optimized cost function of each signal network of the PCB to be designed; and based on the optimized cost function of each signal network of the to-be-designed PCB, automatically designing the to-be-designed PCB. By adopting the method, the automatic design of the high-speed bus of the PCB can be realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of PCB automatic design, in particular to a wiring method and device of high-speed bus and computer equipment. BACKGROUND

[0002] With the development of electronic technology, PCB (Printed Circuit Board) technology has also developed rapidly. In the development process of PCB technology, PCB automatic design is paid more and more attention.

[0003] The existing PCB automatic design method mainly uses the data information required for wiring in the completed PCB layout to divide the PCB wiring area into modules, sorts the divided modules according to the set priority, performs kmeans clustering on the starting points of all the modules to be wired according to the sorted modules to divide the modules into multiple sub-classes, performs multi-agent path planning on the starting points of all the modules to be wired in the sub-classes to wire the sub-classes, and divides the wired area into forbidden areas. Repeat the above process until all the sub-classes are wired. This kind of PCB automatic design method is only suitable for automatic wiring of ordinary signal lines and cannot meet the wiring requirements of high-speed buses.

[0004] For the existing PCB automatic design method, there is no effective solution to the problem that it cannot meet the wiring requirements of high-speed buses. SUMMARY

[0005] Therefore, it is necessary to provide a wiring method, device and computer equipment of high-speed bus in view of the above technical problems.

[0006] In a first aspect, the present application provides a wiring method of high-speed bus, applied to the automatic design process of PCB board. The method comprises:

[0007] determining the wiring layer structure matrix, via matrix and rule matrix of each signal network of the PCB board to be designed;

[0008] determining the wiring layer constraint information corresponding to each signal network of the PCB board to be designed based on the wiring layer structure matrix, determining the via constraint information corresponding to each signal network of the PCB board to be designed based on the via matrix, and determining the dynamic rule information corresponding to each signal network of the PCB board to be designed based on the rule matrix;

[0009] determine a cost function of each of the signal networks of the PCB to be designed based on the wiring layer constraint information, the via constraint information, and the dynamic rule information; the cost function comprising a base cost and a heuristic cost of each of the signal networks of the PCB to be designed; the base cost comprising a quality cost and an efficiency cost;

[0010] perform path optimization on the cost function by using an A-star algorithm to obtain an optimized cost function of each of the signal networks of the PCB to be designed;

[0011] perform automatic design on the PCB to be designed based on the optimized cost function of each of the signal networks of the PCB to be designed.

[0012] In one of the embodiments, the determining of the wiring layer structure matrix of each of the signal networks of the PCB to be designed comprises:

[0013] determine the wiring layer structure matrix of each of the signal networks of the PCB to be designed based on the structure information of each of the wiring layers of the PCB to be designed, information of recommended wiring layers among all the wiring layers of the PCB to be designed, wiring layers on which pads of each of the network nodes of the PCB to be designed are located, and wiring priorities of wiring layers corresponding to each of the network nodes of the PCB to be designed.

[0014] In one of the embodiments, the determining of the via matrix of each of the signal networks of the PCB to be designed comprises:

[0015] obtain design requirements of the PCB to be designed;

[0016] determine a device material high-speed bus database corresponding to the PCB to be designed based on the obtained design requirements of the PCB to be designed; the device material high-speed bus database comprising network names and signal protocol types;

[0017] determine signal protocol types corresponding to network names of each of the signal networks of the PCB to be designed based on the device material high-speed bus database corresponding to the PCB to be designed;

[0018] determine via impedance, via size, and maximum via quantity corresponding to each of the signal networks of the PCB to be designed based on the signal protocol types corresponding to network names of each of the signal networks of the PCB to be designed;

[0019] Determine a via matrix of each signal network of the PCB to be designed based on the via impedance, the via size and the maximum number of vias corresponding to each signal network of the PCB to be designed.

[0020] In one of the embodiments, the determining of the device material high-speed bus database corresponding to the PCB to be designed based on the design requirements of the PCB to be designed comprises:

[0021] Determine the material code corresponding to the PCB to be designed based on the design requirements of the PCB to be designed.

[0022] Filter out the device material high-speed bus database corresponding to the PCB to be designed from a preset electronic material information database based on the material code corresponding to the PCB to be designed; the preset electronic material information database is a pre-stored corresponding relationship database between each material code and device material high-speed bus database.

[0023] In one of the embodiments, the determining of the rule matrix of each signal network of the PCB to be designed comprises:

[0024] Determine the rule matrix of each signal network of the PCB to be designed based on the line width rule and the spacing rule of the PCB to be designed.

[0025] In one of the embodiments, the determining of the wiring layer constraint information corresponding to each signal network of the PCB to be designed based on the wiring layer structure matrix comprises:

[0026] Determine the priority of each wiring layer in the PCB to be designed based on the layer structure of the PCB to be designed and a preset wiring layer rule;

[0027] Determine the wiring layer constraint information corresponding to each signal network of the PCB to be designed based on the priority of each wiring layer in the PCB to be designed and the wiring layer structure matrix.

[0028] In one of the embodiments, the determining of the via constraint information corresponding to each signal network of the PCB to be designed based on the via matrix comprises:

[0029] Determine the number of vias of each signal network of the PCB to be designed during actual wiring based on the via matrix.

[0030] determine the via constraint information corresponding to each of the signal networks of the PCB to be designed based on the via priority of the PCB to be designed and the number of vias of each of the signal networks in actual routing.

[0031] In one of the embodiments, the determination of the dynamic rule information corresponding to each of the signal networks of the PCB to be designed based on the rule matrix comprises:

[0032] determine the line width rule and the spacing rule of each of the signal networks of the PCB to be designed based on the rule matrix;

[0033] determine the dynamic rule information corresponding to each of the signal networks of the PCB to be designed based on the line width rule and the spacing rule of each of the signal networks of the PCB to be designed, the cost weight of the line width rule of each of the signal networks of the PCB to be designed, the cost weight of the spacing rule of each of the signal networks of the PCB to be designed, and the routing density of each of the routing areas of the PCB to be designed.

[0034] In one of the embodiments, the determination of the cost function of each of the signal networks of the PCB to be designed based on the routing layer constraint information, the via constraint information, and the dynamic rule information comprises:

[0035] determine the layer cost corresponding to the routing layer of each of the signal networks of the PCB to be designed based on the routing layer constraint information;

[0036] determine the via cost of each of the signal networks of the PCB to be designed based on the via constraint information;

[0037] determine the rule cost corresponding to each of the signal networks of the PCB to be designed based on the dynamic rule information;

[0038] determine the quality cost in the basic cost of the automatic routing of each of the signal networks of the PCB to be designed based on the layer cost corresponding to the routing layer, the via cost, and the rule cost, and the single-step execution cost in path finding;

[0039] determine the efficiency cost in the basic cost of the automatic routing of each of the signal networks of the PCB to be designed based on the movement cost corresponding to the area where each of the signal networks of the PCB to be designed is located, the fixed cost of the layer change of the signal networks in the same group of the PCB to be designed, and the number of layer changes of each of the signal networks of the PCB to be designed;

[0040] determine the heuristic cost of the automatic routing of each of the signal networks of the PCB to be designed based on the Hamming distance cost, the fixed cost of the layer change of the signal networks in the same group of the PCB to be designed, and the relationship between the current layer of each of the signal networks of the PCB to be designed and the target layer corresponding to the group in which each of the signal networks is located.

[0041] In one of the embodiments, before determining the cost function of each of the signal networks of the PCB to be designed based on the routing layer constraint information, the via constraint information, and the dynamic rule information, the method further comprises:

[0042] determine the network name corresponding to each pin of the PCB to be designed and the network group to which the network name corresponding to each pin belongs based on the device material high-speed bus database corresponding to the design task of the PCB to be designed;

[0043] determine the grouping result of all pins of the PCB to be designed at the network level based on the network name of each pin of the PCB to be designed and the network group to which the network name corresponding to each pin belongs;

[0044] determine the network grouping result of each of the signal networks of the PCB to be designed based on the grouping result of all pins of the PCB to be designed at the network level.

[0045] In one of the embodiments, after determining the network grouping result of each of the signal networks of the PCB to be designed, the method further comprises:

[0046] determine the group strategy of the high-speed bus of the PCB to be designed based on the network information of the group in which the current signal network is located, the average distance between the path segment in which the current signal network is located and the path segment in which the other signal networks in the same group are located, the consistency between the layer in which the path segment in which the current signal network is located is located and the layer in which the path segment in which the other signal networks in the same group are located is located, and the matching degree of the path direction of the path segment in which the current signal network is located and the path direction of the path segment in which the other signal networks in the same group are located.

[0047] determine the fixed cost of the layer change of the signal networks in the same group of the PCB to be designed and the relationship between the current layer of each of the signal networks of the PCB to be designed and the target layer corresponding to the group in which each of the signal networks is located based on the group strategy of the high-speed bus of the PCB to be designed.

[0048] In a second aspect, the application further provides a routing device of a high-speed bus, which is applied to the automatic design process of a PCB. The device comprises:

[0049] The matrix determination module is used to determine the routing layer structure matrix, via matrix, and rule matrix of each signal network of the PCB board to be designed.

[0050] The constraint determination module is used to determine, based on the routing layer structure matrix, the routing layer constraint information corresponding to each signal network of the PCB board to be designed; based on the via matrix, the via constraint information corresponding to each signal network of the PCB board to be designed; and based on the rule matrix, the dynamic rule information corresponding to each signal network of the PCB board to be designed.

[0051] The cost function determination module is used to determine the cost function of each signal network of the PCB board to be designed based on the wiring layer constraint information, the via constraint information, and the dynamic rule information; the cost function includes the basic cost and the heuristic cost of each signal network of the PCB board to be designed; the basic cost includes quality cost and efficiency cost;

[0052] The optimization module is used to perform path optimization on the cost function using the A* algorithm to obtain the optimized cost function of each signal network of the PCB board to be designed.

[0053] And an automatic design module, used to automatically design the PCB board to be designed based on the optimized cost function of each of the signal networks of the PCB board to be designed.

[0054] Thirdly, this application also provides a computer device. The computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the high-speed bus wiring method described in the first aspect.

[0055] The aforementioned high-speed bus routing method, apparatus, and computer equipment determine the routing layer structure matrix, via matrix, and rule matrix of each signal network of the PCB board to be designed. Based on these matrices, they determine the routing layer constraint information, via constraint information, and dynamic rule information corresponding to each signal network. Subsequently, they determine the cost function of each signal network of the PCB board to be designed and use the A* algorithm to optimize the cost function. This optimized cost function can be used for the automatic design of the high-speed bus of the PCB board, thus realizing the automatic design of the high-speed bus of the PCB board.

[0056] Details of one or more embodiments of this application are set forth in the following drawings and description to make other features, objects and advantages of this application more readily apparent. Attached Figure Description

[0057] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0058] Figure 1 A hardware structure block diagram of a terminal for a high-speed bus wiring method provided in an embodiment of this application;

[0059] Figure 2 A flowchart illustrating a high-speed bus routing method provided in an embodiment of this application;

[0060] Figure 3 A flowchart illustrating a high-speed bus routing method provided in a preferred embodiment of this application;

[0061] Figure 4 This is a structural block diagram of a high-speed bus wiring device provided in an embodiment of this application. Detailed Implementation

[0062] To better understand the purpose, technical solution, and advantages of this application, the application is described and illustrated below in conjunction with the accompanying drawings and embodiments.

[0063] Unless otherwise defined, the technical or scientific terms used in this application shall have the general meaning understood by one of ordinary skill in the art to which this application pertains. Words such as “a,” “an,” “an,” “the,” “the,” and “these” used in this application do not indicate quantitative limitation and may be singular or plural. The terms “comprising,” “including,” “having,” and any variations thereof used in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that comprises a series of steps or modules (units) is not limited to the listed steps or modules (units) but may include steps or modules (units) not listed, or may include other steps or modules (units) inherent to these processes, methods, products, or devices. Words such as “connected,” “linked,” and “coupled” used in this application are not limited to physical or mechanical connections but may include electrical connections, whether direct or indirect. “Multiple” used in this application refers to two or more. “And / or” describes the relationship between related objects, indicating that three relationships may exist; for example, “A and / or B” can represent: A alone, A and B simultaneously, and B alone. Normally, the character " / " indicates that the objects before and after it are in an "or" relationship. The terms "first," "second," "third," etc., used in this application are merely to distinguish similar objects and do not represent a specific order of objects.

[0064] The method embodiments provided in this example can be executed on a terminal, computer, or similar computing device. For example, it can run on a computer terminal for automatic PCB board design. Figure 1 This is a hardware structure block diagram of the terminal of the high-speed bus wiring method in this embodiment. For example... Figure 1 As shown, a terminal may include one or more ( Figure 1 Only one is shown in the diagram. A processor 102 and a memory 104 for storing data are also included. The processor 102 may be, but is not limited to, a microprocessor (MCU) or a programmable logic device (FPGA). The terminal may also include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that… Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the terminal described above. For example, the terminal may also include components that are larger than... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown are illustrated.

[0065] The memory 104 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to the high-speed bus wiring method in this embodiment. The processor 102 executes various functional applications and data processing by running the computer programs stored in the memory 104, thus implementing the methods described above. The memory 104 may include high-speed random access memory and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to the terminal via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0066] The transmission device 106 is used to receive or send data via a network. This network includes a wireless network provided by the terminal's communication provider. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 can be a Radio Frequency (RF) module used for wireless communication with the Internet.

[0067] This embodiment provides a high-speed bus routing method, which is applied to the automated design process of PCB boards. Figure 2 This is a flowchart of the high-speed bus routing method in this embodiment, as shown below. Figure 2 As shown, the process includes the following steps:

[0068] Step S210: Determine the routing layer structure matrix, via matrix, and rule matrix of each signal network of the PCB board to be designed.

[0069] The aforementioned high-speed bus can be a chip-level schematic model, specifically a mathematical model based on the device's operating principles and physical characteristics. The aforementioned PCB board to be designed is the printed circuit board that requires design; it can be the physical carrier of an electronic product whose final structure, layout, and electrical characteristics need to be determined through a series of design processes. It can be used for mechanical support and electrical connection of electronic components. The aforementioned signal network refers to the set of paths on the PCB board used to transmit electrical signals. For example, a data transmission line between a microprocessor and a memory chip, or a power supply line from a power module to other circuit components, both belong to signal networks. In PCB design, different signal networks have different electrical characteristic requirements; for example, high-speed signals require consideration of impedance matching and signal integrity, while low-speed signals are relatively simpler.

[0070] In this step, the aforementioned routing layer structure matrix can be a matrix-style data structure used to describe the distribution of various signal networks on different routing layers of a PCB board. The routing layers can be the top layer, bottom layer, or inner layer, etc. In multilayer PCBs, signals can switch between different layers to achieve a more rational layout and routing. For example, a signal might be routed a distance on the top layer and then switched to an inner layer via a via to continue routing. The aforementioned routing layer structure matrix can record the routing status of each signal network on each layer. This embodiment uses the routing layer structure matrix to determine the inter-layer distribution of signals, facilitating subsequent optimization of routing strategies, avoiding inter-layer conflicts, and ensuring signal integrity and reliability.

[0071] Furthermore, the aforementioned vias can be vertical channels connecting signals between different layers of a PCB board. The aforementioned via matrix can be a matrix-style data structure used to describe the via information used by various signal networks when switching between different layers. The via matrix is ​​used to determine the location of vias used by each signal network, as well as the layers connected to each via. For example, when a signal switches from the top layer to the bottom layer, a via needs to be placed at a specific location. The via matrix can record the location coordinates of this via, the connected layer number, and the corresponding signal network number. Through the via matrix, the usage of vias can be clearly recorded, the number and location of vias can be rationally planned, avoiding routing density problems caused by too many vias, while also ensuring that the electrical performance of signals is not affected when switching between layers. The aforementioned rule matrix can be a matrix-style data structure used to define various routing rules in PCB design. The aforementioned routing rules include at least line width rules and spacing rules.

[0072] Step S220: Based on the routing layer structure matrix, determine the routing layer constraint information corresponding to each signal network of the PCB board to be designed; based on the via matrix, determine the via constraint information corresponding to each signal network of the PCB board to be designed; based on the rule matrix, determine the dynamic rule information corresponding to each signal network of the PCB board to be designed.

[0073] The aforementioned routing layer constraint information refers to the constraint management rules for the routing layers corresponding to each signal network of the PCB board to be designed. The aforementioned via constraint information refers to the via constraint management rules corresponding to each signal network of the PCB board to be designed. The aforementioned dynamic rule information refers to the dynamic control rules corresponding to each signal network of the PCB board to be designed; specifically, it refers to the routing rules dynamically adjusted during the PCB design process based on the characteristics of the signal network (such as signal type, frequency, current, etc.) and the routing environment (such as routing density, routing layers, etc.).

[0074] Step S230: Based on routing layer constraint information, via constraint information, and dynamic rule information, determine the cost function of each signal network of the PCB board to be designed; the cost function includes the basic cost and heuristic cost of each signal network of the PCB board to be designed; the basic cost includes quality cost and efficiency cost.

[0075] In this step, the aforementioned cost function can serve as a comprehensive evaluation metric to measure the overall cost of the PCB design. The aforementioned basic cost reflects the basic quality of the design, while the aforementioned heuristic cost can guide design optimization. The aforementioned cost function, based on routing layer constraint information, via constraint information, and dynamic rule information, determines the cost function for each signal network of the PCB to be designed. The cost function process involves determining the layer cost corresponding to the routing layer of each signal network of the PCB to be designed based on routing layer constraint information; furthermore, determining the via cost of each signal network of the PCB to be designed based on via constraint information; determining the rule cost corresponding to each signal network of the PCB to be designed based on dynamic rule information; and finally, determining the automatic routing of each signal network of the PCB to be designed based on the layer cost, via cost, rule cost, and single-step execution cost during pathfinding. The quality cost is included in the basic cost of the wiring. Furthermore, based on the movement cost corresponding to the area where each signal network of the PCB board to be designed is located, the fixed cost of changing layers of the same group of signal networks of the PCB board to be designed, and the number of layers of each signal network of the PCB board to be designed, the efficiency cost is determined in the basic cost of automatic routing of each signal network of the PCB board to be designed. Based on the Harmanton distance cost, the fixed cost of changing layers of the same group of signal networks of the PCB board to be designed, and the relationship between the current layer of each signal network of the PCB board to be designed and the target layer corresponding to the group to which each signal network belongs, the heuristic cost of automatic routing of each signal network of the PCB board to be designed is determined.

[0076] Step S240: Use the A* algorithm to perform path optimization on the cost function to obtain the optimized cost function of each signal network of the PCB board to be designed.

[0077] The A* algorithm described above is a heuristic search algorithm widely used in graph path planning and graph search problems. It efficiently finds the shortest path from the starting point to the target point by comprehensively considering both practical cost and heuristic estimation. The core of the A* algorithm lies in its evaluation function. Here, g(n) represents the actual cost from the starting point to the current node, and h(n) is the heuristically estimated cost from the current node to the target node. Therefore, given the actual cost and heuristically estimated cost of the cost function, the A* algorithm can be used for path optimization to reduce the divergence of the routing path and improve the efficiency of collision identification. Specifically, by establishing the cost function regarding the impact of the high-speed bus, the basic cost and heuristic cost of the A* algorithm are established, and the A* algorithm is used to optimize the path using the cost function. Since high-speed signals in the same group need to comply with the requirement that the network in the same group should be on the same layer or the backbone path should be on the same layer, the A* algorithm needs to prioritize paths within the same layer when planning paths, or if crossing layers, the backbone part should be kept on the same layer. In addition, due to the high speed of high-speed signals, the wiring spacing is generally large, but in actual design, especially in the chip fan-out area, there are dense areas that make it difficult to guarantee the expected regular spacing. Therefore, it is necessary to identify the density characteristics of the area for reasonable path identification. Using the A* algorithm can improve the quality of automatic routing of high-speed buses by more than 5 times and the efficiency of automatic routing by more than 3 times.

[0078] Step S250: Based on the optimized cost function of each signal network of the PCB board to be designed, automatically design the PCB board to be designed.

[0079] Based on the optimized cost function of each signal network of the PCB board to be designed, the high-speed bus layout path of each signal network can be determined, thereby realizing the automatic design of the PCB board to be designed.

[0080] Steps S210 to S250 above determine the routing layer structure matrix, via matrix, and rule matrix of each signal network of the PCB board to be designed. Based on each matrix, the routing layer constraint information, via constraint information, and dynamic rule information corresponding to each signal network are determined. Then, the cost function of each signal network of the PCB board to be designed is determined, and the A* algorithm is used to optimize the cost function so that the optimized cost function can be used for the automatic design of the high-speed bus of the PCB board, thus realizing the automatic design of the high-speed bus of the PCB board.

[0081] In one embodiment, step S210, determining the routing layer structure matrix of each signal network of the PCB board to be designed, includes:

[0082] Step S211: Based on the structural information of each routing layer of the PCB board to be designed, the information of the recommended routing layers among all routing layers of the PCB board to be designed, the routing layers where the pads of each network node of the PCB board to be designed are located, and the routing priority of the routing layers corresponding to each network node of the PCB board to be designed, determine the routing layer structure matrix of each signal network of the PCB board to be designed.

[0083] In this step, the structural information of the aforementioned routing layers can include material properties (such as dielectric constant and thickness), routing capabilities (such as line width and spacing limitations), and whether it is a power layer or a ground layer. This structural information can characterize the electrical characteristics and routing potential of each layer. The information on the recommended routing layers can be the matching information between the routing layer and a specific type of signal based on signal type (such as high-speed signal, low-speed signal, power line, ground line, etc.) and routing rules (such as impedance matching, signal integrity requirements, etc.). The information on the recommended routing layers can include the recommended routing layer number, the reason for recommendation (such as low impedance, low crosstalk, etc.), and the recommended routing method (such as microstrip line, stripline, etc.). The aforementioned network node can be a connection point on a signal or power path on the PCB board, and can be the start point, end point, or relay point of a signal. The routing layer containing the aforementioned pads can be located on the top, bottom, or inner layer of the PCB board. The routing priority of the aforementioned routing layers can be a pre-defined priority order of different signals located on the routing layer based on the importance or characteristics of the signals. For example, high-speed signals typically require priority routing to ensure signal integrity; power and ground lines usually require wider trace widths and should also be given priority. The priorities of different signals located at the routing layer can be set based on factors such as signal speed, impedance requirements, and whether they are critical signals.

[0084] The process of determining the routing layer structure matrix L of each signal network of the PCB board to be designed is as follows:

[0085] ;

[0086] Among them, L s L1 contains the structural information of each routing layer of the PCB board to be designed, and L2 contains the information of the recommended routing layer among all the routing layers of the PCB board to be designed. p L represents the routing layer where the pads of each network node on the PCB board to be designed reside. n This refers to the routing priority of the routing layer corresponding to each network node of the PCB board to be designed.

[0087] In this embodiment, the structural information of the aforementioned routing layers determines the routing capabilities of each layer. The recommended routing layer information provides optimal routing layer suggestions based on signal characteristics. The routing layer where the pads of each network node are located determines the layers where the signal's start and end points are located. The routing priority of the routing layer determines which signals need to be routed first. Through the information of each of the aforementioned routing layers, a routing layer structure matrix reflecting the routing status of each signal network on each routing layer is obtained. This facilitates the determination of the routing layer constraint information corresponding to each signal network on the PCB board to be designed based on the routing layer structure matrix.

[0088] Specifically, in one embodiment, step S210, determining the via matrix of each signal network of the PCB board to be designed, includes:

[0089] Step S212: Obtain the design requirements of the PCB board to be designed.

[0090] The aforementioned design requirements can be a series of technical specifications or constraints determined by the customer based on product specifications, industry standards, or application scenarios. These design requirements are key factors in ensuring that the PCB board meets the expected functions and performance. The main contents of these design requirements can include functional requirements, electrical performance requirements, physical characteristic requirements, environmental requirements, and cost requirements. The functional requirements include circuit functions (the functions the PCB board needs to implement, such as signal processing, power management, communication interfaces, or control functions) and component selection (the types, specifications, and quantities of components to be mounted on the PCB board. For example, processor model, memory chip capacity, capacitor voltage rating, etc.). The electrical performance requirements include operating voltage and current (the PCB board's operating voltage range and maximum current carrying capacity), signal integrity (for high-speed signals, signal integrity must be ensured, including impedance matching, transmission delay, crosstalk control, etc.), and electromagnetic compatibility or power integrity requirements. The aforementioned physical characteristics requirements include size and shape (the physical dimensions, shape, and mounting hole locations of the PCB board to fit the product's casing or mounting space), number of layers (the number of layers on the PCB board, single-layer, double-layer, or multi-layer), and material selection (PCB substrate material or surface treatment process). Obtaining the design requirements for the PCB board to be designed can be based on detailed product specifications, industry standards and specifications, product design requirements, technology roadmaps, and other technical documents provided by the customer.

[0091] Step S213: Based on the obtained design requirements of the PCB board to be designed, determine the high-speed bus database of the components and materials corresponding to the PCB board to be designed; the high-speed bus database of components and materials includes material codes, network names and signal protocol types.

[0092] The above-mentioned determination of the high-speed bus database of components and materials corresponding to the PCB board to be designed based on the obtained design requirements of the PCB board to be designed can be based on the obtained design requirements of the PCB board to be designed, determining the material code corresponding to the PCB board to be designed, and then, based on the material code corresponding to the PCB board to be designed, filtering the high-speed bus database of components and materials corresponding to the PCB board to be designed from the preset electronic material information database.

[0093] The aforementioned high-speed bus database for device materials can be a library storing detailed information about each material. This detailed information may include material code, network name, and signal protocol type, and may also include one or more of the following: pin number, network type, different bus signal rates corresponding to the bus type, and network group name.

[0094] For example, the high-speed bus database of device materials is shown in Table 1:

[0095] Table 1

[0096]

[0097] Among them, "New Part Number" represents the material code; "PIN Number" represents the pin number; "XNetName" represents the network name, which is used to indicate the original network name of the pin and the network name matching the actual project; "Net Type" represents the network type, which can be used to determine the subtype of the signal, and then apply different electrical templates to judge the simulation results; "Signal Type" represents the signal protocol type, which can be used to determine the signal type of this network; "Signal Rate" represents the different bus signal rates corresponding to the bus type; "BUS NAME" represents the network group name, which is used to manage and define different groups of high-speed buses.

[0098] The aforementioned material code is a unique code used internally by the enterprise to identify and manage materials. The aforementioned high-speed bus database for device materials displays the correspondence between the material code and other information. Therefore, given a material code, it is possible to determine the high-speed bus database for the device material corresponding to that material code, and to determine the content of other information corresponding to that material code. This other information may include one or more of the following: network name, signal protocol type, pin number, network type, different bus signal rates corresponding to the bus type, and network group name.

[0099] Step S214: Based on the high-speed bus database of components and materials corresponding to the PCB board to be designed, determine the signal protocol type corresponding to the network name of each signal network of the PCB board to be designed.

[0100] The above-mentioned determination of the signal protocol type corresponding to the network name of each signal network of the PCB board to be designed based on the high-speed bus database of the components and materials corresponding to the PCB board to be designed can be based on the high-speed bus database of the components and materials corresponding to the PCB board to be designed to determine the network name of each signal network of the PCB board to be designed, and the signal protocol type corresponding to each network name.

[0101] Step S215: Based on the signal protocol type corresponding to the network name of each signal network of the PCB board to be designed, determine the via impedance, via size and maximum number of vias corresponding to each signal network of the PCB board to be designed.

[0102] In PCB design, the network name of a signal network corresponds to the signal protocol type. Different signal protocol types have different requirements for signal integrity and power integrity, therefore, the impedance, size, and maximum number of vias need to be determined based on the signal protocol type. These signal protocol types include low-speed and high-speed signal protocols. The signal protocol type defines the electrical characteristics, transmission rate, topology, and other information of the signal network. For example, low-speed signal protocols typically have low transmission rates (a few MHz) and low requirements for signal integrity. High-speed signal protocols, on the other hand, typically have high transmission rates (a few Gbps or even higher) and extremely high requirements for signal integrity, requiring strict control over signal impedance, via size, and number. Via impedance refers to the impedance characteristics of a via during signal transmission. Via impedance affects signal integrity, especially for high-speed signals. Via impedance is mainly related to the via size, isolation pad size, and trace length. Via size includes the via diameter and pad size. Via size affects the via impedance and signal transmission characteristics. For high-speed signals, via diameters typically need to be smaller to reduce parasitic inductance and capacitance. The via sizes mentioned above are related to board density and impedance. The maximum number of vias mentioned above refers to the maximum number of vias allowed along the signal path. A higher number of vias results in a longer signal transmission path, increasing signal loss and reflection. Therefore, for high-speed signals, the maximum number of vias usually needs to be limited. The maximum number of vias mentioned above is related to the via frequency and the chip and company specifications.

[0103] The above-mentioned determination of the via impedance, via size, and maximum number of vias corresponding to the signal protocol type of each signal network of the PCB board to be designed can be based on the signal protocol type of each signal network of the PCB board to be designed, and can also be based on the impedance requirements of the vias, the diameter of the vias and the pad size, as well as the maximum number of vias allowed on the signal path.

[0104] Step S216: Based on the via impedance, via size and maximum number of vias corresponding to each signal network of the PCB board to be designed, determine the via matrix of each signal network of the PCB board to be designed.

[0105] The specific process for determining the via matrix V of each signal network of the PCB board under design, based on the via impedance, via size, and maximum number of vias corresponding to each signal network, is as follows:

[0106] ;

[0107] Among them, V i V is the via impedance. s V represents the via size. n This represents the maximum number of vias.

[0108] Steps S212 to S216 above involve obtaining the design requirements of the PCB board to be designed, determining the high-speed bus database of components and materials corresponding to the PCB board based on the obtained design requirements, determining the signal protocol type corresponding to the network name of each signal network of the PCB board based on the high-speed bus database of components and materials corresponding to the PCB board, determining the via impedance, via size, and maximum number of vias corresponding to each signal network of the PCB board based on the signal protocol type corresponding to the network name, and finally constructing the via matrix of each signal network of the PCB board based on the via impedance, via size, and maximum number of vias. The construction of the via matrix of each signal network of the PCB board facilitates the subsequent determination of the via constraint information corresponding to each signal network of the PCB board.

[0109] In another embodiment, step S213, based on the obtained design requirements of the PCB board to be designed, determines the high-speed bus database of components and materials corresponding to the PCB board to be designed, including:

[0110] Step S2132: Based on the obtained design requirements of the PCB board to be designed, determine the material code corresponding to the PCB board to be designed.

[0111] The above-mentioned determination of the material code corresponding to the PCB board to be designed based on the obtained design requirements of the PCB board to be designed can be achieved by directly parsing the material code corresponding to the PCB board to be designed from the obtained design requirements, or by parsing the functional attributes and electrical attributes of the PCB board according to the design requirements, and then determining the material code that matches the PCB board to be designed.

[0112] Step S2134: Based on the material code corresponding to the PCB board to be designed, select the high-speed bus database of the device material corresponding to the PCB board to be designed from the preset electronic material information database; the preset electronic material information database is a pre-stored database of the correspondence between each material code and the high-speed bus database of the device material.

[0113] Steps S2132 to S2134 above determine the material code corresponding to the PCB board to be designed based on the obtained design requirements of the PCB board to be designed. Then, based on the material code corresponding to the PCB board to be designed, the high-speed bus database of the device material corresponding to the PCB board to be designed is selected from the preset electronic material information database. This facilitates the subsequent determination of the via matrix of each signal network of the PCB board to be designed based on the high-speed bus database.

[0114] In one embodiment, step S210, determining the rule matrix of each signal network of the PCB board to be designed, includes:

[0115] Step S217: Based on the line width rules and spacing rules of the PCB board to be designed, determine the rule matrix of each signal network of the PCB board to be designed.

[0116] In PCB design, different high-speed bus interfaces correspond to different impedance matching circuits and voltage level specifications, thus affecting the corresponding PCB design trace widths and spacing rules. For example, in the DDR4 high-speed bus interface, assuming the data network impedance control is 50 ohms, the internal spacing is 15 mil, and the external spacing is 20 mil; the address network impedance control is 40 ohms, the internal spacing is 12 mil, and the external spacing is 15 mil, satisfying the requirement that the external spacing takes the maximum value of the actual rules. Specific examples are shown in Table 2:

[0117] Table 2

[0118]

[0119] The above line width rules refer to the width rules for PCB traces, which are mainly related to current capacity, signal frequency, and impedance control. The above spacing rules refer to the minimum distance between PCB traces, which are mainly related to electrical isolation, signal integrity, and manufacturing processes.

[0120] The process of determining the rule matrix R of each signal network of the PCB board to be designed, based on the line width and spacing rules, is as follows:

[0121] ;

[0122] Among them, R wFor the trace width rules of the PCB board to be designed, R s The spacing rules for the PCB board to be designed.

[0123] In another embodiment, step S220, based on the routing layer structure matrix, determines the routing layer constraint information corresponding to each signal network of the PCB board to be designed, including:

[0124] Step S221: Based on the layer structure of the PCB board to be designed and the preset routing layer rules, determine the priority of each routing layer in the PCB board to be designed.

[0125] Routing layers must first meet the requirement of routing on signal layers, and the priority of routing layers should be recommended based on the layer structure. In high-speed bus routing, the recommended order of routing layers is: no layer change -> layer change without stubs -> layer change with stubs. The longer the stub length, the lower the priority. The above-mentioned preset routing layer rules can be used to prioritize different layers of routing. The above layer structure can be the number of layers of the PCB board to be designed, as well as the structural information of each layer.

[0126] For example, consider a four-layer circuit board structure, where TOP and BOTTOM are signal routing layers. Extract all layers of the network node pads and calculate their routing structure, ensuring the routing layer order meets requirements. Score and rank various routing scenarios. If the routing is on the same plane and all layers are on the TOP layer, the recommended layer order is TOP->BOTTOM; if all layers of the network node pads are on the same plane and all layers are on the BOTTOM layer, the recommended layer order is BOTTOM->TOP.

[0127] Step S222: Based on the priority of each routing layer in the PCB board to be designed and the routing layer structure matrix, determine the routing layer constraint information corresponding to each signal network of the PCB board to be designed.

[0128] Based on the priority of each routing layer in the PCB board to be designed, and the routing layer structure matrix, the routing layer constraint information corresponding to each signal network of the PCB board to be designed is determined. The process is as follows:

[0129] ;

[0130] Where, N p Priority of each routing layer in the PCB board to be designed.

[0131] Steps S221 to S222 above determine the priority of each routing layer in the PCB board to be designed based on the layer structure of the PCB board to be designed and the preset routing layer rules. Then, based on the priority of each routing layer in the PCB board to be designed and the routing layer structure matrix, the routing layer constraint information corresponding to each signal network of the PCB board to be designed is determined. By determining the routing layer constraint information corresponding to each signal network of the PCB board to be designed, it is convenient to determine the cost function of each signal network of the PCB board to be designed according to the routing layer constraint information.

[0132] Further, in one embodiment, step S220, based on the via matrix, determines the via constraint information corresponding to each signal network of the PCB board to be designed, including:

[0133] Step S223: Based on the via matrix, determine the number of vias for each signal network of the PCB board to be designed during actual routing.

[0134] Step S224: Based on the via priority of the PCB board to be designed and the number of vias for each signal network during actual routing, determine the via constraint information corresponding to each signal network of the PCB board to be designed.

[0135] Generally, the recommended order for routing vias for high-speed signals in a single network is: no layer change -> single layer change -> multiple layer changes, but the number of vias should be less than the maximum number of vias.

[0136] Based on this, the process of determining the via constraint information corresponding to each signal network of the PCB board under design, based on the via priority of the PCB board under design and the number of vias in the actual routing of each signal network, is as follows:

[0137] ;

[0138] in, For the via constraint information corresponding to each signal network of the PCB board to be designed, N i Prioritize the vias of the PCB board to be designed. This represents the number of vias used in the actual wiring of the signal network.

[0139] It should be noted that the via priority varies across different high-speed buses. As the number of vias increases, the corresponding via cost also increases; when the number of vias exceeds the maximum number of vias, the cost becomes infinite.

[0140] Steps S223 to S224 above determine the number of vias for each signal network of the PCB board to be designed during actual routing based on the via matrix. Based on the via priority of the PCB board to be designed and the number of vias for each signal network during actual routing, the via constraint information corresponding to each signal network of the PCB board to be designed is determined. By determining the via constraint information, it is convenient to determine the cost function of each signal network of the PCB board to be designed based on the via constraint information.

[0141] In one embodiment, step S220 involves determining the dynamic rule information corresponding to each signal network of the PCB board to be designed based on the rule matrix, including:

[0142] Step S225: Based on the rule matrix, determine the line width rules and spacing rules of each signal network of the PCB board to be designed.

[0143] Step S226: Based on the line width rules and spacing rules of each signal network of the PCB board to be designed, the cost weight of the line width rules of each signal network of the PCB board to be designed, the cost weight of the spacing rules of each signal network of the PCB board to be designed, and the wiring density of each wiring area of ​​the PCB board to be designed, determine the dynamic rule information corresponding to each signal network of the PCB board to be designed.

[0144] In practical design, due to constraints such as space, both line width and spacing have room for variation. The impact of line width on cost varies at high spatial densities. Therefore, dynamic rule information corresponding to each signal network of the PCB board to be designed can be determined based on line width and spacing rules. The cost weight of the aforementioned line width rule can serve as a representation of the degree of influence of line width rules on cost during the PCB board design process. Similarly, the cost weight of the aforementioned spacing rule can serve as a representation of the degree of influence of spacing rules on cost during the PCB board design process.

[0145] Specifically, determine the dynamic rule information corresponding to each signal network of the PCB board to be designed. The process is as follows:

[0146] ;

[0147] in, Cost weight for linewidth rules As the cost weight of the spacing rule, R represents the component density in the wiring area. w For the trace width rules of the PCB board to be designed, R s The above wiring density is related to the spacing rules of the PCB board to be designed, and is related to wiring, vias, component pads, etc.

[0148] Steps S225 to S226 above determine the linewidth and spacing rules of each signal network of the PCB board to be designed based on the rule matrix. Then, based on the linewidth and spacing rules of each signal network of the PCB board to be designed, the cost weight of the linewidth rules of each signal network of the PCB board to be designed, the cost weight of the spacing rules of each signal network of the PCB board to be designed, and the wiring density of each wiring area of ​​the PCB board to be designed, the dynamic rule information corresponding to each signal network of the PCB board to be designed is determined. By determining the dynamic rule information, it is convenient to determine the cost function of each signal network of the PCB board to be designed based on the dynamic rule information.

[0149] In one embodiment, step S230, based on wiring layer constraint information, via constraint information, and dynamic rule information, determines the cost function of each signal network of the PCB board to be designed, including:

[0150] Step S231: Based on the routing layer constraint information, determine the layer cost corresponding to the routing layer of each signal network of the PCB board to be designed.

[0151] The aforementioned layer cost refers to the cost incurred in routing on a specific routing layer during PCB design, reflecting the expense of routing on different layers. This layer cost can include manufacturing costs, design complexity, and signal integrity impacts.

[0152] The above-mentioned determination of the layer cost corresponding to the routing layer of each signal network of the PCB board to be designed based on routing layer constraint information can be based on the routing layer constraint information to determine which layers each signal network can be routed on, as well as the routing rules on these layers, and comprehensively consider the impact of manufacturing cost, design complexity and signal integrity to calculate the layer cost of each signal network on different routing layers.

[0153] Step S232: Based on the via constraint information, determine the via cost of each signal network of the PCB board to be designed.

[0154] The via cost mentioned above refers to the cost and complexity incurred by using vias in the design. This via cost includes not only manufacturing costs but also aspects such as signal integrity, routing efficiency, and reliability. The determination of the via cost for each signal network of the PCB board under design based on via constraint information can be achieved by comprehensively considering manufacturing costs, signal integrity impact, and design complexity to calculate the via cost for each signal network.

[0155] This embodiment determines the via cost of each signal network based on via constraint information, which can optimize PCB design, reduce overall cost, and improve performance.

[0156] Step S233: Based on dynamic rule information, determine the rule cost corresponding to each signal network of the PCB board to be designed.

[0157] The aforementioned rule cost refers to the cost incurred in routing design under the premise of satisfying dynamic rule information. Rule cost includes not only direct manufacturing costs but also design complexity, signal integrity, and manufacturability. The determination of the rule cost corresponding to each signal network of the PCB board to be designed based on dynamic rule information can be achieved by evaluating manufacturing costs, design complexity costs, signal integrity costs, and manufacturability costs (costs related to PCB manufacturing processes, such as the increased manufacturing difficulty caused by excessively small trace widths or spacing), comprehensively considering all these components to calculate the rule cost corresponding to each signal network.

[0158] Step S234: Based on the layer cost, via cost, and rule cost corresponding to the routing layer, as well as the single-step execution cost during pathfinding, determine the quality cost in the basic cost of automatic routing of each signal network of the PCB board to be designed.

[0159] In this step, the aforementioned quality cost refers to the cost related to design quality in PCB design when the routing scheme meets design rules and constraints. It reflects the quality of the routing scheme in terms of signal integrity, electrical performance, and manufacturability. A lower quality cost indicates that the routing scheme better meets design requirements and the design quality is higher. A higher quality cost indicates that the routing scheme is less likely to meet design requirements and the design quality is lower. The aforementioned single-step execution cost refers to the cost of each step in the routing process, which may be related to the length and complexity of the routing path.

[0160] The above-mentioned quality cost is determined from the basic cost of automatic routing of each signal network on the PCB board to be designed, based on the layer cost, via cost, and rule cost corresponding to the routing layer, as well as the single-step execution cost during pathfinding. The process is as follows:

[0161] ;

[0162] in, The cost of the layer corresponding to the routing layer. For via cost, For the cost of the rules, This represents the single-step execution cost during pathfinding.

[0163] Step S235: Based on the movement cost corresponding to the area where each signal network of the PCB board to be designed is located, the fixed cost of changing the layer of the same group of signal networks of the PCB board to be designed, and the number of layers of each signal network of the PCB board to be designed, determine the efficiency cost in the basic cost of automatic routing of each signal network of the PCB board to be designed.

[0164] The efficiency cost mentioned above refers to the cost related to design efficiency during the automated routing process of PCB design, where the routing scheme meets design rules and constraints. This efficiency cost reflects the advantages and disadvantages of the routing scheme in terms of utilizing routing space and reducing the number of layer changes. Lower efficiency costs indicate a more efficient routing scheme and higher design efficiency. Higher efficiency costs indicate a less efficient routing scheme and lower design efficiency. The movement cost mentioned above reflects the distance the signal network moves within the routing area and can be determined based on the area where the signal network is located and the routing path. The fixed layer change cost mentioned above reflects the fixed cost of changing layers between different routing layers for the signal network. This fixed layer change cost can be calculated based on the fixed cost of changing layers for the same group of signal networks. Because changing layers for the same group of signal networks may require additional routing space and vias, increasing fixed costs, it is necessary to determine the fixed cost of changing layers for the same group of signal networks. Since signal networks may need to change layers multiple times during routing, the cost of changing layers can be determined by multiplying the number of layer changes by the fixed cost of changing layers for the same group of signal networks when calculating efficiency costs.

[0165] Based on this, the efficiency cost in the basic cost of automatic routing of each signal network of the PCB board under design is determined by considering the movement cost corresponding to the region where each signal network of the PCB board under design is located, the fixed cost of layer switching of the same group of signal networks of the PCB board under design, and the number of layer switching of each signal network of the PCB board under design. The process is as follows:

[0166] ;

[0167] in, The movement cost corresponding to the area where each signal network of the PCB board to be designed is located. The fixed cost of switching layers for the same group of signal networks on the PCB board to be designed. The number of layers for each signal network on the PCB board to be designed.

[0168] This step involves calculating efficiency and cost. Efficiency and cost not only help optimize routing schemes but also allow for the selection of the optimal solution from multiple feasible options. By appropriately adjusting the weights of each cost component, design efficiency and cost can be balanced, thereby achieving efficient PCB design.

[0169] Step S236: Based on the Harmanton distance cost, the fixed cost of switching layers of the same group of signal networks on the PCB board to be designed, and the relationship between the current layer of each signal network on the PCB board to be designed and the target layer corresponding to the group to which each signal network belongs, determine the heuristic cost of automatic routing of each signal network on the PCB board to be designed.

[0170] The aforementioned heuristic cost can be used in PCB design to predict the cost of future routing paths based on the difference between the current routing state and the target routing state. The aforementioned Manhattan distance cost can be used to measure the difference between the current routing state and the target routing state. The Manhattan distance refers to the number of different characters at corresponding positions between two strings of equal length. In PCB routing, this can be extended to measure the difference between the current routing path and the target routing path. For example, if the current path and the target path have 3 different points, then the Manhattan distance is 3. The aforementioned Manhattan distance cost is equal to the Manhattan distance multiplied by a weighting factor. This weighting factor can be set as needed; this embodiment does not impose specific limitations on it.

[0171] The relationship between the current layer and the target layer corresponding to each signal network group can be used to measure the difference between the current routing layer of the signal network and the target routing layer. Based on the Harmanton distance cost, the fixed cost of changing layers for signal networks in the same group on the PCB under design, and the relationship between the current layer of each signal network on the PCB under design and the target layer corresponding to each signal network group, the heuristic cost of automatic routing for each signal network on the PCB under design is determined. The calculation process is as follows:

[0172] ;

[0173] The above For Harmanton distance cost, This defines the relationship between the current layer of each signal network in the PCB board to be designed and the target layer corresponding to the group to which each signal network belongs. The fixed cost of changing the layer of the same group of signal networks on the PCB board to be designed.

[0174] Steps S231 to S236 above determine the cost function of each signal network of the PCB board to be designed by determining the quality cost, efficiency cost, and heuristic cost of the automatic routing of each signal network of the PCB board to be designed. The determination of the cost function facilitates further optimization of the cost function to obtain an optimized cost function, thereby realizing the high-speed bus routing during the automatic design of the PCB board.

[0175] Additionally, in one embodiment, prior to step S230, the following steps are included:

[0176] Step S227: Based on the high-speed bus database of components and materials corresponding to the design task of the PCB board to be designed, determine the net name corresponding to each pin of the PCB board to be designed, and the net group to which the net name corresponding to each pin belongs.

[0177] Step S228: Based on the net names of each pin of the PCB board to be designed and the net groups to which the net names of each pin belong, determine the grouping results of all pins of the PCB board to be designed at the net level.

[0178] The aforementioned network group can be multiple signal groups formed by classifying the signal networks on the PCB board according to their electrical characteristics and functions.

[0179] Step S229: Based on the grouping results of all pins of the PCB board to be designed at the network level, determine the network grouping results of each signal network of the PCB board to be designed.

[0180] The above-mentioned grouping results of all pins of the PCB board under design at the network layer determine the network grouping results of each signal network on the PCB board under design. This can be achieved by defining network grouping rules based on the pin grouping results, and then assigning each signal network to the corresponding group according to the defined grouping rules. The aforementioned network grouping rules can be based on the grouping results of signal type, electrical characteristics, or functional modules.

[0181] Steps S227 to S229 above determine the net names corresponding to each pin of the PCB board to be designed, and the net groups to which each net name belongs, based on the high-speed bus database of the components and materials corresponding to the design task of the PCB board to be designed. This determines the network grouping results of each signal net of the PCB board to be designed. Determining the network grouping results of the signal nets facilitates the subsequent determination of the high-speed bus grouping strategy for the PCB board to be designed based on these results.

[0182] In one embodiment, after determining the network grouping results of each signal network of the PCB board to be designed, the method further includes:

[0183] Step S2: Based on the network information of the current signal network group, the average distance between the path segment of the current signal network and the path segments of other signal networks in the same group, the consistency between the layer of the path segment of the current signal network and the layer of the path segments of other signal networks in the same group, and the degree of matching between the path direction of the current signal network and the path direction of the path segments of other signal networks in the same group, determine the group strategy of the high-speed bus of the PCB board to be designed.

[0184] Besides basic routing layers, vias, and rules, the main difference between high-speed bus routing and general routing lies in the need to establish classification information for the bus groups to which the routing networks belong. This allows for the execution of appropriate automatic routing strategies within the same bus group. The key characteristics of high-speed bus routing are based on the requirements of high-speed signal routing on a single network. This necessitates that the entire group of routing paths be similar, the routing should ideally be within the same group and layer, and the routing should be located in adjacent areas. Therefore, it is necessary to determine the grouping strategy for the high-speed buses on the PCB board to be designed. The grouping strategy for the high-speed buses on the PCB board to be designed can be to group high-speed signal networks with similar electrical characteristics and functions together and define unified routing rules and constraints for these signal networks.

[0185] The above describes the grouping strategy for determining the high-speed bus of the PCB board to be designed. The specific process is as follows:

[0186] ;

[0187] in, This refers to the network information of the current signal network group. This represents the average distance between the path segment containing the current signal network and the path segments containing other signal networks in the same group. This ensures consistency between the layer where the current signal network's path segment resides and the layers where the path segments of other signal networks in the same group reside. This represents the degree of matching between the path direction of the current signal network's path segment and the path directions of other signal networks in the same group.

[0188] Step S4: Based on the group strategy of the high-speed bus of the PCB board to be designed, determine the fixed cost of switching layers of the same group of signal networks of the PCB board to be designed, as well as the relationship between the current layer of each signal network of the PCB board to be designed and the target layer corresponding to the group to which each signal network belongs.

[0189] The above-mentioned group strategy based on the high-speed bus of the PCB board to be designed determines the fixed cost of switching layers of the same group of signal networks on the PCB board to be designed, as well as the relationship between the current layer of each signal network on the PCB board to be designed and the target layer corresponding to the group to which each signal network belongs. It can be calculated according to the switching rules in the group strategy, the fixed cost of switching layers of the same group of signal networks is calculated, and the current layer and target layer of the signal network are used to determine whether a layer switch is needed and the cost of the layer switch.

[0190] Steps S2 to S4 above determine the group strategy of the high-speed bus of the PCB board to be designed. Based on the group strategy of the high-speed bus of the PCB board to be designed, the fixed cost of switching layers of the same group of signal networks of the PCB board to be designed is determined, as well as the relationship between the current layer of each signal network of the PCB board to be designed and the target layer corresponding to the group to which each signal network belongs. This facilitates the subsequent determination of the cost function of each signal network of the PCB board to be designed based on the fixed cost of switching layers of the same group of signal networks of the PCB board to be designed and the relationship between the current layer of each signal network of the PCB board to be designed and the target layer corresponding to the group to which each signal network belongs.

[0191] The present embodiment will now be described and illustrated through preferred embodiments.

[0192] Figure 3 This is a flowchart of a high-speed bus routing method provided in a preferred embodiment of this application, applied to the automated design process of a PCB board. Figure 3 As shown, the wiring method for this high-speed bus includes the following steps:

[0193] Step S301: Determine the routing layer structure matrix, via matrix, and rule matrix of each signal network of the PCB board to be designed;

[0194] Step S302: Based on the layer structure of the PCB board to be designed and the preset routing layer rules, determine the priority of each routing layer in the PCB board to be designed.

[0195] Step S303: Based on the priority of each routing layer in the PCB board to be designed and the routing layer structure matrix, determine the routing layer constraint information corresponding to each signal network of the PCB board to be designed.

[0196] Step S304: Based on the via matrix, determine the number of vias for each signal network of the PCB board to be designed during actual routing.

[0197] Step S305: Based on the via priority of the PCB board to be designed and the number of vias in the actual routing of each signal network, determine the via constraint information corresponding to each signal network of the PCB board to be designed.

[0198] Step S306: Based on the rule matrix, determine the line width rules and spacing rules of each signal network of the PCB board to be designed;

[0199] Step S307: Based on the line width rules and spacing rules of each signal network of the PCB board to be designed, the cost weight of the line width rules of each signal network of the PCB board to be designed, the cost weight of the spacing rules of each signal network of the PCB board to be designed, and the wiring density of each wiring area of ​​the PCB board to be designed, determine the dynamic rule information corresponding to each signal network of the PCB board to be designed.

[0200] Step S308: Based on routing layer constraint information, via constraint information, and dynamic rule information, determine the cost function of each signal network of the PCB board to be designed; the cost function includes the basic cost and heuristic cost of each signal network of the PCB board to be designed; the basic cost includes quality cost and efficiency cost.

[0201] Step S309: Use the A* algorithm to perform path optimization on the cost function to obtain the optimized cost function of each signal network of the PCB board to be designed.

[0202] Step S310: Based on the optimized cost function of each signal network of the PCB board to be designed, automatically design the PCB board to be designed.

[0203] Steps S301 to S310 above determine the routing layer structure matrix, via matrix, and rule matrix of each signal network of the PCB board to be designed. Based on each matrix, the routing layer constraint information, via constraint information, and dynamic rule information corresponding to each signal network are determined. Then, the cost function of each signal network of the PCB board to be designed is determined, and the A* algorithm is used to optimize the cost function so that the optimized cost function can be used for the automatic design of the high-speed bus of the PCB board, thus realizing the automatic design of the high-speed bus of the PCB board.

[0204] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0205] Based on the same inventive concept, this embodiment also provides a high-speed bus wiring device for implementing the above embodiments and preferred embodiments, which will not be repeated as already described. The terms "module," "unit," "subunit," etc., used below can refer to a combination of software and / or hardware that performs a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0206] In one embodiment, Figure 4 This is a structural block diagram of a high-speed bus wiring device provided in an embodiment of this application, as shown below. Figure 4 As shown, the high-speed bus routing device, applied in the automated design process of PCB boards, includes:

[0207] The matrix determination module 41 is used to determine the routing layer structure matrix, via matrix, and rule matrix of each signal network of the PCB board to be designed.

[0208] The constraint determination module 42 is used to determine the routing layer constraint information corresponding to each signal network of the PCB board to be designed based on the routing layer structure matrix; to determine the via constraint information corresponding to each signal network of the PCB board to be designed based on the via matrix; and to determine the dynamic rule information corresponding to each signal network of the PCB board to be designed based on the rule matrix.

[0209] The cost function determination module 43 is used to determine the cost function of each signal network of the PCB board to be designed based on routing layer constraint information, via constraint information, and dynamic rule information. The cost function includes the basic cost and heuristic cost of each signal network of the PCB board to be designed. The basic cost includes quality cost and efficiency cost.

[0210] The optimization module 44 is used to perform path optimization on the cost function using the A* algorithm to obtain the optimized cost function of each signal network of the PCB board to be designed.

[0211] And an automatic design module 45, used to automatically design the PCB board to be designed based on the optimized cost function of each signal network of the PCB board to be designed.

[0212] The aforementioned high-speed bus routing device determines the routing layer structure matrix, via matrix, and rule matrix of each signal network of the PCB board to be designed. Based on these matrices, it determines the routing layer constraint information, via constraint information, and dynamic rule information corresponding to each signal network. Subsequently, it determines the cost function of each signal network of the PCB board to be designed and uses the A* algorithm to optimize the cost function. The optimized cost function can be used for the automatic design of the high-speed bus of the PCB board, thus realizing the automatic design of the high-speed bus of the PCB board.

[0213] It should be noted that the above modules can be functional modules or program modules, and can be implemented through software or hardware. For modules implemented through hardware, the above modules can reside in the same processor; or the above modules can be located in different processors in any combination.

[0214] In one embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement any of the high-speed bus wiring methods described in the above embodiments.

[0215] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0216] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0217] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A high-speed bus routing method, applied to the automated design process of PCB boards, characterized in that, The method includes: Determine the routing layer structure matrix, via matrix, and rule matrix of each signal network of the PCB board to be designed; Based on the routing layer structure matrix, the routing layer constraint information corresponding to each signal network of the PCB board to be designed is determined; based on the via matrix, the via constraint information corresponding to each signal network of the PCB board to be designed is determined; based on the rule matrix, the dynamic rule information corresponding to each signal network of the PCB board to be designed is determined. Based on the wiring layer constraint information, the via constraint information, and the dynamic rule information, the cost function of each signal network of the PCB board to be designed is determined; the cost function includes the basic cost and heuristic cost of each signal network of the PCB board to be designed; the basic cost includes quality cost and efficiency cost; The A* algorithm is used to perform path optimization on the cost function to obtain the optimized cost function of each signal network of the PCB board to be designed. The PCB board to be designed is automatically designed based on the optimized cost function of each signal network of the PCB board to be designed.

2. The high-speed bus wiring method according to claim 1, characterized in that, The process of determining the routing layer structure matrix of each signal network of the PCB board to be designed includes: Based on the structural information of each routing layer of the PCB board to be designed, the information of the recommended routing layer among all routing layers of the PCB board to be designed, the routing layer where the pads of each network node of the PCB board to be designed are located, and the routing priority of the routing layer corresponding to each network node of the PCB board to be designed, the routing layer structure matrix of each signal network of the PCB board to be designed is determined.

3. The high-speed bus wiring method according to claim 1, characterized in that, The process of determining the via matrix of each signal network of the PCB board to be designed includes: Obtain the design requirements of the PCB board to be designed; Based on the obtained design requirements of the PCB board to be designed, the high-speed bus database of the components and materials corresponding to the PCB board to be designed is determined; the high-speed bus database of components and materials includes network name and signal protocol type; Based on the high-speed bus database of the device materials corresponding to the PCB board to be designed, determine the signal protocol type corresponding to the network name of each signal network of the PCB board to be designed; Based on the signal protocol type corresponding to the network name of each signal network of the PCB board to be designed, determine the via impedance, via size and maximum number of vias corresponding to each signal network of the PCB board to be designed. Based on the via impedance, via size, and maximum number of vias corresponding to each signal network of the PCB board to be designed, the via matrix of each signal network of the PCB board to be designed is determined.

4. The high-speed bus wiring method according to claim 3, characterized in that, The step of determining the high-speed bus database of components and materials corresponding to the PCB board to be designed based on the obtained design requirements of the PCB board to be designed includes: Based on the obtained design requirements of the PCB board to be designed, the material code corresponding to the PCB board to be designed is determined; Based on the material code corresponding to the PCB board to be designed, the high-speed bus database of the device material corresponding to the PCB board to be designed is selected from the preset electronic material information database; the preset electronic material information database is a pre-stored database of correspondence between each material code and the high-speed bus database of device material.

5. The high-speed bus wiring method according to claim 1, characterized in that, The rule matrix for determining each signal network of the PCB board to be designed includes: Based on the line width and spacing rules of the PCB board to be designed, the rule matrix of each signal network of the PCB board to be designed is determined.

6. The high-speed bus wiring method according to claim 1, characterized in that, The step of determining the routing layer constraint information corresponding to each signal network of the PCB board to be designed based on the routing layer structure matrix includes: Based on the layer structure of the PCB board to be designed and the preset routing layer rules, the priority of each routing layer in the PCB board to be designed is determined. Based on the priority of each routing layer in the PCB board to be designed and the routing layer structure matrix, the routing layer constraint information corresponding to each signal network of the PCB board to be designed is determined.

7. The high-speed bus wiring method according to claim 1, characterized in that, The step of determining the via constraint information corresponding to each signal network of the PCB board to be designed based on the via matrix includes: Based on the via matrix, the number of vias for each signal network of the PCB board to be designed during actual routing is determined. Based on the via priority of the PCB board to be designed and the number of vias for each signal network during actual routing, the via constraint information corresponding to each signal network of the PCB board to be designed is determined.

8. The high-speed bus wiring method according to claim 1, characterized in that, The step of determining the dynamic rule information corresponding to each signal network of the PCB board to be designed based on the rule matrix includes: Based on the rule matrix, the line width rules and spacing rules of each signal network of the PCB board to be designed are determined; Based on the linewidth and spacing rules of each signal network of the PCB board to be designed, the cost weight of the linewidth rules of each signal network of the PCB board to be designed, the cost weight of the spacing rules of each signal network of the PCB board to be designed, and the wiring density of each wiring area of ​​the PCB board to be designed, the dynamic rule information corresponding to each signal network of the PCB board to be designed is determined.

9. The high-speed bus wiring method according to claim 1, characterized in that, The step of determining the cost function of each signal network of the PCB board to be designed based on the wiring layer constraint information, the via constraint information, and the dynamic rule information includes: Based on the routing layer constraint information, the layer cost corresponding to the routing layer of each signal network of the PCB board to be designed is determined. Based on the via constraint information, the via cost of each signal network of the PCB board to be designed is determined; Based on the dynamic rule information, the rule cost corresponding to each signal network of the PCB board to be designed is determined; Based on the layer cost corresponding to the routing layer, the via cost, the rule cost, and the single-step execution cost during pathfinding, the quality cost in the basic cost of automatic routing of each signal network of the PCB board to be designed is determined. Based on the movement cost corresponding to the area where each signal network of the PCB board to be designed is located, the fixed cost of changing the layer of the same group of signal networks of the PCB board to be designed, and the number of layers of each signal network of the PCB board to be designed, the efficiency cost in the basic cost of automatic routing of each signal network of the PCB board to be designed is determined. Based on the Harmanton distance cost, the fixed cost of switching layers of the same group of signal networks on the PCB board to be designed, and the relationship between the current layer of each signal network on the PCB board to be designed and the target layer corresponding to the group to which each signal network belongs, the heuristic cost of automatic routing of each signal network on the PCB board to be designed is determined.

10. The high-speed bus wiring method according to claim 1, characterized in that, Before determining the cost function of each signal network of the PCB board to be designed based on the wiring layer constraint information, the via constraint information, and the dynamic rule information, the process includes: Based on the high-speed bus database of components and materials corresponding to the design task of the PCB board to be designed, determine the net name corresponding to each pin of the PCB board to be designed, and the net group to which the net name corresponding to each pin belongs. Based on the net names of each pin of the PCB board to be designed, and the net group to which the net name of each pin belongs, the grouping result of all pins of the PCB board to be designed at the net level is determined. Based on the grouping results of all pins of the PCB board to be designed at the network level, the network grouping results of each signal network of the PCB board to be designed are determined.

11. The high-speed bus wiring method according to claim 10, characterized in that, After determining the network grouping results of each signal network of the PCB board to be designed, the method further includes: Based on the network information of the current signal network group, the average distance between the path segment of the current signal network and the path segments of other signal networks in the same group, the consistency between the layer of the path segment of the current signal network and the layer of the path segments of other signal networks in the same group, and the degree of matching between the path direction of the path segment of the current signal network and the path direction of the path segments of other signal networks in the same group, the group strategy of the high-speed bus of the PCB board to be designed is determined. Based on the high-speed bus group strategy of the PCB board to be designed, the fixed cost of switching layers of the same group of signal networks of the PCB board to be designed is determined, as well as the relationship between the current layer of each signal network of the PCB board to be designed and the target layer corresponding to the group to which each signal network belongs.

12. A high-speed bus wiring device, applied in the automated design process of PCB boards, characterized in that, The device includes: The matrix determination module is used to determine the routing layer structure matrix, via matrix, and rule matrix of each signal network of the PCB board to be designed. The constraint determination module is used to determine, based on the routing layer structure matrix, the routing layer constraint information corresponding to each signal network of the PCB board to be designed; based on the via matrix, the via constraint information corresponding to each signal network of the PCB board to be designed; and based on the rule matrix, the dynamic rule information corresponding to each signal network of the PCB board to be designed. The cost function determination module is used to determine the cost function of each signal network of the PCB board to be designed based on the wiring layer constraint information, the via constraint information, and the dynamic rule information; the cost function includes the basic cost and the heuristic cost of each signal network of the PCB board to be designed; the basic cost includes quality cost and efficiency cost; The optimization module is used to perform path optimization on the cost function using the A* algorithm to obtain the optimized cost function of each signal network of the PCB board to be designed. And an automatic design module, used to automatically design the PCB board to be designed based on the optimized cost function of each of the signal networks of the PCB board to be designed.

13. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the high-speed bus wiring method according to any one of claims 1 to 11.

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