A high-bandwidth memory module based on DRAM

Abstract

This invention discloses a high-bandwidth memory module based on DRAM. The memory module includes a substrate, a conversion module, and a DRAM module die. The DRAM module die is electrically connected to a first surface of the substrate, and the first surface of the substrate is electrically connected to the conversion module. The conversion module processes the signals exchanged between the DRAM module die and the outside world to improve the signal transmission rate of signal interaction between the DRAM module die and the outside world. This invention can improve the bandwidth of DRAM-based memory modules to varying degrees according to actual needs, is compatible with existing DRAM module dies, has a simple structure and process, high flexibility, is easy to mass-produce and promote on a large scale, and has good application prospects.

Description

Technical Field

[0001] This invention belongs to the field of memory technology, and more specifically, relates to a high-bandwidth memory module based on DRAM. Background Technology

[0002] Low Power Double Data Rate (LPDDR) SDRAM is a type of DDR SDRAM. It's a communication standard developed by the JEDEC Solid State Technology Association for low-power memory, renowned for its low power consumption, and primarily used in mobile electronic products. Compared to DDR and GDDR, LPDDR's biggest advantage is its even lower power consumption. LPDDR also comes in various generations, including MDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR4X, LPDDR5, and LPDDR5X. Like DDR, its data processing speed and energy efficiency improve with each generation.

[0003] With the continuous development of mobile electronic products, the demand for processing large amounts of data is gradually increasing, thus placing higher demands on data processing speed. In addition to reducing power consumption, how to improve bandwidth has become an urgent problem to be solved in the future development of SDRAM. Summary of the Invention

[0004] In view of the above-mentioned defects or improvement needs of the existing technology, the present invention provides a high-bandwidth memory module based on DRAM, which can improve the bandwidth of DRAM-based memory modules to varying degrees according to actual needs, is compatible with existing DRAM module dies, has a simple structure and process, high flexibility, is easy to achieve mass production and large-scale promotion, and has good application prospects.

[0005] To achieve the above objectives, according to one aspect of the present invention, a storage module is provided, comprising: a substrate, a conversion module, and a DRAM module die; the DRAM module die is electrically connected to a first surface of the substrate, and the first surface of the substrate is electrically connected to the conversion module; the conversion module and the DRAM module die interact with each other via the substrate and the first surface of the substrate; the conversion module interacts with the outside world via the substrate, the first surface of the substrate, and a second surface opposite to the first surface; the conversion module processes the signals exchanged between the DRAM module die and the outside world to improve the signal transmission rate of the signal interaction between the DRAM module die and the outside world.

[0006] In some implementations, the conversion module includes a parallel-to-serial conversion module and a serial-to-parallel conversion module; in the write operation, the serial-to-parallel conversion module is used to perform serial-to-parallel conversion on the data signal DQ, and to perform serial-to-parallel conversion on the global clock signal CK and the command / address signal CA; in the read operation, the parallel-to-serial conversion module is used to perform parallel-to-serial conversion on the data signal DQ, and the serial-to-parallel conversion module is used to perform serial-to-parallel conversion on the global clock signal CK and the command / address signal CA.

[0007] In some implementations, during a write operation, the serial-to-parallel conversion module is also used to perform a serial-to-parallel conversion operation on the write clock signal WCK; during a read operation, the serial-to-parallel conversion module is also used to perform a serial-to-parallel conversion operation on the write clock signal WCK, and the parallel-to-serial conversion module is also used to perform a parallel-to-serial conversion operation on the read data strobe signal RDQS.

[0008] In some implementations, during a write operation, the serial-to-parallel conversion module is also used to perform a serial-to-parallel conversion operation on the write clock signal WCK; during a read operation, the parallel-to-serial conversion module is also used to perform a parallel-to-serial conversion operation on the read data strobe signal RDQS.

[0009] In some implementations, during a write operation, the serial-to-parallel conversion module is also used to perform a serial-to-parallel conversion operation on the data strobe signal DQS; during a read operation, the parallel-to-serial conversion module is also used to perform a parallel-to-serial conversion operation on the data strobe signal DQS.

[0010] In some implementations, the parallel-to-serial conversion ratio of the parallel-to-serial module is N:1, and the serial-to-parallel conversion ratio of the serial-to-parallel module is 1:N, where N>1 and N is an integer.

[0011] In some implementations, the parallel-to-serial module is used to convert each of the N parallel low-speed signals output from the DRAM module die into a single serial high-speed signal before outputting it; the serial-to-parallel module is used to convert each externally input serial high-speed signal into N parallel low-speed signals before outputting them to the DRAM module die.

[0012] In some implementations, the signal between the DRAM module die and the conversion module has a first transmission rate v1, and the signal between the conversion module and the outside world has a second transmission rate v2, the second transmission rate v2 being N times the first transmission rate v1.

[0013] In some implementations, the data signal DQ between the DRAM module die and the conversion module has a first data transmission rate v1(DQ), and the data signal DQ between the conversion module and the outside world has a second data transmission rate v2(DQ), the second data transmission rate v2(DQ) being N times the first data transmission rate v1(DQ); the global clock signal CK between the DRAM module die and the conversion module has a first clock transmission rate v1(CK), and the global clock signal CK between the conversion module and the outside world has a second clock transmission rate v2(CK), the second clock transmission rate v2(CK) being N times the first clock transmission rate v1(CK); the command / address signal CA between the DRAM module die and the conversion module has a first command / address transmission rate v1(CA), and the command / address signal CA between the conversion module and the outside world has a second command / address transmission rate v2(CA), the second command / address transmission rate v2(CA) being N times the first command / address transmission rate v1(CA).

[0014] In some implementations, the write clock signal WCK between the DRAM module die and the conversion module has a first write clock transmission rate v1(WCK), and the write clock signal WCK between the conversion module and the outside world has a second write clock transmission rate v2(WCK), the second write clock transmission rate v2(WCK) being N times the first write clock transmission rate v1(WCK); the read data strobe signal RDQS between the DRAM module die and the conversion module has a first read data strobe transmission rate v1(RDQS), and the read data strobe signal RDQS between the conversion module and the outside world has a second read data strobe transmission rate v2(RDQS), the second read data strobe transmission rate v2(RDQS) being N times the first read data strobe transmission rate v1(RDQS).

[0015] In some implementations, the data strobe signal DQS between the DRAM module die and the conversion module has a first data strobe transmission rate v1 (DQS), and the data strobe signal DQS between the conversion module and the outside world has a second data strobe transmission rate v2 (DQS), the second data strobe transmission rate v2 (DQS) being N times the first data strobe transmission rate v1 (DQS).

[0016] In some implementations, the DRAM module die includes a single-layer DRAM die or multiple stacked DRAM dies; the parallel-to-serial converter is used to convert N parallel low-speed signals from the same DRAM die into one serial high-speed signal and then output it; the serial-to-parallel converter is used to convert each externally input serial high-speed signal into N parallel low-speed signals and then output them to the same DRAM die.

[0017] In some implementations, the DRAM module die includes multiple stacked DRAM dies; the parallel-to-serial converter is used to convert each N parallel low-speed signal from different DRAM dies into a single serial high-speed signal before outputting it; the serial-to-parallel converter is used to convert each externally input serial high-speed signal into N parallel low-speed signals before outputting them to different DRAM dies.

[0018] In some implementations, the parallel-to-serial module is used to convert each of the N parallel low-speed signals from the N DRAM dies into a single serial high-speed signal and then output it; the serial-to-parallel module is used to convert each externally input serial high-speed signal into N parallel low-speed signals and then output them to the N DRAM dies respectively.

[0019] In some implementations, the DRAM module die includes a single-layer DRAM die or multiple stacked DRAM dies; the DRAM die is connected to the substrate by wire bonding, and the conversion module and the substrate are packaged using FC (Folded Conversion) method.

[0020] In some embodiments, the DRAM module die is connected to a first side of a substrate via conductive lines. The first side of the substrate is connected to a conversion module via multiple first conductive contacts and multiple second conductive contacts. A second side of the substrate is provided with multiple third conductive contacts. The conversion module and the DRAM module die interact with each other via multiple first conductive contacts, the substrate, and conductive lines. The conversion module interacts with the outside world via multiple second conductive contacts, the substrate, and multiple third conductive contacts.

[0021] In some implementations, the conversion module and the DRAM module die are stacked sequentially on the substrate, with the conversion module disposed between the substrate and the DRAM module die.

[0022] According to another aspect of the present invention, a storage module is provided, including a substrate, a plurality of conversion modules and a plurality of DRAM module dies; the plurality of conversion modules and the plurality of DRAM module dies correspond one-to-one, and the plurality of conversion modules are respectively disposed between the substrate and the corresponding DRAM module dies to form a plurality of stacked structures, each stacked structure being disposed at a different position on the substrate.

[0023] In each stacked structure, the DRAM module die forms a conductive connection with the first side of the substrate, and the first side of the substrate forms a conductive connection with the conversion module. The conversion module and the DRAM module die interact with each other through the substrate and the first side of the substrate. The conversion module interacts with the outside world through the substrate, the first side of the substrate, and the second side opposite to the first side. The conversion module is used to process the signals between the DRAM module die and the outside world to improve the signal transmission rate of the DRAM module die interacting with the outside world.

[0024] In some implementations, each stacked structure includes a parallel-to-serial conversion module and a serial-to-parallel conversion module. The parallel-to-serial conversion module converts each of the N parallel low-speed signals output from the DRAM module die into a single high-speed serial signal before outputting it. The serial-to-parallel conversion module converts each externally input high-speed serial signal into N parallel low-speed signals before outputting them to the DRAM module die. Here, N > 1 and N is an integer.

[0025] In some implementations, multiple DRAM module dies are connected to the substrate by wire bonding, and multiple conversion modules and the substrate are packaged using FC (Folded Conversion) method.

[0026] In summary, compared with the prior art, the above-described technical solution conceived by this invention has the following beneficial effects: A conversion module is set between the DRAM module die and the substrate, which improves the signal transmission rate between the DRAM module die and the processor (e.g., CPU or GPU), thereby increasing the bandwidth of the memory module; it is compatible with inexpensive wire bonding packaging, removing the limitation on signal transmission speed imposed by inexpensive wire bonding packaging, and balancing low cost and high bandwidth requirements; the conversion module includes parallel-to-serial and serial-to-parallel modules, and the parallel-to-serial conversion ratio of the conversion module can be set according to actual needs to improve the bandwidth of the memory module to varying degrees; based on readily available DRAM module dies, the conversion module is also easy to modularize and mass-produce, resulting in a high-bandwidth memory module with a simple structure that is not restricted by JEDEC standards. It facilitates the formation of multiple stacked structures using DRAM module dies and conversion modules, which can be packaged together with the substrate, providing greater capacity, higher I / O density, and bandwidth through a single chip, offering high flexibility and promising application prospects. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of a storage module.

[0028] Figure 2 This is a schematic diagram of another type of storage module;

[0029] Figure 3 This is a schematic diagram of signal transmission in a storage module;

[0030] Figure 4 This is a schematic diagram of data signal transmission in a storage module.

[0031] Figure 5 This is a schematic diagram of the structure of a high-bandwidth DRAM-based storage module according to an embodiment of the present invention;

[0032] Figure 6 This is a schematic diagram of the circuit structure of a high-bandwidth storage module based on DRAM according to an embodiment of the present invention;

[0033] Figure 7A This is a schematic diagram of signal transmission in a DRAM-based high-bandwidth storage module according to an embodiment of the present invention;

[0034] Figure 7B This is a schematic diagram of signal transmission of a high-bandwidth DRAM-based storage module according to another embodiment of the present invention;

[0035] Figure 8 This is a schematic diagram of data signal transmission in a high-bandwidth DRAM-based storage module according to an embodiment of the present invention;

[0036] Figure 9 This is a schematic diagram of the structure of a high-bandwidth DRAM-based storage module according to another embodiment of the present invention. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of this application. Therefore, the drawings and description are considered exemplary in nature and not restrictive.

[0038] Figure 1 A memory module structure is presented, including a DRAM module and a substrate. The DRAM module is mounted on the substrate and connected to one side of the substrate via conductive lines. The other side of the substrate is then connected to a PCB board, enabling signal interaction between the DRAM module and a processor (such as a CPU or GPU).

[0039] Figure 2 Another memory module structure is presented, including a DRAM module, a processor (e.g., CPU or GPU), and a substrate. The processor and DRAM module are sequentially mounted on the substrate. The DRAM module is connected to one side of the substrate via conductive lines, and the processor is connected to the same side of the substrate via conductive contacts. The DRAM module and the processor interact with each other via the substrate.

[0040] like Figure 3 As shown, Figure 1 and Figure 2 The DRAM module shown transmits signals to the substrate through two signal channels 301 and 303. The substrate then transmits the signals from these two channels to the processor through a single signal channel 305. Signal channels 301 and 303 have a first transmission rate v1, and signal channel 305 also has a first transmission rate v1; that is, the signals from signal channels 301 and 303 need to be output sequentially. Figure 4As shown, signal channel 301 transmits data A0 and A1 within time t, signal channel 303 transmits data B0 and B1 within time t, and signal channel 305 transmits data A0 and B0 within the first time t and data A1 and B1 within the second time t.

[0041] With the increasing demand for massive data processing Figure 4 The signal transmission method shown is inefficient and cannot meet the needs of large-scale data processing. Therefore, it is urgent to improve the data transmission rate and bandwidth of the storage module. Figure 1 and Figure 2 The structure shown can only rely on the performance improvement of the DRAM module itself, which has great limitations.

[0042] Figure 5 This is a schematic diagram of the structure of a high-bandwidth DRAM-based storage module according to an embodiment of the present invention. Figure 5 As shown, the storage module includes a substrate 501, a conversion module 503, and a DRAM module die 505. The conversion module 503 and the DRAM module die 505 are stacked sequentially on the substrate 501, with the conversion module 503 disposed between the substrate 501 and the DRAM module die 505. The DRAM module die 505 includes multiple stacked DRAM dies. In other embodiments, the DRAM module die is a single-layer DRAM die. Furthermore, the DRAM module die may conform to the JEDEC standard, i.e., it is a standard DRAM module die; or it may not conform to the JEDEC standard, i.e., it is a custom DRAM module die. This invention is not limited thereto.

[0043] The DRAM die in the DRAM module die 505 is connected to the first side of the substrate 501 via conductive lines (only some conductive lines are shown for clarity). The first side of the substrate 501 is then connected to the conversion module 503 via multiple first conductive contacts 509 and multiple second conductive contacts 511. The second side of the substrate 501, opposite to the first side, is provided with multiple third conductive contacts 513. The substrate 501 can be connected to the PCB board via the third conductive contacts 513, thereby enabling signal interaction between the storage module and external sources (such as CPUs or GPUs).

[0044] The conversion module 503 and the DRAM module die 505 interact via multiple first conductive contacts 509, the substrate 501 (with internal wiring in the substrate 501), and conductive lines. The conversion module 503 and the processor interact via multiple second conductive contacts 511, the substrate 501 (with internal wiring in the substrate 501), and multiple third conductive contacts 513. The conversion module 503 processes the signals exchanged between the DRAM module die 505 and the processor to improve the signal transmission rate of their interaction. The conductive lines between the DRAM module die 505 and the substrate 501 include data signal lines and other signal lines. Data signal lines transmit data signals, while other signal lines transmit other signals, such as clock signals and command / address signals, forming corresponding data signal channels, clock signal channels, and command / address signal channels. All signal types achieve increased transmission rates through the conversion module 503.

[0045] During a write operation, the data signal DQ travels from the processor to the DRAM module die 505 via the conversion module 503. During a read operation, the data signal DQ travels from the DRAM module die 505 to the processor via the conversion module 503. In both read and write operations, the global clock signal CK and the command / address signal CA travel from the processor to the DRAM module die 505 via the conversion module 503. In other words, signals are transmitted bidirectionally between the DRAM module die 505 and the processor, i.e., signal interaction occurs.

[0046] In some implementations, the clock signals include a global clock signal CK, a write clock signal WCK, and a read data strobe signal RDQS. During a write operation, the write clock signal WCK travels from the processor to the DRAM module die 505 via the conversion module 503. During a read operation, the write clock signal WCK travels from the processor to the DRAM module die 505 via the conversion module 503. The DRAM module die 505 generates the read data strobe signal RDQS based on the write clock signal WCK, and the read data strobe signal RDQS travels from the DRAM module die 505 to the processor via the conversion module 503. The write clock signal WCK provides a synchronization clock for the write operation, controls the timing of write data transmission, and ensures that data is stably written to the DRAM module die at a predetermined rhythm. The write clock signal WCK also provides a clock reference for the read data, ensuring that the read data strobe signal RDQS is aligned with the timing of the data signal DQ, improving the stability and anti-interference capability of the read operation. The read data strobe signal RDQS provides a synchronization strobe signal for the read operation, outputting synchronously with the read data to help the processor accurately sample the read data. In some implementations, the DRAM module die is an LPDDR module die.

[0047] In some implementations, the clock signals include a global clock signal CK, a write clock signal WCK, and a read data strobe signal RDQS. During a write operation, the write clock signal WCK travels from the processor to the DRAM module die 505 via the conversion module 503. During a read operation, the read data strobe signal RDQS travels from the DRAM module die 505 to the processor via the conversion module 503. The write clock signal WCK provides a synchronization clock for the write operation, controls the timing of write data transmission, and ensures that data is stably written to the DRAM module die at a predetermined rhythm. The read data strobe signal RDQS provides a synchronization strobe signal for the read operation, is output synchronously with the read data, and helps the processor accurately sample the read data. In some implementations, the DRAM module die is a GDDR module die.

[0048] In some implementations, the clock signal includes a global clock signal CK and a data strobe signal DQS. During a write operation, the data strobe signal DQS travels from the processor to the DRAM module die 505 via conversion module 503. During a read operation, the data strobe signal DQS travels from the DRAM module die 505 to the processor via conversion module 503. The data strobe signal DQS provides a real-time synchronization reference for the data signal DQ, resolving timing deviations under high-frequency transmission and ensuring accurate data read / write. In some implementations, the DRAM module die is a DDR module die.

[0049] like Figure 6 As shown, the conversion module 503 includes a parallel-to-serial conversion module and a serial-to-parallel conversion module. During a write operation, the conversion module 503 uses the serial-to-parallel conversion module to perform a serial-to-parallel conversion on the data signal DQ, and also uses the serial-to-parallel conversion module to perform a serial-to-parallel conversion on the global clock signal CK and the command / address signal CA. During a read operation, the conversion module 503 uses the parallel-to-serial conversion module to perform a parallel-to-serial conversion on the data signal DQ, and also uses the serial-to-parallel conversion module to perform a serial-to-parallel conversion on the global clock signal CK and the command / address signal CA.

[0050] In some implementations, during a write operation, the conversion module 503 also utilizes a serial-to-parallel converter to perform a serial-to-parallel conversion on the write clock signal WCK. During a read operation, the conversion module 503 also utilizes a serial-to-parallel converter to perform a serial-to-parallel conversion on the write clock signal WCK, and utilizes a parallel-to-serial converter to perform a parallel-to-serial conversion on the read data strobe signal RDQS.

[0051] In some implementations, during a write operation, the conversion module 503 also utilizes a serial-to-parallel conversion module to perform a serial-to-parallel conversion on the write clock signal WCK. During a read operation, the conversion module 503 also utilizes a parallel-to-serial conversion module to perform a parallel-to-serial conversion on the read data strobe signal RDQS.

[0052] In some implementations, during a write operation, the conversion module 503 also utilizes a serial-to-parallel conversion module to perform a serial-to-parallel conversion on the data strobe signal DQS. During a read operation, the conversion module 503 also utilizes a parallel-to-serial conversion module to perform a parallel-to-serial conversion on the data strobe signal DQS.

[0053] In some implementations, the parallel-to-serial conversion ratio of the conversion module 503 is N:1, that is, the parallel-to-serial conversion ratio of the parallel-to-serial module of the conversion module 503 is N:1, and the serial-to-parallel conversion ratio of the serial-to-parallel module of the conversion module 503 is 1:N, where N>1 and N is an integer.

[0054] The parallel-to-serial conversion module of conversion module 503 converts each of the N parallel low-speed signals output from the DRAM module die 505 into a single serial high-speed signal before outputting it to the processor. The serial-to-parallel conversion module of conversion module 503 converts each of the serial high-speed signals output from the processor into N parallel low-speed signals before outputting them to the DRAM module die 505. The signals have a first transmission rate v1 between the DRAM module die 505 and conversion module 503, and a second transmission rate v2 between conversion module 503 and the processor. The second transmission rate v2 is N times the first transmission rate v1, meaning the signal transmission rate for signal interaction between the storage module and the outside world is increased to N times the original rate. Correspondingly, the bandwidth of the storage module is increased to N times the original rate.

[0055] Specifically, the parallel-to-serial module of conversion module 503 converts each N parallel low-speed data signals DQ output from DRAM module die 505 into one serial high-speed data signal DQ before outputting it to the processor. The serial-to-parallel module of conversion module 503 converts each serial high-speed data signal DQ output from the processor into N parallel low-speed data signals DQ before outputting them to DRAM module die 505. The data signal DQ between DRAM module die 505 and conversion module 503 has a first data transmission rate v1(DQ), and the data signal DQ between conversion module 503 and processor has a second data transmission rate v2(DQ), which is N times the first data transmission rate v1(DQ).

[0056] The serial-to-parallel converter of the conversion module 503 is used to convert each serial high-speed global clock signal CK output by the processor into N parallel low-speed global clock signals CK before outputting them to the DRAM module die 505. The global clock signal CK between the DRAM module die 505 and the conversion module 503 has a first global clock transmission rate v1(CK), and the global clock signal CK between the conversion module 503 and the processor has a second global clock transmission rate v2(CK), which is N times the first global clock transmission rate v1(CK).

[0057] The serial-to-parallel conversion module of conversion module 503 is also used to convert each serial high-speed command / address signal CA output by the processor into N parallel low-speed command / address signals CA before outputting them to the DRAM module die 505. The command / address signal CA between the DRAM module die 505 and conversion module 503 has a first command / address transmission rate v1(CA), and the command / address signal CA between conversion module 503 and processor has a second command / address transmission rate v2(CA), which is N times the first command / address transmission rate v1(CA).

[0058] In some embodiments, the serial-to-parallel conversion module of the conversion module 503 is further used to convert each serial high-speed write clock signal WCK output by the processor into N parallel low-speed write clock signals WCK before outputting them to the DRAM module die 505. The write clock signal WCK between the DRAM module die 505 and the conversion module 503 has a first write clock transmission rate v1(WCK), and the write clock signal WCK between the conversion module 503 and the processor has a second write clock transmission rate v2(WCK), the second write clock transmission rate v2(WCK) being N times the first write clock transmission rate v1(WCK). The parallel-to-serial conversion module of the conversion module 503 is further used to convert each of the N parallel low-speed read data strobe signals RDQS output by the DRAM module die 505 into one serial high-speed read data strobe signal RDQS and output it to the processor. The read data strobe signal RDQS between the DRAM module die 505 and the conversion module 503 has a first read data strobe transmission rate v1 (RDQS), and the read data strobe signal RDQS between the conversion module 503 and the processor has a second read data strobe transmission rate v2 (RDQS), which is N times the first read data strobe transmission rate v1 (RDQS).

[0059] In some implementations, the parallel-to-serial module of the conversion module 503 is used to convert each of the N parallel low-speed data strobe signals DQS output from the DRAM module die 505 into one serial high-speed data strobe signal DQS and output it to the processor. The serial-to-parallel module of the conversion module 503 is also used to convert each serial high-speed data strobe signal DQS output by the processor into N parallel low-speed data strobe signals DQS and output them to the DRAM module die 505. The data strobe signal DQS between the DRAM module die 505 and the conversion module 503 has a first data strobe transmission rate v1(DQS), and the data strobe signal DQS between the conversion module 503 and the processor has a second data strobe transmission rate v2(DQS), which is N times the first data strobe transmission rate v1(DQS).

[0060] The parallel-to-serial conversion ratio of the conversion module 503 is set according to actual needs to improve the bandwidth of the storage module to varying degrees. In some embodiments, the parallel-to-serial conversion ratio of the conversion module 503 is 2:1, that is, the parallel-to-serial conversion ratio of the parallel-to-serial module of the conversion module 503 is 2:1, and the serial-to-parallel conversion ratio of the serial-to-parallel module of the conversion module 503 is 1:2. In some embodiments, the parallel-to-serial conversion ratio of the conversion module 503 is 4:1, that is, the parallel-to-serial conversion ratio of the parallel-to-serial module of the conversion module 503 is 4:1, and the serial-to-parallel conversion ratio of the serial-to-parallel module of the conversion module 503 is 1:4.

[0061] Taking the parallel-to-serial conversion ratio of conversion module 503 as an example, in some implementations, such as Figure 7A As shown, the data signal DQ is transmitted bidirectionally between the DRAM module die 505 and the processor. The write clock signal WCK is sent from the processor to the DRAM module die 505, and the read data strobe signal RDQS is sent from the DRAM module die 505 to the processor. The data signal DQ, write clock signal WCK, and read data strobe signal RDQS occupy a total of m signal channels between the conversion module 503 and the processor, and a total of 2m signal channels between the DRAM module die 505 and the conversion module 503. Specifically, the transmission rate of the data signal DQ between the conversion module 503 and the processor is twice the transmission rate of the data signal DQ between the DRAM module die 505 and the conversion module 503; correspondingly, the number of data signal channels occupied by the data signal DQ between the DRAM module die 505 and the conversion module 503 is twice the number of data signal channels occupied between the conversion module 503 and the processor. The transmission rate of the write clock signal WCK between the conversion module 503 and the processor is twice that between the DRAM module die 505 and the conversion module 503; correspondingly, the number of write clock signal channels between the DRAM module die 505 and the conversion module 503 is twice the number of write clock signal channels between the conversion module 503 and the processor. The transmission rate of the read data strobe signal RDQS between the conversion module 503 and the processor is twice that between the DRAM module die 505 and the conversion module 503; correspondingly, the number of read data strobe signal channels between the DRAM module die 505 and the conversion module 503 is twice the number of read data strobe signal channels between the conversion module 503 and the processor.

[0062] The global clock signal CK and command / address signal CA are sent by the processor to the DRAM module die 505. The global clock signal CK and command / address signal CA occupy a total of n signal channels between the conversion module 503 and the processor, and a total of 2n signal channels between the DRAM module die 505 and the conversion module 503. Specifically, the transmission rate of the global clock signal CK between the conversion module 503 and the processor is twice the transmission rate of the global clock signal CK between the DRAM module die 505 and the conversion module 503; correspondingly, the number of global clock signal channels between the DRAM module die 505 and the conversion module 503 is twice the number of global clock signal channels between the conversion module 503 and the processor. The transmission rate of the command / address signal CA between the conversion module 503 and the processor is twice that between the DRAM module die 505 and the conversion module 503; correspondingly, the number of command / address signal CA channels between the DRAM module die 505 and the conversion module 503 is twice the number of command / address signal channels between the conversion module 503 and the processor.

[0063] Taking the parallel-to-serial conversion ratio of conversion module 503 as an example of 2:1, in other implementations, such as Figure 7B As shown, the data signal DQ and the data strobe signal DQS are transmitted bidirectionally between the DRAM module die 505 and the processor. The data signal DQ and the data strobe signal DQS occupy a total of m signal channels between the conversion module 503 and the processor, and a total of 2m signal channels between the DRAM module die 505 and the conversion module 503. Specifically, the transmission rate of the data signal DQ between the conversion module 503 and the processor is twice the transmission rate of the data signal DQ between the DRAM module die 505 and the conversion module 503; correspondingly, the number of data signal channels occupied by the data signal DQ between the DRAM module die 505 and the conversion module 503 is twice the number of data signal channels occupied between the conversion module 503 and the processor. The transmission rate of the data strobe signal DQS between the conversion module 503 and the processor is twice that between the DRAM module die 505 and the conversion module 503; correspondingly, the number of data strobe signal channels between the DRAM module die 505 and the conversion module 503 is twice the number of data strobe signal channels between the conversion module 503 and the processor.

[0064] The global clock signal CK and command / address signal CA are sent by the processor to the DRAM module die 505. The global clock signal CK and command / address signal CA occupy a total of n signal channels between the conversion module 503 and the processor, and a total of 2n signal channels between the DRAM module die 505 and the conversion module 503. Specifically, the transmission rate of the global clock signal CK between the conversion module 503 and the processor is twice the transmission rate of the global clock signal CK between the DRAM module die 505 and the conversion module 503; correspondingly, the number of global clock signal channels between the DRAM module die 505 and the conversion module 503 is twice the number of global clock signal channels between the conversion module 503 and the processor. The transmission rate of the command / address signal CA between the conversion module 503 and the processor is twice that between the DRAM module die 505 and the conversion module 503; correspondingly, the number of command / address signal CA channels between the DRAM module die 505 and the conversion module 503 is twice the number of command / address signal channels between the conversion module 503 and the processor.

[0065] In some implementations, the parallel-to-serial module of the conversion module 503 is used to convert each N parallel low-speed signals from the same DRAM die into a single serial high-speed signal and output it to the processor. The serial-to-parallel module of the conversion module 503 is used to convert each serial high-speed signal output by the processor into N parallel low-speed signals and output them to the same DRAM die.

[0066] When the parallel-to-serial conversion ratio of the conversion module 503 is 2:1, taking the data signal as an example, the parallel-to-serial module of the conversion module 503 is used to convert every two parallel low-speed signals from the same DRAM die into one serial high-speed signal and output it to the processor. The serial-to-parallel module of the conversion module 503 is used to convert every serial high-speed signal output by the processor into two parallel low-speed signals and output them to the same DRAM die.

[0067] refer to Figure 5 The DRAM module die 505 has a first DRAM die 5071 and a second DRAM die 5072. The first DRAM die 5071 and the substrate 501 have a first data signal line 5081 and a second data signal line 5082. The second DRAM die 5072 and the substrate 501 have a third data signal line 5083 and a fourth data signal line 5084.

[0068] During the read operation, the first read data flows from the first DRAM die 5071 through the first data signal line 5081, the substrate 501, and a first conductive contact 509 to the conversion module 503. The second read data flows from the first DRAM die 5071 through the second data signal line 5082, the substrate 501, and another first conductive contact 509 to the conversion module 503. The first and second read data have a first data transmission rate v1 (DQ). The conversion module 503 performs a parallel-to-serial conversion operation on the first and second read data to obtain the first serial read data, which is output from a second conductive contact 511, the substrate 501, and a third conductive contact 513. The first serial read data has a second data transmission rate v2 (DQ), which is twice the first data transmission rate v1 (DQ).

[0069] Similarly, the third read data arrives at the conversion module 503 from the second DRAM die 5072 via the third data signal line 5083, the substrate 501, and another first conductive contact 509. The fourth read data arrives at the conversion module 503 from the second DRAM die 5072 via the fourth data signal line 5084, the substrate 501, and another first conductive contact 509. The third and fourth read data have a first data transmission rate v1 (DQ). The conversion module 503 performs a parallel-to-serial conversion operation on the third and fourth read data to obtain a second serial read data, which is output from another second conductive contact 511, the substrate 501, and another third conductive contact 513. The second serial read data has a second data transmission rate v2 (DQ), which is twice the first data transmission rate v1 (DQ).

[0070] During a write operation, the first serial write data flows from a third conductive contact 513, substrate 501, and a second conductive contact 511 of the read operation to the conversion module 503. The conversion module 503 performs a serial-to-parallel conversion operation on the first serial write data to obtain the first write data and the second write data. The first write data flows from a first conductive contact 509, substrate 501, and first data signal line 5081 of the read operation to the first DRAM die 5071. The second write data flows from another first conductive contact 509, substrate 501, and second data signal line 5082 of the read operation to the first DRAM die 5071. The first serial write data has a second data transfer rate v2(DQ), and the first and second write data have a first data transfer rate v1(DQ). The second data transfer rate v2(DQ) is twice the first data transfer rate v1(DQ).

[0071] Similarly, the second serial write data arrives at the conversion module 503 from another third conductive contact 513, substrate 501, and another second conductive contact 511 of the read operation. The conversion module 503 performs a serial-to-parallel conversion operation on the second serial write data to obtain the third and fourth write data. The third write data arrives at the second DRAM die 5072 from yet another first conductive contact 509, substrate 501, and third data signal line 5083 of the read operation. The fourth write data arrives at the second DRAM die 5072 from yet another first conductive contact 509, substrate 501, and fourth data signal line 5084 of the read operation. The second serial write data has a second data transfer rate v2(DQ), and the third and fourth write data have a first data transfer rate v1(DQ). The second data transfer rate v2(DQ) is twice the first data transfer rate v1(DQ).

[0072] In some implementations, the parallel-to-serial module of the conversion module 503 is used to convert each N parallel low-speed signals from different DRAM dies into one serial high-speed signal and output it to the processor, and the serial-to-parallel module of the conversion module 503 is used to convert each serial high-speed signal output by the processor into N parallel low-speed signals and output them to different DRAM dies.

[0073] Furthermore, in some embodiments, the parallel-to-serial module of the conversion module 503 is used to convert each of the N parallel low-speed signals from the N DRAM dies into a single serial high-speed signal and output it to the processor, and the serial-to-parallel module of the conversion module 503 is used to convert each serial high-speed signal output by the processor into N parallel low-speed signals and output them to the N DRAM dies respectively.

[0074] When the parallel-to-serial conversion ratio of the conversion module 503 is 2:1, taking the data signal as an example, the parallel-to-serial module of the conversion module 503 is used to convert each of the two parallel low-speed signals from the two DRAM dies into one serial high-speed signal and output it to the processor. The serial-to-parallel module of the conversion module 503 is used to convert each serial high-speed signal output by the processor into two parallel low-speed signals and output them to the two DRAM dies respectively.

[0075] Still referencing Figure 5During the read operation, the first channel of read data arrives at the conversion module 503 from the first DRAM die 5071 via the first data signal line 5081, the substrate 501, and a first conductive contact 509. The third channel of read data arrives at the conversion module 503 from the second DRAM die 5072 via the third data signal line 5083, the substrate 501, and another first conductive contact 509. The first and third channels of read data have a first data transmission rate v1 (DQ). The conversion module 503 performs a parallel-to-serial conversion operation on the first and third channels of read data to obtain the first channel of serial read data, which is output from a second conductive contact 511, the substrate 501, and a third conductive contact 513. The first channel of serial read data has a second data transmission rate v2 (DQ), which is twice the first data transmission rate v1 (DQ).

[0076] Similarly, the second read data arrives at the conversion module 503 from the first DRAM die 5071 via the second data signal line 5082, the substrate 501, and another first conductive contact 509. The fourth read data arrives at the conversion module 503 from the second DRAM die 5072 via the fourth data signal line 5084, the substrate 501, and yet another first conductive contact 509. The second and fourth read data have a first data transmission rate v1 (DQ). The conversion module 503 performs a parallel-to-serial conversion operation on the second and fourth read data to obtain a second serial read data, which is output from another second conductive contact 511, the substrate 501, and another third conductive contact 513. The second serial read data has a second data transmission rate v2 (DQ), which is twice the first data transmission rate v1 (DQ).

[0077] During a write operation, the first serial write data flows from a third conductive contact 513, substrate 501, and a second conductive contact 511 of the read operation to the conversion module 503. The conversion module 503 performs a serial-to-parallel conversion operation on the first serial write data to obtain the first write data and the third write data. The first write data flows from a first conductive contact 509, substrate 501, and first data signal line 5081 of the read operation to the first DRAM die 5071. The third write data flows from another first conductive contact 509, substrate 501, and third data signal line 5083 of the read operation to the second DRAM die 5072. The first serial write data has a second data transfer rate v2(DQ), and the first and third write data have a first data transfer rate v1(DQ). The second data transfer rate v2(DQ) is twice the first data transfer rate v1(DQ).

[0078] Similarly, the second serial write data arrives at the conversion module 503 from another third conductive contact 513, substrate 501, and another second conductive contact 511 of the read operation. The conversion module 503 performs a serial-to-parallel conversion operation on the second serial write data to obtain the second write data and the fourth write data. The second write data arrives at the first DRAM die 5071 from yet another first conductive contact 509, substrate 501, and second data signal line 5082 of the read operation. The fourth write data arrives at the second DRAM die 5072 from yet another first conductive contact 509, substrate 501, and fourth data signal line 5084 of the read operation. The second serial write data has a second data transmission rate v2(DQ), and the second and fourth write data have a first data transmission rate v1(DQ). The second data transmission rate v2(DQ) is twice the first data transmission rate v1(DQ).

[0079] like Figure 8 As shown, within time t, the first DRAM die 5071 sends first-channel read data A0 and A1 to the conversion module 503, and the second DRAM die 5072 sends third-channel read data B0 and B1 to the conversion module 503. The conversion module 503 converts the two parallel data channels into one serial data channel, i.e., the first serial read data output, outputting read data A0, B0, A1, and B1 within time t. It can be seen that the conversion module 503 increases the data signal transmission rate of the memory module to twice its original value. Assuming the data signal transmission rate of the DRAM module die 505 is 6.4 Gbps, the data signal transmission rate output by the conversion module 503 can be increased to 12.8 Gbps. Correspondingly, the conversion module 503 increases the bandwidth of the memory module to twice its original value.

[0080] In some embodiments, the number of DRAM die layers in the DRAM module die 505 is even. In some embodiments, the DRAM die in the DRAM module die 505 is connected to the substrate 501 via wire bonding. In some embodiments, a conversion module 503 integrates all signals on the DRAM module die 505 onto a single die for processing, and the conversion module 503 and the substrate 501 are packaged using the FC (Flip Chip) method. When using wire bonding for packaging, parasitic inductance exists, which affects signal transmission speed and prevents high-speed transmission. By introducing the conversion module 503 and using FC packaging, and designing the parallel-to-serial conversion ratio of the conversion module 503 as needed, the signal transmission speed between the conversion module 503 and the processor can be freed from the limitation of parasitic inductance caused by wire bonding. In other words, this invention uses inexpensive wire bonding to package memory chips while achieving high speed and high bandwidth, eliminating the limitation on signal transmission speed imposed by inexpensive wire bonding packaging.

[0081] In some embodiments, the first conductive contact 509 and the second conductive contact 511 are both metal bumps, and the third conductive contact 513 is a metal solder ball. The first side of the substrate 501 is connected to the conversion module 503 through the metal bumps, and the second side of the substrate 501 is connected to the PCB board through the metal solder balls.

[0082] In some embodiments, the substrate 501 is made of silicon or an organic material.

[0083] Furthermore, in some implementations, the DRAM module die and conversion module may not be vertically stacked, but rather positioned separately on the substrate, with the connection and packaging methods remaining unchanged. The resulting memory module can still achieve high speed and high bandwidth. However, this method occupies more area, which is detrimental to the miniaturization of the memory module. Therefore, the specific arrangement of the DRAM module die and conversion module can be selected according to actual needs.

[0084] Furthermore, in some embodiments, by using a conversion module to speed up the DRAM module, the resulting memory module is not subject to JEDEC standard restrictions. Therefore, the memory module's packaging can further overcome existing limitations and become more flexible. For example, the size and spacing of the third conductive contacts can be reduced, allowing the second side of the substrate to accommodate more third conductive contacts. Correspondingly, in some embodiments, multiple DRAM module dies and multiple conversion modules are connected one-to-one and packaged together with the substrate, providing greater capacity, higher I / O density, and bandwidth through a single chip to meet more application scenarios.

[0085] like Figure 9 As shown, another embodiment of the high-bandwidth DRAM-based storage module of the present invention includes a substrate 801, a plurality of conversion modules 503, and a plurality of DRAM module dies 505. The conversion modules 503 and the DRAM module dies 505 correspond one-to-one. The conversion modules 503 are disposed between the substrate 501 and the DRAM module dies 505 to form multiple stacked structures, and each stacked structure is disposed at a different position on the substrate 801.

[0086] For each stacked structure, the DRAM module die 505 is connected to the first side of the substrate 801 via conductive lines. The first side of the substrate 801 is then connected to the conversion module 503 via multiple first conductive contacts 509 and multiple second conductive contacts 511. The second side of the substrate 801, opposite to the first side, is provided with multiple third conductive contacts 803. The substrate 801 can be connected to the PCB board via the third conductive contacts 803, thereby enabling the DRAM module die 505 in this stacked structure to interact with the outside world (such as CPU or GPU processors).

[0087] The conversion module 503 and the DRAM module die 505 interact via multiple first conductive contacts 509, the substrate 801 (with internal wiring in the substrate 801), and conductive lines. The conversion module 503 and the processor interact via multiple second conductive contacts 511, the substrate 801 (with internal wiring in the substrate 801), and multiple third conductive contacts 803. The conductive lines between the DRAM module die 505 and the substrate 801 include data signal lines and other signal lines. The data signal lines are used to transmit data signals, and the other signal lines are used to transmit other signals, such as clock signals and command / address signals, forming corresponding data signal channels, clock signal channels, command / address signal channels, etc. All signal types achieve increased transmission rates through the conversion module 503.

[0088] Further implementations of each stacked structure have been described in detail in the previous embodiments and can be directly referenced here; therefore, they will not be repeated in this embodiment.

[0089] The storage module of this invention has multiple stacked structures. These multiple stacked structures are packaged together with the substrate, and a single chip can provide greater capacity, higher I / O density, and bandwidth, resulting in high flexibility.

[0090] This invention incorporates a conversion module between the DRAM module die and the substrate. This module enhances the signal transmission rate between the DRAM module die and the processor (e.g., CPU or GPU), thereby increasing the bandwidth of the memory module. It is compatible with inexpensive wire bonding packaging, eliminating the signal transmission speed limitations imposed by this method and balancing low cost with high bandwidth requirements. The conversion module includes parallel-to-serial and serial-to-parallel conversion modules. The parallel-to-serial conversion ratio can be adjusted according to actual needs to improve the bandwidth of the memory module to varying degrees. Based on readily available DRAM module dies, the conversion module is easily modularized and mass-produced. The resulting high-bandwidth memory module has a simple structure and is not limited by JEDEC standards. It facilitates the formation of multiple stacked structures using DRAM module dies and conversion modules, which can then be packaged together with the substrate. This allows for greater capacity, higher I / O density, and bandwidth from a single chip, offering high flexibility and promising application prospects.

[0091] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of those different embodiments or examples.

[0092] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0093] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more (two or more) executable instructions for implementing a particular logical function or process. Furthermore, the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functionality involved.

[0094] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus or device (such as a computer-based system, a processor-included system or other system that can fetch and execute instructions from, an instruction execution system, apparatus or device).

[0095] It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. All or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware, the program being stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiments.

[0096] Furthermore, the functional units in the various embodiments of this application can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. This storage medium can be a read-only memory, a disk, or an optical disk, etc.

[0097] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in this application, and these should all be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A storage module, characterized in that, include: The substrate, the conversion module, and the DRAM module die are provided; the DRAM module die is electrically connected to a first surface of the substrate, and the first surface of the substrate is electrically connected to the conversion module. The conversion module and the DRAM module die interact with each other via the substrate and from the first side of the substrate; the conversion module interacts with the outside world via the substrate and from the first side of the substrate and the second side opposite to the first side; the conversion module is used to process the signals between the DRAM module die and the outside world to improve the signal transmission rate of the DRAM module die interacting with the outside world. The DRAM module die includes multiple stacked DRAM dies, and the DRAM dies are connected to the substrate by wire bonding. The conversion module includes a parallel-to-serial conversion module and a serial-to-parallel conversion module; During the write operation, the serial-to-parallel conversion module is used to perform serial-to-parallel conversion on the data signal DQ, and to perform serial-to-parallel conversion on the global clock signal CK and the command / address signal CA; during the read operation, the parallel-to-serial conversion module is used to perform parallel-to-serial conversion on the data signal DQ, and the serial-to-parallel conversion module is used to perform serial-to-parallel conversion on the global clock signal CK and the command / address signal CA.

2. The storage module as described in claim 1, characterized in that, During the write operation, the serial-to-parallel conversion module is also used to perform a serial-to-parallel conversion operation on the write clock signal WCK; during the read operation, the serial-to-parallel conversion module is also used to perform a serial-to-parallel conversion operation on the write clock signal WCK, and the parallel-to-serial conversion module is also used to perform a parallel-to-serial conversion operation on the read data strobe signal RDQS.

3. The storage module as described in claim 1, characterized in that, During the write operation, the serial-to-parallel conversion module is also used to perform a serial-to-parallel conversion operation on the write clock signal WCK; during the read operation, the parallel-to-serial conversion module is also used to perform a parallel-to-serial conversion operation on the read data strobe signal RDQS.

4. The storage module as described in claim 1, characterized in that, During the write operation, the serial-to-parallel conversion module is also used to perform a serial-to-parallel conversion operation on the data strobe signal DQS; during the read operation, the parallel-to-serial conversion module is also used to perform a parallel-to-serial conversion operation on the data strobe signal DQS.

5. The storage module as described in claim 1, characterized in that, The parallel-to-serial conversion ratio of the parallel-to-serial module is N:1, and the serial-to-parallel conversion ratio of the serial-to-parallel module is 1:N, where N>1 and N is an integer.

6. The storage module as described in claim 5, characterized in that, The parallel-to-serial module is used to convert each N parallel low-speed signal output from the DRAM module die into a single serial high-speed signal before outputting it; the serial-to-parallel module is used to convert each externally input serial high-speed signal into N parallel low-speed signals before outputting them to the DRAM module die.

7. The storage module as described in claim 6, characterized in that, The signal between the DRAM module die and the conversion module has a first transmission rate v1, and the signal between the conversion module and the outside world has a second transmission rate v2, which is N times the first transmission rate v1.

8. The storage module as described in claim 6, characterized in that, The data signal DQ between the DRAM module die and the conversion module has a first data transmission rate v1(DQ), and the data signal DQ between the conversion module and the outside world has a second data transmission rate v2(DQ), which is N times the first data transmission rate v1(DQ). The global clock signal CK between the DRAM module die and the conversion module has a first clock transmission rate v1(CK), and the global clock signal CK between the conversion module and the outside world has a second clock transmission rate v2(CK), which is N times the first clock transmission rate v1(CK). The command / address signal CA between the DRAM module die and the conversion module has a first command / address transmission rate v1(CA), and the command / address signal CA between the conversion module and the outside world has a second command / address transmission rate v2(CA), which is N times the first command / address transmission rate v1(CA).

9. The storage module as described in claim 8, characterized in that, The write clock signal WCK between the DRAM module die and the conversion module has a first write clock transmission rate v1(WCK), and the write clock signal WCK between the conversion module and the outside world has a second write clock transmission rate v2(WCK), the second write clock transmission rate v2(WCK) being N times the first write clock transmission rate v1(WCK); the read data strobe signal RDQS between the DRAM module die and the conversion module has a first read data strobe transmission rate v1(RDQS), and the read data strobe signal RDQS between the conversion module and the outside world has a second read data strobe transmission rate v2(RDQS), the second read data strobe transmission rate v2(RDQS) being N times the first read data strobe transmission rate v1(RDQS).

10. The storage module as described in claim 8, characterized in that, The data strobe signal DQS between the DRAM module die and the conversion module has a first data strobe transmission rate v1(DQS), and the data strobe signal DQS between the conversion module and the outside world has a second data strobe transmission rate v2(DQS), which is N times the first data strobe transmission rate v1(DQS).

11. The storage module as described in claim 6, characterized in that, The parallel-to-serial module is used to convert N parallel low-speed signals from the same DRAM die into one serial high-speed signal and then output it; the serial-to-parallel module is used to convert each externally input serial high-speed signal into N parallel low-speed signals and then output them to the same DRAM die.

12. The storage module as described in claim 6, characterized in that, The parallel-to-serial module is used to convert each N parallel low-speed signals from different DRAM dies into one serial high-speed signal and then output it; the serial-to-parallel module is used to convert each externally input serial high-speed signal into N parallel low-speed signals and then output them to different DRAM dies.

13. The storage module as described in claim 12, characterized in that, The parallel-to-serial module is used to convert each of the N parallel low-speed signals from N DRAM dies into a single serial high-speed signal and then output it; the serial-to-parallel module is used to convert each externally input serial high-speed signal into N parallel low-speed signals and then output them to the N DRAM dies respectively.

14. The storage module as described in any one of claims 1 to 13, characterized in that, The conversion module and the substrate are packaged using the FC method.

15. The storage module as described in claim 14, characterized in that, The DRAM module die is connected to the first side of the substrate via conductive lines. The first side of the substrate is connected to the conversion module via multiple first conductive contacts and multiple second conductive contacts. The second side of the substrate is provided with multiple third conductive contacts. The conversion module and the DRAM module die interact with each other via the multiple first conductive contacts, the substrate, and the conductive lines. The conversion module interacts with the outside world via the multiple second conductive contacts, the substrate, and the multiple third conductive contacts.

16. The storage module as described in claim 15, characterized in that, The conversion module and the DRAM module die are stacked sequentially on the substrate, with the conversion module disposed between the substrate and the DRAM module die.

17. A storage module, characterized in that, The system includes a substrate, multiple conversion modules, and multiple DRAM module dies; the multiple conversion modules and the multiple DRAM module dies are one-to-one, and the multiple conversion modules are respectively disposed between the substrate and the corresponding DRAM module dies to form multiple stacked structures, with each stacked structure disposed at a different position on the substrate. In each stacked structure, the DRAM module die forms a conductive connection with the first side of the substrate, and the first side of the substrate forms a conductive connection with the conversion module. The conversion module and the DRAM module die interact with each other via the substrate and from the first side of the substrate; the conversion module interacts with the outside world via the substrate and from the first side of the substrate and the second side opposite to the first side; the conversion module is used to process the signals between the DRAM module die and the outside world to improve the signal transmission rate of the DRAM module die interacting with the outside world. The DRAM module die includes multiple stacked DRAM dies, and the multiple DRAM module dies are respectively connected to the substrate by wire bonding. In each stacked structure, the conversion module includes a parallel-to-serial module and a serial-to-parallel module; During the write operation, the serial-to-parallel conversion module is used to perform serial-to-parallel conversion on the data signal DQ, and to perform serial-to-parallel conversion on the global clock signal CK and the command / address signal CA; during the read operation, the parallel-to-serial conversion module is used to perform parallel-to-serial conversion on the data signal DQ, and the serial-to-parallel conversion module is used to perform serial-to-parallel conversion on the global clock signal CK and the command / address signal CA.

18. The storage module as described in claim 17, characterized in that, In each stacked structure, the parallel-to-serial module is used to convert each N parallel low-speed signal output from the DRAM module die into a single serial high-speed signal before outputting it; the serial-to-parallel module is used to convert each externally input serial high-speed signal into N parallel low-speed signals before outputting them to the DRAM module die; where N > 1 and N is an integer.

19. The storage module as described in claim 17 or 18, characterized in that, The multiple conversion modules and the substrate are respectively packaged using the FC method.

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