Method of programming a flash memory array

Abstract

This invention provides a programming method for a flash memory array. When programming a selected memory bit of a selected memory cell, a first voltage is applied to the control gate line corresponding to the selected memory bit of the selected memory cell; a second voltage is applied to the control gate line corresponding to a preset memory bit of a non-selected memory cell adjacent to the selected memory cell; wherein the preset memory bit and the selected memory bit are located in adjacent rows of the same column; by controlling the second voltage applied to the preset memory bit of the non-selected memory cell, crosstalk to the non-selected memory cell located in adjacent rows of the same column as the selected memory cell is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a method for programming a flash memory array. Background Technology

[0002] Flash memory is a type of non-volatile memory that retains data for an extended period even without a power supply, meaning data is not lost when power is off. Flash memory is mainly divided into two types: NOR and NAND, commonly referred to as NOR Flash and NAND Flash. NOR Flash, also known as coded flash memory, has become the mainstream non-volatile memory technology due to its characteristics such as direct code execution, high reliability, and fast read speed.

[0003] As NOR flash memory cells continue to shrink, the distance between floating gates (FGs) becomes increasingly shorter, making crosstalk a critical issue affecting NOR flash reliability. During testing, a new crosstalk pattern was discovered: when programming a selected row, the row closest to it experiences more severe crosstalk than other rows. It is suspected that during programming, PGM current electrons at the junction induce secondary electrons, which are then injected into adjacent floating gates, causing crosstalk. Summary of the Invention

[0004] The purpose of this invention is to provide a programming method for flash memory arrays to solve the programming crosstalk problem of adjacent rows of common bit contact holes.

[0005] To achieve the above objectives, the present invention provides a method for programming a flash memory array, comprising:

[0006] The flash memory array is formed by arranging multiple memory cells, each memory cell including: a gate structure of a stacked floating gate and a control gate, a word line structure located between the gate structures, and a first source-drain region and a second source-drain region formed on both sides of the gate structure;

[0007] Each of the aforementioned gate structures has a floating gate as a storage bit;

[0008] The control gate of each of the gate structures is connected to the corresponding control gate line;

[0009] Each of the aforementioned word line structures is connected to the corresponding word line;

[0010] In the flash memory array, the word line gates of each memory cell in the same row are all connected to the word lines of the same row;

[0011] The control gates of each memory cell in the same row are all connected to the control gate lines in the same row;

[0012] The first source-drain regions of the memory cells in the same column are connected to the corresponding bit lines in the same column;

[0013] The second source-drain regions of the memory cells in the same column are connected to the corresponding bit lines in the same column;

[0014] When programming a selected memory location,

[0015] A first voltage is applied to the control gate line corresponding to the selected memory bit of the selected memory cell;

[0016] A second voltage is applied to the control gate line corresponding to the preset memory bit of a non-selected memory cell adjacent to the selected memory cell;

[0017] The preset storage bit and the selected storage bit are located in adjacent rows of the same column; by controlling the second voltage applied to the preset storage bit of the non-selected storage cell, crosstalk to the non-selected storage cell located in adjacent rows of the same column as the selected storage cell is reduced.

[0018] Optionally, the storage unit employs a discrete-gate floating-gate device.

[0019] Optionally, the selected memory cell and the non-selected memory cell are connected using a common bit line.

[0020] Optionally, when the first voltage applied to the selected memory bit is the programming voltage, the second voltage on the preset memory bit is controlled to be negative.

[0021] Optionally, the second voltage is -0.5V to -3.5V.

[0022] Optionally, when the first voltage applied to the selected memory bit is a programming voltage, a programming verification voltage is applied to another memory bit of the same selected memory cell gate structure to detect whether the threshold voltage of the selected memory cell has reached the expected target value.

[0023] Optionally, the bit line connecting the selected memory bit and the preset memory bit corresponding to the first source-drain region in the same column is the first bit line BL0, and the bit line connecting the selected memory bit and the preset memory bit corresponding to the second source-drain region in the same column is the second bit line BL1, where BL0 = 4.5V and BL1 = Vdp.

[0024] Optionally, the first source / drain region and the second source / drain region are N+ doped regions, and a P-type doped channel region is formed between the first source / drain region and the second source / drain region.

[0025] Optionally, the memory cell includes two gate structures, which are stacked structures consisting of a gate oxide layer, a floating gate, an inter-gate dielectric layer, and a control gate.

[0026] Optionally, the word line structure includes stacked gate dielectric layers and word lines.

[0027] In summary, the present invention provides a programming method for a flash memory array. When programming a selected memory bit of a selected memory cell, a first voltage is applied to the control gate line corresponding to the selected memory bit of the selected memory cell; a second voltage is applied to the control gate line corresponding to a preset memory bit of a non-selected memory cell adjacent to the selected memory cell; wherein the preset memory bit and the selected memory bit are located in adjacent rows of the same column; by controlling the second voltage applied to the preset memory bit of the non-selected memory cell, crosstalk to the non-selected memory cell located in adjacent rows of the same column as the selected memory cell is reduced. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of a flash memory array provided in an embodiment of the present invention;

[0029] Figure 2 for Figure 1 A schematic diagram of the structure of a storage cell in a flash memory array;

[0030] Figure 3 for Figure 1 A schematic diagram of the cross-sectional structure of the memory cell corresponding to the dashed coil P frame in the flash memory array. Detailed Implementation

[0031] To make the content of this invention clearer and easier to understand, the following description, in conjunction with the accompanying drawings, further illustrates the invention. Of course, this invention is not limited to this specific embodiment, and common substitutions well-known to those skilled in the art are also covered within the scope of protection of this invention.

[0032] Secondly, the present invention is described in detail using schematic diagrams. When describing the examples of the present invention in detail, for ease of explanation, the schematic diagrams are not enlarged to a certain extent according to the general proportions, and this should not be regarded as a limitation of the present invention.

[0033] For ease of description, some embodiments of the present invention may use spatially relative terms such as “above,” “below,” “top,” and “under” to describe the relationship between one element or component and another (or more) elements or components as shown in the accompanying drawings of the embodiments. It should be understood that, in addition to the orientations described in the drawings, the spatially relative terms are also intended to include different orientations of the device during use or operation. For example, if the device in the drawings is flipped, it is described as an element or component “below” or “under” other elements or components, and will subsequently be positioned “above” or “on” other elements or components. The terms “first,” “second,” etc., used below are used to distinguish between similar elements and are not necessarily used to describe a particular order or temporal sequence.

[0034] Figure 1 This is a schematic diagram of a flash memory array according to an embodiment of the present invention. Figure 2 for Figure 1 A schematic diagram of the structure of a storage cell in a flash memory array. Figure 3 for Figure 1 A schematic diagram of the cross-sectional structure of the memory cell corresponding to the dashed coil P frame in the flash memory array. Figure 1 In the diagram, dashed coil 110a corresponds to a selected memory cell, dashed coil 110b corresponds to a non-selected memory cell, bit line (BL) is column line, word line (WL / SG) and control gate line (CG) are row line.

[0035] like Figures 1 to 3 As shown, the programming method of the flash memory array provided in this embodiment includes: the flash memory array is formed by arranging a plurality of memory cells 110, the memory cell 110 includes: a gate structure 101 stacked with a floating gate 201 and a control gate 202, a word line structure 102 located between the gate structures 110, and a first source drain region 203 and a second source drain region 206 formed on both sides of the gate structure 101.

[0036] Each of the aforementioned gate structures 101 has a floating gate 201 as a storage bit;

[0037] The control gate 202 of each of the gate structures 101 is connected to the corresponding control gate line CG;

[0038] Each of the aforementioned word line structures 102 is connected to the corresponding word line WL;

[0039] In the flash memory array, the word line gates 204 of each of the memory cells 110 in the same row are all connected to the word lines WL in the same row;

[0040] The control gates 202 of each of the memory cells 110 in the same row are all connected to the control gate line CG in the same row;

[0041] The first source-drain region 205 of the memory cell 110 in the same column is connected to the corresponding bit line BL1 in the same column:

[0042] The second source-drain region 206 of the memory cell 110 in the same column is connected to the bit line BL0 corresponding to the same column;

[0043] When programming a selected memory bit A in a selected memory cell 110a,

[0044] A first voltage is applied to the control gate line CG1 corresponding to the selected memory bit of the selected memory cell 110a;

[0045] A second voltage is applied to the control gate line CG2 corresponding to the preset storage bit B of the non-selected storage cell 110b adjacent to the selected storage cell 110a;

[0046] The preset storage bit B and the selected storage bit A are located in adjacent rows of the same column. By controlling the second voltage applied to the preset storage bit B of the non-selected storage cell 110b, crosstalk to the non-selected storage cell 110b located in adjacent rows of the same column as the selected storage cell 110a is reduced. In particular, the selected storage cell 110a and the non-selected storage cell 110b adopt a common bit line structure to reduce programming interference between adjacent sectors.

[0047] Specifically, the flash memory array provided in this embodiment of the invention is formed by arranging multiple storage cells, such as... Figure 2 and Figure 3 The memory cell 110 shown employs a split-gate floating-gate device, specifically a dual-split-gate floating-gate device, with two gate structures 101. Each gate structure 101 is a stacked structure consisting of a gate oxide layer, a floating gate 201, an inter-gate dielectric layer, and a control gate 203. The word line structure 102 includes stacked gate dielectric layers and word line gates 204. The two control gates 203 of the gate structure 101 can be controlled separately and are connected to control gate lines CG1 and CG2, respectively. The word line gate 204 connects to word lines WL / SG.

[0048] The separated gate floating gate device is, for example, an N-type device. The first source / drain region 203 and the second source / drain region 206 are N+ doped regions, and a P-type doped channel region is formed between the first source / drain region 203 and the second source / drain region 206. The second source / drain region 206 of the memory cell 101 is connected to the bit line BL1. The first source / drain region 205 of the memory cell 101 is connected to the bit line BL0.

[0049] The selected memory cell 110a and the non-selected memory cell 110b are connected via a common bit line. In NOR Flash, a common bit line connection refers to a circuit design in a NOR Flash memory array where multiple (usually two) memory cells share the same bit line (BL). This is a common layout technique in high-density NOR Flash chips, designed to reduce the number of metal bit lines, thereby increasing memory density and reducing chip area. This layout design requires precise word line driving circuitry and timing control to ensure that the shared memory cells do not interfere with each other.

[0050] Two memory cells connected by a common bit line (e.g., controlled by two different word lines WL) are connected to the same bit line. By selecting the word line, it is ensured that at any given time, only one of the multiple memory cells sharing the same bit line is active (i.e., read or programmed).

[0051] During a read operation, assuming the cell connected to word line WL0 is to be read, the controller will only activate WL0 and keep WL1 in an invalid state (e.g., voltage 0V). The memory cell on the activated WL0 will attempt to conduct, and its conduction current (e.g., Figure 3 The current (indicated by the dashed arrow) flows through the shared bit line (BL) and is detected by the inductive amplifier. Since WL1 is not activated, the other cell sharing the same bit line is off and does not contribute to the bit line current, thus causing no interference. Reading a memory cell from WL1 follows the reverse process.

[0052] Similarly, during programming operations, by precisely controlling the word line voltage, a high programming voltage is applied only to the target memory cell (selected memory cell). For the cell that needs to be programmed, a high voltage is applied to its word line, while for the shared memory cell (non-selected memory cell) that needs to be disabled for programming, its word line voltage is controlled at a specific level to ensure that it is not accidentally programmed.

[0053] However, during actual testing, it was found that the co-line connection introduced a new mode of crosstalk, namely, when programming a row in a selected memory cell, the row with the closest neighbor (the non-selected memory cell) will be subject to more severe crosstalk than other rows.

[0054] Therefore, in this embodiment of the invention, when the first voltage applied to the selected memory bit A of the selected memory cell 110a is a programming high voltage (PHV), the second voltage on the preset memory bit B in the adjacent row of the non-selected memory cell 110b is controlled to be a negative voltage, the second voltage being -0.5V to -3.5V. That is, during flash memory array programming, a negative voltage is applied to the non-selected immediately adjacent control gate CG to improve programming crosstalk. In addition, when the first voltage applied to the selected memory bit A is a programming voltage, a programming verification voltage (PMV) is applied to another memory bit of the gate structure of the same selected memory cell 100a to detect whether the threshold voltage of the selected memory cell has reached the expected target value.

[0055] Furthermore, the bit line connecting the selected memory bit A and the preset memory bit corresponding to the first source-drain region 203 in the same column is the first bit line BL0, and the bit line connecting the selected memory bit A and the preset memory bit corresponding to the second source-drain region 206 in the same column is the second bit line BL1. For example, BL0 = 4.5V, BL1 = Vdp, and the specific programming voltage Vdp is the key signal that determines whether the corresponding memory cell is programmed (i.e., data 0 is written).

[0056] In summary, the present invention provides a programming method for a flash memory array. When programming a selected memory bit of a selected memory cell, a first voltage is applied to the control gate line corresponding to the selected memory bit of the selected memory cell; a second voltage is applied to the control gate line corresponding to a preset memory bit of a non-selected memory cell adjacent to the selected memory cell; wherein the preset memory bit and the selected memory bit are located in adjacent rows of the same column; by controlling the second voltage applied to the preset memory bit of the non-selected memory cell, crosstalk to the non-selected memory cell located in adjacent rows of the same column as the selected memory cell is reduced.

[0057] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for programming a flash memory array, characterized in that, include: The flash memory array is formed by arranging multiple memory cells, each memory cell including: a gate structure of a stacked floating gate and a control gate, a word line structure located between the gate structures, and a first source-drain region and a second source-drain region formed on both sides of the gate structure; Each of the aforementioned gate structures has a floating gate as a storage bit; The control gate of each of the gate structures is connected to the corresponding control gate line; Each of the aforementioned word line structures is connected to the corresponding word line; In the flash memory array, the word line gates of each memory cell in the same row are all connected to the word lines of the same row; The control gates of each memory cell in the same row are all connected to the control gate lines in the same row; The first source-drain regions of the memory cells in the same column are connected to the corresponding bit lines in the same column; The second source-drain regions of the memory cells in the same column are connected to the corresponding bit lines in the same column; When programming a selected memory location, A first voltage is applied to the control gate line corresponding to the selected memory bit of the selected memory cell; A second voltage is applied to the control gate line corresponding to the preset memory bit of a non-selected memory cell adjacent to the selected memory cell; Wherein, the preset storage bit and the selected storage bit are located in adjacent rows of the same column; By controlling the second voltage applied to the preset storage bit of the non-selected memory cell, crosstalk to the non-selected memory cell in the adjacent row located in the same column as the selected memory cell is reduced.

2. The programming method for a flash memory array according to claim 1, characterized in that, The storage unit employs a discrete-gate floating-gate device.

3. The programming method for a flash memory array according to claim 2, characterized in that, The selected memory cell and the non-selected memory cell are connected by a common bit line.

4. The programming method for a flash memory array according to claim 3, characterized in that, When the first voltage applied to the selected memory bit is the programming voltage, the second voltage on the preset memory bit is controlled to be negative.

5. The programming method for a flash memory array according to claim 4, characterized in that, The second voltage is -0.5V to -3.5V.

6. The programming method for a flash memory array according to claim 4, characterized in that, When the first voltage applied to the selected memory bit is the programming voltage, a programming verification voltage is applied to another memory bit in the gate structure of the same selected memory cell to detect whether the threshold voltage of the selected memory cell has reached the expected target value.

7. The programming method for a flash memory array according to claim 1, characterized in that, The bit line connecting the selected memory bit and the preset memory bit in the same column corresponding to the first source-drain region is the first bit line BL0, and the bit line connecting the selected memory bit and the preset memory bit in the same column corresponding to the second source-drain region is the second bit line BL1, where BL0 = 4.5V and BL1 = Vdp.

8. The programming method for a flash memory array according to claim 1, characterized in that, The first and second source / drain regions are N+ doped regions, and a P-type doped channel region is formed between the first and second source / drain regions.

9. The programming method for a flash memory array according to claim 1, characterized in that, The memory cell includes two gate structures, each gate structure being a stacked structure consisting of a gate oxide layer, a floating gate, an inter-gate dielectric layer, and a control gate.

10. The programming method for a flash memory array according to claim 1, characterized in that, The word line structure includes stacked gate dielectric layers and word lines.

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