A DDS-based frequency hopping frequency source module

Abstract

The utility model discloses a frequency hopping frequency source module based on DDS relates to microwave radio communication technical field, including crystal oscillator, power divider and frequency mixer, and power divider and frequency mixer are connected in parallel through first branch and second branch, and first branch includes FPGA chip, PLL chip, DDS chip and first filter who connects in order series connection, and FPGA chip and power divider first output electric connection, and first filter and frequency mixer first input electric connection, and the second output of FPGA chip and the frequency control input of DDS chip electric connection. The utility model discloses the hardware construction under relevant layout, still makes it have the advantage that the output frequency coverage is wide under the original already having the advantage that the frequency switching speed is fast, and the frequency resolution is high.

Description

Technical Field

[0001] This utility model relates to the field of microwave radio frequency communication technology, specifically to a frequency hopping source module based on DDS. Background Technology

[0002] A frequency source is an electronic device or circuit module capable of generating and outputting electrical signals at a specific frequency. As one of the core components of modern electronic systems, its performance directly affects the stability and accuracy of the entire system. Frequency sources play a crucial role in fields such as communication systems, radar detection, radio spectrum analysis, audio processing, medical instruments, and precision measuring instruments. Their main functions include providing a highly stable clock reference for the system, generating programmable carrier signals, and achieving precise frequency modulation. These functions are essential for ensuring the normal operation of electronic equipment.

[0003] The principle of Direct Digital Frequency Synthesis (DDS) is as follows: a reference frequency is generated using a high-precision reference clock source. Then, using modules in digital signal processing technology such as phase accumulators, waveform lookup tables, and digital-to-analog converters, the desired frequency signal is synthesized within the target frequency band through digital operations. Compared with traditional analog frequency synthesis techniques, DDS has the following advantages:

[0004] 1) Frequency resolution can reach the microhertz level;

[0005] 2) Supports nanosecond-level rapid frequency switching;

[0006] 3) It adopts a fully digital architecture, with high integration and low power consumption.

[0007] However, this technology also has inherent limitations:

[0008] 1) Narrow output frequency: The output frequency is limited by the Nyquist sampling theorem and is usually no more than 40% of the reference clock.

[0009] 2) Digital quantization error and nonlinearity of digital-to-analog conversion will introduce more stray components.

[0010] In frequency source designs employing DDS technology, these technical defects can lead to limited system frequency coverage, making it difficult to meet the needs of broadband applications. Utility Model Content

[0011] The purpose of this invention is to solve the problems in the prior art by proposing a frequency hopping frequency source module based on DDS. Through the hardware structure under the relevant layout, it not only has the advantages of fast frequency switching speed and high frequency resolution, but also has the advantage of wide output frequency coverage.

[0012] To solve the above problems, this utility model provides the following technical solution:

[0013] A frequency hopping source module based on DDS includes a crystal oscillator, a power divider electrically connected to the crystal oscillator, and a mixer. The power divider and the mixer are connected in parallel through a first branch and a second branch, wherein:

[0014] The first branch includes an FPGA chip, a PLL chip, a DDS chip, and a first filter connected in series. The FPGA chip at the beginning is electrically connected to the first output terminal of the power divider, and the first filter at the end is electrically connected to the first input terminal of the mixer. The second output terminal of the FPGA chip is electrically connected to the frequency control input terminal of the DDS chip.

[0015] The second branch includes a comb generator and a second filter connected in series. The comb generator at the beginning is electrically connected to the second output of the power divider, and the second filter at the end is electrically connected to the second input of the mixer.

[0016] As a further embodiment of this utility model: the output terminal of the mixer is electrically connected to an amplifier, and the output terminal of the amplifier is electrically connected to an output interface.

[0017] As a further embodiment of this invention, the amplifier and the mixer are electrically connected through a filter component.

[0018] As a further embodiment of this utility model: the filtering component includes a first switch electrically connected to the output terminal of the mixer and a second switch electrically connected to the amplifier. A third filter and a fourth filter are electrically connected between the first switch and the second switch, and the third filter and the fourth filter are connected in parallel.

[0019] As a further embodiment of this invention: the first filter, the third filter, and the fourth filter are all configured as bandpass filters, and the second filter is configured as a point-frequency filter.

[0020] As a further embodiment of this invention, both the first switch and the second switch are configured as radio frequency switches.

[0021] As a further embodiment of this utility model, the power divider is configured as a one-to-two power divider.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] 1. A hardware connection structure is constructed using an FPGA chip, a PLL chip, a DDS chip, a comb generator, and a mixer. This structure uses the FPGA chip to control the PLL chip, generating a high-frequency reference signal to drive the DDS chip. Simultaneously, the FPGA chip controls the DDS chip to generate a wideband adjustable signal, which is then mixed and up-converted with a specific high-order harmonic generated by the comb generator. This hardware configuration, in addition to its existing advantages of fast frequency switching speed and high frequency resolution, also offers the advantage of a wide output frequency coverage.

[0024] 2. By adding a power divider, the signal can be evenly distributed to the two independent branches, reducing signal attenuation and crosstalk.

[0025] 3. By using a dual-branch parallel layout, the two sets of signals are processed separately. The first branch is used for digital frequency synthesis, and the second branch is used for analog spectrum generation. The two branches are independent of each other and do not interfere with each other. They rely on the hardware on the branch to perform their respective functions, thereby reducing the interference of digital noise on the analog signal.

[0026] 4. The hardware structure of the amplifier and filter components is set up in a cascaded layout of mixer → filter component → amplifier → output interface, forming a standardized RF link hardware layout of "mixer-cleaner-amplifier". This hardware layout can further suppress harmonics and intermodulation components generated by mixing and improve the signal-to-noise ratio.

[0027] 5. The hardware structure of the filtering component consists of a first switch, multiple narrowband bandpass filters with different bandwidths, and a second switch. This allows the final output signal to pass through a filter with a narrower passband and better out-of-band suppression by the switch selection, thereby reducing the spurious level and noise of the output signal and improving the spectral purity. Attached Figure Description

[0028] The present invention will be further described below with reference to the accompanying drawings.

[0029] Figure 1 This is a schematic diagram of the circuit principle of this utility model.

[0030] In the diagram: 1. Crystal oscillator; 2. Power divider; 3. Mixer; 4. FPGA chip; 5. PLL chip; 6. DDS chip; 7. First filter; 8. Comb generator; 9. Second filter; 10. Amplifier; 11. First switch; 12. Second switch; 13. Third filter; 14. Fourth filter. Detailed Implementation

[0031] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.

[0032] like Figure 1 As shown, a frequency hopping source module based on DDS includes a circuit board and the following components mounted on the circuit board:

[0033] (1) Crystal oscillator 1, used to generate a stable reference frequency signal (e.g., 100MHz);

[0034] (2) Power divider 2, preferably a one-to-two power divider (SBTC-2-10+), whose input terminal is connected to the output terminal of crystal oscillator 1 through a microstrip line, splitting the reference frequency signal into two outputs;

[0035] (3) The clock input pin of the FPGA chip (EP4CE6E2217N) 4 is connected to the first output terminal of the power divider 2 via a microstrip line;

[0036] (4) The PLL chip (HMC833) 5 has its reference input pin connected to the first control output terminal of the FPGA chip 4 via a microstrip line;

[0037] (5) DDS chip (AD9914) 6, whose reference clock input pin is connected to the output of PLL chip 5 via microstrip line (e.g., to receive 3.6GHz signal), and whose frequency control word input port is connected to the second control output of FPGA chip 4 (e.g., via parallel or serial bus).

[0038] (6) First filter (passband 475-745MHz) 7, preferably a bandpass filter, whose input end is connected to the output end of DDS chip 6 through a microstrip line (for preliminary filtering of DDS output spurious signals);

[0039] (7) A comb generator (implemented using MP4023 step diode and matching circuit) 8, whose input terminal is connected to the second output terminal of power divider 2 via a microstrip line;

[0040] (8) Second filter (center frequency 7700MHz) 9, preferably a point frequency filter, whose input is connected to the output of comb generator 8 via a microstrip line (for selecting a specific harmonic, such as 7700MHz);

[0041] (9) Mixer 3, whose first input terminal (such as RF port) is connected to the output terminal of the first filter 7 through a microstrip line, and whose second input terminal (such as LO port) is connected to the output terminal of the second filter 9 through a microstrip line;

[0042] (10) The first switch (HMC232) 11 is preferably an RF switch, whose common terminal is connected to the output terminal (such as the IF port) of the mixer 3 via a microstrip line, and has at least two gating terminals (such as gating terminal one and gating terminal two).

[0043] (11) The third filter (passband 8175-8310MHz) 13 is preferably a bandpass filter, and its input terminal is connected to the selection terminal of the first switch 11 through a microstrip line.

[0044] (12) The fourth filter (passband 8315-8445MHz) 14 is preferably a bandpass filter, whose input terminal is connected to the second selection terminal of the first switch 11 via a microstrip line.

[0045] (13) The second switch (HMC232) 12 is preferably an RF switch, and its two selection terminals (such as selection terminal one and selection terminal two) are connected to the output terminals of the third filter 13 and the fourth filter 14 respectively through microstrip lines;

[0046] (14) Amplifier (HGC363) 10, whose input terminal is connected to the common terminal of the second switch 12 via a microstrip line;

[0047] (15) Output interface, connected to the output terminal of amplifier 10 via microstrip line.

[0048] The specific connections of the above devices are as follows: The output pin of crystal oscillator 1 is connected to the input pin IN of power divider 2 via a 50-ohm microstrip line ML1. The output pin OUT1 of power divider 2 is connected to the global clock input pin GCK0 of FPGA chip 4 via microstrip line ML2. The output pin OUT2 of power divider 2 is connected to the input pin of comb generator 8 via microstrip line ML3. The output control pin of FPGA chip 4 is connected to the control input interface of PLL chip 5 via the SPI bus. The output pin of PLL chip 5 is connected to the reference clock pin of DDS chip 6 via microstrip line ML4. Simultaneously, the DDS control pin of FPGA chip 4 is connected to the configuration pin of DDS chip 6. The output pin of DDS chip 6 is connected to the input pin of first filter 7 via microstrip line ML5. The output pin of first filter 7 is connected to the RF port of mixer 3 via microstrip line ML5. The output pin of comb generator 8 is connected to the input pin of second filter 9 via microstrip line ML6. The output pin of second filter 9 is connected to the LO port of mixer 3 via microstrip line ML7. The IF port of mixer 3 is connected to the common terminal of the first switch 11 via microstrip line ML8. The first selector terminal of the first switch 11 is connected to the input terminal of the third filter 13 via microstrip line ML9. The second selector terminal of the first switch 11 is connected to the input terminal of the fourth bandpass filter 14 via microstrip line ML10. The output terminal of the third filter 13 is connected to the first selector terminal of the second switch 12 via microstrip line ML11. The output terminal of the fourth filter 14 is connected to the second selector terminal of the second switch 12 via microstrip line ML12. The common terminal of the second switch 12 is connected to the input terminal of amplifier 10 via microstrip line ML13. The output pin of amplifier 10 is connected to the center conductor of the output interface (SMA type RF) via microstrip line ML14.

[0049] In this application, a high-precision crystal oscillator is selected as the reference source to generate a 100MHz signal. This signal is then transmitted to the FPGA chip 4 and the spectrum generator 8 via a power divider 2 (preferably a 1-to-2 power divider). The 100MHz signal serves as the clock signal for the FPGA chip 4, providing timing information for its programming. Under the control of the FPGA chip 4, the PLL chip 5 generates a 3.6GHz frequency signal, which is input to the DDS chip 6 as a reference. Under the control of the FPGA chip 4, the DDS chip 6 generates a 475MHz to 745MHz signal, which passes through a first filter 7 to purify the spectrum of the useful signal and remove spurious signals before being transmitted to the mixer. 3; Another 100MHz signal (which can pass through an additional amplifier) ​​provides the excitation signal to the comb generator 8, which generates rich harmonics at 100MHz; the second filter 9 filters out the 7700MHz signal and makes the spectrum of the useful signal purer, removing spurious signals; the 7700MHz signal (which can pass through an additional amplifier) ​​goes to the mixer 3, where it is mixed with the signal generated by the DDS chip 6 to generate an 8175MHz~8445MHz signal; and the signal is directed to the third filter 13 or the fourth filter 14 by a switch controlled by the FPGA chip 4; finally, the useful signal is amplified by the amplifier 10 and output.

[0050] In this configuration, the GPIO pins GPIO0-GPIO6 of FPGA chip 4 are connected to the selection control pins of the first switch 11 and the second switch 12 via seven TTL level control lines (not marked in the figure) to select the signal path. FPGA chip 4 is connected to the configuration interfaces of PLL chip 5 and DDS chip 6 via an SPI bus to set the output frequency of PLL chip 5 and the frequency control word of DDS chip 6.

[0051] The FPGA chip 4 can be programmed to change the signal generated by the PLL chip 5, thereby enabling the DDS chip 6 to generate signals of different frequencies. The second filter 9 after the comb generator 8 can be replaced as needed to filter out signals of different frequency bands. Ultimately, the output signal of the frequency source can cover different frequency bands.

[0052] Among them, FPGA chip 4 can achieve frequency hopping through seven-bit TTL control signals, with each bit spaced 5MHz apart; this allows the frequency source to have a larger bandwidth and more output frequency points.

[0053] Among them, before the third filter 13 and the fourth filter 14, a switch controlled by FPGA chip 4 can be used to select the branch, so that when designing a single bandpass filter, the passband is narrower and the stopband is wider, resulting in better in-band suppression, less signal crosstalk, and lower spurious emissions.

[0054] It should be noted that the description of the electrical connections, layout, control relationships, and working principles of the aforementioned devices in this application is intended to enable those skilled in the art to clearly understand the technical solutions of this application. The module in this utility model is merely a hardware platform constructed by connecting physical components together through a circuit structure. In use, this module can be implemented in conjunction with existing software; however, it must be pointed out that the software used in conjunction with this module is neither an innovative part of this utility model nor a component of it.

[0055] With the combined effect of the software, this invention has the advantages of wide output frequency coverage and low signal spuriousness. However, the protection of this invention only extends to the hardware network composed of physical components and microstrip lines, and does not involve the improvement and protection of the software.

[0056] This application employs a specific hardware connection structure consisting of an FPGA chip 4, a PLL chip 5, a DDS chip 6, a comb generator 8, and a mixer 3. The FPGA chip 4 controls the PLL chip 5 to generate a high-frequency reference signal to drive the DDS chip 6, and simultaneously controls the DDS chip 6 to generate a wideband adjustable signal. This signal is then mixed and up-converted with a specific high-order harmonic generated by the comb generator 8. This hardware configuration achieves advantages such as a wide output frequency range, fast frequency switching speed, and high frequency resolution.

[0057] Meanwhile, frequency source designs employing DDS technology may suffer from reduced spectral purity, impacting the bit error rate performance of the communication system. This application addresses this by using a switch filter bank structure comprised of a first switch 11, multiple narrowband bandpass filters with varying bandwidths, and a second switch 12. This allows the final output signal to pass through a filter with a narrower passband and better out-of-band suppression via switch selection, reducing spurious signal levels and noise, and improving spectral purity.

[0058] The above description provides a detailed account of one embodiment of the present invention. However, this description is merely a preferred embodiment and should not be construed as limiting the scope of the present invention. All equivalent variations and improvements made within the scope of the claims of the present invention should still fall within the patent coverage of the present invention.

Claims

1. A frequency hopping source module based on DDS, characterized in that, The system includes a crystal oscillator (1), a power divider (2) electrically connected to the crystal oscillator (1), and a mixer (3). The power divider (2) and the mixer (3) are connected in parallel through a first branch and a second branch, wherein: The first branch includes an FPGA chip (4), a PLL chip (5), a DDS chip (6), and a first filter (7) connected in series. The FPGA chip (4) at the beginning is electrically connected to the first output terminal of the power divider (2), and the first filter (7) at the end is electrically connected to the first input terminal of the mixer (3). The second output terminal of the FPGA chip (4) is electrically connected to the frequency control input terminal of the DDS chip (6). The second branch includes a comb generator (8) and a second filter (9) connected in series. The comb generator (8) at the beginning is electrically connected to the second output terminal of the power divider (2), and the second filter (9) at the end is electrically connected to the second input terminal of the mixer (3).

2. The frequency hopping source module based on DDS according to claim 1, characterized in that, The output of the mixer (3) is electrically connected to an amplifier (10), and the output of the amplifier (10) is electrically connected to an output interface.

3. The frequency hopping source module based on DDS according to claim 2, characterized in that, The amplifier (10) and the mixer (3) are electrically connected through a filter component.

4. A frequency hopping source module based on DDS according to claim 3, characterized in that, The filtering component includes a first switch (11) electrically connected to the output of the mixer (3) and a second switch (12) electrically connected to the amplifier (10). A third filter (13) and a fourth filter (14) are electrically connected between the first switch (11) and the second switch (12), and the third filter (13) and the fourth filter (14) are connected in parallel.

5. A frequency hopping source module based on DDS according to claim 4, characterized in that, The first filter (7), the third filter (13) and the fourth filter (14) are all set as bandpass filters, and the second filter (9) is set as a point frequency filter.

6. A frequency hopping source module based on DDS according to claim 4, characterized in that, Both the first switch (11) and the second switch (12) are configured as radio frequency switches.

7. A frequency hopping source module based on DDS according to any one of claims 1-6, characterized in that, The power divider (2) is configured as a one-to-two power divider.

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