Broadband silicon-based terahertz frequency hexapler with high gain and high harmonic suppression ratio

Abstract

The invention discloses a broadband silicon-based terahertz frequency hexapler with high gain and high harmonic suppression ratio, which comprises a compensation capacitor Ccom, an input matching network, a triple frequency core circuit, an interstage amplifier, a double frequency core circuit and an output matching network which are connected in sequence, the input matching network is used for converting a received radio frequency signal into a first differential signal and a second differential signal and then injecting the first differential signal and the second differential signal into the triple frequency core circuit; the frequency tripling core circuit is used for receiving the first differential signal and the second differential signal, generating two third harmonic signals after frequency tripling, and performing differential output on the two third harmonic signals; the interstage amplifier is used for amplifying the two third harmonic signals and transmitting the signals to the frequency doubling core circuit; the double frequency multiplication core circuit is used for enabling the two amplified third harmonic signals to generate two sixth harmonic signals after double frequency multiplication, and outputting the sixth harmonic signals to the output matching network at a single end of a drain node of the double frequency multiplication core circuit; and a source inductor LS of the triple frequency core circuit is used for resonating a stray capacitor Cp from the source of the triple frequency core circuit to the ground.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a broadband silicon-based terahertz hexagonal frequency multiplier with high gain and high harmonic suppression ratio. Background Technology

[0002] In wireless mobile communication systems, the frequency source plays an indispensable and crucial role as an integral part of the transmit and receive links. However, in frequency source design, due to manufacturing processes, the quality factor of passive components, and layout parasitic parameters, the phase noise of voltage-controlled oscillators (VCOs) or phase-locked loops (PLLs) deteriorates significantly at high frequencies. This results in poor phase noise when the VCO or PLL is directly connected to the transceiver system as the local oscillator signal frequency source. Therefore, a frequency multiplier module needs to be added after the VCO or PLL to effectively mitigate the phase noise degradation problem caused by the VCO or PLL at high frequencies.

[0003] Despite significant advancements in existing silicon-based processes, such as the cutoff frequency f of commercial SiGe and CMOS processes... T / f max The speed has already reached 300GHz / 500GHz. However, the research on silicon-based terahertz frequency multipliers faces significant challenges due to the difficulty in nonlinear modeling of transistors in the terahertz band using silicon-based processes, the high substrate loss and leakage caused by low-impedance silicon substrates, and the increasingly significant skin effect as the frequency increases.

[0004] In the terahertz band, existing third harmonic generators largely rely on the nonlinear effects of MOSFETs to generate the third harmonic component. However, under class B bias conditions, the drain current I... d The harmonic components decrease sequentially, and under differential output, I d The larger second harmonic component is canceled out and not utilized. The fundamental component of the output is relatively large while the third harmonic component is very small, resulting in high conversion loss, low output power, and low conversion efficiency. In addition, there is a trade-off in the selection of MOSFET size. The size of the MOSFET is closely related to the conversion loss and output power. If low conversion loss is required, a smaller MOSFET will result in lower conversion loss, but the disadvantage is an increased imaginary part of the input impedance. Even with a large inductor connected in series with the MOSFET gate, the imaginary part of the impedance change curve is still very steep and the loss is increased. In this case, input matching through a transformer will result in extremely narrow-band matching, which cannot fully cover the required frequency band. This leads to problems such as large reflection of the input signal at the sideband frequency, low power of the signal source entering the input terminal, severe roll-off of the conversion gain at the output terminal in the sideband, and uneven output power within the frequency band.

[0005] Therefore, improving the utilization rate of the second harmonic, increasing the conversion efficiency of the third harmonic module, and improving the overall harmonic suppression ratio and wider 3dB bandwidth of the sixth harmonic have become urgent problems to be solved. Summary of the Invention

[0006] The purpose of this invention is to provide a high-gain, high-harmonic rejection ratio broadband silicon-based terahertz sixth harmonic frequency multiplier, to solve the technical problems existing in the prior art, such as low second harmonic utilization, low conversion efficiency of the third harmonic module, low harmonic rejection ratio, and narrow bandwidth. The various technical effects of the preferred solutions among the many technical solutions provided by this invention are detailed below.

[0007] To achieve the above objectives, the present invention provides the following technical solution: This invention provides a high-gain, high-harmonic rejection ratio broadband silicon-based terahertz hexadier, comprising compensation capacitors C connected in sequence. com The circuit consists of an input matching network, a third-harmonic generation core circuit, an interstage amplifier, a second-harmonic generation core circuit, and an output matching network. The compensation capacitor C is also present. com Connected between the input terminal IN and the input matching network; The input matching network is used to receive radio frequency signals, convert the radio frequency signals into a first differential signal and a second differential signal, and then inject them into the third frequency multiplier core circuit. The triple frequency core circuit is used to receive the first differential signal and the second differential signal, and generate two third harmonic signals after triple frequency multiplication, and then perform differential output. The interstage amplifier is used to amplify the two third harmonic signals and transmit them to the second harmonic core circuit. The frequency doubling core circuit is used to generate two sixth harmonic signals after the amplified three third harmonic signals are frequency doubling, and then transmit the two sixth harmonic signals to the output matching network after being output at the drain node of the frequency doubling core circuit. The output matching network is used to perform standard matching of the output impedances of the two sixth harmonic signals output from a single end. The triple frequency multiplier core circuit includes a source inductor L. S The source inductor L S Parasitic capacitance used to connect the source of the third-harmonic generation core circuit to ground. Cp To achieve resonance.

[0008] Optionally, the input matching network includes a capacitor C1 and an input balun TF1, wherein the first input terminal of the input balun TF1 is connected to the first terminal of the capacitor C1 and the compensation capacitor C comThe second terminal of the input balun TF1 is connected to the second terminal of the capacitor C1, and both the second terminal of the input balun TF1 and the second terminal of the capacitor C1 are grounded. The first output terminal of the input balun TF1 is connected to the first input terminal of the triplet core circuit, and the second output terminal of the input balun TF1 is connected to the second input terminal of the triplet core circuit.

[0009] Optionally, the tripler core circuit includes transistor M1, transistor M2, capacitor CN1, and capacitor CN2. The gate of transistor M1 is connected to the first output terminal of the input balun TF1 and the first terminal of capacitor CN2. The drain of transistor M1 is connected to the first terminal of capacitor CN1 and the first input terminal of the interstage amplifier. The source of transistor M1 is connected to the source inductor L. S The first terminal of the capacitor CN1 is connected to the source of the transistor M2, the second terminal of the capacitor CN1 is connected to the gate of the transistor M2, and the second terminal of the capacitor CN2 is connected to the drain of the transistor M2 and the second input terminal of the interstage amplifier. The first input terminal of the triple frequency multiplier core circuit includes the gate of transistor M1 and the first terminal of capacitor CN2; the second input terminal of the triple frequency multiplier core circuit includes the gate of transistor M2 and the second terminal of capacitor CN1; the first output terminal of the triple frequency multiplier core circuit is the drain of transistor M1 and the first terminal of capacitor CN1; and the second output terminal of the triple frequency multiplier core circuit is the drain of transistor M2 and the second terminal of capacitor CN2.

[0010] Optionally, the second harmonic signal of the gate node of transistor M1 or transistor M2 The calculation formula is: , s = j × w, in, The source second harmonic voltage of transistor M1 or transistor M2. s For complex frequencies, C gs The gate-source parasitic capacitance of transistor M1 or transistor M2 is given, and t is the time variation. Ls Let Ls be the inductance value of the source inductor. Cp This refers to the parasitic capacitance from the source of the triplet core circuit to ground.

[0011] Optionally, the second harmonic signal of the gate-source node of transistor M1 or transistor M2 The calculation formula is: .

[0012] Optionally, the interstage amplifier includes amplifier TF3, transistor M3, transistor M4, transistor M5, transistor M6, capacitor CN3, capacitor CN4, capacitor CN5, and capacitor CN6. The gate of transistor M3 is connected to the first output terminal of the third harmonic core circuit and the second terminal of capacitor CN4. The drain of transistor M3 is connected to the first terminal of capacitor CN3 and the first input terminal of amplifier TF3. The source of transistor M3 is connected to the source of transistor M4. The gate of transistor M4 is connected to the second output terminal of the third harmonic core circuit and the second terminal of capacitor CN3. The drain of transistor 4 is connected to the first terminal of capacitor CN4 and the second input terminal of amplifier TF3. The first output terminal of amplifier TF3 is connected to the gate of transistor M5 and the second terminal of capacitor CN6. The drain of transistor M5 is connected to the first terminal of capacitor CN5 and the first input terminal of the frequency doubling core circuit. The source of transistor M5 is connected to the source of transistor M6. The gate of transistor M6 is connected to the second output terminal of amplifier TF3 and the second terminal of capacitor CN5. The drain of transistor M6 is connected to the first terminal of capacitor CN6 and the second input terminal of the frequency doubling core circuit. Wherein, the first input terminal of the interstage amplifier is the gate of the transistor M3, and the second input terminal of the interstage amplifier is connected to the gate of the transistor M4; the first output terminal of the interstage amplifier is the drain of the transistor M5, and the second output terminal of the interstage amplifier is the drain of the transistor M6.

[0013] Optionally, the frequency doubling core circuit includes transistor M7 and transistor M8. The gate of transistor M7 is connected to the first output terminal of the interstage amplifier, and the gate of transistor M8 is connected to the second output terminal of the interstage amplifier. The drains of transistor M7 and transistor M8 are connected to the input terminal of the output matching network, and the sources of transistor M7 and transistor M8 are connected to ground. The first input terminal of the frequency doubling core circuit is the gate of transistor M7, the second input terminal of the frequency doubling core circuit is the gate of transistor M8, and the output terminal of the frequency doubling core circuit includes the drain of transistor M7 and the drain of transistor M8.

[0014] Optionally, the output matching network includes capacitor C2, capacitor C3, stub line TL1, and stub line TL2. The first end of stub line TL1 is connected to the first end of capacitor C2 and the output terminal of the frequency doubling core circuit, and the second end of stub line TL1 is connected to the power supply voltage V. DDThe second terminal of capacitor C2 is connected to the first terminal of capacitor C3 and the first terminal of stub line TL2. The second terminal of stub line TL2 is grounded. The second terminal of capacitor C3 is connected to the signal output terminal OUT. The input terminals of the output matching network include the first terminal of the stub line TL1 and the first terminal of the capacitor C2.

[0015] Optionally, the system also includes transformers TF2 and TF4, wherein transformer TF2 is connected in series between the third harmonic core circuit and the interstage amplifier, and transformer TF4 is connected in series between the interstage amplifier and the second harmonic core circuit.

[0016] Implementing one of the above-described technical solutions of the present invention has the following advantages or beneficial effects: The triplet core circuit employs a fully differential structure to suppress common-mode signals, thereby eliminating even-order harmonics at the output of the triplet core circuit. Simultaneously, a source inductor L is introduced at the source. S The self-mixing of the fundamental and second harmonics is improved, the third harmonic component is enhanced, the second harmonic component is utilized while the fundamental component is reduced, and the conversion gain of the third harmonic is increased without affecting input-output matching. The interstage amplifier uses a standard two-stage differential amplifier, biased in Class A operation, to achieve high gain and output power while reducing harmonic components caused by amplifier nonlinearity, effectively improving the harmonic rejection ratio. The second harmonic core circuit adopts a push-push frequency multiplier structure, which is simple, has a small area, and provides a certain conversion gain and output power. The input matching network uses a balun-based transformer, with a compensation capacitor C connected in series between the input port and the balun. com able to win over S 11 The two resonant points within the frequency band effectively improve the 3dB bandwidth of the sixth frequency multiplier. The output matching network uses a single-ended matching network combining stub lines and capacitors, which can effectively perform out-of-band suppression. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings: Figure 1 This is a circuit diagram of a silicon-based terahertz six-fold frequency multiplier according to an embodiment of the present invention; Figure 2 This is a circuit diagram showing the parasitic capacitance Cp to ground of the differential pair source node in an embodiment of the present invention. Figure 3 This is a circuit diagram of the source-grounded common-mode equivalent circuit in an embodiment of the present invention; Figure 4 In the common-mode equivalent circuit of this invention, an inductor L is introduced at the source. S Circuit diagram; Figure 5 This is a graph showing the variation of the third harmonic output power with the degraded inductance Ls according to an embodiment of the present invention. Figure 6a The present invention introduces a compensation capacitor C. com And without introducing compensation capacitor C com S 11 Curve comparison chart; Figure 6b The present invention introduces a compensation capacitor C. com And without introducing compensation capacitor C com The curve of conversion gain as a function of input frequency; Figure 7 This is a graph of the S-parameters of an embodiment of the present invention; Figure 8 This is a conversion gain curve diagram of an embodiment of the present invention; Figure 9a This is a graph showing the output power versus input power at different frequencies according to an embodiment of the present invention. Figure 9b This is a graph showing the harmonic suppression ratio at different frequencies according to an embodiment of the present invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the present invention clearer, various exemplary embodiments described below will be referenced to the accompanying drawings, which form part of the exemplary embodiments, illustrating various exemplary embodiments that may be used to implement the present invention. Unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. It should be understood that they are merely examples of processes, methods, and apparatuses consistent with some aspects of the present invention disclosed as detailed in the appended claims, and other embodiments may be used, or structural and functional modifications may be made to the embodiments listed herein without departing from the scope and spirit of the present invention.

[0019] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," etc., indicate the orientation or positional relationship based on the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the referred element must have a specific orientation, or be constructed and operated in a specific orientation. The terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. The term "multiple" means two or more. The terms "connected" and "linked" should be interpreted broadly, for example, they can be fixed connections, detachable connections, integral connections, mechanical connections, electrical connections, communication connections, direct connections, indirect connections through an intermediate medium, and can be the internal connection of two elements or the interaction relationship between two elements. The term "and / or" includes any and all combinations of one or more of the related listed items. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0020] To illustrate the technical solution described in this invention, specific embodiments are described below, showing only the parts related to the embodiments of this invention.

[0021] Example 1: like Figure 1 As shown, this invention provides a high-gain, high-harmonic suppression ratio broadband silicon-based terahertz hex multiplier, comprising compensation capacitors C connected in sequence. com Input matching network, third harmonic core circuit, interstage amplifier, second harmonic core circuit and output matching network, compensation capacitor C com Connected between the input IN and the input matching network: An input matching network is used to receive radio frequency signals and convert them into first differential signals and second differential signals, which are then injected into the third frequency multiplier core circuit. The triple frequency core circuit is used to receive the first differential signal and the second differential signal, and generate two third harmonic signals after triple frequency multiplication, and then perform differential output. Interstage amplifiers are used to amplify two third harmonic signals and transmit them to the second harmonic core circuit. The frequency doubling core circuit is used to generate two sixth harmonic signals after the amplified two third harmonic signals are frequency doubled, and the two sixth harmonic signals are output at the drain node of the frequency doubling core circuit and then transmitted to the output matching network. An output matching network is used to standard match the output impedance of the two sixth harmonic signals of a single-ended output. The triple frequency multiplier core circuit includes the source inductor L. S Source inductor L SParasitic capacitance used to connect the source of the third-harmonic generation core circuit to ground. Cp To achieve resonance.

[0022] Specifically, the triplet core circuit uses a fully differential structure to suppress the common-mode signal output, thereby eliminating even-order harmonics at the output of the triplet core circuit; simultaneously, a source inductor L is introduced at the source. S Connect the source electrode to the source inductor L S Parasitic capacitance to ground Cp Resonance is achieved, ensuring that the gate-source second harmonic voltage of the MOS transistors (transistors M1 and M2 as described below) in the third harmonic multiplier core circuit is not zero. This improves the self-mixing of the fundamental and second harmonics, increases the third harmonic component, utilizes the second harmonic component, and reduces the fundamental component. Simultaneously, it improves the conversion gain of the third harmonic without affecting input-output matching. The interstage amplifier uses a standard two-stage differential amplifier, biased in Class A operation, to achieve high gain and output power while reducing harmonic components caused by amplifier nonlinearity, effectively improving the harmonic rejection ratio. The second harmonic multiplier core circuit uses a push-push frequency multiplier structure, which is simple, has a small area, and provides a certain conversion gain and output power. The input matching network uses a balun-based transformer, with a compensation capacitor C connected in series between the input port and the balun. com able to win over S 11 The two resonant points within the frequency band effectively improve the 3dB bandwidth of this sixth frequency multiplier. The output matching network uses a single-ended matching network combining stub lines and capacitors, which can effectively perform out-of-band rejection. The output matching network can match the output impedance of the second frequency multiplier core circuit to the standard 50Ω.

[0023] A compensation capacitor C is connected in series between the input terminal IN and the input matching network. com ， By adjusting the compensation capacitor C com The capacitance value is adjusted so that the two resonant frequencies fall within the desired frequency band, thereby expanding the bandwidth. For example... Figure 6a and Figure 6b As shown, a compensation capacitor C with a value of 190fF is connected in series between the input terminal IN and the input matching network. com And non-series compensation capacitor C com At that time, the S input terminal 11 The curves showing the change in gain and the conversion gain change can be used to see the effect of adding compensation capacitor C. com Subsequently, the gain and bandwidth of the six-fold frequency multiplier were increased by 3dB.

[0024] The interstage amplifier is biased in Class A operation, which means that by properly setting the quiescent operating point of the MOSFET, the MOSFET operates in the center of its linear amplification region. Regardless of whether it's the positive or negative half-cycle of the input signal, the MOSFET is in the on state (neither entering the cutoff region nor the saturation / deep saturation region). Therefore, throughout the entire input signal cycle (360°), there is no signal distortion due to "truncation" or "clipping" effects, resulting in low harmonic components.

[0025] As an optional implementation, the input matching network includes a capacitor C1 and an input balun TF1, with the first input terminal of the input balun TF1 connected to the first terminal of the capacitor C1 and the compensation capacitor C. com The second terminal is connected to the second input terminal of the input balun TF1 and the second terminal of the capacitor C1. Both the second input terminal of the input balun TF1 and the second terminal of the capacitor C1 are grounded. The first output terminal of the input balun TF1 is connected to the first input terminal of the triplet core circuit. The second output terminal of the input balun TF1 is connected to the second input terminal of the triplet core circuit.

[0026] As an optional implementation, the tripler core circuit includes transistors M1 and M2, capacitors CN1 and CN2. The gate of transistor M1 is connected to the first output terminal of the input balun TF1 and the first terminal of capacitor CN2. The drain of transistor M1 is connected to the first terminal of capacitor CN1 and the first input terminal of the interstage amplifier. The source of transistor M1 is connected to the source inductor L. S The first terminal of capacitor CN1 is connected to the source of transistor M2, the second terminal of capacitor CN1 is connected to the gate of transistor M2, and the second terminal of capacitor CN2 is connected to the drain of transistor M2 and the second input terminal of the interstage amplifier. The input terminals of the tripler core circuit include the gate of transistor M1 and the first terminal of capacitor CN2; the second input terminal includes the gate of transistor M2 and the second terminal of capacitor CN1; the first output terminal is the drain of transistor M1 and the first terminal of capacitor CN1; and the second output terminal is the drain of transistor M2 and the second terminal of capacitor CN2. Specifically, transistors M1 and M2 are MOSFETs. Since the parasitic capacitance Cp of the tripler core circuit is uncertain, the inductance value of the introduced degenerate inductance Ls can be determined by parameter scanning. Because under odd-mode excitation, the source node is equivalent to virtual ground, Ls is short-circuited, and it does not affect input-output matching. Figure 5 As shown, obtained by scanning The output has a maximum third harmonic. The input signal of this sixth frequency multiplier is around 21.5GHz, and the multiplier stage transistors are small, resulting in a large imaginary part of its input impedance that varies drastically with frequency, making it difficult to broadband match the input impedance to 50Ω. To improve the imaginary part of the input impedance, an inductor L1 is connected in series between the gate of transistor M1 and the first output terminal of the input balun TF1, and an inductor L2 is connected in series between the gate of transistor M2 and the second output terminal of the input balun TF1, effectively reducing the imaginary impedance. However, inductors L1 and L2 introduce losses, and the imaginary part of the input impedance remains large. Therefore, the input matching network is configured with a compensation capacitor C. com The input matching network has an input balun TF1 connected in parallel with capacitor C1 to ground at the input terminal, and a compensation capacitor C is connected in series at the RF input terminal. com .

[0027] As an optional implementation, the second harmonic signal of the gate node of transistor M1 or transistor M2 The calculation formula is: , s = j × w, in, The source second harmonic voltage of transistor M1 or transistor M2 is s, where s is the complex frequency, and C is the source second harmonic voltage. gs The gate-source parasitic capacitance of transistor M1 or transistor M2, t For the time change, Ls Let Ls be the inductance value of the source inductor. Cp This is the parasitic capacitance from the source to ground of the third-harmonic generation core circuit; Second harmonic signal of the gate-source node of transistor M1 or transistor M2 The calculation formula is: .

[0028] Specifically, when a MOSFET operates in the millimeter-wave terahertz frequency band, its own parasitic capacitance cannot be ignored. In the third-harmonic generation core circuit, there is a parasitic capacitance Cp from the source node of the differential circuit to ground, such as... Figure 2 As shown. The parasitic capacitance Cp from the source to ground in the tripler core circuit is obtained through simulation calculation. For a single MOS transistor (i.e., transistor M1 or transistor M2) in the tripler core circuit, its source-drain current contains many harmonic components. Due to the parasitic capacitance Cp from the source node to ground, the second harmonic current component will have a second harmonic voltage at the source. No source inductor L is introduced in the third-harmonic generation core circuit. S Common mode equivalent model such as Figure 3 As shown, the source of the third harmonic generation core circuit is directly grounded, and the second harmonic signal at the gate node... It can be determined by the source second harmonic voltage. Obtained through voltage division: , In practice, ,so The MOS transistors (transistor M1 or transistor M2) have the same second harmonic voltage at their gates. This leads to the gate-source second harmonic voltage. When the second transconductance is constant, the gate-source second harmonic voltage is positively correlated with the source-drain second harmonic current, so the second harmonic current will decrease, and the self-mixing of the fundamental and second harmonics will weaken.

[0029] Introducing source inductor L in the tripler core circuit S The obtained common-mode equivalent model is as follows Figure 4 As shown, the second harmonic voltage at the gate node of transistor M1 Still caused by the source second harmonic voltage Obtained through voltage division: ,when and At resonance, there is , That is, by connecting a source inductor in series. The gate second harmonic voltage of transistor M1 approaches zero due to resonance with the parasitic capacitance Cp. Therefore, a second harmonic voltage difference exists between the gate and source nodes of transistor M1. The second harmonic current will remain constant. The same applies to transistor M2.

[0030] Since transistors M1 and M2 in the triplet core circuit are biased near the threshold voltage, transistors M1 and M2 can be equivalent to mixer switches, with a source inductor L connected in series at the source. S When the signal reaches ground, the self-mixing of the fundamental and second harmonics is enhanced, thereby increasing the conversion gain of the third harmonic.

[0031] As an optional implementation, the interstage amplifier includes amplifier TF3, transistors M3, M4, M5, and M6, capacitors CN3, CN4, CN5, and CN6. The gate of transistor M3 is connected to the first output terminal of the third-harmonic generation core circuit and the second terminal of capacitor CN4. The drain of transistor M3 is connected to the first terminal of capacitor CN3 and the first input terminal of amplifier TF3. The source of transistor M3 is connected to the source of transistor M4. The gate of transistor M4 is connected to the second output terminal of the third-harmonic generation core circuit and the second terminal of capacitor CN3. The drain of transistor M4 is connected to the first terminal of capacitor CN4 and the second input terminal of amplifier TF3. The first output terminal of amplifier TF3 is connected to the gate of transistor M5 and the second terminal of capacitor CN6. The drain of transistor M5 is connected to the first terminal of capacitor CN5 and the first input terminal of the frequency doubling core circuit. The source of transistor M5 is connected to the source of transistor M6. The gate of transistor M6 is connected to the second output terminal of amplifier TF3 and the second terminal of capacitor CN5. The drain of transistor M6 is connected to the first terminal of capacitor CN6 and the second input terminal of the frequency doubling core circuit. Specifically, the first input terminal of the interstage amplifier is the gate of transistor M3, and the second input terminal of the interstage amplifier is connected to the gate of transistor M4; the first output terminal of the interstage amplifier is the drain of transistor M5, and the second output terminal of the interstage amplifier is the drain of transistor M6. Specifically, because the saturated output power of the third harmonic core circuit is attenuated by the interstage transformers (i.e., transformers TF2 and TF4), the input power of the subsequent second harmonic core circuit is very small, resulting in low conversion gain and output power, far from optimal. Therefore, an interstage amplifier is needed. The interstage amplifier uses a two-stage standard common-source differential amplifier, biased in Class A operation to avoid harmonic components introduced by the nonlinearity of amplifier TF3. Capacitors CN3, CN4, CN5, and CN6 are introduced to improve the stability of amplifier TF3. Transistors M3, M4, M5, and M6 are all MOSFETs. The MOSFET size is chosen so that the 1dB compression point of the interstage amplifier input is close to the output power of the third harmonic core circuit, while maintaining a large gain and output power. This 1dB compression point ensures that the subsequent second harmonic core circuit has high conversion gain and output power.

[0032] As an optional implementation, the frequency doubler core circuit includes transistors M7 and M8. The gate of transistor M7 is connected to the first output terminal of the interstage amplifier, and the gate of transistor M8 is connected to the second output terminal of the interstage amplifier. The drains of transistors M7 and M8 are shared by the input terminal of the output matching network, and the sources of transistors M7 and M8 are shared by ground. Specifically, the first input terminal of the frequency doubler core circuit is the gate of transistor M7, the second input terminal is the gate of transistor M8, and the output terminal includes the drains of transistors M7 and M8. More specifically, the frequency doubler core circuit employs a push-push frequency multiplier, which has a simple structure and good odd harmonic suppression, making it widely used in even-order frequency multiplication.

[0033] As an optional implementation, the output matching network includes capacitor C2, capacitor C3, stub line TL1, and stub line TL2. The first end of stub line TL1 is connected to the first end of capacitor C2 and the output terminal of the frequency doubling core circuit, and the second end of stub line TL1 is connected to the power supply voltage V. DD The second terminal of capacitor C2 is connected to the first terminal of capacitor C3 and the first terminal of stub line TL2. The second terminal of stub line TL2 is grounded, and the second terminal of capacitor C3 is connected to the signal output terminal OUT. The input terminals of the output matching network include the first terminal of stub line TL1 and the first terminal of capacitor C2.

[0034] As an optional implementation, transformers TF2 and TF4 are also included. Transformer TF2 is connected in series between the third harmonic core circuit and the interstage amplifier, and transformer TF4 is connected in series between the interstage amplifier and the second harmonic core circuit. Specifically, the saturated output power of the third harmonic core circuit is attenuated by transformers TF2 and TF4 before being transmitted to the second harmonic core circuit. The input power of the second harmonic core circuit is relatively small, resulting in a very small conversion gain and output power, far from reaching the optimal state. Therefore, an interstage amplifier is set between transformers TF2 and TF4.

[0035] More specifically, the S-parameter simulation results are as follows: Figure 7 As shown, S 11 It is better than 10dB in the 19.5GHz-26GHz frequency band, S 22 It outperforms the target frequency band by 10 dB in the 122.7 GHz–133.6 GHz range. The conversion gain curve is shown below. Figure 8As shown, when the fixed signal source power is -0.8dBm, the 3dB operating bandwidth covers 120.3GHz-136.5GHz, with a relative bandwidth of 12.7%. The maximum conversion gain of 1.45dB is found at 127.8GHz. The output power versus input power curves at different frequencies are shown in Figure 9(a). As the input power increases, the output power first increases linearly, then gradually compresses, and finally tends to saturate, with a maximum saturated output power of 3.2dBm at 126GHz. The harmonic suppression ratio and harmonic spectrum at different frequencies are shown in Figure 9(b). The output harmonic suppression ratio at different output frequencies is greater than 35dBc for each harmonic.

[0036] The embodiment is merely a specific example and does not indicate that this is the only way to implement the present invention.

[0037] The above description is merely a preferred embodiment of the present invention. Those skilled in the art will understand that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the present invention. Furthermore, under the teachings of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of the present invention.

Claims

1. A broadband silicon-based terahertz hexadier with high gain and high harmonic suppression ratio, characterized in that, Including the compensation capacitor C connected in sequence com The circuit consists of an input matching network, a third-harmonic generation core circuit, an interstage amplifier, a second-harmonic generation core circuit, and an output matching network. The compensation capacitor C is also present. com Connected between the input terminal IN and the input matching network; The input matching network is used to receive radio frequency signals, convert the radio frequency signals into a first differential signal and a second differential signal, and then inject them into the third frequency multiplier core circuit. The triple frequency core circuit is used to receive the first differential signal and the second differential signal, and generate two third harmonic signals after triple frequency multiplication, and then perform differential output. The interstage amplifier is used to amplify the two third harmonic signals and transmit them to the second harmonic core circuit. The frequency doubling core circuit is used to generate two sixth harmonic signals after the amplified three third harmonic signals are frequency doubling, and then transmit the two sixth harmonic signals to the output matching network after being output at the drain node of the frequency doubling core circuit. The output matching network is used to perform standard matching of the output impedances of the two sixth harmonic signals output from a single end. The triple frequency multiplier core circuit includes a source inductor L. S The source inductor L S Parasitic capacitance used to connect the source of the third-harmonic generation core circuit to ground. Cp To achieve resonance.

2. The broadband silicon-based terahertz hexadier with high gain and high harmonic suppression ratio according to claim 1, characterized in that, The input matching network includes a capacitor C1 and an input balun TF1, wherein the first input terminal of the input balun TF1 is connected to the first terminal of the capacitor C1 and the compensation capacitor C. com The second terminal of the input balun TF1 is connected to the second terminal of the capacitor C1, and both the second terminal of the input balun TF1 and the second terminal of the capacitor C1 are grounded. The first output terminal of the input balun TF1 is connected to the first input terminal of the triplet core circuit, and the second output terminal of the input balun TF1 is connected to the second input terminal of the triplet core circuit.

3. The broadband silicon-based terahertz hexadier with high gain and high harmonic suppression ratio according to claim 2, characterized in that, The tripler core circuit includes transistors M1 and M2, capacitors CN1 and CN2. The gate of transistor M1 is connected to the first output terminal of the input balun TF1 and the first terminal of capacitor CN2. The drain of transistor M1 is connected to the first terminal of capacitor CN1 and the first input terminal of the interstage amplifier. The source of transistor M1 is connected to the source inductor L. S The first terminal of the capacitor CN1 is connected to the source of the transistor M2, the second terminal of the capacitor CN1 is connected to the gate of the transistor M2, and the second terminal of the capacitor CN2 is connected to the drain of the transistor M2 and the second input terminal of the interstage amplifier. The first input terminal of the triple frequency multiplier core circuit includes the gate of transistor M1 and the first terminal of capacitor CN2; the second input terminal of the triple frequency multiplier core circuit includes the gate of transistor M2 and the second terminal of capacitor CN1; the first output terminal of the triple frequency multiplier core circuit is the drain of transistor M1 and the first terminal of capacitor CN1; and the second output terminal of the triple frequency multiplier core circuit is the drain of transistor M2 and the second terminal of capacitor CN2.

4. The high-gain, high-harmonic suppression ratio broadband silicon-based terahertz hexadier according to claim 3, characterized in that, The second harmonic signal of the gate node of transistor M1 or transistor M2 The calculation formula is: ， s = j × w, in, The source second harmonic voltage of transistor M1 or transistor M2. s For complex frequencies, C gs The gate-source parasitic capacitance of transistor M1 or transistor M2. t For the time change, Ls Let Ls be the inductance value of the source inductor. Cp This refers to the parasitic capacitance from the source of the triplet core circuit to ground.

5. The broadband silicon-based terahertz hexadier with high gain and high harmonic suppression ratio according to claim 4, characterized in that, The second harmonic signal of the gate-source node of transistor M1 or transistor M2 The calculation formula is: 。 6. The high-gain, high-harmonic suppression ratio broadband silicon-based terahertz hexadier according to claim 3, characterized in that, The interstage amplifier includes amplifier TF3, transistors M3, M4, M5, and M6, capacitors CN3, CN4, CN5, and CN6. The gate of transistor M3 is connected to the first output terminal of the third harmonic core circuit and the second terminal of capacitor CN4. The drain of transistor M3 is connected to the first terminal of capacitor CN3 and the first input terminal of amplifier TF3. The source of transistor M3 is connected to the source of transistor M4. The gate of transistor M4 is connected to the second output terminal of the third harmonic core circuit and the second terminal of capacitor CN3. The drain of transistor M5 is connected to the first terminal of capacitor CN4 and the second input terminal of amplifier TF3. The first output terminal of amplifier TF3 is connected to the gate of transistor M5 and the second terminal of capacitor CN6. The drain of transistor M5 is connected to the first terminal of capacitor CN5 and the first input terminal of the frequency doubling core circuit. The source of transistor M5 is connected to the source of transistor M6. The gate of transistor M6 is connected to the second output terminal of amplifier TF3 and the second terminal of capacitor CN5. The drain of transistor M6 is connected to the first terminal of capacitor CN6 and the second input terminal of the frequency doubling core circuit. Wherein, the first input terminal of the interstage amplifier is the gate of the transistor M3, and the second input terminal of the interstage amplifier is connected to the gate of the transistor M4; the first output terminal of the interstage amplifier is the drain of the transistor M5, and the second output terminal of the interstage amplifier is the drain of the transistor M6.

7. The broadband silicon-based terahertz hexadier with high gain and high harmonic suppression ratio according to claim 6, characterized in that, The frequency doubling core circuit includes transistor M7 and transistor M8. The gate of transistor M7 is connected to the first output terminal of the interstage amplifier, and the gate of transistor M8 is connected to the second output terminal of the interstage amplifier. The drains of transistor M7 and transistor M8 are connected to the input terminal of the output matching network, and the sources of transistor M7 and transistor M8 are connected to ground. The first input terminal of the frequency doubling core circuit is the gate of transistor M7, the second input terminal of the frequency doubling core circuit is the gate of transistor M8, and the output terminal of the frequency doubling core circuit includes the drain of transistor M7 and the drain of transistor M8.

8. The high-gain, high-harmonic suppression ratio broadband silicon-based terahertz hexadier according to claim 7, characterized in that, The output matching network includes capacitor C2, capacitor C3, stub line TL1, and stub line TL2. The first end of stub line TL1 is connected to the first end of capacitor C2 and the output terminal of the frequency doubling core circuit. The second end of stub line TL1 is connected to the power supply voltage V. DD The second terminal of capacitor C2 is connected to the first terminal of capacitor C3 and the first terminal of stub line TL2. The second terminal of stub line TL2 is grounded. The second terminal of capacitor C3 is connected to the signal output terminal OUT. The input terminals of the output matching network include the first terminal of the stub line TL1 and the first terminal of the capacitor C2.

9. The high-gain, high-harmonic suppression ratio broadband silicon-based terahertz hexadier according to claim 1, characterized in that, It also includes transformers TF2 and TF4, with transformer TF2 connected in series between the third harmonic core circuit and the interstage amplifier, and transformer TF4 connected in series between the interstage amplifier and the second harmonic core circuit.

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