Semiconductor structure and forming method thereof
By introducing a second and a third spacer layer into the gate spacer, the leakage current problem caused by hot carrier injection in high-voltage semiconductor devices is solved, thereby improving the performance of electronic devices.
Patent Information
- Application Number
- CN202411069458.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-07-11
- Filing Date
- 2024-08-06
- Publication Date
- 2026-01-13
AI Technical Summary
Existing electronic devices have not effectively solved the leakage current problem caused by hot carrier injection (HCI) in high-voltage semiconductor components, which cannot meet the requirements for performance improvement.
A second and a third spacer layer are introduced into the gate spacer, extending along the sidewall of the gate electrode and towards the source/drain, respectively, to increase the width of the gate spacer and improve the leakage current caused by HCI.
By increasing the width of the gate gap wall, leakage current caused by hot carrier injection is effectively reduced, thus improving the performance of electronic devices.
Smart Images
Figure CN121335149A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a semiconductor structure and a method for forming the same. Background Technology
[0002] As electronic devices move towards miniaturization and users' performance requirements for these devices gradually increase, metal-oxide-semiconductor (MOS) devices used in high-voltage semiconductor components are increasingly affected by hot carrier injection (HCI), making current electronic devices insufficient to meet current or future expectations. Summary of the Invention
[0003] The present invention provides a semiconductor structure and a method for forming the same, wherein a second spacer layer and a third spacer layer in the gate spacer each have a portion extending in the direction from the gate electrode to the source / drain electrode, thereby improving leakage current caused by hot carrier injection (HCI) by increasing the width of the gate spacer.
[0004] An embodiment of the present invention provides a semiconductor structure including a substrate, a gate structure disposed on the substrate, and a source / drain electrode disposed in the substrate on opposite sides of the gate structure. The gate structure includes a gate dielectric layer disposed on the substrate, a gate electrode disposed on the gate dielectric layer, a first gate spacer wall disposed on opposite sidewalls of the gate electrode, and a second gate spacer wall disposed on the first gate spacer wall. Each of the first gate spacers includes a first spacer wall layer on the sidewall of the gate electrode, a second spacer wall layer on the first spacer wall layer, and a third spacer wall layer on the second spacer wall layer. The second and third spacer wall layers each include a first portion extending along the sidewall of the gate electrode and a second portion extending in the direction from the gate electrode to the source / drain electrode.
[0005] In some embodiments, the thickness of the first portion of the second spacer wall layer is approximately equal to the thickness of the second portion of the second spacer wall layer.
[0006] In some embodiments, the thickness of the first portion of the third spacer wall layer is approximately equal to the thickness of the second portion of the third spacer wall layer.
[0007] In some embodiments, the gate dielectric layer includes a first portion below the gate electrode and a second portion below the second portions of each of the second and third spacer layers.
[0008] In some embodiments, the thickness of the first portion of the gate dielectric layer is greater than the thickness of the second portion of the gate dielectric layer.
[0009] In some embodiments, the second gate spacer includes a fourth spacer layer disposed on the third spacer layer and a fifth spacer layer disposed on the fourth spacer layer. The fourth spacer layer includes a first portion extending along the sidewall of the gate electrode and a second portion extending in the direction from the gate electrode to the source / drain electrode.
[0010] In some embodiments, the thickness of the first portion of the fourth spacer layer is approximately equal to the thickness of the second portion of the fourth spacer layer, while the fifth spacer layer includes a portion in which the thickness varies with the direction perpendicular to the surface of the substrate.
[0011] In some embodiments, the bottom surface of the fifth gap wall layer is disposed at a level higher than the top surface of the gate dielectric layer.
[0012] In some embodiments, the fifth gap wall layer includes a first profile and a second profile different from the first profile on the side surface away from the gate electrode.
[0013] In some embodiments, the first profile is positioned above the second profile relative to the surface of the substrate and has a slope that is less than that of the second profile.
[0014] In some embodiments, the materials of the first, second, and fifth spacer layers comprise nitrides, while the materials of the third and fourth spacer layers comprise oxides.
[0015] In some embodiments, the material of the first spacer layer is different from the materials of the second and fifth spacer layers.
[0016] An embodiment of the present invention provides a method for forming a semiconductor structure, comprising the following steps: forming a gate dielectric layer on a substrate; forming a gate electrode on the gate dielectric layer; forming a first spacer layer on opposite sidewalls of the gate electrode; forming a second spacer material layer covering the gate dielectric layer, the first spacer layer, and the gate electrode over the substrate; forming a third spacer material layer on the second spacer material layer; forming a second gate spacer material layer on the third spacer material layer; removing a portion of the second gate spacer material layer to form a second gate spacer over opposite sidewalls of the gate electrode; removing portions of the third spacer material layer and the second spacer material layer to form the third spacer layer and the second spacer layer respectively on the first spacer layer; and forming a source / drain electrode in the substrate at opposite sides of the gate electrode. The second spacer layer and the third spacer layer each include a first portion extending along the sidewall of the gate electrode and a second portion extending in the direction from the gate electrode to the source / drain electrode.
[0017] In some embodiments, the substrate includes a first region on which a gate dielectric layer is formed and a second region different from the first region and in which an epitaxial pattern is formed, and the steps of forming a second spacer material layer and a third spacer material layer include: forming a first mask layer on the substrate to define the epitaxial pattern before forming the epitaxial pattern, wherein the first mask layer covers the gate dielectric layer, the first spacer layer and the gate electrode in the first region; forming a second mask layer on the first mask layer and the epitaxial pattern after forming the epitaxial pattern; patterning the second mask layer to form the third spacer material layer; and removing the portion of the first mask layer not covered by the third spacer material layer to form the second spacer material layer.
[0018] In some embodiments, the thickness of the first portion of the second or third spacer layer is approximately equal to the thickness of the second portion of the second or third spacer layer.
[0019] In some embodiments, the second gate spacer includes: a fourth spacer layer formed on the third spacer layer; and a fifth spacer layer formed on the fourth spacer layer. The fourth spacer layer includes a first portion extending along the sidewall of the gate electrode and a second portion extending in the direction from the gate electrode to the source / drain.
[0020] In some embodiments, the thickness of the first portion of the fourth spacer layer is approximately equal to the thickness of the second portion of the fourth spacer layer, while the fifth spacer layer includes a portion in which the thickness varies with the direction perpendicular to the surface of the substrate.
[0021] In some embodiments, the bottom surface of the fifth gap wall layer is formed at a level higher than the top surface of the gate dielectric layer.
[0022] In some embodiments, the fifth gap wall layer includes a first profile and a second profile different from the first profile on the side surface away from the gate electrode, and the first profile is positioned above the second profile and has a slope less than that of the second profile relative to the surface of the substrate.
[0023] In some embodiments, the materials of the first, second, and fifth spacer layers comprise nitrides, while the materials of the third and fourth spacer layers comprise oxides.
[0024] Based on the above, in the above semiconductor structure and its formation method, the second spacer layer and the third spacer layer each include an extension portion extending from the gate electrode to the source / drain electrode, so the leakage current caused by hot carrier injection (HCI) can be improved by increasing the width of the gate spacer. Attached Figure Description
[0025] Figures 1 to 10This is a cross-sectional schematic diagram of a method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation
[0026] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.
[0027] The invention is described more fully with reference to the accompanying drawings of this embodiment. However, the invention may be embodied in various different forms and should not be limited to the embodiments described herein. The thicknesses of layers and regions in the drawings are enlarged for clarity. The same or similar reference numerals denote the same or similar elements, which will not be repeated in the following paragraphs.
[0028] It should be understood that when an element is referred to as being "on" or "connected" to another element, it may be directly on or connected to the other element, or there may be an intermediate element present. If an element is referred to as being "directly on" or "directly connected" to another element, there is no intermediate element present. As used herein, "connection" may refer to a physical and / or electrical connection, while "electrical connection" or "coupling" may refer to the presence of other elements between the two elements.
[0029] As used herein, “about,” “approximately,” or “substantially” includes the average of the mentioned value and a specific value within an acceptable range of deviations that can be determined by a person skilled in the art, taking into account the measurement under discussion and a specific number of errors associated with the measurement (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations of the value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, the use of “about,” “approximately,” or “substantially” herein may be chosen based on the optical, etched, or other properties to select a more acceptable range of deviations or standard deviations, and may not require a single standard deviation to apply to all properties.
[0030] The terminology used herein is for illustrative purposes only and is not intended to limit the invention. In this context, the singular form includes the plural form unless the context otherwise requires.
[0031] Figures 1 to 10 This is a cross-sectional schematic diagram of a method for forming a semiconductor structure according to an embodiment of the present invention.
[0032] First, please refer to Figure 1A substrate 100 is provided. The substrate 100 may include a first region R1, a second region R2, and a third region R3. In some embodiments, the first region R1 may be a region in which a medium-voltage semiconductor element is disposed. In some embodiments, the second region R2 and the third region R3 may be regions in which low-voltage semiconductor elements are disposed, respectively. The operating voltage of the medium-voltage semiconductor element (e.g., 8V) may be greater than the operating voltage of the low-voltage semiconductor element (e.g., 0.9V).
[0033] Substrate 100 may include a semiconductor substrate or a semiconductor-on-insulator (SOI) substrate. The semiconductor material in the semiconductor substrate or SOI substrate may include elemental semiconductors, alloy semiconductors, or compound semiconductors. For example, elemental semiconductors may include Si or Ge. Alloy semiconductors may include SiGe, SiGeC, etc. Compound semiconductors may include SiC, III-V semiconductor materials, or II-VI semiconductor materials. III-V semiconductor materials may include GaN, GaP, GaAs, AlN, AlP, AlAs, InN, InP, InAs, GaNP, GaNAs, GaPAs, AlNP, AlNAs, AlPAs, InNP, InNAs, InPAs, GaAlNP, GaAlNAs, GaAlPAs, GaInNP, GaInNAs, GaInPAs, InAlNP, InAlNAs, or InAlPAs. Group II-VI semiconductor materials may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, HgS, HgSe, HgTe, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, or HgZnSTe. The semiconductor material may be doped with a dopant of a first conductivity type or a dopant of a second conductivity type complementary to the first conductivity type. For example, the first conductivity type may be N-type, and the second conductivity type may be P-type. In some embodiments, the second region R2 and the third region R3 of the substrate 100 may be doped with dopants of different conductivity types. For example, the substrate 100 may be doped with a first conductivity type (e.g., N-type) dopant in the second region R2, and the substrate 100 may be doped with a second conductivity type (e.g., P-type) dopant in the third region R3. In some embodiments, the first region R1, the second region R2, and the third region R3 of the substrate 100 may be defined by a component isolation structure (not shown), but are not limited thereto.
[0034] Next, a gate dielectric material layer 110 is formed on a first region R1 of the substrate 100. In some embodiments, the gate dielectric material layer 110 may include a material such as silicon oxide for the gate dielectric layer. In some embodiments, the gate dielectric material layer 110 may be formed by the following steps: First, a portion of the substrate 100 is removed to form a trench. Then, the gate dielectric material layer 110 is formed by processes such as thermal oxidation and / or deposition. Figure 1 As shown, the top surface of the gate dielectric material layer 110 formed in the groove may be lower than the top surface of the substrate 100 in other regions (e.g., the second region R2 or the third region R3).
[0035] Then, a gate electrode 120 is formed on the gate dielectric material layer 110. In some embodiments, a capping layer 130 comprising a first material layer 132 and a second material layer 134 is also formed on the gate electrode 120. In some embodiments, the material of the first material layer 132 may be different from the material of the second material layer 134. For example, the first material layer 132 may comprise a nitride, while the second material layer 134 may comprise an oxide. In some embodiments, a stacked structure STK comprising the gate electrode 120 and the capping layer 130 may be formed on the second region R2 and the third region R3 of the substrate 100.
[0036] Then, a first spacer layer 140 is formed on the opposite sidewalls of the stacked structure STK. In some embodiments, the first spacer layer 140 may include a nitride such as SiCN. In some embodiments, the gate dielectric layer 110 includes a first portion below the gate electrode 120 and the first spacer layer 140 and a second portion different from the first portion, wherein the thickness of the first portion is greater than the thickness of the second portion.
[0037] Subsequently, a first mask layer 150 covering the gate dielectric material layer 110, the first spacer layer 140, and the stacked structure STK is formed over the substrate 100. In some embodiments, in a third region R3 of the substrate 100, the first mask layer 150, together with the stacked structure STK and the first spacer layer 140, may define a region for forming an epitaxial pattern 102 in the third region R3 of the substrate 100. Then, an epitaxial process can be performed on this region to form a pattern such as... Figure 1 The epitaxial pattern 102 is shown. In some embodiments, the epitaxial pattern 102 may include a material such as silicon germanium (SiGe). In some embodiments, the first mask layer 150 may include a nitride such as silicon nitride (SiN).
[0038] In some embodiments, such as Figure 1As shown, the substrate 100 may include a first region R1 on which a gate dielectric material layer 110 is formed, a third region R3 different from the first region R1 and in which an epitaxial pattern 102 is formed, and a second region R2 different from the first region R1 and the third region R3. In this embodiment, the first region R1 of the substrate 100 may be a region in which a medium-voltage semiconductor element is formed, the second region R2 of the substrate 100 may be a region in which a low-voltage semiconductor element is formed and doped with a first conductivity type (e.g., N-type), and the third region R3 of the substrate 100 may be a region in which a low-voltage semiconductor element is formed and doped with a second conductivity type (e.g., P-type).
[0039] Next, please refer to Figure 1 and Figure 2 After forming the epitaxial pattern 102, a second mask layer 160 is formed on the first mask layer 150 and the epitaxial pattern 102. The material of the second mask layer 160 is different from the material of the first mask layer 150. In some embodiments, the second mask layer 160 may include an oxide such as silicon oxide. In some embodiments, the thickness of the second mask layer 160 may be about 50 Å, but is not limited thereto.
[0040] Then, the second mask layer 160 is patterned to form a third spacer wall material layer 162. In some embodiments, the third spacer wall material layer 162 may be formed by the following steps. First, please refer to... Figure 3 A mask pattern PR1 is formed on a first region R1 of the substrate 100 to cover the second mask layer 160 in the first region R1 and expose the second mask layers 160 in the second region R2 and the third region R3. In some embodiments, the mask pattern PR1 may be a photoresist pattern. Next, please refer to... Figure 4 The second mask layer 160 exposed by the mask pattern PR1 is removed to form a third spacer wall material layer 162 in the first region R1. In some embodiments, wet etching may be used to remove the second mask layer 160 exposed by the mask pattern PR1.
[0041] Next, please refer to Figure 4 and Figure 5 The mask pattern PR1 is removed, and the portion of the first mask layer 150 not covered by the third spacer wall material layer 162 is removed to form the second spacer wall material layer 152. In some embodiments, the portion of the first mask layer 150 not covered by the third spacer wall material layer 162 can be removed by wet etching using an etchant such as phosphoric acid (H3PO4).
[0042] like Figure 5As shown, a second spacer material layer 152 is formed over the substrate 100 to cover the gate dielectric material layer 110, the first spacer layer 140 and the stacked structure STK, while a third spacer material layer 162 is formed on the second spacer material layer 152.
[0043] Next, please refer to Figure 5 and Figure 6 A fourth spacer material layer 170 and a fifth spacer material layer 180 are sequentially formed on a substrate 100 to form a second gate spacer material layer containing the fourth spacer material layer 170 and the fifth spacer material layer 180 on a third spacer material layer 162 in a first region R1; a second gate spacer material layer containing the fourth spacer material layer 170 and the fifth spacer material layer 180 is formed on a substrate 100, an epitaxial pattern 102, a first spacer layer 140, and a stacked structure STK in a third region R3; and a second gate spacer material layer containing the fourth spacer material layer 170 and the fifth spacer material layer 180 is formed on a substrate 100, an epitaxial pattern 102, a first spacer layer 140, and a stacked structure STK in a third region R3. The material of the fourth spacer material layer 170 is different from the material of the fifth spacer material layer 180. For example, the fourth spacer material layer 170 may include an oxide such as silicon oxide, while the fifth spacer material layer 180 may include a nitride such as silicon nitride.
[0044] Then, as Figures 6 to 10 As shown, a portion of the fourth spacer material layer 170 and the fifth spacer material layer 180 (e.g., a portion located above the top surface of the stacked structure STK and the top surface of the substrate 100) is removed to form a second gate spacer SP2 above the opposite sidewalls of the stacked structure STK. The second gate spacer SP2 may be formed to include the fourth spacer layer 172 and the fifth spacer layer 182.
[0045] Then, a portion of the third spacer material layer 162 and the second spacer material layer 152 is removed (e.g., a portion located above the top surface of the stacked structure STK and above the top surface of the substrate 100) to form the third spacer layer 164 and the second spacer layer 154 on the first spacer layer 140, thereby forming a first gate spacer SP1 comprising the first spacer layer 140, the second spacer layer 154 and the third spacer layer 164.
[0046] In some embodiments, such as Figure 6 and Figure 7As shown, in the step of forming the second gate spacer SP2, a portion of the third spacer material layer 162 located above the top surface of the stacked structure STK and above the top surface of the substrate 100 is also removed to form the third spacer layer 164. In some embodiments, the second spacer layer 154 can be formed by the following steps. First, please refer to... Figure 8 A mask pattern PR2 is formed that covers the second region R2 and the third region R3 and exposes the first region R1. In some embodiments, the mask pattern PR2 may be a photoresist pattern. Next, please refer to... Figure 8 and Figure 9 Dry etching can be used to remove the portion of the second spacer material layer 152 exposed by the second gate spacer SP2 and the underlying third spacer layer 164, as well as a portion of the gate dielectric material layer 110 below that portion, to form the second spacer layer 154 and the gate dielectric layer 112. In some embodiments, the dry etching described above may be used in conjunction with, for example, some necessary mask patterns, but is not limited thereto. Then, please refer to... Figure 9 and Figure 10 After forming the second spacer layer 154 and the gate dielectric layer 112, the mask pattern PR2 is removed. After the above steps, a gate structure GS comprising the gate dielectric layer 112, the gate electrode 120, the capping layer 130, the first gate spacer SP1, and the second gate spacer SP2 can be formed in the first region R1.
[0047] Next, please refer to Figure 10 A source / drain 190 is formed in the substrate 100 on the opposite side of the gate structure GS. In this embodiment, as... Figure 10 As shown, the second spacer layer 154 and the third spacer layer 164 in the gate structure GS each include a first portion extending along the sidewall of the gate electrode 120 and a second portion extending in the direction from the gate electrode 120 to the source / drain 190. In this way, the gate structure GS can have a wider gate spacer (first gate spacer SP1 and second gate spacer SP2) to avoid leakage current caused by hot carrier injection (HCI).
[0048] In some embodiments, such as Figure 10 As shown, the thickness of the second spacer wall layer 154 or the third spacer wall layer 164 in the first part can be formed to be approximately equal to the thickness of the second spacer wall layer 154 or the third spacer wall layer 164 in the second part.
[0049] The second gate spacer SP2 may be formed to include a fourth spacer layer 172 and a fifth spacer layer 182, wherein the fourth spacer layer 172 is formed on the third spacer layer 164, and the fifth spacer layer 182 is formed on the fourth spacer layer 172. In some embodiments, such as Figure 10 As shown, the fourth spacer layer 172 may include a first portion extending along the sidewall of the gate electrode 120 and a second portion extending in the direction from the gate electrode 120 to the source / drain 190. In some embodiments, the thickness of the first portion of the fourth spacer layer 172 may be formed to be approximately equal to the thickness of the second portion of the fourth spacer layer 172, while the fifth spacer layer 182 may be formed to include a portion in which the thickness varies with a direction perpendicular to the surface of the substrate 100.
[0050] In some embodiments, the bottom surface of the fifth spacer layer 182 may be formed at a level higher than the top surface of the gate dielectric layer 112. In some embodiments, the fifth spacer layer 182 may be formed on a side surface away from the gate electrode 120 including a first profile and a second profile different from the first profile, wherein the first profile is positioned above the second profile and has a slope less than that of the second profile relative to the surface of the substrate 100.
[0051] The following will be through Figure 10 The following example illustrates a semiconductor structure according to an embodiment of the present invention. This semiconductor structure can be formed using the methods described above, but is not limited thereto.
[0052] Please refer to Figure 10 The semiconductor structure includes a substrate 100, a gate structure GS disposed on the substrate 100, and a source / drain electrode 190 disposed on opposite sides of the gate structure GS in the substrate 100. The gate structure GS includes a gate dielectric layer 112 disposed on the substrate 100, a gate electrode 120 disposed on the gate dielectric layer 112, a first gate spacer SP1 disposed on opposite sidewalls of the gate electrode 120, and a second gate spacer SP2 disposed on the first gate spacer SP1. Each of the first gate spacers SP1 includes a first spacer layer 140 on the sidewall of the gate electrode 120, a second spacer layer 154 on the first spacer layer 140, and a third spacer layer 164 on the second spacer layer 154. The second spacer layer 154 and the third spacer layer 164 each include a first portion extending along the sidewall of the gate electrode 120 and a second portion extending in the direction from the gate electrode 120 to the source / drain electrode 190.
[0053] In some embodiments, the thickness of the first portion of the second spacer wall layer 154 may be approximately equal to the thickness of the second portion of the second spacer wall layer 154. In some embodiments, the thickness of the first portion of the third spacer wall layer 164 may be approximately equal to the thickness of the second portion of the third spacer wall layer 164.
[0054] In some embodiments, the gate dielectric layer 112 may include a first portion below the gate electrode 120 and a second portion below the second portions of each of the second spacer layers 154 and the third spacer layer 164. In some embodiments, the thickness of the first portion of the gate dielectric layer 112 may be greater than the thickness of the second portion of the gate dielectric layer 112.
[0055] In some embodiments, the second gate spacer SP2 may include a fourth spacer layer 172 disposed on the third spacer layer 164 and a fifth spacer layer 182 disposed on the fourth spacer layer 172. The fourth spacer layer 172 may include a first portion extending along the sidewall of the gate electrode 120 and a second portion extending in the direction from the gate electrode 120 to the source / drain 190. In some embodiments, the thickness of the first portion of the fourth spacer layer 172 may be approximately equal to the thickness of the second portion of the fourth spacer layer 172, while the fifth spacer layer 182 may include a portion in which the thickness varies with a direction perpendicular to the surface of the substrate 100.
[0056] In some embodiments, the bottom surface of the fifth spacer layer 182 may be disposed at a level higher than the top surface of the gate dielectric layer 112. In some embodiments, the fifth spacer layer 182 includes a first profile and a second profile different from the first profile on its side surface away from the gate electrode 120. In some embodiments, the first profile is positioned above the second profile and has a slope less than that of the second profile relative to the surface of the substrate 100.
[0057] In some embodiments, the materials of the first spacer layer 140, the second spacer layer 154, and the fifth spacer layer 182 comprise nitrides, while the materials of the third spacer layer 164 and the fourth spacer layer 172 comprise oxides. In some embodiments, the material of the first spacer layer 140 may be different from the materials of the second spacer layer 154 and the fifth spacer layer 182. For example, the first spacer layer 140 may comprise SiCN, while the second spacer layer 154 and the fifth spacer layer 182 may comprise SiN.
[0058] In summary, in the semiconductor structure and its formation method of the above embodiments, in the first gate gap wall of the gate structure, the second gap wall layer and the third gap wall layer each include an extension portion extending from the gate electrode to the source / drain electrode. This extension portion can further increase the width of the gate gap wall, thereby improving the leakage current caused by hot carrier injection (HCI).
[0059] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A semiconductor structure, characterized in that, include: Base; A gate structure is disposed on the substrate; as well as The source and drain electrodes are disposed in the substrate on opposite sides of the gate structure. The gate structure includes: A gate dielectric layer is disposed on the substrate; A gate electrode is disposed on the gate dielectric layer; A first gate spacer wall is disposed on opposite sidewalls of the gate electrode and each includes a first spacer wall layer on the sidewall of the gate electrode, a second spacer wall layer on the first spacer wall layer, and a third spacer wall layer on the second spacer wall layer; and The second gate spacer wall is disposed on the first gate spacer wall. The second spacer layer and the third spacer layer each include a first portion extending along the sidewall of the gate electrode and a second portion extending in the direction from the gate electrode to the source / drain electrode.
2. The semiconductor structure according to claim 1, characterized in that, The thickness of the first portion of the second gap wall layer is equal to the thickness of the second portion of the second gap wall layer.
3. The semiconductor structure according to claim 1, characterized in that, The thickness of the first portion of the third gap wall layer is equal to the thickness of the second portion of the third gap wall layer.
4. The semiconductor structure according to claim 1, characterized in that, The gate dielectric layer includes a first portion below the gate electrode and a second portion below the second portions of each of the second spacer layers and the third spacer layer.
5. The semiconductor structure according to claim 4, characterized in that, The thickness of the first portion of the gate dielectric layer is greater than the thickness of the second portion of the gate dielectric layer.
6. The semiconductor structure according to claim 1, characterized in that, The second gate spacer wall includes: A fourth spacer wall layer is disposed on the third spacer wall layer; and The fifth spacer wall layer is disposed on the fourth spacer wall layer. The fourth gap wall layer includes a first portion extending along the sidewall of the gate electrode and a second portion extending in the direction from the gate electrode to the source / drain.
7. The semiconductor structure according to claim 6, characterized in that, The thickness of the first portion of the fourth gap wall layer is equal to the thickness of the second portion of the fourth gap wall layer, while the fifth gap wall layer includes a portion in which the thickness changes in a direction perpendicular to the surface of the substrate.
8. The semiconductor structure according to claim 6, characterized in that, The bottom surface of the fifth gap wall layer is positioned at a level higher than the top surface of the gate dielectric layer.
9. The semiconductor structure according to claim 6, characterized in that, The fifth gap wall layer includes a first profile and a second profile different from the first profile on the side surface away from the gate electrode.
10. The semiconductor structure according to claim 9, characterized in that, The first profile is positioned above the second profile relative to the surface of the substrate and has a slope that is less than that of the second profile.
11. The semiconductor structure according to claim 6, characterized in that, The materials of the first, second, and fifth spacer layers comprise nitrides, while the materials of the third and fourth spacer layers comprise oxides.
12. The semiconductor structure according to claim 11, characterized in that, The material of the first spacer wall layer is different from the materials of the second spacer wall layer and the fifth spacer wall layer.
13. A method for forming a semiconductor structure, characterized in that, include: A gate dielectric layer is formed on the substrate; A gate electrode is formed on the gate dielectric layer; A first gap wall layer is formed on the opposite sidewall of the gate electrode; A second spacer material layer covering the gate dielectric layer, the first spacer layer, and the gate electrode is formed over the substrate; A third spacer wall material layer is formed on the second spacer wall material layer; A second gate spacer material layer is formed on the third spacer material layer; A portion of the second gate spacer material layer is removed to form a second gate spacer over the opposite sidewalls of the gate electrode; Remove a portion of the third spacer wall material layer and the second spacer wall material layer to form the third spacer wall layer and the second spacer wall layer on the first spacer wall layer, respectively; as well as Source / drain electrodes are formed in the substrate on the opposite side of the gate electrode. The second spacer layer and the third spacer layer each include a first portion extending along the sidewall of the gate electrode and a second portion extending in the direction from the gate electrode to the source / drain electrode.
14. The method according to claim 13, characterized in that, The substrate includes a first region on which the gate dielectric layer is formed and a second region different from the first region and in which an epitaxial pattern is formed, and the steps of forming the second spacer material layer and the third spacer material layer include: Before forming the epitaxial pattern, a first mask layer is formed on the substrate to define the epitaxial pattern, wherein the first mask layer covers the gate dielectric layer, the first spacer layer, and the gate electrode in the first region; After the epitaxial pattern is formed, a second mask layer is formed on the first mask layer and the epitaxial pattern; Patterning the second mask layer to form a third spacer wall material layer; and Remove the portion of the first mask layer not covered by the third spacer wall material layer to form the second spacer wall material layer.
15. The method according to claim 13, characterized in that, The thickness of the first portion of the second or third spacer wall layer is equal to the thickness of the second portion of the second or third spacer wall layer.
16. The method according to claim 13, characterized in that, The second gate spacer wall includes: A fourth spacer wall layer is formed on the third spacer wall layer; and A fifth spacer layer is formed on the fourth spacer layer. The fourth gap wall layer includes a first portion extending along the sidewall of the gate electrode and a second portion extending in the direction from the gate electrode to the source / drain.
17. The method according to claim 16, characterized in that, The thickness of the first portion of the fourth gap wall layer is equal to the thickness of the second portion of the fourth gap wall layer, while the fifth gap wall layer includes a portion in which the thickness changes in a direction perpendicular to the surface of the substrate.
18. The method according to claim 16, characterized in that, The bottom surface of the fifth gap wall layer is formed at a level higher than the top surface of the gate dielectric layer.
19. The method according to claim 16, characterized in that, The fifth gap wall layer includes a first profile and a second profile different from the first profile on the side surface away from the gate electrode, and the first profile is positioned above the second profile and has a slope that is smaller than that of the second profile relative to the surface of the substrate.
20. The method according to claim 16, characterized in that, The materials of the first, second, and fifth spacer layers comprise nitrides, while the materials of the third and fourth spacer layers comprise oxides.