Queue-based clock frequency deviation monitoring device

Abstract

The invention relates to the technical field of integrated circuit verification, in particular to a queue-based clock frequency deviation monitoring device, which comprises an initialization module used for setting module-related initialization data; the clock event capturing module is used for monitoring the edge of a clock signal in real time and obtaining the accurate simulation time of the moment; the queue management and reference model module is used for storing timestamp information into a dynamic queue as required; the comparison and report module is used for obtaining the size of the queue, comparing the size of the queue with the alarm upper limit and the alarm lower limit in real time and outputting a corresponding report according to a comparison result, the dynamic distribution and efficient operation characteristics of the SystemVerilog queue are utilized, clock events are stored and processed in real time, long-time and multi-clock-domain continuous monitoring is supported, and the real-time performance of the system is improved. An efficient, reliable and low-cost solution is provided for clock verification of a modern digital integrated circuit, and verification completeness and automation level are greatly improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit verification, and particularly provides a clock frequency deviation checking device based on SystemVerilog queue. BACKGROUND

[0002] With the rapid increase in the complexity of integrated circuit design, modern system on chip (SoC) and processors generally integrate multiple clock domains. These clocks may be generated by the same PLL (same source different frequency) or may be derived from independent crystal oscillators or clock generators (different sources). Although multiple clock domains meet the differentiated timing requirements of complex circuits, clock signals are easily affected by factors such as process deviation, voltage fluctuation, and temperature drift during transmission and frequency division, resulting in clock frequency deviation, which poses a hidden danger to the stable operation of the system. Clock frequency deviation can directly cause serious problems: on the one hand, if the deviation exceeds the timing constraint range, it will cause timing violations such as data sampling errors and signal synchronization failures. For example, in high-speed interfaces, abnormal phase difference between clock and data may cause data transmission errors; on the other hand, long-term accumulation of small deviations may cause functional errors, such as processor instruction execution period disorder, storage unit read-write timing mismatch, and even entire integrated circuit downtime, which has a particularly significant impact on fields with high reliability requirements such as automotive electronics and industrial control. Traditional clock frequency deviation detection methods have obvious limitations: first, they are highly dependent on external test equipment such as oscilloscopes and frequency counters, which are costly and bulky, and can only be used for offline detection in laboratory environments, which cannot meet the efficiency requirements of integrated circuit production testing or field operation; second, some scenarios rely on manual analysis of time-frequency data by engineers, which is not only inefficient but also prone to human error, and it is difficult to cover the full-scene detection needs of complex multi-clock domains, so a more efficient, accurate, and integrated detection solution is needed. The present application uses the queue structure and frequency division technology built into the hardware description language to automatically complete real-time monitoring and evaluation of frequency deviation in a simulation environment. SUMMARY

[0003] To solve the problems in the prior art, the present application provides a clock frequency deviation monitoring device based on a queue.

[0004] The technical solution adopted by the present application to solve its technical problems is: a clock frequency deviation monitoring device based on a queue, comprising: An initialization module for setting initialization data related to the module; A clock event capture module for real-time monitoring of the edges of the clock signal and obtaining the accurate simulation time at that moment; The queue management and reference model module stores the timestamp information into the dynamic queue according to needs; The comparison and report module obtains the size of the queue, compares the size of the queue with the upper limit of the alarm and the lower limit of the alarm in real time, and outputs the corresponding report according to the comparison result.

[0005] Further, the initialization data related to the module include the division of the reference clock, the division of the monitoring clock, the initial value of the queue, the upper limit of the alarm, the lower limit of the alarm and the check time.

[0006] Further, the real-time monitoring of the edge of the clock signal includes monitoring the rising edge of the target clock through an always block; The accurate simulation time at the moment includes calling a $realtime system function to obtain the accurate simulation time at the moment when an effective clock edge is captured.

[0007] Further, the queue management and reference model module writes the queue a number of times equal to the division value of the reference clock, and reads the timestamp from the queue according to the division value of the monitoring clock.

[0008] Further, when the size of the queue reaches one of the upper limit of the alarm and the lower limit of the alarm, an assertion error is triggered immediately, and a detailed alarm value is reported.

[0009] Further, when the size of the queue is always between the upper limit of the alarm and the lower limit of the alarm, the check time is waited to end, and a check pass report is output.

[0010] Further, when the homologous different frequency clock detection is performed, the initialization division of the reference clock is set as ref_div=1, and the division of the monitoring clock test_div is initially set according to the clock multiples of the two.

[0011] Further, when the different source clock detection is performed, the initialization division of the reference clock is set as ref_div=N, and the division of the monitoring clock test_div is initially set as test_div=M.

[0012] The beneficial effects of the present application are: The present application can be used as verification IP (VIP) seamlessly integrated into existing verification methodologies such as UVM, to realize full-automatic checking and achieve automation and integration; The present application performs real-time mathematical calculation and comparison during simulation, has high precision, and can immediately report errors, and has high precision and real-time performance; The present application can find clock problems in the design stage before tape-out, avoiding huge late-stage costs, and has the characteristics of foresight and low cost; The application can process complex multi-clock domain scenes and asynchronous clock synchronization problems, provide comprehensive and reliable detection coverage, store and process clock events in real time, support long-time and multi-clock domain continuous monitoring, and is flexible and powerful. The application provides a high-efficiency, reliable and low-cost solution for clock verification of modern digital integrated circuits, and greatly improves the completeness and automation level of verification. BRIEF DESCRIPTION OF DRAWINGS

[0013] Other features, objects and advantages of the application will become more apparent from the following detailed description of non-limiting embodiments, made with reference to the accompanying drawings: Figure 1 The monitoring flowchart of the queue-based clock frequency deviation monitoring device of the application; Figure 2 The input data interface schematic diagram of the queue-based clock frequency deviation monitoring device of the application. DETAILED DESCRIPTION

[0014] In order to make the technical means, creative features, purposes and effects achieved by the application easy to understand, the application is further described below in combination with specific embodiments.

[0015] The core of the application is to construct a SystemVerilog-based hardware-software co-verification component (usually as a verification IP, VIP). The component runs in a simulation environment, monitors clock signals, dynamically records data and performs real-time analysis to determine whether the clock frequency deviation is within an acceptable tolerance range. Specifically as follows: Please refer to Figure 1 and Figure 2 The application provides a queue-based clock frequency deviation monitoring device, mainly including a clock event capture module, a queue management and reference model module, and a comparison and reporting module. The specific device includes the following modules: An initialization module for setting initialization data related to the module; The initialization data related to the module includes the division of the reference clock, the division of the monitoring clock, the initial value of the queue, the upper limit of the alarm, the lower limit of the alarm, and the check time.

[0016] The clock event capture module is used to monitor the edge of the clock signal in real time and obtain the accurate simulation time at this moment. The real-time monitoring of the clock signal edge includes monitoring the rising edge of the target clock through the always@ block. The accurate simulation time at this moment includes calling the $realtime system function to obtain the accurate simulation time at this moment when an effective clock edge is captured.

[0017] Queue management and reference model module, according to the needs of the timestamp information into the dynamic queue; Queue management and reference model module writes the number of times of the queue reference clock division value, and reads out the timestamp from the queue according to the division value of the monitoring clock.

[0018] The comparison and reporting module obtains the size of the queue, and compares the queue size with the upper and lower alarm limits in real time, and outputs the corresponding report according to the comparison result.

[0019] When the queue size reaches one of the upper and lower alarm limits, an assertion error is triggered immediately, and the detailed alarm value is reported.

[0020] If the queue size is always between the upper and lower alarm limits, wait until the end of the check time, and output a report of passing the check.

[0021] When the same source different frequency clock detection is performed, the initialization division of the reference clock is set to ref_div=1, and the division of the monitoring clock test_div is initially set according to the clock multiplication of the two.

[0022] When the different source clock detection is performed, the initialization division of the reference clock is set to ref_div=N, and the division of the monitoring clock test_div is initially set to test_div=M.

[0023] The present application can perform same source different frequency clock detection and different source clock detection, utilize the advanced first-in first-out data structure and object-oriented programming characteristics of SystemVerilog queue, automatically complete real-time monitoring and evaluation of frequency deviation in simulation environment, have the advantages of high efficiency, reliability and low cost, and perfectly solve the problems of low efficiency and easy error in traditional methods.

[0024] The working process of the whole device is as shown in Figure 1 , forming a continuous monitoring closed loop. The clock monitoring process in Figure 1 is introduced as follows: 1. Initialization and configuration (Initialization): Set the division of the reference clock (ref_div), the division of the monitoring clock (test_div), the initial value of the queue (init_value), the upper limit of the alarm (high_alarm_value), the lower limit of the alarm (low_alarm_value), and the check time (chk_time).

[0025] 2. Configure enable signal (chk_en) and record start time (start_time), clock event capture module starts working, through always@ (posedge clk) block to monitor the rising edge of target clock. Whenever a valid clock edge is captured, the module calls $realtime system function to obtain the accurate simulation time (usually in picoseconds or nanoseconds) at that moment.

[0026] 3. The queue management module writes this timestamp (Timestamp) into the SystemVerilog dynamic queue (such as realtime_queue [$]), and the number of times of writing into the queue (push_back) is determined according to the frequency division value (ref_div) of the reference clock. At the same time, the timestamp is read out of the queue (pop_front) according to the frequency division value (test_div) of the monitoring clock.

[0027] 4. Obtain the size of the queue (size) and compare it with the upper alarm value (high_alarm_value) and the lower alarm value (low_alarm_value). 5. If the alarm value is reached, an assertion error is triggered immediately, and the detailed alarm value is reported.

[0028] 6. If the alarm condition has not been reached, wait until the check time ends, and output a report of passing the check.

[0029] 7. If multiple monitoring is required, the queue state needs to be cleared (configure the alarm clearing signal clear_alarm), the check enable signal is turned off (configure the check enable signal to be 0), and the initialization process is performed again.

[0030] The input and output interface signals are shown in Figure 2 The implementation of the present application mainly works in the chip simulation stage for monitoring the deviation of clock frequencies of the same frequency or having a corresponding multiple relationship. Please refer to the following two embodiments for details.

[0031] In the first embodiment, when the same source different frequency clock is detected by the clock frequency deviation monitoring device based on the queue of the present application, a plurality of expected frequencies are generated by frequency division of the reference clock, the actual clock edge is recorded by using the queue, and the frequency deviation is automatically calculated by comparing the queue data with the expected model. The specific implementation is as follows: a1. Initialization: set the division of reference clock (ref_div=1), the division of test clock (test_div according to the clock multiple), the initial value of queue (init_value), the upper limit of alarm (high_alarm_value), the lower limit of alarm (low_alarm_value), the check time (chk_time).

[0032] a2. Configure the enable signal (chk_en) and record the start time (start_time), and the clock event capture module starts to work. The rising edge of the target clock is monitored through the always@ (posedge clk) block. When a valid clock edge is captured, the module calls the $realtime system function to obtain the accurate simulation time (usually in picoseconds or nanoseconds) at that moment, a3. The queue management module writes the timestamp into the SystemVerilog dynamic queue (such as realtime_queue[$]). The number of times of writing into the queue (push_back) refers to the division value of the reference clock (ref_div writes 1 time). At the same time, the timestamp is read out of the queue (pop_front) according to the division value of the test clock (read test_div times).

[0033] a4. Compare the size of the queue with the upper limit of the alarm (high_alarm_value) and the lower limit of the alarm (low_alarm_value). a5. If the alarm value is reached, an assertion error is triggered immediately, and the detailed alarm value is reported.

[0034] a6. If the alarm condition is not reached, wait until the check time ends, and output a report of passing the check.

[0035] a7. If multiple monitoring is required, the queue state needs to be cleared (configure the alarm clearing signal clear_alarm), the check enable signal is closed (configure the check enable signal to 0), and the initialization process is performed again.

[0036] In example two, when the clock frequency deviation monitoring device based on the queue is used to detect different source clocks, the different source clock signals are aligned to a unified detection window based on the asynchronous clock synchronization technology, the number of cycles is counted through the queue, and the frequency difference is analyzed. The specific implementation is as follows: b1. Initialization: set the division of reference clock (ref_div=N), the division of monitor clock (test_div=M), the initial value of queue (init_value), the upper limit of alarm (high_alarm_value), the lower limit of alarm (low_alarm_value), check time (chk_time) Note: M:N is the ratio of the clock frequency of the reference clock and the clock to be tested, which ensures the consistency of the speed of dequeuing and enqueuing.

[0037] b2. Configure the enable signal (chk_en) and record the start time (start_time), and the clock event capture module starts to work, and the rising edge of the target clock is monitored through the always@ (posedge clk) block. When an effective clock edge is captured, the module calls the $realtime system function to obtain the accurate simulation time (usually in picoseconds or nanoseconds) at that moment, b3. The queue management module writes the timestamp (Timestamp) into the SystemVerilog dynamic queue (such as realtime_queue[$]), and the number of times of writing into the queue (push_back) is determined by the division value of the reference clock (written ref_div times). At the same time, the timestamp is read out of the queue (pop_front) according to the division value of the monitor clock (read test_div times).

[0038] b4. Get the size of the queue (size) and compare it with the upper limit of the alarm (high_alarm_value) and the lower limit of the alarm (low_alarm_value). b5. If the alarm value is reached, an assertion error is triggered immediately, and the detailed alarm value is reported.

[0039] b6. If the alarm condition is not reached all the time, wait until the check time ends, and output a report of passing the check.

[0040] b7. If multiple monitoring is required, the queue state needs to be cleared (configure the alarm clearing signal clear_alarm), the check enable signal is closed (configure the check enable signal to be 0), and the initialization process is performed again.

[0041] The application utilizes the dynamic allocation and efficient operation characteristics of the SystemVerilog queue, stores and processes clock events in real time, supports long-time and multi-clock domain continuous monitoring, realizes dynamic queue management, and can be seamlessly integrated into existing verification methodologies such as UVM as a verification IP (VIP), realizes full-automatic check, and realizes automation and integration.

[0042] refer to Figure 1 The detection flowchart in this invention shows that it can perform mathematical calculations and comparisons in real time during simulation with high accuracy and can immediately report errors. It has high precision and real-time performance, and can detect clock problems in the design stage before tape-out, avoiding huge later costs. It has the characteristics of foresight and low cost. In addition, this invention can also handle complex multi-clock domain scenarios and asynchronous clock synchronization problems, provide comprehensive and reliable detection coverage, store and process clock events in real time, and support long-term, multi-clock domain continuous monitoring.

[0043] This invention provides an efficient, reliable, and low-cost solution for clock verification of modern digital integrated circuits, greatly improving the completeness and automation level of verification.

[0044] Although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A queue-based clock frequency skew monitoring apparatus, characterized by, The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device.

2. The queue-based clock frequency skew monitoring apparatus of claim 1, wherein: The application relates to a clock detection method and device.

3. The queue-based clock frequency skew monitoring apparatus of claim 2, wherein: The application relates to a clock detection method and device. The application relates to a clock detection method and device.

4. The queue-based clock frequency skew monitoring apparatus of claim 1, wherein: The application relates to a clock detection method and device.

5. The queue-based clock frequency skew monitoring apparatus of claim 2, wherein: The application relates to a clock detection method and device.

6. The queue-based clock frequency skew monitoring apparatus of claim 2, wherein: The application relates to a clock detection method and device.

7. The queue-based clock frequency skew monitoring apparatus of claim 2, wherein: The application relates to a clock detection method and device.

8. The queue-based clock frequency skew monitoring apparatus of claim 2, wherein: The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The application relates to a clock detection method and device. The

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