LDMOS device and preparation method thereof

Abstract

The invention provides an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a preparation method thereof, in the preparation method, a first inner core structure, a first sub epitaxial layer, a second inner core structure, a second sub epitaxial layer, an Nth inner core structure and an Nth sub epitaxial layer are sequentially formed in a groove in a main epitaxial layer of a first conduction type until the whole groove is filled, n is an integer greater than or equal to 2. According to the invention, the inner core structures of the second conductive type and the sub epitaxial layers of the first conductive type, which are stacked in a staggered manner, are arranged in each groove in the main epitaxial layer of the first conductive type, and the device is subjected to electric field modulation through the multi-layer stacked inner core structures of the second conductive type. The doping concentration of the first inner core structure, the second inner core structure to the Nth inner core structure can be adjusted according to requirements, and the uniformity is controllable, so that a drift region can be fully exhausted, and the on resistance of the device is remarkably reduced while the withstand voltage of the device is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, specifically to an LDMOS device and its fabrication method. Background Technology

[0002] In traditional LDMOS (Laterally Diffused Metal Oxide Semiconductor) device structures, double-RESURF (Double Reduced Surface Field) technology is typically used. This technology introduces a doped structure of a second conductivity type into an epitaxial layer of the first conductivity type to improve the breakdown voltage. However, the traditional use of double-RESURF technology can lead to a large on-resistance of the device, resulting in a significant trade-off between breakdown voltage and on-resistance. Summary of the Invention

[0003] This application provides an LDMOS device and its fabrication method, which can solve the problem of high on-resistance in traditional LDMOS devices using double-RESURF technology.

[0004] On one hand, embodiments of this application provide a method for fabricating an LDMOS device, including:

[0005] Step 1: Provide a substrate in which a first buried layer of a first conductivity type and a second buried layer of a second conductivity type are formed, and a main epitaxial layer of the first conductivity type, a first hard mask layer and a second hard mask layer are formed on the substrate.

[0006] Step 2: Coat the surface of the second hard mask layer with a photoresist layer;

[0007] Step 3: Define trench patterns on the photoresist layer using photolithography to form a patterned photoresist layer;

[0008] Step 4: Using the patterned photoresist layer as a mask, etch the second hard mask layer, the first hard mask layer, and the main epitaxial layer of the first thickness to form a plurality of spaced trenches in the main epitaxial layer.

[0009] Step 5: Remove the patterned photoresist layer;

[0010] Step 6: Sequentially form a first inner core structure, a first sub-epipolar layer, a second inner core structure, a second sub-epipolar layer, an Nth inner core structure, and an Nth sub-epipolar layer in the trench until the entire trench is filled, where N is an integer greater than or equal to 2;

[0011] Step 7: Remove the second hard mask layer and the first hard mask layer to planarize the surface of the main epitaxial layer and the surface of the Nth sub-epiaxial layer at the top of the trench.

[0012] Optionally, in the method for fabricating the LDMOS device, step 6, which involves sequentially forming a first core structure, a first sub-epipolar layer, a second core structure, a second sub-epipolar layer, an Nth core structure, and an Nth sub-epipolar layer in the trench until the entire trench is filled, includes:

[0013] Step 6.1: Form a first sacrificial layer, which covers the sidewalls and bottom wall of the trench;

[0014] Step 6.2: Continue etching downwards the first sacrificial layer and the second thickness of the main epitaxial layer on the bottom wall of the trench in the trench;

[0015] Step 6.3: Form a first core structure of the second conductivity type, the first core structure filling part of the trench, the upper surface of the first core structure not exceeding the bottom surface of the first sacrificial layer on the sidewall of the trench;

[0016] Step 6.4: Remove the first sacrificial layer on the sidewall of the trench;

[0017] Step 6.5: Form a first sub-epipolar layer of a first conductivity type, the first sub-epipolar layer covering the first core structure and filling a portion of the space of the trench;

[0018] Step 6.6: Form the Nth sacrificial layer, the second sacrificial layer covering the first sub-epicentric layer and the sidewalls of the trench;

[0019] Step 6.7: Continue etching downwards into the trench, etching the Nth sacrificial layer and a portion of the (N-1)th sub-epipolar layer on the bottom wall of the trench;

[0020] Step 6.8: Form an Nth core structure of the second conductivity type, wherein the Nth core structure fills a portion of the trench, and the upper surface of the Nth core structure does not exceed the bottom surface of the Nth sacrificial layer on the sidewall of the trench;

[0021] Step 6.9: Remove the Nth sacrificial layer from the sidewall of the trench;

[0022] Step 6.10: Form the Nth sub-epitaxial layer of the first conductivity type, the Nth sub-epitaxial layer covering the Nth core structure and filling a portion of the space of the trench;

[0023] Step 6.11: Repeat steps 6.6 to 6.10 until the trench is completely filled.

[0024] Optionally, in the method for fabricating the LDMOS device, step 6.3, which forms the first core structure of the second conductivity type, includes:

[0025] A first core structure of a second conductivity type is formed, the first core structure filling the trench;

[0026] The first core structure of a certain thickness is etched back so that the upper surface of the remaining thickness of the first core structure does not exceed the bottom surface of the first sacrificial layer on the trench sidewall.

[0027] Optionally, in the method for fabricating the LDMOS device, step 6.5, forming the first sub-epitaxial layer of the first conductivity type, includes:

[0028] A first sub-epipolar layer of a first conductivity type is formed, the first sub-epipolar layer covering the first core structure and filling the trench;

[0029] The first sub-epipolar layer of a certain thickness is etched back so that the remaining thickness of the first sub-epipolar layer covers the first core structure and fills part of the space of the trench.

[0030] Optionally, in the method for fabricating the LDMOS device, step 6.8, which forms the Nth core structure of the second conductivity type, includes:

[0031] An Nth core structure of a second conductivity type is formed, the Nth core structure filling the trench;

[0032] The Nth core structure is etched back to a certain thickness so that the upper surface of the remaining thickness of the Nth core structure does not exceed the bottom surface of the Nth sacrificial layer on the trench sidewall.

[0033] Optionally, in the method for fabricating the LDMOS device, step 6.10, which forms the Nth sub-epitaxial layer of the first conductivity type, includes:

[0034] An Nth sub-epitaxial layer of a first conductivity type is formed, the Nth sub-epitaxial layer covering the Nth core structure and filling a portion of the space of the trench;

[0035] If the Nth sub-epilithography layer is the topmost sub-epilithography layer in the trench, then no etch-back process is performed on the Nth sub-epilithography layer;

[0036] If the Nth sub-epitaxial layer is not the topmost sub-epitaxial layer in the trench, then a certain thickness of the Nth sub-epitaxial layer is etched back so that the remaining thickness of the Nth sub-epitaxial layer covers the Nth core structure and fills part of the space in the trench.

[0037] Optionally, in the fabrication method of the LDMOS device, the thickness of the Nth sub-epipolar layer at the top layer in the trench is 0.3 μm to 1 μm.

[0038] Optionally, in the fabrication method of the LDMOS device, in the trench, except for the topmost Nth sub-epitaxial layer, the thickness of the first sub-epitaxial layer, the thickness of the second sub-epitaxial layer, and the thickness of the (N-1)th sub-epitaxial layer are all 0.2 μm to 1 μm.

[0039] Optionally, in the fabrication method of the LDMOS device, the thickness of the first core structure, the thickness of the second core structure, and the thickness of the Nth core structure in the trench are all 0.05 μm to 0.3 μm.

[0040] On the other hand, embodiments of this application also provide an LDMOS device, including:

[0041] A substrate having a first buried layer of a first conductivity type and a second buried layer of a second conductivity type located on the side of the first buried layer;

[0042] A primary epitaxial layer of a first conductivity type, the primary epitaxial layer covering the substrate;

[0043] A plurality of trenches arranged at intervals, the trenches being located in the main epitaxial layer;

[0044] The second conductivity type includes the first inner core structure, the second inner core structure, and the Nth inner core structure, where N is an integer greater than or equal to 2.

[0045] The first sub-epitaxial layer, the second sub-epitaxial layer to the Nth sub-epitaxial layer of the first conductivity type, wherein the first core structure, the first sub-epitaxial layer, the second core structure, the second sub-epitaxial layer, the Nth core structure and the Nth sub-epitaxial layer are stacked in the trench from bottom to top and fill the entire trench, wherein the upper surface of the topmost Nth sub-epitaxial layer in the trench is flush with the upper surface of the main epitaxial layer.

[0046] The technical solution of this application has at least the following advantages:

[0047] This application provides an LDMOS device and its fabrication method. In the fabrication method, a first core structure, a first sub-epilayer, a second core structure, a second sub-epilayer, an Nth core structure, and an Nth sub-epilayer are sequentially formed in a trench within a main epitaxial layer of a first conductivity type until the entire trench is filled, where N is an integer greater than or equal to 2. In each trench of the main epitaxial layer of the first conductivity type, staggered stacked first, second to Nth core structures of the second conductivity type and first, second to Nth sub-epilayers of the first conductivity type are provided. The device is electrically modulated by the multi-layered stacked first, second to Nth core structures of the second conductivity type. The doping concentration of the first, second to Nth core structures of the second conductivity type can be adjusted as needed and its uniformity is controllable, allowing the drift region to be fully depleted. This improves the device's breakdown voltage while significantly reducing its on-resistance, effectively resolving the contradiction between breakdown voltage and on-resistance in LDMOS devices using double-RESURF technology. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0049] Figure 1 This is a flowchart of the fabrication method of the LDMOS device according to an embodiment of the present invention;

[0050] Figures 2-13 This is a schematic diagram of the semiconductor structure in each process step of fabricating an LDMOS device according to an embodiment of the present invention;

[0051] The reference numerals in the attached figures are explained as follows:

[0052] 10-Substrate, 11-First buried layer, 12-Second buried layer, 20-Main epitaxial layer, 21-Trench, 30-First hard mask layer, 40-Second hard mask layer, 50-Photoresist layer, 51-Trench pattern, 61-First sacrificial layer, 62-Second sacrificial layer, 71-First core structure, 72-Second core structure, 81-First sub-epitaxial layer, 82-Second sub-epitaxial layer. Detailed Implementation

[0053] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0054] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0055] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0056] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0057] This application provides a method for fabricating an LDMOS device, referring to... Figure 1 , Figure 1 This is a flowchart of a method for fabricating an LDMOS device according to an embodiment of the present invention. The method for fabricating the LDMOS device includes:

[0058] First, perform step 1: Refer to Figure 2 , Figure 2 This is a schematic diagram of a semiconductor structure after a patterned photoresist layer is formed according to an embodiment of this application. A substrate 10 is provided, in which a first buried layer 11 of a first conductivity type and a second buried layer 12 of a second conductivity type located on the side of the first buried layer 11 are formed. A main epitaxial layer 20 of the first conductivity type, a first hard mask layer 30 and a second hard mask layer 40 are formed on the substrate 10.

[0059] In this embodiment, the first conductivity type is N-type; the second conductivity type is P-type.

[0060] Preferably, the first hard mask layer 30 is made of silicon dioxide.

[0061] Furthermore, the second hard mask layer 40 is made of silicon nitride.

[0062] Then, proceed to step 2: continue referring to... Figure 2 A photoresist layer 50 is coated on the surface of the second hard mask layer 40.

[0063] Next, proceed to step 3: Continue to refer to... Figure 2 The groove pattern 51 is defined on the photoresist layer 50 by photolithography to form a patterned photoresist layer.

[0064] Further, proceed to step 4: Refer to Figure 3 , Figure 3 This is a schematic diagram of the semiconductor structure after forming a plurality of spaced trenches and removing the photoresist layer according to an embodiment of this application. Using the patterned photoresist layer 50 as a mask, the second hard mask layer 40, the first hard mask layer 30 and the main epitaxial layer 20 of the first thickness are etched to form a plurality of spaced trenches 21 in the main epitaxial layer 20.

[0065] The lateral opening size of the groove is 0.1μm to 0.5μm.

[0066] Next, proceed to step 5: Continue to refer to... Figure 3 Remove the patterned photoresist layer 50.

[0067] Further, proceed to step 6: Refer to Figures 4-12 In the trench 21, a first inner core structure 71, a first sub-epipolar layer 81, a second inner core structure 72, a second sub-epipolar layer 82, an Nth inner core structure, and an Nth sub-epipolar layer are formed sequentially until the entire trench is filled, where N is an integer greater than or equal to 2.

[0068] Preferably, step 6 may specifically include:

[0069] Step 6.1: Form a first sacrificial layer, which covers the sidewalls and bottom wall of the trench;

[0070] Step 6.2: Continue etching downwards the first sacrificial layer and the second thickness of the main epitaxial layer on the bottom wall of the trench in the trench;

[0071] Step 6.3: Form a first core structure of the second conductivity type, the first core structure filling part of the trench, the upper surface of the first core structure not exceeding the bottom surface of the first sacrificial layer on the sidewall of the trench;

[0072] Step 6.4: Remove the first sacrificial layer on the sidewall of the trench;

[0073] Step 6.5: Form a first sub-epipolar layer of a first conductivity type, the first sub-epipolar layer covering the first core structure and filling a portion of the space of the trench;

[0074] Step 6.6: Form the Nth sacrificial layer, the second sacrificial layer covering the first sub-epicentric layer and the sidewalls of the trench;

[0075] Step 6.7: Continue etching downwards into the trench, etching the Nth sacrificial layer and a portion of the (N-1)th sub-epipolar layer on the bottom wall of the trench;

[0076] Step 6.8: Form an Nth core structure of the second conductivity type, wherein the Nth core structure fills a portion of the trench, and the upper surface of the Nth core structure does not exceed the bottom surface of the Nth sacrificial layer on the sidewall of the trench;

[0077] Step 6.9: Remove the Nth sacrificial layer from the sidewall of the trench;

[0078] Step 6.10: Form the Nth sub-epitaxial layer of the first conductivity type, the Nth sub-epitaxial layer covering the Nth core structure and filling a portion of the space of the trench;

[0079] Step 6.11: Repeat steps 6.6 to 6.10 until the trench is completely filled.

[0080] Preferably, step 6.10, which forms the Nth sub-epitaxial layer of the first conductivity type, may specifically include:

[0081] Step 6.101: Form the Nth sub-epitaxial layer of the first conductivity type, the Nth sub-epitaxial layer covering the Nth core structure and filling a portion of the space of the trench;

[0082] Step 6.102: If the Nth sub-epitaxial layer is the topmost sub-epitaxial layer in the trench, then no back etching process is performed on the Nth sub-epitaxial layer; if the Nth sub-epitaxial layer is not the topmost sub-epitaxial layer in the trench, then a certain thickness of the Nth sub-epitaxial layer is etched back so that the remaining thickness of the Nth sub-epitaxial layer covers the Nth core structure and fills part of the space in the trench.

[0083] Preferably, the thickness of the topmost Nth sub-epipolar layer in the trench is 0.3 μm to 1 μm.

[0084] Furthermore, in the trench, except for the topmost Nth sub-epitaxial layer, the thicknesses of the first sub-epitaxial layer, the second sub-epitaxial layer, and the (N-1)th sub-epitaxial layer are all 0.2 μm to 1 μm.

[0085] Preferably, in the groove, the thickness of the first inner core structure, the thickness of the second inner core structure, and the thickness of the Nth inner core structure are all 0.05μm to 0.3μm.

[0086] Furthermore, the thickness of the main epitaxial layer at the bottom of the first inner core structure at the bottom of the trench is 4μm to 10μm.

[0087] Specifically, this embodiment takes N=2 as an example to describe step 6, which may include:

[0088] Step 6.1: Reference Figure 4 , Figure 4 This is a schematic diagram of the semiconductor structure after the formation of the first sacrificial layer according to an embodiment of this application. The first sacrificial layer 61 is formed, and the first sacrificial layer 61 covers the sidewalls and bottom wall of the trench 21.

[0089] In this embodiment, the first sacrificial layer 61 can be made of silicon dioxide, and the first sacrificial layer 61 can be formed on the sidewalls and bottomwalls of the trench 21 by a thermal oxidation process.

[0090] Step 6.2: Reference Figure 5 , Figure 5 This is a schematic diagram of the semiconductor structure after the first sacrificial layer and the second thickness of the main epitaxial layer on the bottom wall of the trench are etched downwards in an embodiment of this application. In the trench 21, the first sacrificial layer 61 and the second thickness of the main epitaxial layer 20 on the bottom wall of the trench 20 are etched downwards.

[0091] Step 6.3: Reference Figure 6 , Figure 6 This is a schematic diagram of the semiconductor structure after the formation of the first core structure according to an embodiment of this application. A first core structure 71 of the second conductivity type is formed. The first core structure 71 fills part of the trench 21. The upper surface of the first core structure 71 does not exceed the bottom surface of the first sacrificial layer 61 on the sidewall of the trench 21.

[0092] Specifically, step 6.3, which involves forming the first core structure of the second conductivity type, may include:

[0093] Step 6.31: Form a first core structure 71 of the second conductivity type, wherein the first core structure 71 fills the trench 21;

[0094] Step 6.32: Etch back the first core structure 71 to a certain thickness so that the upper surface of the remaining thickness of the first core structure 71 does not exceed the bottom surface of the first sacrificial layer 61 on the sidewall of the trench 21.

[0095] Step 6.4: Reference Figure 7 , Figure 7 This is a schematic diagram of the semiconductor structure after removing the first sacrificial layer 61 on the sidewall of the trench according to an embodiment of this application, where the first sacrificial layer 61 on the sidewall of the trench 21 is removed;

[0096] Step 6.5: Reference Figure 8 , Figure 8 This is a schematic diagram of the semiconductor structure after the formation of the first sub-epipolar layer of the first conductivity type in an embodiment of this application. The first sub-epipolar layer 81 of the first conductivity type is formed. The first sub-epipolar layer 81 covers the first core structure 71 and fills part of the space of the trench 21 (the trench is not fully filled at this time).

[0097] Specifically, in this embodiment, step 6.5 of forming the first sub-epieptaxial layer of the first conductivity type includes:

[0098] Step 6.51: Form a first sub-epipolar layer 81 of a first conductivity type, the first sub-epipolar layer 81 covering the first core structure 71 and filling the trench 21;

[0099] Step 6.52: Etch back the first sub-epipolar layer 81 to a certain thickness so that the remaining thickness of the first sub-epipolar layer 81 covers the first core structure 71 and fills part of the space of the trench 21.

[0100] Step 6.6: Reference Figure 9 , Figure 9 This is a schematic diagram of the semiconductor structure after the formation of the second sacrificial layer according to an embodiment of this application. The second sacrificial layer 62 is formed, and the second sacrificial layer 62 covers the first sub-epipolar layer 81 and the sidewall of the trench 21.

[0101] In this embodiment, the second sacrificial layer 62 can be made of silicon dioxide, and the second sacrificial layer 62 can be formed on the sidewall of the trench 21 and the second inner core structure 72 by a thermal oxidation process.

[0102] Step 6.7: Reference Figure 10 , Figure 10 This is a schematic diagram of a semiconductor structure after the second sacrificial layer and a portion of the thickness of the first sub-epipolar layer on the bottom wall of the trench are etched downwards in an embodiment of this application. In the trench 21, the second sacrificial layer 62 and a portion of the thickness of the first sub-epipolar layer 81 on the bottom wall of the trench 21 are etched downwards.

[0103] Step 6.8: Reference Figure 11 , Figure 11 This is a schematic diagram of the semiconductor structure after the formation of the second core structure of the second conductivity type in an embodiment of this application. The second core structure 72 of the second conductivity type is formed. The second core structure 72 fills part of the trench 21. The upper surface of the second core structure 72 does not exceed the bottom surface of the second sacrificial layer 62 on the sidewall of the trench 21.

[0104] Furthermore, step 6.8, which involves forming the second core structure of the second conductivity type, may specifically include:

[0105] Step 6.81: Form a second core structure 72 of the second conductivity type, wherein the second core structure 72 fills the trench 21;

[0106] Step 6.82: Etch back a certain thickness of the second core structure 72 so that the upper surface of the remaining thickness of the second core structure 72 does not exceed the bottom surface of the second sacrificial layer 62 on the sidewall of the trench 21.

[0107] Step 6.9: Reference Figure 12 , Figure 12 This is a schematic diagram of the semiconductor structure after the formation of the second sub-epipolar layer of the first conductivity type in an embodiment of this application, with the second sacrificial layer 62 on the sidewall of the trench 21 removed;

[0108] Step 6.10: Continue to refer to Figure 12 A second sub-epipolar layer 82 of the first conductivity type is formed. The second sub-epipolar layer 82 covers the second core structure 72 and fills part of the space of the trench 21. At this time, the trench 21 is completely filled.

[0109] In this embodiment, step 6.10, which forms the second sub-epitaxial layer of the first conductivity type, may specifically include:

[0110] Step 6.101: Form a second sub-epipolar layer 82 of the first conductivity type, the second sub-epipolar layer 82 covering the second core structure 72 and filling a portion of the space of the trench 21;

[0111] Step 6.102: Since the second sub-epilithial layer 82 is the topmost sub-epilithial layer in the trench, the back etching process is no longer performed on the second sub-epilithial layer 82. At this time, the trench 21 is completely filled.

[0112] Finally, proceed to step 7: (Refer to...) Figure 13 , Figure 13This is a schematic diagram of the semiconductor structure after removing the second hard mask layer and the first hard mask layer according to an embodiment of this application. The second hard mask layer 40 and the first hard mask layer 30 are removed to planarize the surface of the main epitaxial layer 20 and the surface of the Nth sub-epiaxial layer at the top of the trench 21.

[0113] In this embodiment, the second hard mask layer 40 and the first hard mask layer 30 are removed to planarize the surface of the main epitaxial layer 20 and the surface of the second sub-epitaxy layer 82 at the top of the trench 21.

[0114] In this embodiment, the thickness of the second sub-epipolar layer 82 at the top layer of the trench 21 is 0.3 μm to 1 μm.

[0115] Furthermore, in the trench 21, apart from the topmost second sub-epipolar layer 82, the thickness of the first sub-epipolar layer 81 is 0.2μm to 1μm.

[0116] Preferably, in the groove, the thickness of the first inner core structure 71 and the thickness of the second inner core structure 72 are both 0.05μm to 0.3μm.

[0117] In this application, each trench in the main epitaxial layer of the first conductivity type is provided with staggered stacked first, second to Nth core structures of the second conductivity type and first, second to Nth sub-epitaxy layers of the first conductivity type. The device is electric field modulated by the multi-layer stacked first, second to Nth core structures of the second conductivity type. The doping concentration of the first, second to Nth core structures of the second conductivity type can be adjusted as needed and the uniformity is controllable, so that the drift region can be fully exhausted. While improving the device breakdown voltage, the on-resistance of the device is significantly reduced, thereby effectively solving the contradiction between the breakdown voltage and on-resistance of LDMOS devices using double-RESURF technology.

[0118] Based on the same inventive concept, this application also provides an LDMOS device, see reference. Figure 13 The LDMOS device includes:

[0119] Substrate 10, wherein a first buried layer 11 of a first conductivity type and a second buried layer 12 of a second conductivity type are formed in the substrate 10;

[0120] A primary epitaxial layer 20 of a first conductivity type covers the substrate 10;

[0121] A plurality of trenches 21 are arranged at intervals, the trenches 21 being located in the main epitaxial layer 20;

[0122] The first inner core structure 71, the second inner core structure 72 to the Nth inner core structure of the second conductivity type, wherein N is an integer greater than or equal to 2;

[0123] The first sub-epitaxial layer 81, the second sub-epitaxial layer 82 to the Nth sub-epitaxial layer of the first conductivity type, wherein the first core structure 71, the first sub-epitaxial layer 81, the second core structure 72, the second sub-epitaxial layer 82, the Nth core structure and the Nth sub-epitaxial layer are stacked in the trench from bottom to top and fill the entire trench 21, wherein the upper surface of the topmost Nth sub-epitaxial layer in the trench is flush with the upper surface of the main epitaxial layer 20.

[0124] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A method of fabricating an LDMOS device, characterized by, Comprising: Step 1: providing a substrate, wherein a first buried layer of a first conductivity type and a second buried layer of a second conductivity type are formed in the substrate, and a main epitaxial layer of the first conductivity type, a first hard mask layer and a second hard mask layer are formed on the substrate; Step 2: coating a photoresist layer on the surface of the second hard mask layer; Step 3: defining a trench pattern on the photoresist layer by a photolithography process to form a patterned photoresist layer; Step 4: taking the patterned photoresist layer as a mask, etching the second hard mask layer, the first hard mask layer and the main epitaxial layer of the first thickness to form a plurality of spaced trenches in the main epitaxial layer; Step 5: removing the patterned photoresist layer; Step 6: sequentially forming a first inner core structure, a first sub-epitaxial layer, a second inner core structure, a second sub-epitaxial layer, an Nth inner core structure and an Nth sub-epitaxial layer in the trench until the entire trench is filled, wherein N is an integer greater than or equal to 2; Step 7: removing the second hard mask layer and the first hard mask layer to planarize the surface of the main epitaxial layer and the surface of the Nth sub-epitaxial layer on the top layer of the trench.

2. The method of claim 1, wherein, The step 6 of sequentially forming a first inner core structure, a first sub-epitaxial layer, a second inner core structure, a second sub-epitaxial layer, an Nth inner core structure and an Nth sub-epitaxial layer in the trench until the entire trench is filled comprises: Step 6.1: forming a first sacrificial layer covering the sidewall and bottom wall of the trench; Step 6.2: continuing to etch the first sacrificial layer of the trench bottom wall and the main epitaxial layer of the second thickness in the trench; Step 6.3: forming a first inner core structure of the second conductivity type, the first inner core structure filling part of the trench, the upper surface of the first inner core structure not exceeding the bottom surface of the first sacrificial layer on the sidewall of the trench; Step 6.4: removing the first sacrificial layer on the sidewall of the trench; Step 6.5: forming a first sub-epitaxial layer of the first conductivity type, the first sub-epitaxial layer covering the first inner core structure and filling part of the space of the trench; Step 6.6: forming an Nth sacrificial layer covering the first sub-epitaxial layer and the sidewall of the trench; Step 6.7: continuing to etch the Nth sacrificial layer of the trench bottom wall and part of the thickness of the N-1th sub-epitaxial layer in the trench; Step 6.8: forming an Nth inner core structure of the second conductivity type, the Nth inner core structure filling part of the trench, the upper surface of the Nth inner core structure not exceeding the bottom surface of the Nth sacrificial layer on the sidewall of the trench; Step 6.9: removing the Nth sacrificial layer on the sidewall of the trench; Step 6.10: forming an Nth sub-epitaxial layer of the first conductivity type, the Nth sub-epitaxial layer covering the Nth inner core structure and filling part of the space of the trench; Step 6.11: repeating steps 6.6 to 6.10 until the trench is completely filled.

3. The method of claim 2, wherein the LDMOS device is formed by: The step 6.3 of forming a first inner core structure of the second conductivity type comprises: forming a first inner core structure of a second conductive type, the first inner core structure filling up the trench; etching back a thickness of the first inner core structure so that an upper surface of a remaining thickness of the first inner core structure does not exceed a bottom surface of the first sacrificial layer on the trench sidewall.

4. The method of claim 2, wherein the LDMOS device is formed by the steps of: Step 6.5 of forming a first sub-epitaxial layer of a first conductive type comprises: forming a first sub-epitaxial layer of a first conductive type, the first sub-epitaxial layer covering the first inner core structure and filling up the trench; etching back a thickness of the first sub-epitaxial layer so that a remaining thickness of the first sub-epitaxial layer covers the first inner core structure and fills part of the space of the trench.

5. The method of claim 2, wherein the LDMOS device is formed by the steps of: Step 6.8 of forming an Nth inner core structure of a second conductive type comprises: forming an Nth inner core structure of a second conductive type, the Nth inner core structure filling up the trench; etching back a thickness of the Nth inner core structure so that an upper surface of a remaining thickness of the Nth inner core structure does not exceed a bottom surface of the Nth sacrificial layer on the trench sidewall.

6. The method of claim 2, wherein the LDMOS device is formed by the steps of: Step 6.10 of forming an Nth sub-epitaxial layer of a first conductive type comprises: forming an Nth sub-epitaxial layer of a first conductive type, the Nth sub-epitaxial layer covering the Nth inner core structure and filling part of the space of the trench; if the Nth sub-epitaxial layer is the topmost sub-epitaxial layer in the trench, then no etching back process is performed on the Nth sub-epitaxial layer; if the Nth sub-epitaxial layer is not the topmost sub-epitaxial layer in the trench, then etching back a thickness of the Nth sub-epitaxial layer so that a remaining thickness of the Nth sub-epitaxial layer covers the Nth inner core structure and fills part of the space of the trench.

7. The method of claim 1, wherein the LDMOS device is formed by the steps of: In the trench, a thickness of the Nth sub-epitaxial layer which is the topmost sub-epitaxial layer is 0.3 μm to 1 μm.

8. The method of claim 1, wherein, In the trench, a thickness of the first sub-epitaxial layer, a thickness of the second sub-epitaxial layer, and a thickness of the N-1th sub-epitaxial layer, except for the Nth sub-epitaxial layer which is the topmost sub-epitaxial layer, are 0.2 μm to 1 μm.

9. The method of claim 1, wherein, In the trench, a thickness of the first inner core structure, a thickness of the second inner core structure, and a thickness of the Nth inner core structure are 0.05 μm to 0.3 μm.

10. An LDMOS device, characterized by, comprises: a substrate in which a first buried layer of a first conductive type and a second buried layer of a second conductive type located on a side of the first buried layer are formed; a main epitaxial layer of a first conductive type, the main epitaxial layer covering the substrate; a plurality of spaced-apart trenches in the main epitaxial layer; first inner core structure, second inner core structure to Nth inner core structure of a second conductive type, wherein N is an integer greater than or equal to 2; first sub-epitaxial layer, second sub-epitaxial layer to Nth sub-epitaxial layer of a first conductive type, wherein the first inner core structure, the first sub-epitaxial layer, the second inner core structure, the second sub-epitaxial layer, the Nth inner core structure and the Nth sub-epitaxial layer are stacked in the trench from bottom to top and fill up the entire trench, wherein an upper surface of the Nth sub-epitaxial layer which is the topmost sub-epitaxial layer in the trench is flush with an upper surface of the main epitaxial layer.

Images