200ge service data transmission method, chip and communication system based on 224g high-speed serdes

Abstract

The application provides a 200GE service data transmission method, a chip and a communication system based on a 224G high-speed SerDes, and the method comprises the following steps: a PCS sending module performs PCS sending processing on upstream data obtained, to obtain first PCS data; the PCS sending module sends the first PCS data to a PMA sending module according to a first PCS clock rate and a first PCS data bit width; a rate improvement module determines first clock information according to a first PMA data bit width, a first PMA clock rate, the first PCS clock rate, the first PCS data bit width and a set bandwidth, to improve the first PCS clock rate; the PCS sending module sends the first PCS data according to the first PMA data bit width and the improved first PCS clock rate; and the PMA sending module processes the first PCS data and sends first serial data. The application can be applied to the field of internet access and related services, avoids the alignment mark insertion process to improve the sending rate of the PCS layer, and accelerates link convergence and improves link stability by introducing a PMA state frame.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication, in particular to a 200GE service data transmission method based on 224G high-speed SerDes, a chip and a communication system. BACKGROUND

[0002] 224G SerDes (Serializer / Deserializer) is a new generation of ultra-high-speed SerDes. When a single physical transmission channel adopts PAM4 modulation, it can achieve a transmission rate of 224 Gbps.

[0003] Reference Figure 1 The 200GBASE-R data transmission process of the existing 200G Ethernet physical coding sublayer (PCS, Physical Coding Sublayer) and physical medium attachment sublayer (PMA, Physical Medium Attachment) is shown, which specifically includes a sending path from PCS to PMA and a receiving path from PMA to PCS.

[0004] In the sending path from PCS to PMA, the PCS receives data from the MAC layer through the 200GMII interface (data bit width TXD[63:0], control bit width TXC[7:0], and clock TX_CLK), and sequentially undergoes encoding and rate matching, 256B / 257B transcoding, scrambling, alignment mark insertion, pre-FEC distribution, FEC encoding, distribution and interleaving processing. The processed data is transmitted to the PMA through the PMA:IS_UNITDATA_i.request interface, and the PMA completes the driving and sending of the physical signal.

[0005] In the receiving path from PMA to PCS, the PMA receives signals from the physical medium, and then transmits the data of 8 lanes to the PCS through the PMA:IS_UNITDATA_i.indication interface. The PCS sequentially undergoes alignment locking and lane deskewing, lane reordering and deinterleaving, FEC decoding, post-FEC interleaving, alignment removal, descrambling, reverse transcoding, decoding and rate matching, so as to be converted into a format recognizable by the MAC layer, and is sent back to the MAC layer (data bit width RXD[63:0], control bit width RXC[7:0], and clock RX_CLK).

[0006] The PMA:IS_SIGNAL.indication interface is used for the transmission of link state, signal quality and other control information, for example, the PMA reports to the PCS whether the link is locked.

[0007] The existing IEEE protocol stipulates that, for the PMA, the clock domain clock rate is represented as pma_tx_clk, and the PMA bandwidth is pma_tx_clk·257. Since 200GE data needs to be transmitted, the total bandwidth that the PMA needs to maintain is 2·103.125Gbps. After the data bit width sent by the PCS to the PMA is compressed to 257b, there is not enough space to completely accommodate the alignment markers inserted in the alignment marker insertion process, so encoding and rate matching are needed to control the sending end to slow down from time to time. SUMMARY

[0008] The first object of the present application is to provide a 200GE service data transmission method based on a 224G high-speed SerDes, which can improve the transmission rate of service data.

[0009] The second object of the present application is to provide a physical layer chip for implementing the 200GE service data transmission method based on the 224G high-speed SerDes.

[0010] The third object of the present application is to provide a communication system for implementing the 200GE service data transmission method based on the 224G high-speed SerDes, which can improve the link convergence speed and stability.

[0011] In order to achieve the first object, the present application provides a 200GE service data transmission method based on a 224G high-speed SerDes, which is applied to a physical layer chip including a 224G SerDes, and includes: obtaining upstream data; performing PCS transmission on the upstream data to obtain first PCS data; transmitting the first PCS data according to a first PCS clock rate and a first PCS data bit width; determining first clock information according to a first PMA data bit width, a first PMA clock rate, the first PCS clock rate, the first PCS data bit width, and a set bandwidth, and improving the first PCS clock rate according to the first clock information; continuing to transmit the first PCS data by a PCS transmission module according to the first PMA data bit width and the improved first PCS clock rate; and transmitting first serial data according to the first PCS data.

[0012] From the above scheme, the application utilizes the characteristic of 224G SerDes to realize the transmission of 200GE service data in a single physical channel, so that the transmission process of the PCS layer does not need to insert alignment markers, and then the first PCS clock rate of the PCS layer is improved based on the first PMA clock rate, the first PMA data bit width and the set bandwidth adjustment, so that the PCS layer can improve the transmission rate of the first PCS data. The application realizes faster processing speed in the PCS layer, reduces the waiting time of data in the PCS layer, avoids the alignment marker insertion process, reduces the processing delay, and reduces the chip area, power consumption and design difficulty. In addition, since the alignment marker insertion is not needed, a part of the original alignment markers can be replaced by service data, thereby increasing the original 200G bandwidth capacity and making the service data carrying capacity stronger.

[0013] Further, the PMA receiving module obtains second serial data; the PMA receiving module processes the second serial data to obtain parallel data, and sends the parallel data to the PCS receiving module through a rate reduction module according to the second PMA clock rate and the second PMA data bit width; the rate reduction module determines second clock information according to the second PMA data bit width, the second PMA clock rate, the set bandwidth and the second PCS data bit width, and sends the second clock information to a second clock control module of the PCS receiving module; the second clock control module determines the second PCS clock rate according to the second clock information; the PCS receiving module receives the parallel data according to the second PCS data bit width and the second PCS clock rate; and the PCS receiving module sequentially performs FEC decoding, FEC decoding and interleaving, descrambling, reverse transcoding and decoding on the parallel data to obtain second PCS data.

[0014] Therefore, since the PCS layer during receiving also does not need to perform the alignment removal process, the receiving rate of the PCS layer during receiving can also be faster compared with the existing scheme that needs to perform the alignment removal process.

[0015] Further, the set bandwidth is 206.25Gbps, the first PCS data bit width is 264b, the first PMA data bit width is 257b, the PCS transmission process includes 256B / 257B transcoding, the second PCS data bit width is 264b, and the second PMA data bit width is 257b.

[0016] Further, the first serial data and the second serial data include PMA status frames.

[0017] Therefore, since the alignment marker does not need to be set, the spare bandwidth can be used to transmit the PMA status frame, the initialization / training information for fast convergence and the dynamic adaptive information for real-time tracking are provided, and the immature problem of the 224G SerDes link is solved.

[0018] Further, the PMA status frame of the first serial data includes at least one of the following: transmitter analog front-end information, transmitter digital equalizer information, and transmitter clock information.

[0019] Thus, link convergence can be accelerated (Faster Convergence) because the 224G link training (Training) time can be long. By delivering the transmitter PMA status information in-band, the training time can be shortened from milliseconds to microseconds, which is critical for data center fast restart and power management.

[0020] Further, the PMA status frame of the second serial data includes feedback information.

[0021] Thus, link stability can be enhanced (Enhanced Stability). In the face of dynamic changes such as power supply noise and thermal drift, the traditional equalizer adaptation may not keep up with the changes. Through the feedback mechanism of the PMA status frame, the link can be continuously fine-tuned to maintain the best state, significantly reducing the risk of burst errors.

[0022] Further, the fields of the PMA status frame include: frame header, information type, pre-emphasis / de-emphasis setting, TX FEE tap coefficient, TX amplitude, RX error monitoring status, RX margin indication, CRC check, link status indication, link flow control, time stamp, and reserved field.

[0023] To achieve the second purpose, the application provides a physical layer chip, which comprises: a data sending module, the data sending module comprising a PCS sending module, a rate increasing module, and a PMA sending module, the PCS sending module being connected to the rate increasing module, and the rate increasing module being connected to the PMA sending module; the PCS sending module comprising a first clock control module; the PMA sending module comprising a serializer module and a configuration and link frame generation module, the serializer module being connected to the configuration and link frame generation module, and the configuration and link frame generation module being used for sending first serial data; a data receiving module, the data receiving module comprising a PCS receiving module, a rate decreasing module, and a PMA receiving module, the PCS receiving module being connected to the rate decreasing module, and the rate decreasing module being connected to the PMA receiving module; the PCS receiving module comprising a second clock control module; the PMA receiving module comprising a configuration and link frame analysis module and a deserializer module, the configuration and link frame analysis module being connected to the deserializer module, and the configuration and link frame analysis module being used for receiving second serial data; and the data receiving module and the data sending module implementing the above-mentioned 200GE service data transmission method based on 224G high-speed SerDes.

[0024] To achieve the third object, the application provides a communication system, which comprises a sending end and a receiving end, the sending end is connected to the receiving end, and the sending end and the receiving end are respectively provided with the physical layer chip; in the initialization and fast training stage, the sending end starts to send the first serial data in the default configuration; the receiving end extracts the PMA state frame in the first serial data, and sends the TX FFE tap coefficient and the TX amplitude to the equalizer control logic of the receiving end; the equalizer control logic of the receiving end determines the front-end compensation condition of the channel, and configures the equalizer circuit.

[0025] Further, in the dynamic self-adaptive stage, the sending end and the receiving end comprise: the receiving end continuously monitors the key performance indicators; the receiving end sends the key performance indicators to the sending end to form the corresponding PMA state frame; and the sending end adjusts the sending according to the received second serial data

[0026] As can be seen from the above scheme, by introducing the PMA state frame, the analog circuit design can be simplified to a certain extent while accelerating the link convergence and improving the link stability, that is, more complex digital logic and algorithms can be used to compensate for the insufficient performance of the analog front end, the PMA analog circuit with lower cost and lower power consumption can be adopted, so as to reduce the research and development difficulty and cost of the whole chip. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 is the functional relationship diagram of the PCS and the PMA in the prior art 200G Ethernet.

[0028] Figure 2 is the architecture diagram of the physical layer chip of the embodiment of the application.

[0029] Figure 3 is the specific structure diagram of the data sending module of the embodiment of the application.

[0030] Figure 4 is the specific structure diagram of the data receiving module of the embodiment of the application.

[0031] Figure 5 is the flowchart of the initialization and fast training stage when the embodiment of the application is applied.

[0032] Figure 6 is the flowchart of the dynamic self-adaptive stage when the embodiment of the application is applied.

[0033] The application will be further described below in combination with the drawings and embodiments. DETAILED DESCRIPTION

[0034] The 200GE service data transmission method based on the 224G high-speed SerDes can accelerate link convergence and improve link stability by adjusting the clock rate, and can be applied to the field of Internet access and related services. The application further provides a physical layer chip for implementing the 200GE service data transmission method based on the 224G high-speed SerDes.

[0035] The technical solutions in the embodiments of the application will be clearly and completely described below with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are only part of the embodiments of the application, rather than all the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the application.

[0036] Referring to Figure 2 The physical layer chip 1 of the embodiment includes a data sending module 10 and a data receiving module 20. The data sending module 10 is used for processing upstream data from a MAC layer and then sending the data out through a physical medium. The data receiving module 20 is used for processing 200GE service data received from the physical medium, and the processed data is transmitted to the MAC layer as downstream data. For example, the physical layer chip 1 of the embodiment is applied to a communication device A, data transmission is realized between the communication device A and a communication device B, the communication device A serves as a sending end, the communication device B serves as a receiving end, the communication device A sends data of the communication device A to the communication device B through the data sending module 10, and the data sent by the communication device B is received through the data receiving module 20.

[0037] Referring to Figure 3 The data sending module 10 includes a PCS sending module 101, a rate boosting module 102 and a PMA sending module 103. The PCS sending module 101 is connected to the rate boosting module 102, and the rate boosting module 102 is connected to the PMA sending module 103. The PCS sending module 101, the rate boosting module 102 and the PMA sending module 103 cooperate to process upstream data from the MAC layer to obtain first serial data. The first serial data is then sent out through the physical medium by the physical medium dependent (PMD) of the Ethernet physical layer (PHY).

[0038] The PCS sending module 101 implements the PCS sending process, which includes sequentially performing encoding, transcoding, scrambling, forward FEC allocation, interleaving and distribution. The PCS sending module 101 includes an encoding unit, a 256B / 257B transcoding unit, a scrambling unit, a forward FEC allocation unit, an FEC encoding unit, an interleaving and distribution unit. The encoding unit is used to encode the upstream data from the MAC layer into the PCS internal format. The 256B / 257B transcoding unit is used to add 1B byte control information and convert the 256B size data block into a 257B size data block. The scrambling unit is used to disrupt the data pattern, avoid long strings of 0 or 1, and ensure signal stability to facilitate clock recovery. The forward FEC allocation unit is used to preprocess the data before allocation to different lanes to prepare for subsequent FEC encoding. The FEC encoding unit is used to add redundant error correction codes so that the receiving end can correct errors in transmission. The interleaving and distribution unit is used to distribute the data to 8 lanes and balance the lane load through interleaving to improve interference resistance.

[0039] The PCS sending module 101 sequentially encodes, transcodes, scrambles, forward FEC allocates, interleaves and distributes the upstream data to obtain first PCS data.

[0040] The rate improvement module 102 is used to determine the first clock information according to the first PMA data bit width and the first PMA clock rate of the PMA sending module 103, the first PCS clock rate and the first PCS data bit width of the PCS sending module 101, and the set bandwidth, and send the first clock information to the first clock control module of the PCS sending module 101. The first clock control module increases the first PCS clock rate according to the first clock information.

[0041] The PCS sending module 101 first sends the first PCS data to the PMA sending module 103 through the rate improvement module 102 according to the first PCS clock rate and the first PCS data bit width, and then sends the first PCS data to the PMA sending module 103 through the rate improvement module 102 according to the first PMA data bit width and the improved first PCS clock rate after the first PCS clock rate is improved.

[0042] The PMA sending module 103 includes a serializer module and a configuration and link frame generation module. The serializer module is used to perform parallel-to-serial conversion on the first PCS data, and the configuration and link frame generation module is used to insert a PMA status frame into the serial bit stream obtained by parallel-to-serial conversion, thereby obtaining first serial data, and sending the first serial data.

[0043] The PMA status frame of the first serial data includes one of the following: sending end analog front end information, sending end digital equalizer information, sending end clock information.

[0044] The transmitting end analog front-end information includes pre-emphasis / de-emphasis setting and output swing control information. The pre-emphasis / de-emphasis setting specifically includes the tap coefficients (such as the amplitude values of the main cursor Pre-Cursor and the post cursor Post-Cursor) used by the current transmitting end, so that the receiving end can immediately understand the approximate attenuation characteristics of the channel after receiving, and use it as the optimal guess for the initial setting of its own equalizer (such as CTLE), greatly shortening the link training convergence time. The output swing control information specifically includes the driving amplitude level of the current end, so that the receiving end can set the gain of the analog front-end (AFE) after receiving, to prevent signal overload or too small, and optimize the sampling dynamic range of the ADC.

[0045] For the transmitting end digital equalizer information, for example, using FFE, the specific content includes FFE tap coefficients, which specifically include the weight coefficients of each tap of the transmitting end, so that the receiving end can more accurately evaluate the residual inter-symbol interference (ISI) of the channel after knowing the accurate setting of the FFE of the transmitting end, and thus more accurately set its own decision feedback equalizer (DFE) coefficients. As a result, the equalization of the transmitting end and the receiving end is jointly optimized as a whole, and the performance is far superior to the case of independent adaptation of the transmitting end and the receiving end.

[0046] For the transmitting end clock information, including clock tuning information, the clock tuning information specifically includes PLL lock state, DCD (duty cycle distortion) correction value, and characteristic information of high-frequency jitter components. In this way, the CDR (clock data recovery) circuit of the receiving end can be assisted, especially when dealing with deterministic jitter of a specific frequency, it can lock and track faster.

[0047] Referring to Figure 4 , the data receiving module 20 includes a PCS receiving module 201, a rate reduction module 202, and a PMA receiving module 203. The PCS receiving module 201 is connected to the rate reduction module 202, and the rate reduction module 202 is connected to the PMA receiving module 203. The PCS receiving module 201, the rate reduction module 202, and the PMA receiving module 203 cooperate to process the received second serial data to obtain second PCS data, and send the second PCS data to the MAC layer as downstream data.

[0048] The PCS receiving module 201 implements PCS receiving processing, which includes FEC decoding, post-FEC decoding interleaving, descrambling, reverse transcoding, and decoding. The PCS receiving module 201 includes an FEC decoding unit, a post-FEC decoding interleaving unit, a descrambling unit, a reverse transcoding unit, and a decoding unit. The FEC decoding unit is configured to correct transmission errors by using a redundant error correction code to improve data reliability. The post-FEC decoding interleaving unit is configured to interleave the error-corrected data to optimize subsequent processing efficiency. The descrambling unit is configured to implement the inverse process of scrambling. The reverse transcoding unit is configured to convert a data block of 257B size into a data block of 256B size. The decoding unit is configured to convert the obtained data into downstream data recognizable by a MAC layer.

[0049] The PMA receiving module 203 includes a configuration and link frame analysis module and a deserializer module. The configuration and link frame analysis module is configured to configure optimization of receiving according to the PMA status frame in the obtained second serial data, for example, to implement configuration and adaptive adjustment of a receiving equalizer (CTLE, DFE), parameter setting of a clock data recovery (CDR) circuit, and working mode setting of a deserializer (1:8 Demux). The deserializer module is configured to perform serial-parallel conversion on the first serial data to obtain parallel data.

[0050] The PMA status frame in the second serial data includes receiving end feedback information. The receiving end can send information such as a bit error rate (BER) monitored by itself, a signal margin, and a best sampling point position to the sending end, so that the sending end can dynamically adjust its sending parameters (such as weighting and amplitude) according to the actual receiving condition of the receiving end, implement real-time adaptive channel optimization, and resist drift caused by temperature and voltage changes.

[0051] The rate reduction module 202 determines second clock information according to the second PMA data bit width and the second PMA clock rate of the PMA receiving module 203, the set bandwidth, and the second PCS data bit width of the PCS receiving module 201, and sends the second clock information to a second clock control module of the PCS receiving module 201. The second clock control module reduces the second PCS clock rate according to the second clock information.

[0052] The PMA receiving module 203 processes the second serial data to obtain parallel data, and sends the parallel data to the PCS receiving module 201 through the rate reduction module 202 according to the second PMA clock rate and the second PMA data bit width. The PCS receiving module receives the parallel data according to the second PMA data bit width and the second PCS clock rate. After the second PCS clock rate is reduced, the PCS receiving module 201 receives the parallel data according to the second PCS data bit width and the reduced second PCS clock rate.

[0053] The PCS receiving module 201 sequentially performs FEC decoding, FEC decoding and interleaving, descrambling, reverse transcoding and decoding on the parallel data to obtain second PCS data.

[0054] In this embodiment, the bandwidth is set to 206.25 Gbps, the first PCS data bit width is 264b, the first PMA data bit width is 257b, the transcoding is 256B / 257B transcoding, the second PCS data bit width is 264b, and the second PMA data bit width is 257b.

[0055] Referring to Figure 3 , the first PCS clock rate is represented as pcs_tx_clk, the first PCS data bit width is 264b, and the bandwidth of the first PCS data sent by the PCS sending module is pcs_tx_clk·264b=2·103.125 Gbps. After 264 / 257 transcoding by the rate increasing module 102, it is necessary to send it with 257b, i.e., the first PMA data bit width, at this time the data bandwidth is reduced to pcs_tx_clk·257b<2·103.125 Gbps, and then it is sent to the PMA sending module 103. The first PMA clock rate of the PMA sending module 103 is represented as pma_tx_clk, and the data bandwidth of the PMA sending module 103 is pma_tx_clk·257b. In order to keep the total bandwidth of the 200GE service data 2·103.125 Gbps unchanged, it is necessary to increase the first PCS clock rate, and the increased first PCS clock rate is represented as pcs_tx_clk_new, so that pcs_tx_clk_new·257b=2·103.125 Gbps. Therefore, the source is speeded up, the first PCS clock rate is increased, and the increased first PCS clock rate is represented as pcs_tx_clk_new=pcs_tx_clk·264 / 257. Since pma_tx_clk and pcs_tx_clk are in an asynchronous relationship, the clocks of 2 different sources, it is necessary to dynamically adjust the clock information. The final result of the adjustment is dynamically achieved, pcs_tx_clk_new=pma_tx_clk·264 / 257.

[0056] Referring to Figure 4The rate reduction module 202 performs opposite operation to the rate promotion module 102, and converts to a second relatively lower PCS clock rate based on a second PMA clock rate. The second PMA clock rate is represented as pma_rx_clk, the second PMA data bit width is 257b, and the bandwidth of the parallel data sent by the PMA receiving module 203 is pma_rx_clk·257=2·103.125Gbps. After the 257 / 264 conversion of the rate reduction module 202, the PCS receiving module 201 needs to receive at 264b, i.e. the second PCS data bit width, and the second reduced PCS clock rate is represented as pcs_rx_clk_new = pma_rx_clk·257 / 264.

[0057] Thus, since the data processed by the PCS sending module 101 and the PCS receiving module 201 does not have the alignment symbol, the rate of the data sent by the PCS sending module can be improved relative to the scheme requiring the alignment symbol, without changing the original SerDes rate (the protocol stipulates that the PMA sending module and the PMA receiving module are both 2·103.125Gbps). Optionally, by replacing part of the alignment symbol with part of the service data, the bandwidth capacity of the original 200GE can be increased, so that the single 200GE has stronger service carrying capacity and can carry more service data.

[0058] On this basis, since the data processed by the PCS sending module 101 and the PCS receiving module does not have the alignment symbol, in order to utilize the spare bandwidth brought by not using the alignment symbol, the application introduces a PMA state frame mechanism at the PMA layer, and transmits the real-time state information of the PMA layer through the PMA state frame. Specifically, the first serial data sent by the PMA sending module 103 includes the corresponding PMA state, and the second serial data obtained by the PMA receiving module includes the corresponding PMA state frame.

[0059] It should be noted that the first serial data refers to the serial data sent by the data sending module 10 in the physical layer chip 1, and the second serial data refers to the serial data received by the data receiving module 20 in the physical layer chip 1. The first serial data is sent by a communication device including the physical layer chip 1 to another communication device, and the second serial data is obtained by the communication device including the physical layer chip 1 from another communication device. For example, for a communication device A including the physical layer chip 1 and a communication device B including another physical layer chip 1, when the communication device A is the sending end and the communication device B is the receiving end, the first serial data sent by the communication device A is the second serial data for the communication device B; when the communication device A is the receiving end and the communication device B is the sending end, the first serial data sent by the communication device B is the second serial data for the communication device A.

[0060] The fields included in the structure of the PMA status frame are shown in Table 1, including: frame header, information type, pre-emphasis / de-emphasis setting, TX amplitude, TX FFE tap coefficient, RX error code monitoring state, RX margin indication, CRC check, link state indication, link flow control, time stamp, reserved field.

[0061] Table 1. Structure of PMA status frame

[0062]

[0063] The setting of the PMA status frame described above can accelerate link convergence, improve link stability and simplify analog design.

[0064] Taking a communication system including a communication device A and a communication device B as an example, the communication device A is taken as a sending end (TX) and the communication device B is taken as a receiving end (RX) for illustration. The communication device A and the communication device B are respectively provided with the physical layer chip of the embodiment.

[0065] Referring to Figure 5 In the initialization and fast training stage, the following steps are included:

[0066] S11: The sending end starts sending the first serial data with a default or conservative configuration.

[0067] Among them, after the power-on of the link, the PMA status frame of the first serial data sent by the sending end carries the current TX FFE tap coefficient and TX amplitude.

[0068] S12: The deinterleaver of the receiving end extracts the PMA status frame of the first serial data, and sends the TX FFE tap coefficient and TX amplitude to the equalizer control logic of the receiving end.

[0069] S13: The equalizer control logic of the receiving end determines the front-end compensation of the channel and configures the equalizer circuit.

[0070] Among them, the receiving end can calculate the optimal DFE (decision feedback equalizer) coefficient and CTLE (continuous time linear equalizer) setting according to the TX FFE tap coefficient and TX amplitude, so as to directly adjust the DFE coefficient and CTLE setting.

[0071] In this way, the receiving end almost skips the long blind search process, so that the link establishment time is shortened by more than 50%. This is very important for the energy-saving mode (such as FLUSH) that needs to be frequently restarted in the data center.

[0072] Referring to Figure 6 In the dynamic adaptive stage, the following steps are included:

[0073] S21: The receiving end continuously monitors the key performance indicators.

[0074] The key performance indicators include BER levels, eye margin, and sampling point phase.

[0075] S22: The receiving end quantizes the key performance indicators and forms a corresponding PMA state frame to send to the sending end.

[0076] The quantized key performance indicators are the field contents of the "RX error code monitoring state" and "RX margin indication" and are set in the PMA state frame of the second serial data and returned to the sending end.

[0077] S23: The sending end adjusts the sending according to the received second serial data.

[0078] The PMA sending module of the sending end adjusts the process of sending the first serial signal according to the PMA state frame in the second serial data, for example, fine-tunes the FFE coefficient or output amplitude to compensate for the deterioration of channel performance caused by temperature rise or voltage noise when the BER level is found to be rising or the margin is found to be falling.

[0079] Thus, a real-time and closed-loop adaptive system is realized, the link stability is greatly improved, environmental changes can be actively responded to, and link rupture caused by error code accumulation can be avoided.

[0080] In addition, engineers can actively inject test commands to read almost all analog parameters of TX and RX through the PMA state frame. Since all operations are completed in-band, no additional debugging interface or pin is needed, which greatly facilitates the testing and troubleshooting of the integrated system.

[0081] In summary, the application utilizes the characteristics of the 224G SerDes to realize the transmission of 200GE service data in a single physical channel, so that the PCS sending module does not need to insert alignment marks, thereby the first PCS clock rate can be improved, the PCS sending module can improve the sending rate of the first PCS data, and on this basis, the PMA state frame is introduced at the PMA layer, through the PMA state frame, the link convergence is accelerated and the link stability is improved, and to some extent, the analog circuit design can be simplified.

[0082] Finally, it should be emphasized that the above description is only a preferred embodiment of the application and is not intended to limit the application. For those skilled in the art, the application can have various changes and modifications, and any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the application shall be included in the protection scope of the application.

Claims

1. A 200GE service data transmission method based on 224G high-speed SerDes, applied to a physical layer chip comprising a 224G SerDes, characterized in that, The data sending module of the physical layer chip realizes: acquiring upstream data; performing PCS sending processing on the upstream data to obtain first PCS data; wherein a PCS sending module of the data sending module realizes the PCS sending processing, and the PCS sending processing comprises sequentially performing encoding, transcoding, scrambling, forward FEC allocation, interleaving and distribution without performing alignment marker insertion; sending the first PCS data according to a first PCS clock rate and a first PCS data bit width; determining first clock information according to a first PMA data bit width, a first PMA clock rate, the first PCS clock rate, the first PCS data bit width and a set bandwidth, and increasing the first PCS clock rate according to the first clock information; continuing to send the first PCS data according to the first PMA data bit width and the increased first PCS clock rate; sending first serial data according to the first PCS data; the first serial data comprises a corresponding PMA status frame, and real-time status information of a PMA layer is transmitted through the PMA status frame by using spare bandwidth caused by not using an alignment symbol.

2. The 224G high-speed SerDes-based 200GE service data transmission method according to claim 1, wherein, The data receiving module of the physical layer chip realizes: acquiring second serial data; processing the second serial data to obtain parallel data, and sending the parallel data according to a second PMA clock rate and a second PMA data bit width; determining second clock information according to a second PMA data bit width, a second PMA clock rate, the set bandwidth and a second PCS data bit width, and determining a second PCS clock rate according to the second clock information; receiving the parallel data according to the second PCS data bit width and the second PCS clock rate; performing PCS receiving processing on the parallel data to obtain second PCS data.

3. The 200GE service data transmission method based on 224G high-speed SerDes according to claim 2, wherein: the set bandwidth is 206.25Gbps, the first PCS data bit width is 264b, the first PMA data bit width is 257b, the PCS sending processing comprises 256B / 257B transcoding, the second PCS data bit width is 264b, and the second PMA data bit width is 257b.

4. The 200GE service data transmission method based on 224G high-speed SerDes according to claim 2, wherein: the second serial data comprises a corresponding PMA status frame.

5. The 200GE service data transmission method based on 224G high-speed SerDes according to claim 4, wherein: the PMA status frame of the first serial data at least comprises one of the following: sending end analog front end information, sending end digital equalizer information and sending end clock information.

6. The 200GE service data transmission method based on 224G high-speed SerDes according to claim 4, wherein: the PMA status frame of the second serial data comprises feedback information.

7. The 224G high-speed SerDes-based 200GE service data transmission method of claim 4, wherein: the fields of the PMA status frame include: a frame header, an information type, a pre-emphasis / de-emphasis setting, a TX FFE tap coefficient, a TX amplitude, an RX error code monitoring state, an RX margin indication, a CRC check, a link state indication, a link flow control, a time stamp, and a reserved field.

8. A physical layer chip, comprising: comprising: a data sending module, the data sending module comprising a PCS sending module, a rate up module, and a PMA sending module, the PCS sending module being connected to the rate up module, the rate up module being connected to the PMA sending module; the PCS sending module comprising a first clock control module; the PMA sending module comprising a serializer module and a configuration and link frame generation module, the serializer module being connected to the configuration and link frame generation module, the configuration and link frame generation module being configured to send the first serial data; a data receiving module, the data receiving module comprising a PCS receiving module, a rate down module, and a PMA receiving module, the PCS receiving module being connected to the rate down module, the rate down module being connected to the PMA receiving module; the PCS receiving module comprising a second clock control module; the PMA receiving module comprising a configuration and link frame analysis module and a deserializer module, the configuration and link frame analysis module being connected to the deserializer module, the configuration and link frame analysis module being configured to receive the second serial data; the data receiving module and the data sending module implement the 224G high-speed SerDes-based 200GE service data transmission method of any one of claims 1 to 7.

9. A communication system, characterized by comprising: a sending end and a receiving end, the sending end being connected to the receiving end, the sending end and the receiving end each being provided with the physical layer chip of claim 8; the sending end and the receiving end in the initialization and fast training phase comprising: the sending end starting to send the first serial data with a default configuration; the receiving end extracting the PMA status frame in the first serial data and sending the TX FFE tap coefficient and the TX amplitude to the equalizer control logic of the receiving end; the equalizer control logic of the receiving end determining the front-end compensation of the channel and configuring the equalizer circuit.

10. The communication system of claim 9 wherein, comprising: the sending end and the receiving end in the dynamic self-adaptation phase comprising: the receiving end continuously monitoring the key performance indicators; the receiving end sending the corresponding PMA status frame of the key performance indicators to the sending end; the sending end performing sending adjustment according to the received second serial data.

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