Semiconductor structure and method of manufacturing the same

Abstract

This disclosure provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a substrate and at least one capacitor located on the substrate. The capacitor includes: a plurality of first nanosheets extending along a first direction and arranged in an array along a second direction and a third direction; wherein the first direction and the second direction intersect and are parallel to the surface of the substrate, and the third direction is perpendicular to the surface of the substrate; a plurality of first capacitor structures located on both sides of the first nanosheets along the first direction and electrically connected to the first nanosheets; and conductive structures penetrating the plurality of first nanosheets along the second direction and the third direction, respectively, and electrically connected to the plurality of first capacitor structures through the first nanosheets.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for manufacturing the same. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor device in electronic devices such as computers. DRAM chips are typically divided into an array area and a peripheral area. The array area includes an array of memory cells for storing data, while the peripheral area includes the peripheral circuitry located around the memory cell array.

[0003] The capacitors in the peripheral region, commonly known as NICAPs, are used to provide stable power and clean signals to the peripheral circuits. As semiconductor process nodes continue to shrink, DRAM technology is rapidly developing towards higher density, higher speed, and lower power consumption. This trend places more stringent requirements on the capacitance and response speed of the capacitors in the peripheral region. Summary of the Invention

[0004] This disclosure provides a semiconductor structure, including:

[0005] A substrate and at least one capacitor located on the substrate, the capacitor comprising:

[0006] Multiple first nanosheets extend along a first direction and are arranged in an array along a second direction and a third direction; wherein the first direction and the second direction intersect and are parallel to the surface of the substrate, and the third direction is perpendicular to the surface of the substrate;

[0007] Multiple first capacitor structures are respectively located on both sides of the first nanosheet along the first direction and electrically connected to the first nanosheet;

[0008] A conductive structure extends through multiple first nanosheets along the second direction and the third direction, respectively, and is electrically connected to multiple first capacitor structures through the first nanosheets.

[0009] In some embodiments, the conductive structure includes one or a plurality of first sub-parts spaced apart along the first direction, wherein the first sub-parts are plate-like structures extending along the second direction and the third direction, and each first sub-part penetrates a plurality of first nanosheets along the second direction and the third direction, respectively.

[0010] In some embodiments, the number of first sub-parts is multiple; the conductive structure further includes multiple second sub-parts, the second sub-parts being located between two adjacent first sub-parts and connected to two adjacent first sub-parts, and the orthographic projection of the second sub-parts on the surface of the substrate falls between the orthographic projections of two adjacent first nanosheets on the surface of the substrate in the second direction.

[0011] In some embodiments, the extension length of the second sub-part in the third direction is equal to the extension length of the first sub-part in the third direction.

[0012] In some embodiments, the first nanosheet includes doped portions located at both ends thereon along the first direction, and the first capacitor structure is in contact with the doped portions;

[0013] At least one of the first sub-parts is located on the side of the doped portion away from the first capacitor structure that is in contact with it, and is in contact with the doped portion.

[0014] In some embodiments, the first capacitor structure includes:

[0015] A first electrode layer is electrically connected to the first nanosheet; the first electrode layer is a cup-shaped structure extending along the first direction, and the opening of the first electrode layer is away from the first nanosheet that is electrically connected to the first electrode layer along the first direction.

[0016] A capacitor dielectric layer that at least covers the inner wall of the first space defined by the first electrode layer;

[0017] The second electrode layer covers the capacitor dielectric layer and at least fills the second space defined by the capacitor dielectric layer.

[0018] In some embodiments, the number of capacitors is multiple, and the multiple capacitors are arranged along the first direction, with the second electrode layers of two adjacent first capacitor structures belonging to different capacitors electrically connected.

[0019] In some embodiments, the substrate includes a peripheral region and a storage region, and the capacitor is located in the peripheral region; the semiconductor structure further includes a storage array located in the storage region; wherein the storage array includes:

[0020] Multiple second nanosheets extend along a fourth direction and are arranged in an array along a fifth direction and the third direction; wherein the fourth direction and the fifth direction intersect and are parallel to the surface of the substrate;

[0021] Multiple second capacitor structures are located on at least one side of the second nanosheet along the fourth direction and are electrically connected to the second nanosheet;

[0022] Multiple word line structures extend along the fifth direction and are arranged along the third direction, each of the word line structures covering a portion of the surface of multiple second nanosheets arranged along the fifth direction;

[0023] Multiple bitline structures extend along the third direction and are arranged along the fifth direction, each bitline structure penetrating and electrically connecting to the multiple second nanosheets arranged along the third direction.

[0024] This disclosure also provides a method for manufacturing a semiconductor structure, including:

[0025] Provide substrate;

[0026] At least one capacitor is formed on the substrate; wherein forming the capacitor includes:

[0027] A plurality of first nanosheets are formed on the substrate, the plurality of first nanosheets extending along a first direction and arranged in an array along a second direction and a third direction; wherein the first direction and the second direction intersect and are parallel to the surface of the substrate, and the third direction is perpendicular to the surface of the substrate;

[0028] Multiple first capacitor structures are formed, and the multiple first capacitor structures are respectively located on both sides of the first nanosheet along the first direction and electrically connected to the first nanosheet.

[0029] A conductive structure is formed, which penetrates multiple first nanosheets along the second direction and the third direction, and is electrically connected to multiple first capacitor structures through the first nanosheets.

[0030] In some embodiments, a plurality of the first nanosheets and a plurality of the first capacitor structures are formed on the substrate, including:

[0031] An initial stacked structure is formed on the substrate, the initial stacked structure comprising a first isolation layer and a semiconductor layer alternately stacked along the third direction;

[0032] The initial stacked structure is graphically represented to form a plurality of stacked structures extending along the first direction and arranged along the second direction, and a first isolation trench located between adjacent stacked structures in the second direction; the semiconductor layer in the stacked structure is defined as an initial nanosheet;

[0033] A second isolation layer is filled into the first isolation trench;

[0034] A portion of the initial nanosheets is removed to form a capacitor groove extending along the first direction, and the remaining initial nanosheets constitute the first nanosheet, with the capacitor groove located on both sides of the first nanosheet along the first direction.

[0035] The first capacitor structure is formed within the capacitor slot.

[0036] In some embodiments, forming the conductive structure includes:

[0037] The stacked structure and the second isolation layer are etched to form openings that cut through a plurality of the first nanosheets along the second direction and the third direction, respectively.

[0038] The opening is filled with conductive material to form the conductive structure.

[0039] In some embodiments, forming the opening includes:

[0040] The stacked structure and the second isolation layer are etched to form one or a plurality of first openings spaced apart along the first direction. Each first opening extends continuously along the second direction and the third direction, and cuts off a plurality of first nanosheets arranged in an array along the second direction and the third direction.

[0041] Filling the opening with conductive material to form the conductive structure includes: filling the first opening with the conductive material to form one or more first sub-parts.

[0042] In some embodiments, the number of the first openings is multiple; forming the openings further includes:

[0043] The second isolation layer is etched to form a second opening between two adjacent first openings, the second opening communicating with the two adjacent first openings, and the orthographic projection of the second opening on the surface of the substrate falling between the orthographic projections of two adjacent first nanosheets on the surface of the substrate in the second direction.

[0044] The process of filling the opening with conductive material to form the conductive structure further includes filling the second opening with the conductive material to form a second sub-part, the second sub-part being connected to two adjacent first sub-parts.

[0045] In some embodiments, after forming the capacitor trench and before forming the first capacitor structure, the method further includes performing a doping process on the portion of the first nanosheet exposed by the capacitor trench to form a doped portion.

[0046] In some embodiments, forming the first capacitor structure includes:

[0047] A first electrode layer is formed, which covers the inner wall of the capacitor trench and is electrically connected to the first nanosheet; the first electrode layer is a cup-shaped structure extending along the first direction, and the opening of the first electrode layer is away from the first nanosheet that is electrically connected to the first electrode layer along the first direction.

[0048] A capacitor dielectric layer is formed, the capacitor dielectric layer at least covering the inner wall of the first space defined by the first electrode layer;

[0049] A second electrode layer is formed, which covers the capacitor dielectric layer and at least fills the second space defined by the capacitor dielectric layer.

[0050] In some embodiments, the substrate includes a peripheral region and a storage region, and the capacitor is located in the peripheral region; the method further includes: forming a storage array in the storage region; wherein forming the storage array includes:

[0051] Multiple second nanosheets are formed, which extend along a fourth direction and are arranged in an array along a fifth direction and the third direction; wherein the fourth direction and the fifth direction intersect and are parallel to the surface of the substrate;

[0052] Multiple second capacitor structures are formed, and the multiple second capacitor structures are located on at least one side of the second nanosheet along the fourth direction and are electrically connected to the second nanosheet;

[0053] Multiple word line structures are formed, the multiple word line structures extend along the fifth direction and are arranged along the third direction, and each word line structure covers a portion of the surface of the multiple second nanosheets arranged along the fifth direction;

[0054] Multiple bitline structures are formed, the multiple bitline structures extend along the third direction and are arranged along the fifth direction, and each bitline structure penetrates and is electrically connected to the multiple second nanosheets arranged along the third direction.

[0055] In some embodiments, the first nanosheet and the second nanosheet are formed in the same step; and / or,

[0056] The first capacitor structure and the second capacitor structure are formed in the same step; and / or,

[0057] The conductive structure and the bit line structure are formed in the same step.

[0058] In this embodiment, by setting a conductive structure to penetrate multiple first nanosheets arranged in an array along the second and third directions, the conductive structure and the multiple first nanosheets are electrically connected to each other. This enables multiple first capacitor structures located on the same side of the multiple first nanosheets along the first direction to be connected in parallel within a capacitor, thereby increasing the overall capacitance of the capacitor. When the external circuit experiences a sudden large current demand, the larger capacitance can provide more abundant charge. Thus, it can more effectively suppress voltage drops and overshoots, maintain power supply voltage stability, and increase the capacitor's signal crosstalk performance. At the same time, by setting the conductive structure and the multiple first nanosheets to be electrically connected to each other, multiple first capacitor structures located on one side of the multiple first nanosheets along the first direction are connected in series with multiple first capacitor structures located on the other side of the multiple first nanosheets along the first direction within a capacitor. This improves the capacitor's withstand voltage performance and prevents the capacitor from failing under voltage stress in the event of an unexpected, brief overvoltage event in the external circuit, thereby improving the capacitor's reliability.

[0059] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features and advantages of this disclosure will become apparent from the specification and the drawings. Attached Figure Description

[0060] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0061] Figure 1 This is a three-dimensional structural diagram of a semiconductor structure provided in some embodiments of the present disclosure;

[0062] Figure 2 Some embodiments of this disclosure follow Figure 1 A schematic diagram of the cross-sectional structure taken by line A1A2 in the diagram;

[0063] Figure 3 Three-dimensional structural schematic diagrams of semiconductor structures provided in other embodiments of this disclosure;

[0064] Figure 4 For other embodiments of this disclosure along Figure 3 A schematic diagram of the cross-sectional structure taken by line A1A2 in the diagram;

[0065] Figure 5 A three-dimensional structural schematic diagram of a semiconductor structure provided for some embodiments of this disclosure;

[0066] Figure 6This is a three-dimensional structural schematic diagram of a semiconductor structure provided in some embodiments of the present disclosure;

[0067] Figure 7 This disclosure includes flowcharts of methods for manufacturing semiconductor structures according to some embodiments;

[0068] Figure 8 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 1 Schematic diagram of the cross-sectional structure taken from line A1A2 in the middle. Figure 1 ;

[0069] Figure 9 Top view of the semiconductor structure during the manufacturing process provided in some embodiments of this disclosure. Figure 2 ;

[0070] Figure 10 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 1 Schematic diagram of the cross-sectional structure taken from line A1A2 in the middle. Figure 3 ;

[0071] Figure 11 Top view of the semiconductor structure during the manufacturing process provided in some embodiments of this disclosure. Figure 4 ;

[0072] Figure 12 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 1 Schematic diagram of the cross-sectional structure taken by line A1A2 in the middle. Figure 5 ;

[0073] Figure 13 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 1 Schematic diagram of the cross-sectional structure taken from line A1A2 in the middle. Figure 6 ;

[0074] Figure 14 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 1 Schematic diagram of the cross-sectional structure taken from line A1A2 in the middle. Figure 7 ;

[0075] Figure 15 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 1 Schematic diagram of the cross-sectional structure taken by line A1A2 in the middle. Figure 8 ;

[0076] Figure 16 Top view of the semiconductor structure during the manufacturing process provided in some embodiments of this disclosure. Figure 9 ;

[0077] Figure 17 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 1 Schematic diagram of the cross-sectional structure taken by line A1A2 in the middle. Figure 10 ;

[0078] Figure 18 Top view of the semiconductor structure during manufacturing process provided for other embodiments of this disclosure. Figure 10 one;

[0079] Figure 19 The semiconductor structures provided for other embodiments of this disclosure follow the manufacturing process along Figure 3 Schematic diagram of the cross-sectional structure taken by line A1A2 in the middle. Figure 10 two;

[0080] Figure 20 The semiconductor structures provided for other embodiments of this disclosure follow the manufacturing process along Figure 3 Schematic diagram of the cross-sectional structure taken by line A1A2 in the middle. Figure 10 three;

[0081] Figure 21 The semiconductor structures provided for other embodiments of this disclosure follow the manufacturing process along Figure 3 Schematic diagram of the cross-sectional structure taken by line A1A2 in the middle. Figure 10 Four;

[0082] Figure 22 Top view of the semiconductor structure during manufacturing process provided for other embodiments of this disclosure. Figure 10 five;

[0083] Figure 23 The semiconductor structures provided for other embodiments of this disclosure follow the manufacturing process along Figure 3 Schematic diagram of the cross-sectional structure taken by line A1A2 in the middle. Figure 10 six. Detailed Implementation

[0084] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0085] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0086] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0087] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0088] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0089] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0090] In this embodiment, by setting a conductive structure to penetrate multiple first nanosheets arranged in an array along the second and third directions, the conductive structure and the multiple first nanosheets are electrically connected to each other. This enables multiple first capacitor structures located on the same side of the multiple first nanosheets along the first direction to be connected in parallel within a capacitor, thereby increasing the overall capacitance of the capacitor. When the external circuit experiences a sudden large current demand, the larger capacitance can provide more abundant charge. Thus, it can more effectively suppress voltage drops and overshoots, maintain power supply voltage stability, and increase the capacitor's signal crosstalk performance. At the same time, by setting the conductive structure and the multiple first nanosheets to be electrically connected to each other, multiple first capacitor structures located on one side of the multiple first nanosheets along the first direction are connected in series with multiple first capacitor structures located on the other side of the multiple first nanosheets along the first direction within a capacitor. This improves the capacitor's withstand voltage performance and prevents the capacitor from failing under voltage stress in the event of an unexpected, brief overvoltage event in the external circuit, thereby improving the capacitor's reliability.

[0091] To make the above-mentioned objects, features, and advantages of this disclosure more apparent and understandable, the specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. In describing the embodiments of this disclosure in detail, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to general proportions, and the schematic diagrams are merely examples and should not limit the scope of protection of this disclosure.

[0092] The semiconductor structure provided in the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings. Specifically, to illustrate the distribution of the first capacitor structure, Figure 1 , Figure 3 and Figure 5 The portion of the capacitor dielectric layer and portion of the second electrode layer located outside the capacitor trench in the first capacitor structure located on the outermost side along the first direction in the semiconductor structure are omitted.

[0093] like Figure 1As shown, the semiconductor structure includes: a substrate 10 and at least one capacitor 20 located on the substrate 10. The capacitor 20 includes: a plurality of first nanosheets 15 extending along a first direction and arranged in an array along a second direction and a third direction; wherein the first direction and the second direction intersect and are parallel to the surface of the substrate 10, and the third direction is perpendicular to the surface of the substrate 10; a plurality of first capacitor structures 16 located on both sides of the first nanosheets 15 along the first direction and electrically connected to the first nanosheets 15; and conductive structures 17 penetrating the plurality of first nanosheets 15 along the second direction and the third direction, respectively, and electrically connected to the plurality of first capacitor structures 16 through the first nanosheets 15.

[0094] Here, the second direction and the third direction can be perpendicular or oblique to each other.

[0095] In some embodiments, the materials of the substrate 10 and the first nanosheet 15 can be semiconductor materials. The materials of the substrate 10 and the first nanosheet 15 can each independently include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In some embodiments, the substrate 10 can be a silicon substrate, which may be doped or undoped, and the material of the first nanosheet 15 can be silicon, which may be doped or undoped.

[0096] In some embodiments, in each capacitor 20, a plurality of first capacitor structures 16 located on the same side of a plurality of first nanosheets 15 along a first direction are arranged in an array along a second direction and a third direction.

[0097] like Figure 1 and Figure 2 As shown, in some embodiments, the first capacitor structure 16 may include a first electrode layer 161, which is electrically connected to the first nanosheet 15. In some embodiments, the first electrode layer 161 is a cup-shaped structure extending along a first direction, and the opening of the first electrode layer 161 is away from the first nanosheet 15 electrically connected to the first electrode layer 161 along the first direction. In some embodiments, the material of the first electrode layer 161 includes one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicides, and metal alloys, such as titanium nitride.

[0098] In some embodiments, the first capacitor structure 16 may further include: a capacitor dielectric layer 162, which at least covers the inner wall of the first space S1 defined by the first electrode layer 161; and a second electrode layer 163, which covers the capacitor dielectric layer 162 and at least fills the second space S2 defined by the capacitor dielectric layer 162.

[0099] In some embodiments, the material of the capacitor dielectric layer 162 includes a high dielectric constant material, such as, but not limited to, aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), and zirconium silicon oxide (ZrSi). x O y Hafnium oxide (HfO2), Hafnium silicon oxide (HfSi) x O y Hafnium silicon nitride oxide (HfSiON), hafnium zirconate (HfZrO4), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAl) x O y ), lanthanum hafnium oxide (LaHf) x O y ), Hafnium aluminum oxide (HfAl) x O y The material of the second electrode layer 163 may include at least one or a combination of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicides, metal alloys, conductive doped germanium-silicon-carbon, or silicon-germanium.

[0100] like Figure 1 and Figure 2 As shown, in some embodiments, the capacitor 20 may include a capacitor groove 14, which is located on both sides of the first nanosheet 15 along a first direction, and the opening of the capacitor groove 14 is aligned with the opening of the first electrode layer 161, which covers the inner wall of the capacitor groove 14. In the third direction, adjacent first nanosheets 15 and adjacent capacitor grooves 14 may be separated by a first isolation layer 11. In the second direction, adjacent capacitor grooves 14 may be separated by a second isolation layer 13. The materials of the first isolation layer 11 and the second isolation layer 13 may each independently include one or more of oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride), and oxynitrides (e.g., silicon oxynitride).

[0101] like Figure 2As shown, in some embodiments, in a capacitor 20, the capacitor dielectric layer 162 of a plurality of first capacitor structures 16 located on the same side of a plurality of first nanosheets 15 along a first direction may also cover the sidewalls of the first isolation layer 11 and the second isolation layer 13 in the first direction and be connected to each other. The second electrode layer 163 of the plurality of first capacitor structures 16 located on the same side of a plurality of first nanosheets 15 along the first direction covers the capacitor dielectric layer 162 and is electrically connected to each other. In this embodiment of the present disclosure, by setting a conductive structure 17 to penetrate a plurality of first nanosheets 15 arranged in an array along the second direction and the third direction, the conductive structure 17 is electrically connected to the plurality of first nanosheets 15, thereby realizing the electrical connection of the first electrode layer 161 of the plurality of first capacitor structures 16 located on the same side of a plurality of first nanosheets 15 along the first direction.

[0102] Thus, by setting the first nanosheet 15 and the conductive structure 17, multiple first capacitor structures 16 located on the same side of the multiple first nanosheets 15 along the first direction are connected in parallel with each other.

[0103] Meanwhile, in a capacitor 20, by setting a conductive structure 17 and multiple first nanosheets 15 to be electrically connected to each other, multiple first capacitor structures 16 located on one side of the multiple first nanosheets 15 along the first direction are connected in series with multiple first capacitor structures 16 located on the other side of the multiple first nanosheets 15 along the first direction.

[0104] The semiconductor structure provided in this disclosure can be a three-dimensional dynamic random access memory. However, it is not limited to this; the semiconductor structure can also be any semiconductor structure with a capacitor. In some embodiments, the substrate 10 may include a peripheral region 101 and a storage region 102. The capacitor 20 may be located in the peripheral region 101. The capacitor 20 located in the peripheral region 101 can provide instantaneous current to the high-speed switching circuit located in the peripheral region 101, thereby maintaining the stability of the power supply voltage.

[0105] Specifically, when semiconductor structures (such as DRAM) operate at high speeds (e.g., read / write, refresh operations), millions or even billions of transistors in the peripheral circuitry switch on and off simultaneously and rapidly. This sudden current switching causes instantaneous voltage fluctuations (i.e., "power supply noise") on the power lines. If the power supply voltage is unstable, the circuit cannot function properly, potentially leading to data read / write errors. When the high-speed switching circuit in peripheral area 101 is momentarily turned on, capacitor 20 can quickly discharge, providing instantaneous current to the peripheral circuitry to compensate for any delays in the power line response and prevent the power supply voltage from being pulled down (voltage drop). When the peripheral circuit is momentarily turned off, the excess charge generated can be quickly absorbed (charged) by capacitor 20, preventing the power supply voltage from being raised (voltage overshoot), thus stabilizing the power supply voltage.

[0106] Meanwhile, capacitor 20 can act as a filter capacitor to filter out electromagnetic coupling interference and high-frequency noise during signal transmission, thus achieving the function of cleaning the signal.

[0107] In this embodiment, by electrically connecting the conductive structure 17 and the multiple first nanosheets 15 to each other, multiple first capacitor structures 16 located on the same side of the multiple first nanosheets 15 along the first direction in a capacitor 20 are connected in parallel, thereby increasing the overall capacitance of the capacitor 20. When the external circuit has a sudden large current demand, the larger capacitance can provide more abundant charge. In this way, the voltage drop and overshoot of the power supply can be suppressed more effectively, the power supply voltage can be maintained stably, and the signal crosstalk removal performance of the capacitor 20 can be increased. At the same time, by electrically connecting the conductive structure 17 and the multiple first nanosheets 15 to each other, multiple first capacitor structures 16 located on one side of the multiple first nanosheets 15 along the first direction in a capacitor 20 are connected in series with multiple first capacitor structures 16 located on the other side of the multiple first nanosheets 15 along the first direction, thereby improving the withstand voltage performance of the capacitor 20. In the event of an unexpected and brief overvoltage event in the external circuit, the capacitor 20 is prevented from failing under voltage stress, thereby improving the reliability of the capacitor 20.

[0108] like Figure 1 and Figure 2 As shown, in some embodiments, the conductive structure 17 includes one or a plurality of first sub-parts 171 arranged at intervals along a first direction. The first sub-parts 171 are plate-like structures extending along a second direction and a third direction, and each first sub-part 171 penetrates a plurality of first nanosheets 15 along the second direction and the third direction, respectively. Figure 1 and Figure 2 The number of first sub-parts 171 shown is 3. However, it is not limited to this; the number of first sub-parts 171 can be more or less, such as 1, 2, 4, etc.

[0109] In practical operation, the conductive structure 17 can be used to charge and discharge multiple first capacitor structures 16. In this embodiment, all the first nanosheets 15 of a capacitor 20 are electrically connected through the first sub-part 171 of the plate-like structure, thus enabling all the first capacitor structures 16 of a capacitor 20 to be electrically connected to each other. Simultaneously, the first sub-part 171 with the plate-like structure has lower resistance. The first sub-part 171 with the plate-like structure and the multiple first nanosheets 15 are cross-connected, reducing the overall resistance of the conductive structure 17 and the multiple first nanosheets 15, thereby reducing the connection resistance between the multiple first capacitor structures 16 and improving the response speed of the capacitor 20.

[0110] In some embodiments, the number of first sub-parts 171 is multiple; the conductive structure 17 may further include multiple second sub-parts 172, the second sub-parts 172 being located between and connected to two adjacent first sub-parts 171, and the orthographic projection of the second sub-parts 172 on the surface of the substrate 10 falling between the orthographic projections of two adjacent first nanosheets 15 in the second direction on the surface of the substrate 10. In this embodiment of the present disclosure, adjacent first sub-parts 171 can be electrically connected through second sub-parts 172, and the first sub-parts 171 and second sub-parts 172 constitute a mesh-like conductive structure 17. In this way, the resistance of the conductive structure 17 can be further reduced, and the overall resistance of the conductive structure 17 and the multiple first nanosheets 15 can be further reduced, so as to further improve the response speed of the capacitor 20.

[0111] In some embodiments, the extension length of the second sub-part 172 in the third direction is equal to the extension length of the first sub-part 171 in the third direction, thereby further reducing the resistance of the conductive structure 17 and the overall resistance of the conductive structure 17 and the plurality of first nanosheets 15.

[0112] In some embodiments, the material of the conductive structure 17 may include one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicides, and metal alloys, such as tungsten.

[0113] like Figure 1 and Figure 2 As shown, in some embodiments, the first nanosheet 15 includes doped portions 151 located at both ends along a first direction, and the first capacitor structure 16 is in contact with the doped portions 151. In some embodiments, the first electrode layer 161 of the first capacitor structure 16 is in contact with the doped portions 151, thereby reducing the contact resistance between the first nanosheet 15 and the first capacitor structure 16 and further improving the response speed of the first capacitor structure 16. The doped portions 151 are doped with a dopant, which can be one or more elements such as boron, phosphorus, and arsenic. The doping concentration of the dopant in the doped portions 151 is greater than the doping concentration of the dopant in other parts of the first nanosheet 15 excluding the doped portions 151.

[0114] In some embodiments, the doped portion 151 can be formed by performing a doping process on the first nanosheet 15, or by an epitaxial process. In some embodiments, a semiconductor metallization process can also be used to process the doped portion 151. Specifically, a metal layer can be formed on the side of the doped portion 151 facing the first capacitor structure 16, and the metal layer can be annealed to allow the metal elements in the metal layer to diffuse into the doped portion 151, thereby further improving the conductivity of the doped portion 151 and reducing the contact resistance between the first nanosheet 15 and the first capacitor structure 16.

[0115] In some embodiments, at least one first sub-part 171 is located on the side of the doped part 151 opposite to the first capacitor structure 16 that is in contact with it, and is in contact with the doped part 151. In this way, the contact resistance between the first sub-part 171 and the first capacitor structure 16 can be reduced, the connection resistance between the plurality of first capacitor structures 16 can be further reduced, and the response speed of the capacitor can be improved.

[0116] like Figure 1 As shown, in some embodiments, the semiconductor structure may further include a lead 18 located on the capacitor 20 and electrically connected to the conductive structure 17. In practical applications, the capacitor 20 can be charged and discharged via the lead 18.

[0117] like Figure 3 and Figure 4 or Figure 5 As shown, in some embodiments, there are multiple capacitors 20 arranged along a first direction, and the second electrode layers 163 of two adjacent first capacitor structures 16 belonging to different capacitors 20 are electrically connected. In this way, multiple capacitors 20 arranged along the first direction are connected in series, thereby improving the overall withstand voltage performance of the multiple capacitors 20 and further improving the reliability of the capacitors 20.

[0118] like Figure 3 and Figure 4 As shown, in some embodiments, the two capacitors 20 can be connected in series. For example... Figure 5 As shown, in some embodiments, the three capacitors 20 can also be connected in series. In some embodiments, the upper voltage limit of the structure formed by multiple series-connected capacitors 20 can be between 1.5V and 2.5V, such as 1.5V, 1.8V, 2V, 2.5V, etc. Here, the upper voltage limit refers to the upper voltage limit that the structure formed by multiple series-connected capacitors 20 can safely withstand during design and operation.

[0119] In some embodiments, among a plurality of capacitors 20 connected in series along a first direction, the conductive structures 17 of the capacitors 20 located at both ends along the first direction can be connected to one or more leads 18 respectively, so that the capacitor structure composed of a plurality of capacitors 20 connected in series can be charged and discharged through the leads 18.

[0120] like Figure 6 As shown, in some embodiments, the semiconductor structure further includes: a memory array 30 located in the memory region 102; wherein the memory array 30 includes: a plurality of second nanosheets 21 extending along a fourth direction and arranged in an array along a fifth and a third direction; wherein the fourth and fifth directions intersect and are parallel to the surface of the substrate 10; a plurality of second capacitor structures 22 located along the fourth direction on at least one side of the second nanosheets 21 and electrically connected to the second nanosheets 21; a plurality of word line structures WL extending along the fifth direction and arranged along a third direction, each word line structure WL covering a portion of the surface of the plurality of second nanosheets 21 arranged along the fifth direction; and a plurality of bit line structures BL extending along a third direction and arranged along the fifth direction, each bit line structure BL penetrating the plurality of second nanosheets 21 arranged along the third direction and electrically connected to them.

[0121] Here, the fourth and fifth directions can be perpendicular or oblique, the fourth direction can be the same as or different from the first direction, and the fifth direction can be the same as or different from the second direction.

[0122] The storage array 30 located in storage area 102 is used to store data, and the peripheral circuitry located in peripheral area 101 is used to control the storage array 30. The second capacitor structure 22 serves as information storage. In one embodiment, the second capacitor structure 22 may include a lower electrode electrically connected to the second nanosheet 21, a dielectric layer covering the lower electrode, and a common upper electrode covering the dielectric layer. In some embodiments, the lower electrode may have a cup-shaped structure similar to the first electrode layer 161, with the opening of the cup-shaped structure facing the fourth direction. However, this is not a limitation; in other embodiments, the lower electrode may also be columnar and extend along the fourth direction.

[0123] like Figure 6 As shown, in some embodiments, the two ends of the second nanosheet 21 in the fourth direction are each electrically connected to a second capacitor structure 22, and the word line structure WL is located between the bit line structure BL and the second capacitor structure 22 along the second direction. Each word line structure WL can extend along the fifth direction and surround the plurality of second nanosheets 21 arranged along the fifth direction.

[0124] In some embodiments, the first nanosheet 15 and the second nanosheet 21 can be formed in the same step; and / or, the first capacitor structure 16 and the second capacitor structure 22 can be formed in the same step; and / or, the conductive structure 17 and the bit line structure BL can be formed in the same step. This simplifies the semiconductor structure manufacturing process, and the mask used to form the memory array 30 and the capacitor 20 can be shared, saving costs.

[0125] This disclosure also provides a method for manufacturing a semiconductor structure, such as... Figure 7 As shown, the manufacturing method includes:

[0126] Step S101: Provide a substrate;

[0127] Step S102: Form at least one capacitor on a substrate; wherein forming the capacitor includes: forming a plurality of first nanosheets on the substrate, the plurality of first nanosheets extending along a first direction and arranged in an array along a second direction and a third direction; wherein the first direction and the second direction intersect and are parallel to the surface of the substrate, and the third direction is perpendicular to the surface of the substrate; forming a plurality of first capacitor structures, the plurality of first capacitor structures being located on both sides of the first nanosheets along the first direction and electrically connected to the first nanosheets; forming conductive structures, the conductive structures penetrating the plurality of first nanosheets along the second direction and the third direction, and electrically connected to the plurality of first capacitor structures through the first nanosheets.

[0128] The manufacturing method of the semiconductor structure provided in the embodiments of this application will be further described in detail below with reference to the accompanying drawings. Figure 9 , Figure 11 , Figure 16 , Figure 18 as well as Figure 22 They are respectively Figure 10 , Figure 12 , Figure 17 , Figure 19 as well as Figure 23 A top view schematic diagram of the semiconductor structure is shown.

[0129] First, execute step S101, as follows: Figure 8 As shown, a substrate 10 is provided.

[0130] The material of substrate 10 is as described above and will not be repeated here.

[0131] Next, proceed to step S102, as follows: Figures 8 to 17 as well as Figure 1 and Figure 2As shown, at least one capacitor 20 is formed on a substrate 10; wherein forming the capacitor 20 includes: forming a plurality of first nanosheets 15 on the substrate 10, the plurality of first nanosheets 15 extending along a first direction and arranged in an array along a second direction and a third direction; wherein the first direction and the second direction intersect and are parallel to the surface of the substrate 10, and the third direction is perpendicular to the surface of the substrate 10; forming a plurality of first capacitor structures 16, the plurality of first capacitor structures 16 being located on both sides of the first nanosheets 15 along the first direction and electrically connected to the first nanosheets 15; forming a conductive structure 17, the conductive structure 17 penetrating the plurality of first nanosheets 15 along the second direction and the third direction, and electrically connected to the plurality of first capacitor structures 16 through the first nanosheets 15.

[0132] Here, the second direction and the third direction can be perpendicular or oblique to each other.

[0133] In some embodiments, the substrate 10 may include a peripheral region 101, and the capacitor 20 may be formed on the peripheral region 101.

[0134] See you again Figures 8 to 15 In some embodiments, a plurality of first nanosheets 15 and a plurality of first capacitor structures 16 are formed on the substrate 10, including:

[0135] An initial stacked structure ST' is formed on substrate 10. The initial stacked structure ST' includes a first isolation layer 11 and a semiconductor layer 12 alternately stacked along a third direction. Figures 8 to 10 );

[0136] The initial stacked structure ST' is patterned to form a plurality of stacked structures ST extending along a first direction and arranged along a second direction, and a first isolation trench T1 located between adjacent stacked structures ST in the second direction; the semiconductor layer 12 in the stacked structure ST is defined as an initial nanosheet 15'; a second isolation layer 13 (e.g., ...) is filled in the first isolation trench T1. Figures 11 to 12 );

[0137] A portion of the initial nanosheets 15' is removed to form a capacitor trench 14 extending along a first direction. The remaining initial nanosheets 15' constitute the first nanosheet 15, and the capacitor trench 14 is located on both sides of the first nanosheet 15 along the first direction (e.g., Figure 13 );

[0138] A first capacitor structure 16 is formed within the capacitor slot 14 (e.g., Figures 14 to 15 ).

[0139] See you again Figures 8 to 10 In some embodiments, forming the initial stacked structure ST' includes: first, as... Figure 8As shown, alternating stacked semiconductor material layers 111 and 12 can be formed on substrate 10 using an epitaxial growth process; wherein, the material of semiconductor material layer 111 may include, but is not limited to, silicon-germanium, and the material of semiconductor layer 12 may include, but is not limited to, silicon; then, as... Figure 9 As shown, the semiconductor material layer 111 is replaced with the first isolation layer 11 to form the initial stacked structure ST'. However, it is not limited to this, the first isolation layer 11 and the semiconductor layer 12 can also be deposited alternately on the substrate 10 to form the initial stacked structure ST'.

[0140] In some embodiments, the materials of the first isolation layer 11 and the second isolation layer 13 may each independently include one or more of oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride), oxynitrides (e.g., silicon oxynitride), etc.

[0141] See you again Figures 11 to 12 In some embodiments, the graphical initial stacked structure ST' further includes: forming second isolation trenches T2 on both sides of the stacked structure ST in a first direction, the second isolation trenches T2 extending along a second direction and exposing the second isolation layer 13 and the sidewalls of the stacked structure ST. Figure 11 and Figure 16 The stacked structure ST identified in the middle includes an initial nanosheet 15' and a first isolation layer 11 that are stacked upwards and alternately arranged in a third-party manner.

[0142] See you again Figure 13 In some embodiments, a portion of the initial nanosheet 15' can be removed from the second isolation trench T2 located on both sides of the plurality of stacked structures ST to form the first nanosheet 15 and the capacitor trench 14. In the third direction, adjacent first nanosheets 15 and adjacent capacitor trenches 14 can be separated by a first isolation layer 11, and in the second direction, adjacent first nanosheets 15 and adjacent capacitor trenches 14 can be separated by a second isolation layer 13.

[0143] In some embodiments, multiple stacked structures ST arranged along the second direction can form a stacked structure group Z, and a capacitor 20 can be formed based on a stacked structure group Z. In some embodiments, in each stacked structure group Z, multiple first nanosheets 15 are arranged in an array along the second direction and the third direction, and multiple capacitor trenches 14 located on the same side of the multiple first nanosheets 15 are arranged in an array along the second direction and the third direction.

[0144] See you again Figures 14 to 15 In some embodiments, a first capacitor structure 16 is formed, comprising:

[0145] A first electrode layer 161 is formed, which covers the inner wall of the capacitor trench 14 and is electrically connected to the first nanosheet 15. The first electrode layer 161 is a cup-shaped structure extending along a first direction, and the opening of the first electrode layer 161 is away from the first nanosheet 15 that is electrically connected to the first electrode layer 161 along the first direction (e.g., ...). Figure 14 );

[0146] A capacitor dielectric layer 162 is formed, which at least covers the inner wall of the first space S1 defined by the first electrode layer 161; a second electrode layer 163 is formed, which covers the capacitor dielectric layer 162 and at least fills the second space S2 defined by the capacitor dielectric layer 162 (e.g., ...). Figure 15 ).

[0147] The materials of the first electrode layer 161, the capacitor dielectric layer 162, and the second electrode layer 163 are as described above and will not be repeated here.

[0148] See you again Figure 15 In some embodiments, in a capacitor 20, the capacitor dielectric layer 162 of a plurality of first capacitor structures 16 located on the same side of the first nanosheet 15 along the first direction also covers the sidewalls of the first isolation layer 11 and the second isolation layer 13 in the first direction and is connected to each other. The second electrode layer 163 of the plurality of first capacitor structures 16 located on the same side of the first nanosheet 15 along the first direction also fills the second isolation trench T2 and is electrically connected to each other.

[0149] See you again Figures 16 to 17 ,as well as Figures 1 to 2 In some embodiments, a conductive structure 17 is formed, comprising:

[0150] The stacked structure ST and the second isolation layer 13 are etched to form an opening K, which cuts multiple first nanosheets 15 along the second and third directions, respectively. Figures 16 to 17 );

[0151] The opening K is filled with conductive material to form a conductive structure 17 (e.g.) Figure 1 and Figure 2 ).

[0152] In some embodiments, the material of the conductive structure 17 may include one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicides, and metal alloys, such as tungsten.

[0153] In this embodiment, the second electrode layers 163 of the plurality of first capacitor structures 16 located on the same side of the plurality of first nanosheets 15 along the first direction are electrically connected to each other; by setting a conductive structure 17 through the plurality of first nanosheets 15 arranged in an array along the second direction and the third direction, the conductive structure 17 and the plurality of first nanosheets 15 are electrically connected to each other, thereby realizing that the first electrode layers 161 of the plurality of first capacitor structures 16 located on the same side of the plurality of first nanosheets 15 along the first direction are electrically connected to each other.

[0154] Thus, by setting the first nanosheet 15 and the conductive structure 17, multiple first capacitor structures 16 located on the same side of the multiple first nanosheets 15 along the first direction are connected in parallel with each other.

[0155] Meanwhile, in a capacitor 20, by setting a conductive structure 17 and multiple first nanosheets 15 to be electrically connected to each other, multiple first capacitor structures 16 located on one side of the multiple first nanosheets 15 along the first direction are connected in series with multiple first capacitor structures 16 located on the other side of the multiple first nanosheets 15 along the first direction.

[0156] In this embodiment, by electrically connecting the conductive structure 17 and the multiple first nanosheets 15 to each other, multiple first capacitor structures 16 located on the same side of the multiple first nanosheets 15 along the first direction in a capacitor 20 are connected in parallel, thereby increasing the overall capacitance of the capacitor 20. When the external circuit has a sudden large current demand, the larger capacitance can provide more abundant charge. In this way, the voltage drop and overshoot of the power supply can be suppressed more effectively, the power supply voltage can be maintained stably, and the signal crosstalk removal performance of the capacitor 20 can be increased. At the same time, by electrically connecting the conductive structure 17 and the multiple first nanosheets 15 to each other, multiple first capacitor structures 16 located on one side of the multiple first nanosheets 15 along the first direction in a capacitor 20 are connected in series with multiple first capacitor structures 16 located on the other side of the multiple first nanosheets 15 along the first direction, thereby improving the withstand voltage performance of the capacitor 20. In the event of an unexpected and brief overvoltage event in the external circuit, the capacitor 20 is prevented from failing under voltage stress, thereby improving the reliability of the capacitor 20.

[0157] See you again Figures 16 to 17 In some embodiments, forming an opening K includes: etching a stacked structure ST and a second isolation layer 13 to form one or a plurality of first openings K1 spaced apart along a first direction. Each first opening K1 extends continuously along a second direction and a third direction, respectively, and cuts off a plurality of first nanosheets 15 arranged in an array along the second direction and the third direction. See again Figures 1 to 2In some embodiments, filling the opening K with conductive material to form a conductive structure 17 includes: filling the first opening K1 with conductive material to form one or more first sub-parts 171. Figure 16 and Figure 17 The number of first openings K1 shown is 3. Figure 1 and Figure 2 The number of first sub-parts 171 shown is 3. However, it is not limited to this, the number of first openings K1 and first sub-parts 171 can be more or less, such as 1, 2, 4, etc.

[0158] In practical operation, the conductive structure 17 can be used to charge and discharge multiple first capacitor structures 16. In this embodiment, all the first nanosheets 15 of a capacitor 20 are electrically connected through the first sub-part 171 of the plate-like structure, thus enabling all the first capacitor structures 16 of a capacitor 20 to be electrically connected to each other. Simultaneously, the first sub-part 171 with the plate-like structure has lower resistance. The first sub-part 171 with the plate-like structure and the multiple first nanosheets 15 are cross-connected, reducing the overall resistance of the conductive structure 17 and the multiple first nanosheets 15, thereby reducing the connection resistance between the multiple first capacitor structures 16 and improving the response speed of the capacitor 20.

[0159] See you again Figures 16 to 17 In some embodiments, the number of first openings K1 is multiple; forming the openings K further includes: etching a second isolation layer 13 to form a second opening K2 between two adjacent first openings K1, the second opening K2 communicating with the two adjacent first openings K1, and the orthographic projection of the second opening K2 on the surface of the substrate 10 falling between the orthographic projections of two first nanosheets 15 adjacent in the second direction on the surface of the substrate 10. See again Figures 1 to 2 In some embodiments, filling the opening K with conductive material to form a conductive structure 17 further includes filling the second opening K2 with conductive material to form a second sub-part 172, the second sub-part 172 being connected to two adjacent first sub-parts 171.

[0160] In this embodiment of the present disclosure, adjacent first sub-parts 171 can be electrically connected through second sub-parts 172. The first sub-parts 171 and the second sub-parts 172 constitute a mesh-like conductive structure 17. In this way, the resistance of the conductive structure 17 can be further reduced, and the overall resistance of the conductive structure 17 and the plurality of first nanosheets 15 can be further reduced, so as to further improve the response speed of the capacitor 20.

[0161] In some embodiments, the extension length of the second opening K2 in the third direction is equal to the extension length of the first opening K1 in the third direction, and the extension length of the second sub-part 172 in the third direction is equal to the extension length of the first sub-part 171 in the third direction. In this way, the resistance of the conductive structure 17 can be further reduced, and the overall resistance of the conductive structure 17 and the plurality of first nanosheets 15 can be further reduced.

[0162] See you again Figure 14 In some embodiments, after forming the capacitor trench 14 and before forming the first capacitor structure 16, the method further includes performing a doping process on the portion of the first nanosheet 15 exposed by the capacitor trench 14 to form a doped portion 151. After the doped portion 151 and the first capacitor structure 16 are formed, the doped portion 151 may be located at both ends of the first nanosheet 15 along a first direction, and the first capacitor structure 16 is in contact with the doped portion 151; at least one first sub-part 171 is located on the side of the doped portion 151 opposite to the first capacitor structure 16 in contact with it, and is in contact with the doped portion 151. In some embodiments, the first electrode layer 161 of the first capacitor structure 16 is in contact with the doped portion 151, thereby reducing the contact resistance between the first nanosheet 15 and the first capacitor structure 16 and further improving the response speed of the first capacitor structure 16. The doped portion 151 is doped with a dopant, which may be one or more elements such as boron, phosphorus, and arsenic. The doping concentration of the dopant in the doped portion 151 is greater than the doping concentration of the dopant in other portions of the first nanosheet 15 excluding the doped portion 151.

[0163] In some embodiments, the doped portion 151 can also be processed using a semiconductor metallization process. Specifically, a metal layer can be formed on the side of the doped portion 151 facing the first capacitor structure 16, and the metal layer can be annealed to allow the metal elements in the metal layer to diffuse into the doped portion 151, thereby further improving the conductivity of the doped portion 151 and reducing the contact resistance between the first nanosheet 15 and the first capacitor structure 16.

[0164] See you again Figure 1 In some embodiments, after forming capacitor 20, the method may further include forming leads 18, which are located on capacitor 20 and electrically connected to conductive structure 17. In practical applications, capacitor 20 can be charged and discharged via leads 18.

[0165] In some embodiments, the lead 18 can be formed by the following method: First, an insulating layer (not shown) is formed, which covers the capacitor 20; then, the insulating layer is patterned to form a groove (not shown) that exposes the conductive structure 17; then, the lead 18 electrically connected to the conductive structure 17 is formed in the groove.

[0166] like Figures 18 to 23 as well as Figures 3 to 4 As shown, in some embodiments of this disclosure, a plurality of capacitors 20 may be formed on the substrate 10, the plurality of capacitors 20 being arranged along a first direction, and the second electrode layers 163 of two adjacent first capacitor structures 16 belonging to different capacitors 20 being electrically connected. In this way, the plurality of capacitors 20 arranged along the first direction are connected in series, thereby improving the overall withstand voltage performance of the plurality of capacitors 20 and further improving the reliability of the capacitors 20.

[0167] Below, in conjunction with Figures 18 to 23 as well as Figures 3 to 4 The method for forming multiple capacitors 20 will be further explained.

[0168] First, such as Figures 18 to 19 As shown, multiple stacked structures ST can be formed on the substrate 10. These stacked structures ST can be arranged in an array along a first direction and a second direction. The multiple stacked structures ST arranged along the second direction constitute a stacked structure group Z. Each stacked structure group Z has a second isolation trench T2 on both sides. The multiple stacked structure groups Z are arranged along the first direction, and adjacent stacked structure groups Z are separated by the second isolation trench T2. In subsequent processes, multiple capacitors 20 connected in series along the first direction can be formed based on the multiple stacked structure groups Z arranged along the first direction.

[0169] in, Figure 18 The stacked structure ST identified in the middle includes an initial nanosheet 15' and a first isolation layer 11 that are stacked upwards and alternately arranged in a third-party manner.

[0170] Next, as Figure 20 As shown, a portion of the initial nanosheet 15' is removed from the second isolation trench T2 to form a plurality of first nanosheets 15 extending in a first direction and a plurality of capacitor trenches 14 within each stacked structure group Z.

[0171] Next, as Figure 21 As shown, multiple first capacitor structures 16 are formed. Among them, the second electrode layers 163 of two adjacent first capacitor structures 16 belonging to different stacked structure groups Z fill the second isolation trench T2 located between adjacent stacked structure groups Z and are connected to each other, so that the second electrode layers 163 of two adjacent first capacitor structures 16 belonging to different capacitors 20 are electrically connected to each other.

[0172] Next, as Figures 22 to 23 As shown, the stacked structure ST and the second isolation layer 13 are etched to form an opening K, which cuts off multiple first nanosheets 15 along the second direction and the third direction, respectively.

[0173] Next, as Figures 3 to 4As shown, conductive material is filled into the opening K to form a conductive structure 17.

[0174] See you again Figure 3 In some embodiments, the method may further include: forming one or more leads 18 on the capacitors 20 located at both ends of a plurality of capacitors 20 connected in series along a first direction, wherein the leads 18 are electrically connected to the conductive structure 17, thereby charging and discharging the capacitor structure composed of the plurality of capacitors 20 connected in series through the leads 18.

[0175] Figure 3 and Figure 4 The semiconductor structure shown consists of two capacitors 20 connected in series. However, it is not limited to this, for example... Figure 5 As shown, in some embodiments, the three capacitors 20 can also be connected in series. In some embodiments, the upper voltage limit of the structure formed by multiple series-connected capacitors 20 can be between 1.5V and 2.5V, such as 1.5V, 1.8V, 2V, 2.5V, etc. Here, the upper voltage limit refers to the upper voltage limit that the structure formed by multiple series-connected capacitors 20 can safely withstand during design and operation.

[0176] like Figure 6 As shown, in some embodiments, the substrate 10 may further include a storage region 102; the method may further include: forming a storage array 30 in the storage region 102; wherein forming the storage array 30 includes:

[0177] Multiple second nanosheets 21 are formed, which extend along the fourth direction and are arranged in an array along the fifth and third directions; wherein the fourth and fifth directions intersect and are parallel to the surface of the substrate 10.

[0178] A plurality of second capacitor structures 22 are formed, and the plurality of second capacitor structures 22 are located along the fourth direction on at least one side of the second nanosheet 21 and are electrically connected to the second nanosheet 21.

[0179] Multiple word line structures WL are formed, which extend along the fifth direction and are arranged along the third direction. Each word line structure WL covers a portion of the surface of multiple second nanosheets 21 arranged along the fifth direction.

[0180] Multiple bit line structures BL are formed, which extend along the third direction and are arranged along the fifth direction. Each bit line structure BL penetrates multiple second nanosheets 21 arranged along the third direction and is electrically connected to them.

[0181] Here, the fourth and fifth directions can be perpendicular or oblique, the fourth direction can be the same as or different from the first direction, and the fifth direction can be the same as or different from the second direction.

[0182] The storage array 30 located in storage area 102 is used to store data, and the peripheral circuitry located in peripheral area 101 is used to control the storage array 30. The second capacitor structure 22 serves as information storage. In one embodiment, the second capacitor structure 22 may include a lower electrode electrically connected to the second nanosheet 21, a dielectric layer covering the lower electrode, and a common upper electrode covering the dielectric layer. In some embodiments, the lower electrode may have a cup-shaped structure similar to the first electrode layer 161, with the opening of the cup-shaped structure facing the fourth direction. However, this is not a limitation; in other embodiments, the lower electrode may also be columnar and extend along the fourth direction.

[0183] like Figure 6 As shown, in some embodiments, the two ends of the second nanosheet 21 in the fourth direction are each electrically connected to a second capacitor structure 22, and the word line structure WL is located between the bit line structure BL and the second capacitor structure 22 along the second direction. Each word line structure WL can extend along the fifth direction and surround the plurality of second nanosheets 21 arranged along the fifth direction.

[0184] In some embodiments, the formation process of the second nanosheet 21 can be similar to that of the first nanosheet 15, and the first nanosheet 15 and the second nanosheet 21 can be formed in the same step. In some embodiments, the structures of the first capacitor structure 16 and the second capacitor structure 22 can be similar, and their formation processes can be similar, with the first capacitor structure 16 and the second capacitor structure 22 formed in the same step. In some embodiments, the conductive structure 17 and the bit line structure BL can be formed in the same step.

[0185] This simplifies the semiconductor structure manufacturing process, and the mask plates used to form the memory array 30 and the capacitor 20 can be shared, which can save costs.

[0186] The technical features described in the above embodiments can be arbitrarily combined without conflict. Those skilled in the art can change the order of the above-described forming method steps without departing from the protection scope of this disclosure. In the embodiments of this disclosure, some steps can be executed simultaneously or sequentially without conflict.

[0187] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A semiconductor structure, characterized by, include: A substrate and at least one capacitor located on the substrate, the capacitor comprising: Multiple first nanosheets extend along a first direction and are arranged in an array along a second direction and a third direction; wherein the first direction and the second direction intersect and are parallel to the surface of the substrate, and the third direction is perpendicular to the surface of the substrate; Multiple first capacitor structures are respectively located on both sides of the first nanosheet along the first direction and electrically connected to the first nanosheet; A conductive structure penetrates multiple first nanosheets along the second direction and the third direction, respectively, and is electrically connected to multiple first capacitor structures through the first nanosheets; wherein... The conductive structure includes: a plurality of first sub-parts, spaced apart along the first direction, wherein the first sub-parts are plate-like structures extending along the second direction and the third direction, and penetrating through the plurality of first nanosheets along the second direction and the third direction; and a plurality of second sub-parts, located between two adjacent first sub-parts and connected to the two adjacent first sub-parts.

2. The semiconductor structure of claim 1, wherein, The orthographic projection of the second sub-part onto the surface of the substrate falls between the orthographic projections of the two first nanosheets adjacent to each other in the second direction onto the surface of the substrate.

3. The semiconductor structure of claim 1, wherein, The extension length of the second sub-part in the third direction is equal to the extension length of the first sub-part in the third direction.

4. The semiconductor structure of claim 1, wherein, The first nanosheet includes doped portions located at both ends along the first direction, and the first capacitor structure is in contact with the doped portions; At least one of the first sub-parts is located on the side of the doped portion away from the first capacitor structure that is in contact with it, and is in contact with the doped portion.

5. The semiconductor structure of any of claims 1-4, wherein, The first capacitor structure includes: A first electrode layer is electrically connected to the first nanosheet; the first electrode layer is a cup-shaped structure extending along the first direction, and the opening of the first electrode layer is away from the first nanosheet that is electrically connected to the first electrode layer along the first direction. A capacitor dielectric layer that at least covers the inner wall of the first space defined by the first electrode layer; The second electrode layer covers the capacitor dielectric layer and at least fills the second space defined by the capacitor dielectric layer.

6. The semiconductor structure of claim 5, wherein, The number of capacitors is multiple, and the multiple capacitors are arranged along the first direction. The second electrode layers of two adjacent first capacitor structures belonging to different capacitors are electrically connected.

7. The semiconductor structure of any of claims 1-4, wherein, The substrate includes a peripheral region and a storage region, and the capacitor is located in the peripheral region; The semiconductor structure further includes: a memory array located in the memory region; wherein the memory array includes: Multiple second nanosheets extend along a fourth direction and are arranged in an array along a fifth direction and the third direction; wherein the fourth direction and the fifth direction intersect and are parallel to the surface of the substrate; Multiple second capacitor structures are located on at least one side of the second nanosheet along the fourth direction and are electrically connected to the second nanosheet; Multiple word line structures extend along the fifth direction and are arranged along the third direction, each of the word line structures covering a portion of the surface of multiple second nanosheets arranged along the fifth direction; Multiple bitline structures extend along the third direction and are arranged along the fifth direction, each bitline structure penetrating and electrically connecting to the multiple second nanosheets arranged along the third direction.

8. A method of manufacturing a semiconductor structure, characterized by, include: Provide substrate; At least one capacitor is formed on the substrate; wherein forming the capacitor includes: A plurality of first nanosheets are formed on the substrate, the plurality of first nanosheets extending along a first direction and arranged in an array along a second direction and a third direction; wherein the first direction and the second direction intersect and are parallel to the surface of the substrate, and the third direction is perpendicular to the surface of the substrate; Multiple first capacitor structures are formed, and the multiple first capacitor structures are respectively located on both sides of the first nanosheet along the first direction and electrically connected to the first nanosheet. A conductive structure is formed, wherein the conductive structure penetrates multiple first nanosheets along the second direction and the third direction respectively, and is electrically connected to multiple first capacitor structures through the first nanosheets; wherein the conductive structure includes: multiple first sub-parts, arranged at intervals along the first direction, the first sub-parts being plate-like structures extending along the second direction and the third direction, and penetrating multiple first nanosheets along the second direction and the third direction; and multiple second sub-parts, located between two adjacent first sub-parts, and connected to two adjacent first sub-parts.

9. The manufacturing method according to claim 8, wherein Forming a plurality of the first nanosheets and a plurality of the first capacitor structures on the substrate includes: An initial stacked structure is formed on the substrate, the initial stacked structure comprising a first isolation layer and a semiconductor layer alternately stacked along the third direction; The initial stacked structure is graphically represented to form a plurality of stacked structures extending along the first direction and arranged along the second direction, and a first isolation trench located between adjacent stacked structures in the second direction; the semiconductor layer in the stacked structure is defined as an initial nanosheet; A second isolation layer is filled into the first isolation trench; A portion of the initial nanosheets is removed to form a capacitor groove extending along the first direction, and the remaining initial nanosheets constitute the first nanosheet, with the capacitor groove located on both sides of the first nanosheet along the first direction. The first capacitor structure is formed within the capacitor slot.

10. The manufacturing method according to claim 9, wherein Forming the conductive structure includes: The stacked structure and the second isolation layer are etched to form openings that cut through a plurality of the first nanosheets along the second direction and the third direction, respectively. The opening is filled with conductive material to form the conductive structure.

11. The manufacturing method according to claim 10, wherein Forming the opening includes: The stacked structure and the second isolation layer are etched to form a plurality of first openings spaced apart along the first direction, each of the first openings extending continuously along the second direction and the third direction, and cutting off a plurality of first nanosheets arranged in an array along the second direction and the third direction. Filling the opening with conductive material to form the conductive structure includes: filling the first opening with the conductive material to form a plurality of first sub-parts.

12. The manufacturing method according to claim 11, wherein Forming the opening further includes: The second isolation layer is etched to form a second opening between two adjacent first openings, the second opening communicating with the two adjacent first openings, and the orthographic projection of the second opening on the surface of the substrate falling between the orthographic projections of two adjacent first nanosheets on the surface of the substrate in the second direction. The process of filling the opening with conductive material to form the conductive structure further includes: filling the second opening with the conductive material to form a second sub-part, the second sub-part being connected to two adjacent first sub-parts.

13. The manufacturing method according to claim 9, wherein After forming the capacitor trench and before forming the first capacitor structure, the method further includes performing a doping process on the portion of the first nanosheet exposed by the capacitor trench to form a doped portion.

14. The manufacturing method according to any one of claims 9 to 13, characterized in that, Forming the first capacitor structure includes: A first electrode layer is formed, which covers the inner wall of the capacitor trench and is electrically connected to the first nanosheet; the first electrode layer is a cup-shaped structure extending along the first direction, and the opening of the first electrode layer is away from the first nanosheet that is electrically connected to the first electrode layer along the first direction. A capacitor dielectric layer is formed, the capacitor dielectric layer at least covering the inner wall of the first space defined by the first electrode layer; A second electrode layer is formed, which covers the capacitor dielectric layer and at least fills the second space defined by the capacitor dielectric layer.

15. The manufacturing method according to any one of claims 8 to 13, characterized in that, The substrate includes a peripheral region and a storage region, and the capacitor is located in the peripheral region; The method further includes: forming a storage array in the storage area; wherein forming the storage array includes: Multiple second nanosheets are formed, which extend along a fourth direction and are arranged in an array along a fifth direction and the third direction; wherein the fourth direction and the fifth direction intersect and are parallel to the surface of the substrate; Multiple second capacitor structures are formed, and the multiple second capacitor structures are located on at least one side of the second nanosheet along the fourth direction and are electrically connected to the second nanosheet; Multiple word line structures are formed, the multiple word line structures extend along the fifth direction and are arranged along the third direction, and each word line structure covers a portion of the surface of the multiple second nanosheets arranged along the fifth direction; Multiple bitline structures are formed, the multiple bitline structures extend along the third direction and are arranged along the fifth direction, and each bitline structure penetrates and is electrically connected to the multiple second nanosheets arranged along the third direction.

16. The manufacturing method according to claim 15, wherein The first nanosheet and the second nanosheet are formed in the same step; and / or, The first capacitor structure and the second capacitor structure are formed in the same step; and / or, The conductive structure and the bit line structure are formed in the same step.

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