A method for manufacturing an SGT transistor with variable capacitance and an SGT transistor

Abstract

The application relates to a semiconductor technology and discloses a manufacturing method of a variable-capacitance SGT transistor and the SGT transistor, which comprises the following steps: after a dielectric layer is manufactured on the upper surface of a main body, corresponding source contact holes and gate contact holes are respectively manufactured at different layout positions of the main body; a front metal layer is manufactured on the upper surface of the main body, and the front metal layer is etched to form a source electrode connected with the source contact holes, a main gate electrode connected with the main gate contact holes and a sub gate electrode connected with the sub gate contact holes; a back metal layer is manufactured on the back surface of the main body as a drain electrode, so that the SGT transistor is obtained; when the main gate electrode and the sub gate electrode are connected and the sub gate electrode is disconnected with the source electrode, the SGT transistor has a first capacitance value; when the main gate electrode is disconnected with the sub gate electrode and the sub gate electrode is connected with the source electrode, the SGT transistor has a second capacitance value; and the first capacitance value is greater than the second capacitance value. The application aims to realize the manufacturing of the variable-capacitance SGT transistor, so as to adapt to the requirements of different application scenarios on input capacitance.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a method for fabricating a variable-capacitance SGT transistor and the variable-capacitance SGT transistor. Background Technology

[0002] The input capacitance (Ciss) requirements for SGT transistors (Shielded Gate Trench Transistors) vary depending on the application. For example, the input capacitance requirement is not very high in motor drive applications, while in synchronous rectification applications, the input capacitance needs to be as small as possible to reduce switching losses and suppress power supply spikes. Currently, most SGT transistors on the market have fixed input capacitance values, making it difficult to simultaneously meet the diverse input capacitance requirements of different application scenarios.

[0003] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention

[0004] The main objective of this application is to provide a method for fabricating a variable capacitance SGT transistor and a variable capacitance SGT transistor, aiming to realize the fabrication of a variable capacitance SGT transistor so that the SGT transistor can switch between different capacitance values ​​to adapt to the input capacitance requirements of different application scenarios.

[0005] To achieve the above objectives, this application provides a method for fabricating a variable-capacitance SGT transistor, comprising the following steps:

[0006] A substrate with multiple trenches covered by an oxide layer is provided; wherein each trench contains a first polysilicon and a second polysilicon disposed on the first polysilicon, the first polysilicon and the second polysilicon are separated by an oxide layer, and the first polysilicon, the second polysilicon and the inner wall of the trench are separated by an oxide layer.

[0007] First and second doped regions of different doping types are formed on the adjacent sides of each trench;

[0008] After fabricating a dielectric layer on the upper surface of the main body, corresponding source contact holes and gate contact holes are fabricated at different layout positions of the main body; wherein, the source contact holes are used to expose the first doped region; the gate contact holes are used to expose the second polysilicon, and the gate contact holes are further divided into main gate contact holes and sub-gate contact holes, which are located above different trenches.

[0009] A front metal layer is fabricated on the upper surface of the main body, and the front metal layer is etched to form the source electrode that connects to the source contact hole, the main gate electrode that connects to the main gate contact hole, and the sub-gate electrode that connects to the sub-gate contact hole.

[0010] A back metal layer is fabricated on the back side of the main body as the drain to obtain an SGT transistor; wherein, when the main gate and the sub-gate are connected and the sub-gate is disconnected from the source, the SGT transistor has a first capacitance value; when the main gate and the sub-gate are disconnected and the sub-gate is connected to the source, the SGT transistor has a second capacitance value; the first capacitance value is greater than the second capacitance value.

[0011] Optionally, the method for fabricating the variable-capacitance SGT transistor further includes:

[0012] The groove located below the main gate contact hole is designated as the first groove, and the remaining grooves other than the first groove are designated as the second groove located below the secondary gate contact hole.

[0013] The larger the ratio of the first trench to the total number of trenches, the larger the ratio of the second capacitance value to the first capacitance value.

[0014] Optionally, after the step of fabricating a back metal layer as a drain on the back side of the main body to obtain the SGT transistor, the method further includes:

[0015] When bonding wires to an SGT transistor package, the sub-gate is connected to either the main gate or the source via wire bonding to select the capacitance value of the SGT transistor.

[0016] Optionally, the step of providing a substrate with a plurality of trenches covered by an oxide layer, wherein each trench contains a first polysilicon and a second polysilicon disposed on the first polysilicon, the first polysilicon and the second polysilicon are separated by an oxide layer, and the first polysilicon, the second polysilicon and the inner wall of the trench are separated by an oxide layer, includes:

[0017] After forming the first oxide layer on the substrate, the first oxide layer and part of the substrate are etched to form multiple trenches;

[0018] After growing a second oxide layer on the inner surface of each trench, the first polysilicon is filled in, and the top of the first polysilicon is lower than the top of the trench.

[0019] Remove the first oxide layer and remove the top portion of the second oxide layer, so that the top portion of the first polysilicon protrudes from the second oxide layer;

[0020] A third oxide layer is grown on the upper surface of the substrate, and a protruding structure is formed on the top portion of the first polysilicon encased in the third oxide layer.

[0021] A second polysilicon layer is filled on top of the third oxide layer in each trench, with the top of the second polysilicon layer lower than the top of the trench.

[0022] Optionally, the method for fabricating the variable-capacitance SGT transistor further includes:

[0023] In the process of fabricating the first polysilicon, a 7000~10000 Å polysilicon is deposited using a thin film process, and the polysilicon is etched to remove the polysilicon above the trench and to make the top of the polysilicon in each trench lower than the top of the trench, thus obtaining the first polysilicon.

[0024] And / or, in the process of fabricating the second polysilicon, a 5000~8000 Å polysilicon is deposited using a thin film process, and the polysilicon is etched to remove the polysilicon above the trench, and to make the top of the polysilicon in each trench lower than the top of the trench, thereby obtaining the second polysilicon.

[0025] Optionally, the depth of the trench is 5~6μm;

[0026] And / or, the height difference between the top of the first polysilicon and the top of the trench is 1.0~1.4μm;

[0027] And / or, the height difference between the top of the second polysilicon and the top of the trench is 0.1um to 0.18um.

[0028] Optionally, the method for fabricating the variable-capacitance SGT transistor further includes:

[0029] When the corresponding source contact holes and gate contact holes are fabricated at different layout positions of the main body, shielding gate contact holes are also fabricated at the corresponding positions; wherein, the shielding gate contact holes are used to expose the first polysilicon.

[0030] When manufacturing the source electrode, the source electrode is also connected to the shielding gate contact hole.

[0031] Optionally, after the step of fabricating a dielectric layer on the upper surface of the body and then fabricating corresponding source contact holes and gate contact holes at different layout positions of the body, the method further includes:

[0032] After injecting the same type of dopant into the upper surface of the first doped region within the source contact hole, a rapid thermal annealing process is performed to form the corresponding doped contact region.

[0033] Optionally, the substrate is an N-type silicon substrate; the step of forming a first doped region and a second doped region of different doping types stacked on the adjacent sides of each trench includes:

[0034] P+ ions are implanted into the substrate surface adjacent to each trench using an ion implantation process. After furnace tube annealing, a P-type well region is formed, which serves as the first doped region.

[0035] The active region is exposed using photolithography. N+ ions are implanted above each P-type well region, and after annealing in a furnace tube, an N-type source region is formed, which serves as the second doped region.

[0036] To achieve the above objectives, this application also provides a variable capacitance SGT transistor, which is fabricated using the variable capacitance SGT transistor fabrication method described above.

[0037] The present application provides a method for fabricating a variable-capacitance SGT transistor and a variable-capacitance SGT transistor. By setting a main gate and a sub-gate that connect polysilicon in different trenches, and by changing the connection between the main gate, the sub-gate and the source, the SGT transistor can switch between different capacitance values, thereby obtaining a variable-capacitance SGT transistor to flexibly adapt to the input capacitance requirements of the SGT transistor in different application scenarios.

[0038] Furthermore, compared to existing SGT transistor structures, the process flow of this SGT transistor structure is compatible with existing processes, enabling the addition of variable capacitors to the same chip. When the SGT transistor is applied to different fields, the capacitance value can be adjusted during the packaging wire bonding process, which can reduce R&D and production costs, better match the application, and achieve the goal of multiple uses for a single chip, making it very flexible and convenient. Attached Figure Description

[0039] Figure 1 This is a schematic diagram of the fabrication steps of a variable capacitor SGT transistor in one embodiment of this application;

[0040] Figure 2 This is a schematic diagram of the fabrication process of a variable capacitor SGT transistor in one embodiment of this application;

[0041] Figure 3 This is a schematic diagram of another fabrication process of the variable capacitor SGT transistor in one embodiment of this application;

[0042] Figure 4 This is a schematic diagram of another fabrication process of a variable capacitor SGT transistor in one embodiment of this application;

[0043] Figure 5 This is a top view showing the device layout of a variable-capacitance SGT transistor in one embodiment of this application;

[0044] Figure 6 This is a top view of the device layout of a variable capacitor SGT transistor without a source in one embodiment of this application;

[0045] Figure 7 In one embodiment of this application, the SGT transistor is... Figure 5 Structural cross-section diagram at the location of section AA;

[0046] Figure 8 In one embodiment of this application, the SGT transistor is... Figure 5Structural cross-section diagram at the location of section AB;

[0047] Figure 9 In one embodiment of this application, the SGT transistor is... Figure 5 Structural cross-section diagram at the AC section location;

[0048] Figure 10 In one embodiment of this application, the SGT transistor is... Figure 5 Structural cross-section view at the location of section AD;

[0049] Figure 11 This is a schematic diagram of the wire bonding method of a variable capacitor SGT transistor package in one embodiment of this application;

[0050] Figure 12 This is a schematic diagram of another package bonding method for a variable capacitor SGT transistor in one embodiment of this application.

[0051] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0052] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0053] Furthermore, descriptions using terms such as "first" and "second" in this application are for descriptive purposes only (e.g., to distinguish identical or similar features) and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, technical solutions from different embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If a combination of technical solutions is contradictory or impossible to implement, such a combination should be considered nonexistent and not within the scope of protection claimed in this application.

[0054] Reference Figure 1 In one embodiment, the method for fabricating a variable-capacitance SGT transistor includes:

[0055] Step S10: Provide a substrate with multiple trenches covered by an oxide layer; wherein each trench contains a first polysilicon and a second polysilicon disposed on the first polysilicon, the first polysilicon and the second polysilicon are separated by an oxide layer, and the first polysilicon, the second polysilicon and the inner wall of the trench are separated by an oxide layer.

[0056] Step S20: Form a first doped region and a second doped region with different doping types stacked on the adjacent sides of each trench;

[0057] Step S30: After fabricating a dielectric layer on the upper surface of the main body, corresponding source contact holes and gate contact holes are fabricated at different layout positions of the main body; wherein, the source contact holes are used to expose the first doped region; the gate contact holes are used to expose the second polysilicon, and the gate contact holes are further divided into main gate contact holes and sub-gate contact holes, which are located above different trenches.

[0058] Step S40: A front metal layer is fabricated on the upper surface of the main body, and the front metal layer is etched to form the source electrode that connects to the source contact hole, the main gate electrode that connects to the main gate contact hole, and the sub-gate electrode that connects to the sub-gate contact hole, respectively.

[0059] Step S50: A back metal layer is fabricated on the back side of the main body as the drain to obtain an SGT transistor; wherein, when the main gate and the sub-gate are connected and the sub-gate is disconnected from the source, the SGT transistor has a first capacitance value; when the main gate and the sub-gate are disconnected and the sub-gate is connected to the source, the SGT transistor has a second capacitance value; the first capacitance value is greater than the second capacitance value.

[0060] In this embodiment, as described in step S10, refer to Figure 2 A suitable semiconductor substrate (such as a silicon substrate) is selected, and an oxide layer (such as silicon dioxide) is grown on the substrate surface. The oxide layer can be formed through processes such as thermal oxidation, and its function is to provide protection and masking during subsequent etching.

[0061] Photoresist is coated onto the oxide layer surface. Exposure and development are performed using a photomask to form openings in the photoresist corresponding to the desired trench pattern. Photolithography is then used to etch the oxide layer and a portion of the substrate through these openings. After etching, the photoresist is removed, resulting in multiple trenches.

[0062] Then, using methods such as thermal oxidation or chemical vapor deposition (CVD), an oxide layer is further grown on the inner surface of each trench, so that the oxide layer serves as an insulating layer between the shielding gate and the substrate.

[0063] A first polysilicon layer is filled on top of an oxide layer within the trench using a thin-film deposition process, with the top of the first polysilicon layer lower than the top of the trench. This first polysilicon layer will serve as a shielding gate polysilicon, acting as a shield for the electric field in the transistor.

[0064] Optionally, an oxide layer may be grown on the surface of the first polysilicon as an isolation layer between the first polysilicon and the subsequently filled second polysilicon.

[0065] Optionally, a second polysilicon layer is filled into each trench using a thin-film deposition process, with the top of the second polysilicon layer lower than the top of the trench. In this case, an oxide layer separates the first and second polysilicon layers, and an oxide layer also separates the first and second polysilicon layers from the inner wall of the trench.

[0066] As described in step S20, refer to Figure 3 Photoresist is coated on the substrate surface, and the area to be doped (i.e., the top part of the substrate on each side of each trench or between each trench) is defined by photolithography.

[0067] Ion implantation is used to implant specific types of impurity ions into a defined region to form the first doped region. For example, if a P-type doped region is required, boron (B) ions can be implanted; if an N-type doped region is required, phosphorus (P) or arsenic (As) ions can be implanted.

[0068] Ion implantation is performed again on top of the first doped region, implanting impurity ions of a different type than those in the first doped region, forming a first doped region and a second doped region with different doping types stacked on top of each other.

[0069] Optionally, after ion implantation, annealing is performed to activate the implanted impurities and repair lattice damage caused by ion implantation.

[0070] As described in step S30, a dielectric layer is fabricated on the upper surface of the host (including the oxide layer and the second polysilicon) using methods such as chemical vapor deposition. The dielectric layer can be an insulating material such as silicon dioxide or silicon nitride, used to further isolate different conductive layers.

[0071] Optionally, a dielectric layer of 7000~10000 Å can be deposited using thin film processes.

[0072] Optionally, photoresist is coated on the surface of the dielectric layer, and exposure and development are performed using a photomask to form source contact holes and gate contact holes patterns on the photoresist.

[0073] Optional, refer to Figure 4 The etching process is used to sequentially etch the dielectric layer, oxide layer and the second doped region on the top of the substrate through the photoresist opening to form source contact holes for exposing the first doped region.

[0074] Similarly, using an etching process, the dielectric layer above different trenches is etched through photoresist openings to form gate contact holes, which are used to expose the second polysilicon. Furthermore, the gate contact holes are divided into main gate contact holes and sub-gate contact holes, which are located above different trenches.

[0075] Among them, reference Figure 5 and Figure 6 (To facilitate the display of the layout of related components, Figure 6 (Source not shown) After screening the trenches to which the main gate contact hole and the sub-gate contact hole belong, the opening positions of the main gate contact hole and the sub-gate contact hole can be determined according to the expected positions of the main gate and the sub-gate in the future.

[0076] Optionally, every two grooves are selected as the first groove, and the two grooves between two adjacent first grooves are selected as the second groove; wherein, the main grid contact hole is located above the second groove, and the auxiliary grid contact hole is located above the first groove.

[0077] Optionally, two sub-grid contact holes can be provided in the same first trench; and two main grid contact holes can be provided in the same second trench.

[0078] As described in step S40, a front metal layer is fabricated on the upper surface of the substrate using methods such as physical vapor deposition (PVD) and chemical vapor deposition (CVD). The metal material can be a metal with good electrical conductivity, such as aluminum or copper.

[0079] Optionally, titanium / titanium nitride / tungsten / aluminum layers can be deposited sequentially using CVD or PVD thin film processes as the front metal layer.

[0080] Reference Figure 5 , Figures 7 to 10 The photoresist pattern is transferred to the metal layer using an etching process (such as wet etching or dry etching), and the unwanted metal parts are removed to form the source electrode that connects to the source contact hole, the main gate electrode that connects to the main gate contact hole, and the sub-gate electrode that connects to the sub-gate contact hole.

[0081] Optionally, regarding the layout of the main gate contact holes, after each main gate contact hole has been filled with the corresponding metal layer, during the etching process of the metal layer, the metal strip located above the metal layer in each main gate contact hole is retained as the main gate, and the main gate is separated from other metal layers, thus creating a main gate that is connected to each main gate contact hole through metal filling; similarly, regarding the layout of the secondary gate contact holes, after each secondary gate contact hole has been filled with the corresponding metal layer, during the etching process of the metal layer, the metal strip located above the metal layer in each secondary gate contact hole is retained as the secondary gate, and the secondary gate is separated from other metal layers, thus creating a secondary gate that is connected to each secondary gate contact hole through metal filling; after the main gate and secondary gate are fabricated, the remaining metal layer can be used to fabricate the source.

[0082] In this way, the front metal layer, which was originally formed as a single piece through metal deposition, can be divided into the source, main gate, and sub-gate.

[0083] As described in step S50, the back side of the main body is thinned, ground, and polished to ensure that the back side is flat, which facilitates the subsequent production of the metal layer.

[0084] A metal layer is deposited on the back side of the substrate using PVD or CVD methods to serve as the drain. The metal material can be the same as that used for the front side metal layer.

[0085] The SGT transistor fabricated in this way has a first capacitance value when the main gate and the sub-gate are connected and the sub-gate is disconnected from the source; and a second capacitance value when the main gate and the sub-gate are disconnected and the sub-gate is connected to the source, with the first capacitance value being greater than the second capacitance value.

[0086] That is, the main gate serves as the gate control terminal of the transistor, while the secondary gate serves as the variable gate control terminal. (See reference...) Figure 11 When the sub-gate is connected to the main gate (while the sub-gate is disconnected from the source), it is equivalent to all cells on the chip being normally open, with a cell utilization rate of 100% (equivalent to the conventional SGT transistor, where all second polysilicon terminals are connected and used as gate control terminals), and at this time, it has the highest first capacitance value; refer to Figure 12 When the sub-gate is disconnected from the main gate control terminal and connected to the source (i.e., connected to the source region of the chip), it is equivalent to a portion of the chip cells being "short-circuited," resulting in a cell utilization rate of less than 100%. In this case, the chip's input capacitance is a second capacitance value, less than the first capacitance value. This effectively reduces the chip's input capacitance, and the magnitude of the reduction is roughly consistent with the proportion of "short-circuited" cells. Additionally, the on-resistance will increase slightly; a reasonable trade-off must be considered depending on the application.

[0087] Taking a 100V N-type SGT transistor as an example, its on-resistance reference value is 3.3 milliohms. When 50% of the unit cell on this chip is "grounded" (even if the main gate and sub-gate are disconnected and the sub-gate is connected to the source), the on-resistance rises to approximately 4.15 milliohms (an increase of about 25%), but the input capacitance decreases to about 50% of its original value. This allows for better compatibility with applications that do not have very high requirements for on-resistance but have very strict requirements for input capacitance, enabling wide-range adjustment of the input capacitance on the same chip (by setting the proportion of the grounded portion of the unit cell according to actual needs), expanding the application scenarios and significantly reducing production costs.

[0088] Optionally, depending on the voltage platform, such as 30V / 40V / 60V SGT products, by grounding a certain proportion of the chip cells using the above design method (even if the main gate and sub-gate are disconnected, and the sub-gate is connected to the source), the increase in on-resistance will be further reduced (30V~60V SGT products are mainly low-turn-on), thereby achieving a more cost-effective variable capacitor regulation effect. In other words, the lower the voltage platform of the product, the less the increase in on-resistance will occur after grounding the same proportion of cells.

[0089] In one embodiment, a main gate and a sub-gate of polysilicon in different trenches are provided, and the connection between the main gate, the sub-gate and the source is changed to enable the SGT transistor to switch between different capacitance values, thereby obtaining a variable capacitance SGT transistor to flexibly adapt to the input capacitance requirements of the SGT transistor in different application scenarios.

[0090] Furthermore, compared to existing SGT transistor structures, the process flow of this SGT transistor structure is compatible with existing processes, enabling the addition of variable capacitors to the same chip. When the SGT transistor is applied to different fields, the capacitance value can be adjusted during the packaging wire bonding process, which can reduce R&D and production costs, better match the application, and achieve the goal of multiple uses for a single chip, making it very flexible and convenient.

[0091] In one embodiment, based on the above embodiments, the method for fabricating the variable capacitor SGT transistor further includes:

[0092] The groove located below the main gate contact hole is designated as the first groove, and the remaining grooves other than the first groove are designated as the second groove located below the secondary gate contact hole.

[0093] The larger the ratio of the first trench to the total number of trenches, the larger the ratio of the second capacitance value to the first capacitance value.

[0094] In this embodiment, after the source contact hole and gate contact hole are fabricated, the gate contact hole is divided into a main gate contact hole and a secondary gate contact hole, and the main gate contact hole and the secondary gate contact hole are located above different trenches. At this time, the trench located below the main gate contact hole is defined as the first trench, and the remaining trenches other than the first trench are defined as the second trench, which is located below the secondary gate contact hole.

[0095] This establishes a specific relationship between the ratio of the number of first trenches to the total number of trenches and the capacitance value. Specifically, the larger the ratio of the number of first trenches to the total number of trenches, the larger the ratio of the second capacitance value to the first capacitance value.

[0096] From a physics perspective, the capacitance of an SGT transistor is closely related to the trench layout and connection method. Different connection states of the main gate and sub-gate will cause the transistor to exhibit different capacitance values, namely, the first capacitance value (when the main gate and sub-gate are connected, and the sub-gate is disconnected from the source) and the second capacitance value (when the main gate and sub-gate are disconnected, and the sub-gate is connected to the source). Since the first and second trenches are connected to the main gate contact hole and the sub-gate contact hole respectively, their contributions to capacitance differ under different connection states. When the number of first trenches increases, it means that the portion connected to the main gate accounts for a larger proportion of the overall structure. When the main gate and sub-gate are disconnected, and the sub-gate is connected to the source, the influence of the first trenches on the overall capacitance characteristics of the transistor is relatively reduced, resulting in a larger ratio of the second capacitance value to the first capacitance value.

[0097] In practical applications, the variable capacitance characteristics of SGT transistors can be precisely controlled by adjusting the ratio of the number of first and second trenches, according to specific circuit requirements. For example, if a larger capacitance variation range is needed, the ratio of the first trench to the total number of trenches can be appropriately reduced; if a relatively small change in capacitance value under different connection states is desired, the ratio of the first trench to the total number of trenches can be increased. This helps improve the adaptability and performance of SGT transistors in various circuits.

[0098] In one embodiment, based on the above embodiment, after the step of fabricating a back metal layer as a drain on the back side of the main body to obtain the SGT transistor, the method further includes:

[0099] When bonding wires to an SGT transistor package, the sub-gate is connected to either the main gate or the source via wire bonding to select the capacitance value of the SGT transistor.

[0100] In this embodiment, wire bonding is a key step in the semiconductor device manufacturing process. It is mainly responsible for electrically connecting the internal electrodes of the chip to the external pins to realize signal transmission and power supply between the chip and the external circuit.

[0101] During the wire bonding process, wire bonding is used to connect the sub-gate to the main gate or the source. Based on previous manufacturing methods, when the main gate and sub-gate are connected and the sub-gate is disconnected from the source, the SGT transistor has a first capacitance value; when the main gate and sub-gate are disconnected and the sub-gate is connected to the source, the SGT transistor has a second capacitance value, and the first capacitance value is greater than the second capacitance value.

[0102] Optional, refer to Figure 11 When the SGT transistor needs to exhibit its first capacitance value, the sub-gate is connected to the main gate via a bonding wire. This connection method allows the main gate and sub-gate to be electrically connected, while the sub-gate is disconnected from the source, thus enabling the transistor to operate with its first capacitance value.

[0103] Optional, refer to Figure 12 To make the SGT transistor exhibit a second capacitance value, the sub-gate is connected to the source using a bonding wire. At this time, the main gate and the sub-gate are disconnected, and the sub-gate is connected to the source, and the transistor enters an operating state with a second capacitance value.

[0104] This method of selecting capacitance values ​​through wire bonding during the packaging process brings great flexibility to the practical applications of SGT transistors. Different circuit applications may require different capacitance values ​​to meet specific performance requirements. For example, in circuits that need to switch capacitance characteristics according to different operating modes, the appropriate wire bonding method can be selected during the packaging stage based on specific needs, without requiring large-scale adjustments to the transistor manufacturing process. This not only improves production efficiency and reduces costs, but also allows SGT transistors to better adapt to diverse market demands.

[0105] In one embodiment, based on the above embodiments, the step of providing a substrate with a plurality of trenches covered by an oxide layer, wherein each trench contains a first polysilicon and a second polysilicon disposed on the first polysilicon, the first polysilicon and the second polysilicon are separated by an oxide layer, and the first polysilicon, the second polysilicon and the inner wall of the trench are separated by an oxide layer, includes:

[0106] After forming the first oxide layer on the substrate, the first oxide layer and part of the substrate are etched to form multiple trenches;

[0107] After growing a second oxide layer on the inner surface of each trench, the first polysilicon is filled in, and the top of the first polysilicon is lower than the top of the trench.

[0108] Remove the first oxide layer and remove the top portion of the second oxide layer, so that the top portion of the first polysilicon protrudes from the second oxide layer;

[0109] A third oxide layer is grown on the upper surface of the substrate, and a protruding structure is formed on the top portion of the first polysilicon encased in the third oxide layer.

[0110] A second polysilicon layer is filled on top of the third oxide layer in each trench, with the top of the second polysilicon layer lower than the top of the trench.

[0111] In this embodiment, a suitable substrate material is first selected, typically a semiconductor material such as silicon (Si). The substrate is placed in an oxidation furnace, and oxidizing gases such as oxygen (O2) or water vapor (H2O) are introduced at a high temperature. The oxygen or water vapor reacts chemically with the silicon atoms on the substrate surface to generate silicon dioxide (SiO2), thereby forming a uniform first oxide layer on the upper surface of the substrate. The function of this first oxide layer is to act as a mask layer during subsequent etching processes, protecting certain areas of the substrate from etching.

[0112] Optionally, a first oxide layer of 1500~5000 Å is deposited on the upper surface of the substrate.

[0113] The process employs photolithography, where photoresist is coated onto a first oxide layer. The photoresist is then exposed using a photomask and, after development, forms openings in the areas requiring etching. Next, using an etching process (such as reactive ion etching) with the photoresist as a mask, the first oxide layer is etched away, removing the openings and exposing the underlying substrate. This is followed by further etching of the exposed substrate, creating multiple trenches. The size, shape, and spacing of these trenches are precisely controlled according to the specific SGT transistor design requirements.

[0114] Optionally, the depth of the trench is 5~6μm to ensure that the space inside the trench is sufficient to accommodate the structure to be fabricated later.

[0115] Optionally, the etched trench substrate is placed in an oxidation furnace for further oxidation. On the inner surface of each trench (including the trench sidewalls and bottom), silicon atoms react with the oxidizing gas to grow a second oxide layer. This second oxide layer acts as an insulating layer, preventing the subsequently filled first polysilicon from directly contacting the substrate on the inner wall of the trench, thus avoiding problems such as leakage.

[0116] The second oxide layer is a thick oxide layer with a thickness ranging from 4000 to 6000 Å.

[0117] Optionally, a method such as chemical vapor deposition can be used to introduce silicon-containing gases such as silane (SiH4) into the reaction chamber. Under high temperature conditions, the silane decomposes, and silicon atoms are deposited in the trenches to fill the trenches for polycrystalline silicon filling.

[0118] Optionally, during the fabrication of the first polysilicon, a 7000-10000 Å polysilicon layer is deposited using a thin-film process, and the polysilicon is etched to remove the polysilicon above the trenches and to ensure that the top of the polysilicon within each trench is lower than the top of the trench, thus obtaining the first polysilicon, which serves as the shielding gate polysilicon. The height difference between the top of the first polysilicon and the top of the trenches must satisfy the space required for the subsequent fabrication of the second polysilicon.

[0119] Optionally, a pattern of the shielding gate polysilicon (first polysilicon) is exposed using a photolithography process, and the first polysilicon is etched using a dry etching process so that the top of the first polysilicon is located below the top of the substrate, with the height difference controlled at 1.0~1.4μm.

[0120] Optionally, a suitable etchant (such as hydrofluoric acid solution) can be used to wet-etch the first oxide layer. Because the first oxide layer differs in material properties from the second oxide layer and the substrate, the first oxide layer is selectively removed during the etching process, while the second oxide layer and the substrate remain largely unaffected.

[0121] Optionally, the same etching process is used to etch the top portion of the second oxide layer. By precisely controlling the etching time and etching parameters, the top portion of the first polysilicon protrudes from the second oxide layer (i.e., the oxide layer near and above the top of the polysilicon is removed).

[0122] The substrate, after the above treatment, is placed in an oxidation furnace for oxidation. A third oxide layer is grown on the upper surface of the substrate (including the protruding top portion of the first polysilicon and the portion of the trench where the oxide layer has been removed). The third oxide layer serves as a gate oxide layer and covers the top portion of the first polysilicon, the sidewalls of the trench above the second oxide layer, and the upper surface of the substrate where there are no trenches.

[0123] Optionally, the third oxide layer is a thin oxide layer with a thickness of 500~1000 Å.

[0124] Because the top portion of the first polysilicon layer protrudes, a raised structure forms on the top portion of the first polysilicon layer encased by the third oxide layer during the growth of the third oxide layer. This raised structure plays an important role in improving the electrical performance of the SGT transistor.

[0125] A second polycrystalline silicon layer was filled on top of the third oxide layer in each trench using methods such as chemical vapor deposition.

[0126] Optionally, in the process of fabricating the second polysilicon, a 5000~8000 Å polysilicon is deposited using a thin film process, and the polysilicon is etched to remove the polysilicon above the trench, and the top of the polysilicon in each trench is lower than the top of the trench to obtain the second polysilicon as the gate polysilicon.

[0127] Optionally, the height difference between the top of the second polysilicon and the top of the trench is 0.1µm to 0.18µm.

[0128] In this way, a multilayer structure consisting of a first polysilicon layer, a second oxide layer, a third oxide layer, and a second polysilicon layer is formed in the trench, laying the foundation for the further fabrication of SGT transistors.

[0129] In this design, the first polysilicon serves as the shielding gate polysilicon, and the second polysilicon serves as the gate polysilicon. When the second polysilicon is fabricated on top of a protrusion formed on the first polysilicon encased in a third oxide layer, a nested structure of the second polysilicon surrounding the protrusion is formed. This unique structure, where the second polysilicon nests around the protrusion on top of the first polysilicon encased in a third oxide layer, offers several improvements to the electrical performance of the SGT transistor.

[0130] (1) In the SGT transistor, the first polysilicon acts as the shielding gate polysilicon, serving to shield the electric field. When the second polysilicon is nested around the raised structure of the first polysilicon, it is equivalent to increasing the effectiveness of the shielding layer. The shielding gate can effectively block the electric field coupling path between the gate and the drain, thus significantly reducing the gate-drain capacitance. The reduction in gate-drain capacitance can reduce the charging and discharging time of the transistor during the switching process, improve the switching speed, and reduce switching losses. This is particularly important for circuits used in high-frequency applications, such as switching power supplies and RF power amplifiers, as it can improve the efficiency and performance of the circuit.

[0131] (2) The second polysilicon serves as the gate polysilicon, used to control the conduction and cutoff of the channel. By nesting and wrapping the bump structure around the first polysilicon, the second polysilicon can more effectively control the electric field distribution in the channel region. The bump structure can increase the coupling area between the gate and the channel, allowing the gate voltage to more precisely control the carrier concentration in the channel. The enhanced gate control capability can make the threshold voltage of the transistor more stable and reduce subthreshold leakage current. When the transistor is turned on, a conductive channel can be formed more quickly, increasing the conduction current; when the transistor is turned off, leakage current can be suppressed more effectively, reducing static power consumption.

[0132] (3) The shielding effect of the first polysilicon and the nested structure of the second polysilicon can improve the electric field distribution inside the transistor. When the transistor is subjected to high voltage, the electric field will be redistributed inside the device, avoiding local electric field concentration. The raised structure and nested wrapping can make the electric field more uniformly distributed throughout the structure, reducing electric field peaks. A uniform electric field distribution can improve the breakdown voltage of the transistor, enabling it to operate safely at higher voltages. This is crucial for transistors in high-voltage applications, such as in power electronics, where high breakdown voltage transistors can be used to achieve higher voltage level power conversion and control.

[0133] (4) By improving gate control capability and optimizing electric field distribution, the channel resistance can be reduced more effectively when the transistor is turned on. The nested wrapping of the second polysilicon around the first polysilicon bump structure can increase the effective width of the channel, allowing more charge carriers to pass through the channel, thereby reducing the on-resistance. The reduction in on-resistance can reduce the power loss of the transistor in the on-state and improve the efficiency of the transistor. In high-power applications, reducing the on-resistance can significantly reduce heat generation and improve the reliability and stability of the system.

[0134] In one embodiment, based on the above embodiments, the method for fabricating the variable capacitor SGT transistor further includes:

[0135] When the corresponding source contact holes and gate contact holes are fabricated at different layout positions of the main body, shielding gate contact holes are also fabricated at the corresponding positions; wherein, the shielding gate contact holes are used to expose the first polysilicon.

[0136] When manufacturing the source electrode, the source electrode is also connected to the shielding gate contact hole.

[0137] In this embodiment, while fabricating corresponding source contact holes and gate contact holes at different layout locations on the main body, shielding gate contact holes also need to be fabricated at specific corresponding locations. The opening location of the shielding gate contact holes must avoid the opening location of the gate contact holes.

[0138] Optional, refer to Figure 6 Alternatively, shielding grid contact holes can be sequentially set for each trench at the central axis (corresponding to the AD section) perpendicular to the longitudinal direction of the trench arrangement.

[0139] Optional, refer to Figure 10 Etching is performed above the selected opening position of the shielding gate contact hole to remove the functional layer above the first polysilicon, thereby obtaining the shielding gate contact holes for exposing the first polysilicon in each trench.

[0140] When fabricating the source electrode, in addition to connecting the source contact vias, it is also necessary to connect the source electrode to the shielding gate contact vias. A photolithography process is used to define the source electrode pattern on the front-side metal layer, including the portions connected to the source contact vias and the shielding gate contact vias. The source electrode pattern is transferred to photoresist using a photomask. After development, the front-side metal layer is etched using the photoresist as a mask. The etching process removes unwanted metal portions, leaving the source electrode pattern connected to the source contact vias and the shielding gate contact vias.

[0141] By connecting the source to the first polysilicon via a shielded gate contact hole, the electrical performance of the SGT transistor can be improved. The first polysilicon, acting as a shielded gate, when connected to the source, allows for better control of the electric field distribution, reducing the transistor's on-resistance and switching losses, and improving the transistor's efficiency and reliability.

[0142] In one embodiment, based on the above embodiment, after the step of fabricating a dielectric layer on the upper surface of the body and fabricating corresponding source contact holes and gate contact holes at different layout positions of the body, the method further includes:

[0143] After injecting the same type of dopant into the upper surface of the first doped region within the source contact hole, a rapid thermal annealing process is performed to form the corresponding doped contact region.

[0144] In this embodiment, within the pre-fabricated source contact hole, an implantation operation of the same type of dopant is performed on the upper surface of the first doped region. The same type of dopant refers to an impurity element of the same type as the original dopant in the first doped region. For example, if the first doped region was originally N-type doped (typically using elements such as phosphorus), then the implanted dopant will also be an N-type impurity; if the first doped region was P-type doped (typically using elements such as boron), then the implanted dopant will also be a P-type impurity.

[0145] The purpose of this step is to further increase the doping concentration on the upper surface of the first doped region. By increasing the doping concentration, the contact resistance can be reduced, allowing for a better electrical connection between the subsequently formed electrode and the first doped region. This reduces energy loss during signal transmission and improves transistor performance, such as increasing its switching speed and reducing power consumption.

[0146] After the implantation of similar dopants is completed, the entire substrate is then subjected to rapid thermal annealing. Rapid thermal annealing is a process that heats the material to a high temperature in a short time and then cools it rapidly.

[0147] In this process, the high-temperature environment promotes a more uniform distribution of the implanted dopants within the crystal lattice, repairing lattice damage caused by ion implantation. During ion implantation, high-energy ions bombard lattice atoms, leading to defects in the lattice structure, which can affect the electrical properties of the material. Rapid thermal annealing allows the lattice atoms to rearrange, restoring the integrity of the lattice.

[0148] Simultaneously, the high temperature can activate the injected dopants, making them effective carrier sources and further improving the conductivity of the upper surface of the first doped region. After rapid thermal annealing, a corresponding doped contact region will be formed on the upper surface of the first doped region. This doped contact region has good electrical properties, providing a high-quality contact interface for subsequent source fabrication, thereby optimizing the overall performance of the SGT transistor.

[0149] In one embodiment, based on the above embodiment, the substrate is an N-type silicon substrate; the step of forming a first doped region and a second doped region of different doping types stacked on the adjacent sides of each trench includes:

[0150] P+ ions are implanted into the substrate surface adjacent to each trench using an ion implantation process. After furnace tube annealing, a P-type well region is formed, which serves as the first doped region.

[0151] The active region is exposed using photolithography. N+ ions are implanted above each P-type well region, and after annealing in a furnace tube, an N-type source region is formed, which serves as the second doped region.

[0152] In this embodiment, when it is necessary to fabricate a 100V N-type SGT transistor, an N-type silicon substrate can be selected as the substrate.

[0153] Optional, refer to Figure 4 , Figure 7 and Figure 10 During the fabrication of the first doped region, P+ ions are implanted onto the substrate surface adjacent to each trench using an ion implantation process. The substrate here is an N-type silicon substrate, and the P+ ions are typically positively charged impurity ions such as boron (B) ions (i.e., implanting P-type impurities (boron)). Ion implantation is a technique for precisely controlling impurity doping. By accelerating the ion beam, it is given sufficient energy to penetrate the substrate surface and enter the silicon lattice to a certain depth.

[0154] The reason for choosing to implant on the adjacent side of the trench is to form the required P-type region at a specific location to meet the structural and performance requirements of the transistor.

[0155] After P+ ion implantation, furnace tube annealing is required. Furnace tube annealing involves placing the substrate in a high-temperature furnace tube and heating it under specific temperature and atmosphere conditions. The main purposes of annealing are twofold: first, to activate the implanted P+ ions, making them effective acceptor impurities capable of generating holes in the silicon lattice, thus forming P-type conductivity; and second, to repair the damage to the silicon lattice caused during ion implantation. During ion implantation, high-energy ions bombard silicon atoms, causing defects in the lattice structure. These defects affect the electrical properties of the material, and annealing allows the lattice atoms to rearrange, restoring the integrity of the lattice. After furnace tube annealing, a P-type well region is formed on the substrate surface adjacent to the trench, serving as the first doped region.

[0156] Photolithography is used to expose active regions, which involves precisely defining the areas on the substrate surface that will undergo further processing through exposure and development steps. In this process, photoresist is coated on the substrate surface, and then a specific pattern is exposed onto the photoresist using a photomask. After development, the desired pattern is left on the photoresist, thus exposing the active regions, which are the areas where N+ ions will be implanted subsequently.

[0157] N+ ions are implanted over the exposed active regions, i.e., the P-type well regions. N+ ions are typically negatively charged impurity ions such as phosphorus (P) ions or arsenic (As) ions (e.g., implanting N-type impurities (arsenic)). The purpose of implanting N+ ions is to form an N-type region over the P-type well regions, which serves as the source region of the transistor.

[0158] After N+ ion implantation, furnace tube annealing is also required. Similar to the annealing after P+ ion implantation, this annealing aims to activate the implanted N+ ions, making them effective donor impurities capable of generating electrons in the silicon lattice, forming N-type conductivity, and simultaneously repairing lattice damage. After furnace tube annealing, N-type source regions are formed above each P-type well region, serving as the second doping region.

[0159] In this way, first doped regions (P-type well regions) and second doped regions (N-type source regions) with different doping types were successfully formed on the adjacent sides of each trench, laying the foundation for the subsequent fabrication of the source and other structures of SGT transistors.

[0160] Of course, after fabricating the source contact hole, P+ ions can be further injected into the hole, and after rapid thermal annealing, a P-type contact region can be formed on the upper surface of the P-type trap region.

[0161] Furthermore, this application also proposes a variable capacitance SGT transistor, which is fabricated using the method for fabricating a variable capacitance SGT transistor as described in the above embodiments.

[0162] Since the SGT transistor of this variable capacitor adopts all the technical solutions of all the above embodiments, it has at least all the technical effects brought about by the technical solutions of the above embodiments, and will not be described in detail here.

[0163] In summary, the method for fabricating a variable-capacitance SGT transistor and the variable-capacitance SGT transistor provided in this application embodiment are described. By setting a main gate and a sub-gate that connect polysilicon in different trenches, and by changing the connection method between the main gate, the sub-gate and the source, the SGT transistor can be switched between different capacitance values, thereby obtaining a variable-capacitance SGT transistor to flexibly adapt to the input capacitance requirements of the SGT transistor in different application scenarios.

[0164] Furthermore, compared to existing SGT transistor structures, the process flow of this SGT transistor structure is compatible with existing processes, enabling the addition of variable capacitors to the same chip. When the SGT transistor is applied to different fields, the capacitance value can be adjusted during the packaging wire bonding process, which can reduce R&D and production costs, better match the application, and achieve the goal of multiple uses for a single chip, making it very flexible and convenient.

[0165] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, apparatus, article, or method that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, apparatus, article, or method. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, apparatus, article, or method that includes that element.

[0166] The above description is only a preferred embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made based on the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A method for fabricating a variable-capacitance SGT transistor, characterized in that, include: A substrate with multiple trenches covered by an oxide layer is provided; wherein each trench contains a first polysilicon and a second polysilicon disposed on top of the first polysilicon, the first and second polysilicon are separated by an oxide layer, and the first polysilicon, the second polysilicon and the inner wall of the trench are separated by an oxide layer; after forming a first oxide layer on the substrate, the first oxide layer and a portion of the substrate are etched to form multiple trenches; after growing a second oxide layer on the inner surface of each trench, the first polysilicon is filled, and the top of the first polysilicon is lower than the top of the trench; the first oxide layer and the top portion of the second oxide layer are removed, so that the top portion of the first polysilicon protrudes from the second oxide layer; a third oxide layer is grown on the upper surface of the substrate, and the top portion of the first polysilicon wrapped by the third oxide layer forms a protrusion structure; the second polysilicon is filled on top of the third oxide layer in each trench, and the top of the second polysilicon is lower than the top of the trench, and the second polysilicon is nested around the protrusion structure; the first polysilicon serves as a shielding gate polysilicon, and the second polysilicon serves as a gate polysilicon; First and second doped regions of different doping types are formed on the adjacent sides of each trench; After fabricating a dielectric layer on the upper surface of the main body, corresponding source contact holes and gate contact holes are fabricated at different layout positions of the main body; wherein, the source contact holes are used to expose the first doped region; the gate contact holes are used to expose the second polysilicon, and the gate contact holes are further divided into main gate contact holes and sub-gate contact holes, which are located above different trenches. A front metal layer is fabricated on the upper surface of the main body, and the front metal layer is etched to form the source electrode that connects to the source contact hole, the main gate electrode that connects to the main gate contact hole, and the sub-gate electrode that connects to the sub-gate contact hole. A back metal layer is fabricated on the back side of the main body as the drain to obtain an SGT transistor; wherein, when the main gate and the sub-gate are connected and the sub-gate is disconnected from the source, the SGT transistor has a first capacitance value; when the main gate and the sub-gate are disconnected and the sub-gate is connected to the source, the SGT transistor has a second capacitance value; the first capacitance value is greater than the second capacitance value. In the process of fabricating the first polysilicon, a 7000-10000 Å polysilicon layer is deposited using a thin-film process, and the polysilicon is etched to remove the polysilicon above the trenches and to ensure that the top of the polysilicon in each trench is lower than the top of the trench, thus obtaining the first polysilicon. In the process of fabricating the second polysilicon, a 5000-8000 Å polysilicon layer is deposited using a thin-film process, and the polysilicon is etched to remove the polysilicon above the trenches and to ensure that the top of the polysilicon in each trench is lower than the top of the trench, thus obtaining the second polysilicon. The trench has a depth of 5-6 μm; the height difference between the top of the first polysilicon and the top of the trench is 1.0-1.4 μm; and the height difference between the top of the second polysilicon and the top of the trench is 0.1 μm-0.18 μm.

2. The method for fabricating a variable-capacitance SGT transistor as described in claim 1, characterized in that, The method for fabricating the variable capacitor SGT transistor further includes: The groove located below the main gate contact hole is designated as the first groove, and the remaining grooves other than the first groove are designated as the second groove located below the secondary gate contact hole. The larger the ratio of the first trench to the total number of trenches, the larger the ratio of the second capacitance value to the first capacitance value.

3. The method for fabricating a variable-capacitance SGT transistor as described in claim 1 or 2, characterized in that, After the step of fabricating a back metal layer as a drain on the back side of the main body to obtain the SGT transistor, the method further includes: When bonding wires to an SGT transistor package, the sub-gate is connected to either the main gate or the source via wire bonding to select the capacitance value of the SGT transistor.

4. The method for fabricating a variable-capacitance SGT transistor as described in claim 1, characterized in that, The method for fabricating the variable capacitor SGT transistor further includes: When fabricating corresponding source contact holes and gate contact holes at different layout positions of the main body, shielding gate contact holes are also fabricated at corresponding positions; wherein, the shielding gate contact holes are used to expose the first polysilicon. When manufacturing the source electrode, the source electrode is also connected to the shielding gate contact hole.

5. The method for fabricating a variable-capacitance SGT transistor as described in claim 1, characterized in that, After fabricating a dielectric layer on the upper surface of the main body, and then fabricating corresponding source contact holes and gate contact holes at different layout positions of the main body, the method further includes: After injecting the same type of dopant into the upper surface of the first doped region within the source contact hole, a rapid thermal annealing process is performed to form the corresponding doped contact region.

6. The method for fabricating a variable-capacitance SGT transistor as described in claim 1 or 5, characterized in that, The substrate is an N-type silicon substrate; The step of forming a first doped region and a second doped region of different doping types stacked on the adjacent sides of each trench includes: P+ ions are implanted into the substrate surface adjacent to each trench using an ion implantation process. After furnace tube annealing, a P-type well region is formed, which serves as the first doped region. The active region is exposed using photolithography. N+ ions are implanted above each P-type well region, and after annealing in a furnace tube, an N-type source region is formed, which serves as the second doped region.

7. A variable-capacitance SGT transistor, characterized in that, The SGT transistor is fabricated using the method for fabricating a variable-capacitance SGT transistor as described in any one of claims 1-6.

Images