Display device

Abstract

According to one aspect of the present disclosure, a display device includes: a substrate including an active area in which a plurality of pixels are defined and a non-active area extending from the active area; one or more pixel driving circuits disposed in the active area; a plurality of micro LEDs disposed in the plurality of pixels and electrically connected to the pixel driving circuit; a plurality of power lines disposed in the non-active area and electrically connected to the pixel driving circuit; and ground lines disposed between the plurality of power lines, and different power signals are applied to the plurality of power lines. Accordingly, the ground line is provided between the plurality of power lines to which different power signals are applied, so as to minimize an electric field between the plurality of power lines.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0094418, filed on July 17, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The disclosure relates to a display device. BACKGROUND

[0004] Display devices are being applied to various electronic devices, such as TVs, mobile phones, notebooks, and tablets.

[0005] As a display device, there are an organic light emitting display (OLED) that is a self-emitting device and a liquid crystal display (LCD) that requires a separate light source.

[0006] In recent years, a display device including a micro light emitting diode (mLED or μLED) as a light emitting element is attracting attention as a next-generation display device. The micro LED is formed of an inorganic material rather than an organic material, so that the light emitting speed is faster, the light emitting efficiency is excellent, and an image having a higher brightness is displayed, as compared with a liquid crystal display or an organic light emitting display. SUMMARY

[0007] An object to be achieved by the disclosure is to provide a display device having a simplified structure of a plurality of pixel circuits.

[0008] Another object to be achieved by the disclosure is to provide a display device in which a plurality of pixel circuits are integrated in one pixel driving circuit to be driven with low power and reduce power consumption.

[0009] Still another object to be achieved by the disclosure is to provide a display device in which an electric field between a plurality of power lines in an inactive area is weakened.

[0010] Still another object to be achieved by the disclosure is to provide a display device in which an electric field between a plurality of power lines in an inactive area is reduced to minimize corrosion of surrounding wiring.

[0011] The objects of the disclosure are not limited to the above-mentioned objects, and other objects not mentioned above can be clearly understood by those skilled in the art from the following description.

[0012] According to an aspect of the disclosure, a display device includes a substrate including an active area in which a plurality of pixels are defined and a non-active area extending from the active area, one or more pixel driving circuits disposed in the active area, a plurality of micro-LEDs disposed in the plurality of pixels and electrically connected to the pixel driving circuits, a plurality of power lines disposed in the non-active area and electrically connected to the pixel driving circuits, and a ground line disposed between the plurality of power lines and to which a plurality of ground signals are applied. Different power signals are applied to the plurality of power lines. Accordingly, the ground line is disposed between the plurality of power lines to which different power signals are applied to minimize an electric field between the plurality of power lines.

[0013] Further details of exemplary embodiments include those described in the detailed description and drawings.

[0014] According to the disclosure, a plurality of pixel circuits are integrated in one pixel driving circuit to efficiently drive with low power.

[0015] According to the disclosure, a ground line is disposed between a plurality of power lines disposed in parallel in a non-active area to weaken an electric field formed between the plurality of power lines.

[0016] According to the disclosure, a ground line is disposed between a plurality of power lines disposed in parallel in a non-active area to weaken an electric field formed between the plurality of power lines and minimize corrosion of a wiring due to the electric field.

[0017] Effects according to the disclosure are not limited to the above-illustrated contents, and more various effects can be achieved according to the disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0018] The above and other aspects, features, and advantages of the disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0019] Figure 1 is a perspective view illustrating a display device according to an exemplary embodiment of the disclosure;

[0020] Figure 2 is a plan view of a display device according to an exemplary embodiment of the disclosure;

[0021] Figure 3 is an enlarged view of a display device according to an exemplary embodiment of the disclosure;

[0022] Figure 4 is a view illustrating a circuit structure according to an exemplary embodiment of the disclosure;

[0023] Figures 5 to 7is a plan view of a display device according to an exemplary embodiment of the present disclosure;

[0024] Figure 8 is a cross-sectional view of a display device according to an exemplary embodiment of the present disclosure;

[0025] Figure 9 is a cross-sectional view of a display device according to an exemplary embodiment of the present disclosure;

[0026] Figure 10 is an enlarged view of a display device according to an exemplary embodiment of the present disclosure;

[0027] Figure 11 and Figure 12 is a diagram showing a placement structure of a plurality of power lines according to an exemplary embodiment of the present disclosure; and

[0028] Figures 13 to 16 is a diagram showing a device to which a display device according to an exemplary embodiment of the present disclosure is applied. DETAILED DESCRIPTION

[0029] The advantages and features of the present disclosure and a method for achieving the advantages and features will be apparent by referring to exemplary embodiments described below in detail in conjunction with the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein and will be implemented in various forms. The exemplary embodiments are provided by way of example only, so that one skilled in the art can fully understand the disclosure and the scope of the present disclosure.

[0030] The shapes, sizes, ratios, angles, numbers, and the like shown in the drawings for describing the exemplary embodiments of the present disclosure are merely examples and the present disclosure is not limited thereto. Throughout the disclosure, like reference numerals generally indicate like elements. Furthermore, in the following description of the present disclosure, detailed descriptions of known related technologies can be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. The terms such as "include," "have," and "consist of" used herein are generally intended to allow the addition of other components, unless the terms are used with the term "only." Unless explicitly stated otherwise, any reference to a singular can include a plural.

[0031] Components are interpreted to include ordinary error ranges even if not explicitly stated.

[0032] When terms such as "on," "above," "below," and "near" are used to describe a positional relationship between two parts, one or more parts can be positioned between the two parts, unless the terms are used with the term "immediately" or "directly."

[0033] When terms such as "after," "subsequently," "next," and "before" are used to describe a temporal relationship, there can also be cases where they are not continuous unless "immediately" or "directly" is used.

[0034] Although the terms "first," "second," and the like are used to describe various components, the components are not limited by these terms. The terms are used only to distinguish one component from another component. Thus, the first component mentioned below can be a second component in the technical idea of the disclosure.

[0035] In describing the components of the disclosure, terms such as first, second, A, B, (a), or (b) can be used. These terms are only intended to distinguish one component from another component, and the nature, order, sequence, or number of components are not limited by these terms.

[0036] When a component is described as being "connected," "coupled," or "attached" to another component, it should be understood that the component can be directly connected, coupled, or attached to the other component, but other components can be placed between each component that can be indirectly connected, coupled, or attached without any specific explicit description.

[0037] When a component or layer is described as being "in contact" or "overlapping," it should be understood that the component or layer can be in direct contact or overlapping with another component or layer, but other components can be placed between each component that can be indirectly in contact or overlapping without any specific explicit description.

[0038] "at least one" should be understood to include any combination of one or more of the associated components. For example, "at least one of the first component, the second component, and the third component" can be interpreted to mean not only the first component, the second component, or the third component individually, but also any combination of two or more of the first component, the second component, and the third component.

[0039] "first direction," "second direction," "third direction," "X-axis direction," "Y-axis direction," and "Z-axis direction" should not be interpreted as a geometric relationship in which they are perpendicular to each other, but can mean a wider directionality within the range in which the configuration of the disclosure can functionally play a role.

[0040] Each feature of various embodiments of the disclosure can be partially or wholly combined or combined with each other, and various technical connections and operations are possible, and each embodiment can be implemented independently of each other or can be implemented together in a related relationship.

[0041] Hereinafter, exemplary embodiments of the disclosure will be described in detail with reference to the accompanying drawings.

[0042] Figure 1 is a perspective view showing a display device according to an exemplary embodiment of the present disclosure. Figure 2 is a plan view of a display device according to an exemplary embodiment of the present disclosure. Figure 3 is an enlarged view of a display device according to an exemplary embodiment of the present disclosure.

[0043] Referring to Figures 1 to 3 The display device 1000 according to an exemplary embodiment of the present disclosure can include a display panel 100, a polarizing layer 293, an adhesive layer 295, a cover member 200, a support substrate 300, a flexible circuit board 400, and a printed circuit board 500.

[0044] For example, the display panel 100 of the display device 1000 can include a substrate 110. The substrate 110 can be a member that supports other components of the display device 1000. The substrate 110 is formed of an insulating material. For example, the substrate 110 can be formed of glass or resin. Also, the substrate 110 can be formed of a material having flexibility. For example, the substrate 110 can be formed of a plastic material having flexibility, such as polyimide (PI). However, exemplary embodiments of the present disclosure are not limited thereto.

[0045] The display panel 100 can implement information, a video, and / or an image provided to a user. For example, the display panel 100 can include an active area AA and a non-active area NA. For example, the substrate 110 can include the active area AA and the non-active area NA. However, it is not said that the active area AA and the non-active area NA are limited to the substrate 110, but is said with respect to the entire display device 1000.

[0046] The active area AA is an area in which an image is displayed. The active area AA includes a plurality of pixels PX. Each of the plurality of pixels PX can be configured by a plurality of sub-pixels. A plurality of light emitting diodes can be disposed in each of the plurality of sub-pixels. The plurality of light emitting diodes can be configured in different ways according to a type of the display device 1000. For example, when the display device 1000 is an inorganic light emitting display device, the light emitting diode can be a light emitting diode (LED), a micro light emitting diode (micro LED), or a mini light emitting diode (mini LED), but exemplary embodiments of the present disclosure are not limited thereto. Hereinafter, a description will be made by assuming that the light emitting diode of the display device 1000 according to an exemplary embodiment of the present disclosure is a micro LED, but exemplary embodiments of the present disclosure are not limited thereto.

[0047] The non-active area NA is an area in which an image is not displayed. In the non-active area NA, various wirings and circuits for driving a plurality of pixels PX of the active area AA can be disposed. For example, in the non-active area NA, various wirings and driving circuits can be mounted, and a pad unit PAD to which an integrated circuit and a printed circuit are connected can be disposed, but exemplary embodiments of the present disclosure are not limited thereto.

[0048] For example, the driving circuit can be a data driving circuit and / or a gate driving circuit, but exemplary embodiments of the present disclosure are not limited thereto. A wiring through which a control signal for controlling the driving circuit is supplied can be disposed. For example, the control signal can include various timing signals including a clock signal, an input data enable signal, and a synchronization signal, but exemplary embodiments of the present disclosure are not limited thereto. The control signal can be received through the pad unit PAD. For example, in the non-active area NA, a link line LL can be disposed to transmit a signal. For example, a driving part such as a flexible circuit board 400 and a printed circuit board 500 can be connected to the pad unit PAD.

[0049] According to the present disclosure, the non-active area NA can include a first non-active area NA1, a bending area BA, and a second non-active area NA2. For example, the first non-active area NA1 can be an area that surrounds at least a portion of the active area AA. The bending area BA is an area that extends from at least one of a plurality of sides of the first non-active area NA1, and can be a bendable area. The second non-active area NA2 is an area that extends from the bending area BA, and the pad unit PAD can be disposed in the area. The second non-active area NA2 in which the pad unit PAD including a plurality of pad electrodes PE is disposed can also be defined as a pad area. For example, the bending area BA is in a bent state, and other areas of the substrate 110 except for the bending area BA can be in a flat state. In this case, when the bending area BA is bent, the second non-active area NA2 can be located on a rear surface of the active area AA, but exemplary embodiments of the present disclosure are not limited thereto.

[0050] According to the design of the display device 1000, the substrate 110 or the active area AA of the display device 1000 can be configured in various shapes. For example, the active area can be configured in a rectangular shape formed with four rounded corners, but exemplary embodiments of the present disclosure are not limited thereto. As another example, the active area AA can be configured in a rectangular shape formed with four straight corners or a circular shape, but exemplary embodiments of the present disclosure are not limited thereto.

[0051] According to the disclosure, a width of the second non-active area NA2 in which the plurality of pad electrodes PE are disposed can be greater than a width of the bending area BA in which only the plurality of link lines LL are disposed. Further, a width of the active area AA in which the plurality of sub-pixels are disposed can be greater than the width of the bending area BA in which only the plurality of link lines LL are disposed. Although the width of the bending area BA is shown to be less than the width of other areas of the substrate 110 in the drawings, the shape of the substrate 110 including the bending area BA is exemplary, and the exemplary embodiments of the disclosure are not limited thereto.

[0052] Referring to Figure 3 , a plurality of pixel driving circuits PD can be disposed in the active area AA. The plurality of pixel driving circuits PD can be circuits for driving the micro-LEDs of the plurality of sub-pixels. Each of the plurality of pixel driving circuits PD includes a plurality of transistors including a driving transistor and a storage capacitor, and supplies a control signal, power, and a driving current to the micro-LEDs of the plurality of sub-pixels to control the emission operation of the plurality of micro-LEDs. For example, the pixel driving circuit PD can include a power line and a signal line for controlling the emission on / off and / or emission time of the micro-LED. For example, the plurality of pixel driving circuits PD can be driving drivers manufactured using a metal oxide silicon field effect transistor (MOSFET) manufacturing process on a semiconductor substrate, but the exemplary embodiments of the disclosure are not limited thereto. The driving driver includes the plurality of pixel driving circuits PD, and can drive the plurality of sub-pixels.

[0053] Referring to Figure 1 , the flexible circuit board 400 and the printed circuit board 500 can be disposed below the display panel 100. The flexible circuit board 400 and the printed circuit board 500 can be disposed at at least one edge of the display panel 100, but the exemplary embodiments of the disclosure are not limited thereto. One side of the flexible circuit board 400 is attached to the display panel 100, and the other side is attached to the printed circuit board 500, but the exemplary embodiments of the disclosure are not limited thereto. The flexible circuit board 400 can be a flexible film, but the exemplary embodiments of the disclosure are not limited thereto.

[0054] The pad unit PAD including the plurality of pad electrodes PE can be disposed in the second non-active area NA2. In the pad unit PAD, driving components including one or more flexible circuit boards (or flexible films) 400 and printed circuit boards 500 can be attached or bonded. The plurality of pad electrodes PE of the pad unit PAD are electrically connected to the one or more flexible circuit boards (or flexible films) 400, and can transmit various signals (or power) from the printed circuit boards 500 and the flexible circuit boards (or flexible films) 400 to the plurality of pixel driving circuits PD of the active area AA.

[0055] The flexible circuit board (or flexible film) 400 can be a film in which various components are disposed on a base film having ductility. For example, a driving IC such as a gate driver IC or a data driver IC can be disposed in the flexible circuit board (or flexible film) 400, but exemplary embodiments of the present disclosure are not limited thereto. The driving IC can be a component that processes data and driving signals to display an image. According to a mounting method, the driving IC can be disposed by chip on glass (COG), chip on film (COF), or tape carrier package (TCP) technology, but exemplary embodiments of the present disclosure are not limited thereto. The flexible circuit board (or flexible film) 400 can be attached or bonded to the plurality of pad electrodes PE by a conductive adhesive layer, but exemplary embodiments of the present disclosure are not limited thereto.

[0056] The printed circuit board 500 can be a component that is electrically connected to one or more flexible circuit boards (or flexible films) 400 and supplies signals to the driving IC. The printed circuit board 500 is disposed on one side of the flexible circuit board (or flexible film) 400 to be electrically connected to the flexible circuit board (or flexible film) 400. On the printed circuit board 500, various components for supplying various signals to the driving IC can be disposed. For example, on the printed circuit board 500, various components such as a timing controller, a power supply, a memory, or a processor can be disposed. For example, the printed circuit board 500 can include a power management integrated circuit (PMIC), but exemplary embodiments of the present disclosure are not limited thereto.

[0057] The printed circuit board 500 can include at least one hole 510, but exemplary embodiments of the present disclosure are not limited thereto. An internal component that senses ambient light or temperature to be supplied to the plurality of sensors can be disposed in an area corresponding to the at least one hole 510. For example, the internal component can include an ambient light sensor (ALS) or a temperature sensor, but exemplary embodiments of the present disclosure are not limited thereto. For example, the hole 510 can be a transmission hole, but exemplary embodiments of the present disclosure are not limited thereto.

[0058] Referring to Figure 1 A polarization layer 293 can be disposed on the display panel 100. The polarization layer 293 can suppress or reduce an influence on the micro-LEDs caused by light generated from an external light source and entering the display panel 100.

[0059] The cover member 200 can be disposed on the polarizing layer 293. The cover member 200 can be a member for protecting the display panel 100. An adhesive layer 295 can be disposed between the polarizing layer 293 and the cover member 200. The cover member 200 can be attached to the display panel 100 using the adhesive layer 295. The adhesive layer 295 can include an optical clear adhesive (OCA), an optical clear resin (OCR), or a pressure sensitive adhesive (PSA), but exemplary embodiments of the present disclosure are not limited thereto.

[0060] The support substrate 300 can be disposed between the display panel 100 and the printed circuit board 500. The support substrate 300 can enhance the rigidity of the display panel 100. The support substrate 300 can be a back plate, but exemplary embodiments of the present disclosure are not limited thereto.

[0061] Referring to Figures 1 to 3 The plurality of link lines LL can be disposed in the non-active area NA. The plurality of link lines LL can be wiring lines that transmit various signals from the one or more flexible circuit boards (or flexible films) 400 and the printed circuit board 500 to the active area AA. The plurality of link lines LL extend from the plurality of pad electrodes PE of the second non-active area NA2 toward the bending area BA and the first non-active area NA1 to be electrically connected to the plurality of drive lines VL of the active area AA. The plurality of pixel driving circuits PD are supplied with signals from the one or more flexible circuit boards (or flexible films) 400 and the printed circuit board 500 through the drive lines VL of the active area AA and the link lines LL of the non-active area NA to be driven.

[0062] For example, the plurality of link lines LL include a plurality of power lines that transmit a plurality of power signals, a data signal line that transmits a data signal, a transmission signal line that transmits a transmission signal, a clock signal line that transmits a clock signal, and a control signal line that transmits a control signal. The control signal controls the driving circuit. However, exemplary embodiments of the present disclosure are not limited thereto.

[0063] For example, the plurality of drive lines VL can be wiring lines for transmitting signals output from the flexible circuit board (or flexible film) 400 and the printed circuit board 500 to the plurality of pixel driving circuits PD together with the plurality of link lines LL. The plurality of drive lines VL are disposed in the active area AA to be electrically connected to each of the plurality of pixel driving circuits PD. The plurality of drive lines VL extend from the active area AA toward the non-active area NA to be electrically connected to the plurality of link lines LL. Accordingly, the signals output from the flexible circuit board (or flexible film) 400 and the printed circuit board 500 can be transmitted to each of the plurality of pixel driving circuits PD through the plurality of link lines LL and the plurality of drive lines VL.

[0064] When the bending area BA is bent, a portion of the plurality of link lines LL is bent together. Stress is concentrated in the bent portion of the link line LL, which causes a crack on the link line LL. Accordingly, the plurality of link lines LL can be configured of a conductive material having excellent ductility to reduce a crack caused when the bending area BA is bent. For example, the plurality of link lines LL can be configured of a conductive material having excellent ductility, such as gold (Au), silver (Ag), or aluminum (Al), but exemplary embodiments of the present disclosure are not limited thereto. Also, the plurality of link lines LL can be configured of one of various conductive materials used for the active area AA. For example, the plurality of link lines LL can be configured of molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and an alloy of silver (Ag) and magnesium (Mg), or an alloy thereof, but exemplary embodiments of the present disclosure are not limited thereto. The plurality of link lines LL can be configured of a multi-layer structure including various conductive materials. For example, the plurality of link lines LL can be configured with a three-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti), but exemplary embodiments of the present disclosure are not limited thereto.

[0065] The plurality of link lines LL can be configured with various shapes to reduce stress. At least a portion of the plurality of link lines LL disposed on the bending area BA can extend in the same direction as the extension direction of the bending area BA, or extend in a direction different from the extension direction of the bending area BA, to reduce stress. For example, when the bending area BA extends in one direction from the first non-active area NA1 toward the second non-active area NA2, at least a portion of the link lines LL disposed on the bending area BA can extend in an oblique direction with respect to the one direction. As another example, at least a portion of the plurality of link lines LL can be configured with various shapes of patterns. For example, at least a portion of the plurality of link lines LL disposed on the bending area BA can have a shape in which a conductive pattern having at least one of a diamond shape, a rhombus shape, a trapezoidal wave shape, a triangular wave shape, a sawtooth wave shape, a sine wave shape, a circular shape, an omega (Ω) shape is repeatedly disposed. However, exemplary embodiments of the present disclosure are not limited thereto. Accordingly, to minimize stress concentrated on the plurality of link lines LL and a crack caused thereby, the shape of the plurality of link lines LL can be various shapes including the above-mentioned shapes, but exemplary embodiments of the present disclosure are not limited thereto.

[0066] Figure 4 FIG. 1 is a diagram illustrating a circuit structure according to an exemplary embodiment of the present disclosure.

[0067] The pixel driving circuit PD can include a micro driver (μDriver). The micro LED (ED) is electrically connected to the micro driver (μDriver) of the pixel driving circuit PD to be driven. Although in the exemplary embodiment of the present disclosure, the pixel driving circuit PD is described as including the micro driver (μDriver), the pixel driving circuit PD can include a micro driver (μDriver) and a micro switch (μSwitch) according to another exemplary embodiment of the present disclosure.Figure 4 One micro LED (ED) is connected to one micro driver (μDriver) as shown in the middle, but the present disclosure is not limited thereto. For example, eight micro LEDs (EDs) can be connected to one micro driver (μDriver). As another example, 16 micro LEDs (EDs) can be connected to one micro driver (μDriver), or 32 micro LEDs (EDs) or 64 micro LEDs (EDs) can be simultaneously connected to one micro driver (μDriver).

[0068] One micro driver (μDriver) can include a drive transistor T DR and an emission transistor T EM but the exemplary embodiments of the present disclosure are not limited thereto.

[0069] For example, a high potential power voltage VDD is applied to the first electrode of the drive transistor T DR and the first electrode of the emission transistor T EM is connected to the second electrode of the drive transistor T DR and a scan signal SC can be applied to the gate electrode of the drive transistor T DR The scan signal SC applied to the gate electrode of the drive transistor T DR is direct current (DC) power, and a fixed reference voltage can be applied in each frame, but the exemplary embodiments of the present disclosure are not limited thereto.

[0070] The second electrode of the drive transistor T DR is connected to the first electrode of the emission transistor T EM The micro LED (ED) is connected to the second electrode of the emission transistor T EM and an emission signal EM can be applied to the gate electrode of the emission transistor T EM The emission signal EM applied to the gate electrode of the emission transistor T EM may be a pulse width modulation signal that changes in each frame, but the exemplary embodiments of the present disclosure are not limited thereto.

[0071] The first electrode of the micro LED (ED) is connected to the second electrode of the emission transistor T EM and the second electrode of the micro LED (ED) can be connected to ground. For example, the first electrode of the micro LED (ED) is an anode electrode, and the second electrode of the micro LED (ED) can be a cathode electrode, but the exemplary embodiments of the present disclosure are not limited thereto.

[0072] The drive transistor T DR and the emission transistor T EMEach of the transistors T1 to T4 can be an n-type transistor or a p-type transistor.

[0073] The drive transistor T DR is turned on by a scan signal SC applied from a timing controller T-CON to a micro driver (μDriver), and the emission transistor T EM is turned on by an emission signal EM. By doing so, a drive current is applied to the micro LED (ED) via the drive transistor T DR and the emission transistor T DR by a high potential power voltage VDD applied to a first electrode of the drive transistor T EM , so that the micro LED (ED) can emit light.

[0074] Figures 5 to 7 is a plan view of a display device according to an exemplary embodiment of the present disclosure. For example, Figure 5 is an enlarged plan view of an active area including a plurality of pixels. For example, Figure 6 is an enlarged plan view of an active area including one pixel. For example, Figure 7 is an enlarged plan view of an active area including a plurality of pixels. In Figure 5 and Figure 6 , only a plurality of signal lines TL, a plurality of communication lines NL, a plurality of first electrodes CE1, a plurality of banks BNK, and a plurality of micro LEDs (EDs) are illustrated, but exemplary embodiments of the present disclosure are not limited thereto. Figure 7 is an enlarged plan view in which a plurality of second electrodes are additionally provided to Figure 5 .

[0075] Referring to Figure 5 and Figure 6 , a plurality of pixels PX configured by a plurality of sub-pixels can be provided in an active area AA. Each of the plurality of sub-pixels includes a micro LED (ED) and can independently emit light. The plurality of sub-pixels can be provided in a matrix by forming a plurality of rows and a plurality of columns, but exemplary embodiments of the present disclosure are not limited thereto.

[0076] The plurality of sub-pixels can include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. For example, any one of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 is a red sub-pixel, another is a green sub-pixel, and the third can be a blue sub-pixel. The types of the plurality of sub-pixels are illustrative, but exemplary embodiments of the present disclosure are not limited thereto.

[0077] Each of the plurality of pixels PX can include one or more first sub-pixels SP1, one or more second sub-pixels SP2, and one or more third sub-pixels SP3. For example, one pixel PX can include a pair of first sub-pixels SP1, a pair of second sub-pixels SP2, and a pair of third sub-pixels SP3. The pair of first sub-pixels SP1 can be configured by a 1-1 sub-pixel SP1a and a 1-2 sub-pixel SP1b. The pair of second sub-pixels SP2 can be configured by a 2-1 sub-pixel SP2a and a 2-2 sub-pixel SP2b. The pair of third sub-pixels SP3 can be configured by a 3-1 sub-pixel SP3a and a 3-2 sub-pixel SP3b. For example, one pixel PX can include the 1-1 sub-pixel SP1a and the 1-2 sub-pixel SP1b, the 2-1 sub-pixel SP2a and the 2-2 sub-pixel SP2b, and the 3-1 sub-pixel SP3a and the 3-2 sub-pixel SP3b, but exemplary embodiments of the present disclosure are not limited thereto.

[0078] The plurality of sub-pixels forming one pixel PX can be disposed in various ways. For example, in one pixel PX, a pair of first sub-pixels SP1 is disposed on the same column, a pair of second sub-pixels SP2 is disposed on the same column, and a pair of third sub-pixels SP3 can be disposed on the same column. The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be disposed on the same row. The number and position of the plurality of sub-pixels configuring one pixel PX are illustrative, but exemplary embodiments of the present disclosure are not limited thereto.

[0079] The plurality of signal lines TL can be disposed in the area between the plurality of sub-pixels. The plurality of signal lines TL can extend in the column direction between the plurality of sub-pixels. The plurality of signal lines TL can be a wiring that transmits an anode voltage from the pixel driving circuit PD to the plurality of sub-pixels. For example, the plurality of signal lines TL can be electrically connected to the plurality of pixel driving circuits PD and the first electrodes CE1 of the plurality of sub-pixels. The anode voltage output from the pixel driving circuit PD can be transmitted to the first electrodes CE1 of the plurality of sub-pixels through the plurality of signal lines TL. For example, the first electrode CE1 can be an electrode electrically connected to the anode electrode 134 of the micro LED (ED). Accordingly, the anode voltage from the signal line TL can be transmitted to the anode electrode 134 of the micro LED (ED) through the first electrode CE1.

[0080] Accordingly, instead of the plurality of transistors and storage capacitors formed in each of the plurality of sub-pixels, the pixel driving circuit PD in which the plurality of pixel circuits are integrated is used to simplify the structure of the display device 1000. Further, the circuits disposed in each of the plurality of sub-pixels are integrated in one pixel driving circuit PD, so that efficient low-power driving is possible.

[0081] The plurality of signal lines TL can include a first signal line TL1, a second signal line TL2, a third signal line TL3, a fourth signal line TL4, a fifth signal line TL5, and a sixth signal line TL6. The first signal line TL1 and the second signal line TL2 can be electrically connected to one pair of first sub-pixels SP1, respectively. The third signal line TL3 and the fourth signal line TL4 can be electrically connected to one pair of second sub-pixels SP2, respectively. The fifth signal line TL5 and the sixth signal line TL6 can be electrically connected to one pair of third sub-pixels SP3, respectively.

[0082] The first signal line TL1 is provided on one of the pair of first sub-pixels SP1, and the second signal line TL2 can be provided on the other first sub-pixel SP1 of the pair of first sub-pixels SP1. The first signal line TL1 can be electrically connected to one first sub-pixel SP1 among the pair of first sub-pixels SP1, for example, to the first electrode CE1 of the 1-1 sub-pixel SP1a. The second signal line TL2 can be electrically connected to the other first sub-pixel SP1 among the pair of first sub-pixels SP1, for example, to the first electrode CE1 of the 1-2 sub-pixel SP1b.

[0083] The third signal line TL3 is provided on one of the pair of second sub-pixels SP2, and the fourth signal line TL4 can be provided on the other second sub-pixel SP2 of the pair of second sub-pixels SP2. For example, the third signal line TL3 can be provided adjacent to the second signal line TL2. The third signal line TL3 can be electrically connected to one second sub-pixel SP2 among the pair of second sub-pixels SP2, for example, to the first electrode CE1 of the 2-1 sub-pixel SP2a. The fourth signal line TL4 can be electrically connected to the other second sub-pixel SP2 among the pair of second sub-pixels SP2, for example, to the first electrode CE1 of the 2-2 sub-pixel SP2b.

[0084] The fifth signal line TL5 is provided on one of the pair of third sub-pixels SP3, and the sixth signal line TL6 can be provided on the other third sub-pixel SP3 of the pair of third sub-pixels SP3. For example, the fifth signal line TL5 can be provided adjacent to the fourth signal line TL4. The sixth signal line TL6 can be provided adjacent to the first signal line TL1 connected to the adjacent pixel PX. The fifth signal line TL5 can be electrically connected to one third sub-pixel SP3 among the pair of third sub-pixels SP3, for example, to the first electrode CE1 of the 3-1 sub-pixel SP3a. The sixth signal line TL6 can be electrically connected to the other third sub-pixel SP3 among the pair of third sub-pixels SP3, for example, to the first electrode CE1 of the 3-2 sub-pixel SP3b.

[0085] The plurality of signal lines TL can be formed of a conductive material. For example, the plurality of signal lines TL can be configured of a conductive material such as titanium (Ti), aluminum (Al), copper (Cu), molybdenum (Mo), nickel (Ni), chromium (Cr), indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO). However, exemplary embodiments of the present disclosure are not limited thereto. As another example, the plurality of signal lines TL can be formed of a multi-layer structure of a conductive material. For example, the plurality of signal lines TL can be formed of a multi-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti) / indium tin oxide (ITO), although exemplary embodiments of the present disclosure are not limited thereto.

[0086] The plurality of communication lines NL can be disposed in a region between the plurality of pixels PX. The plurality of communication lines NL can be disposed to extend in a row direction in the region between the plurality of pixels PX. The plurality of communication lines NL are disposed in a region between the plurality of second electrodes CE2 and do not overlap the plurality of second electrodes CE2. For example, the plurality of communication lines NL can be wiring for short distance communication such as near field communication (NFC). The plurality of communication lines NL can be used as an antenna. For example, the plurality of communication lines NL can be a plurality of connection lines, although exemplary embodiments of the present disclosure are not limited thereto.

[0087] According to the present disclosure, a bank BNK can be disposed in each of the plurality of sub-pixels. The plurality of banks BNK can be a structure in which the plurality of micro-LEDs (EDs) are seated. The plurality of banks BNK can guide the positions of the plurality of micro-LEDs (EDs) during a transfer process of transferring the plurality of micro-LEDs (EDs) to the display device 1000. The plurality of micro-LEDs (EDs) can be transferred onto the plurality of banks BNK during the transfer process of the plurality of micro-LEDs (EDs). The plurality of banks BNK can be a bank pattern or structure, although exemplary embodiments of the present disclosure are not limited thereto.

[0088] The bank BNK of the first sub-pixel SP1, the bank BNK of the second sub-pixel SP2, and the bank BNK of the third sub-pixel SP3 can be disposed to be spaced apart from each other. The bank BNK of the first sub-pixel SP1, the bank BNK of the second sub-pixel SP2, and the bank BNK of the third sub-pixel SP3 can be configured to be separated from each other. Accordingly, the banks BNK of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 to which different types of micro-LEDs (EDs) are transferred can be easily identified.

[0089] The bank BNK of the 1-1 sub-pixel SP1a and the bank BNK of the 1-2 sub-pixel SP1b can be connected to each other or spaced apart or separated from each other. For example, the bank BNK of the 1-1 sub-pixel SP1a and the bank BNK of the 1-2 sub-pixel SP1b, in which the same type of micro-LED (ED) is disposed, can be connected to each other or spaced apart or separated from each other, in consideration of design, for example, a transfer process requiring. Also, the bank BNK of the 2-1 sub-pixel SP2a and the bank BNK of the 2-2 sub-pixel SP2b can be connected to each other, spaced apart or separated from each other. The bank BNK of the 3-1 sub-pixel SP3a and the bank BNK of the 3-2 sub-pixel SP3b can be connected to each other, spaced apart or separated from each other. Accordingly, the banks BNK of the pair of first sub-pixels SP1, the pair of second sub-pixels SP2, and the pair of third sub-pixels SP3 are formed in various forms, but the exemplary embodiment of the disclosure is not limited thereto.

[0090] For example, the plurality of banks BNK can be formed of an organic insulating material. The plurality of banks BNK is configured by a single layer or a double layer of the organic insulating material. For example, the plurality of banks BNK is configured by a photoresist, a polyimide (PI), or an acryl-based material, but the exemplary embodiment of the disclosure is not limited thereto.

[0091] The first electrode CE1 can be disposed in each of the plurality of sub-pixels. The first electrode CE1 can be disposed on the bank BNK. The first electrode CE1 can be electrically connected to one of the plurality of signal lines TL. At least a portion of the first electrode CE1 extends to the outside of the bank BNK to be electrically connected to the signal line TL most adjacent to the first electrode CE1. For example, a portion of the first electrode CE1 of the 1-1 sub-pixel SP1a extends to one area of the 1-1 sub-pixel SP1a to be electrically connected to the first signal line TL1. A portion of the first electrode CE1 of the 1-2 sub-pixel SP1b extends to another area of the 1-2 sub-pixel SP1b to be electrically connected to the second signal line TL2. A portion of the first electrode CE1 of the 2-1 sub-pixel SP2a extends to one area of the 2-1 sub-pixel SP2a to be electrically connected to the third signal line TL3. A portion of the first electrode CE1 of the 2-2 sub-pixel SP2b extends to another area of the 2-2 sub-pixel SP2b to be electrically connected to the fourth signal line TL4. A portion of the first electrode CE1 of the 3-1 sub-pixel SP3a extends to one area of the 3-1 sub-pixel SP3a to be electrically connected to the fifth signal line TL5. A portion of the first electrode CE1 of the 3-2 sub-pixel SP3b extends to another area of the 3-2 sub-pixel SP3b to be electrically connected to the sixth signal line TL6.

[0092] The first electrode CE1 is electrically connected to the anode electrode 134 of the micro-LED (ED), and an anode voltage can be transmitted from the pixel driving circuit PD to the micro-LED (ED) through the signal line TL. According to an image to be displayed, different voltages can be applied to the first electrodes CE1 of the plurality of sub-pixels. For example, different voltages can be applied to the first electrodes CE1 of the plurality of sub-pixels. Thus, the first electrode CE1 can be a pixel electrode, but exemplary embodiments of the present disclosure are not limited thereto.

[0093] The first electrode CE1 can be configured of a conductive material. For example, the first electrode CE1 can be integrally configured with the plurality of signal lines TL. For example, the first electrode CE1 can be configured of the same conductive material as the plurality of signal lines TL, but exemplary embodiments of the present disclosure are not limited thereto. For example, the first electrode CE1 can be configured of a conductive material, such as titanium (Ti), aluminum (Al), copper (Cu), molybdenum (Mo), nickel (Ni), chromium (Cr), indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO). However, exemplary embodiments of the present disclosure are not limited thereto. As another example, the first electrode CE1 can be configured of a multi-layer structure of a conductive material. For example, the plurality of first electrodes CE1 can be configured of a multi-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti) / indium tin oxide (ITO), but exemplary embodiments of the present disclosure are not limited thereto.

[0094] The micro-LED (ED) can be provided in each of the plurality of sub-pixels. The plurality of micro-LEDs (ED) can be provided on the bank BNK and the first electrode CE1. The plurality of micro-LEDs (ED) are provided on the first electrode CE1 and are electrically connected to the first electrode CE1. Thus, the micro-LED (ED) is applied with an anode voltage from the pixel driving circuit PD through the signal line TL and the first electrode CE1 to emit light.

[0095] The plurality of micro-LEDs (EDs) can include a first micro-LED 130, a second micro-LED 140, and a third micro-LED 150. The first micro-LED 130 can be disposed in the first sub-pixel SP1. The second micro-LED 140 can be disposed in the second sub-pixel SP2. The third micro-LED 150 can be disposed in the third sub-pixel SP3. For example, any one of the first micro-LED 130, the second micro-LED 140, and the third micro-LED 150 is a red micro-LED, another is a green micro-LED, and the third is a blue micro-LED, but exemplary embodiments of the present disclosure are not limited thereto. Thus, red light, green light, and blue light emitted from the plurality of micro-LEDs (EDs) are combined to achieve light of various colors including white. The types of the plurality of micro-LEDs (EDs) are illustrative, but exemplary embodiments of the present disclosure are not limited thereto.

[0096] The first micro-LED 130 can include a first-1 micro-LED 130a disposed in a first-1 sub-pixel SP1a and a first-2 micro-LED 130b disposed in a first-2 sub-pixel SP1b. The second micro-LED 140 can include a second-1 micro-LED 140a disposed in a second-1 sub-pixel SP2a and a second-2 micro-LED 140b disposed in a second-2 sub-pixel SP2b. The third micro-LED 150 includes a third-1 micro-LED 150a disposed in a third-1 sub-pixel SP3a and a third-2 micro-LED 150b disposed in a third-2 sub-pixel SP3b.

[0097] Referring to Figure 5 , Figure 6 and Figure 7 , a second electrode CE2 can be disposed in each of the plurality of sub-pixels. The second electrode CE2 can be disposed on the micro-LED (ED). The second electrode CE2 can be electrically connected to the pixel driving circuit PD through the plurality of contact electrodes CCE.

[0098] For example, the second electrode CE2 is electrically connected to the cathode electrode 135 of the micro-LED (ED) to transmit a cathode voltage from the pixel driving circuit PD to the micro-LED (ED). The same cathode voltage can be applied to the second electrodes CE2 of the plurality of sub-pixels. For example, the same voltage can be applied to the second electrode CE2 of each of the plurality of sub-pixels and the cathode electrode 135 of the micro-LED (ED). Thus, the second electrode CE2 can be a common electrode, but exemplary embodiments of the present disclosure are not limited thereto.

[0099] At least some of the plurality of sub-pixels can share the second electrode CE2. At least some of the second electrodes CE2 of the plurality of sub-pixels can be electrically connected to each other. When the same voltage is applied to the second electrodes CE2, the second electrodes CE2 of at least some of the sub-pixels are shared. For example, the second electrodes of at least some of the pixels PX among the plurality of pixels PX disposed on the same row can be connected to each other. For example, one second electrode CE2 can be disposed in the plurality of pixels PX. One second electrode CE2 can be disposed in every n sub-pixels.

[0100] For example, some of the second electrodes CE2 of the plurality of sub-pixels can be spaced apart or separated from each other. For example, the second electrode CE2 connected to the pixels PX in the nth row and the second electrode CE2 connected to the pixels PX in the (n+1)th row can be spaced apart or separated from each other. For example, the plurality of second electrodes CE2 can be disposed to be spaced apart from each other with a plurality of communication lines NL extending in the row direction therebetween. Accordingly, the number of the plurality of sub-pixels can be greater than the number of the plurality of second electrodes CE2. As another example, all of the second electrodes CE2 of the plurality of sub-pixels are connected to each other so that only one second electrode CE2 can be disposed on the substrate 110, but exemplary embodiments of the present disclosure are not limited thereto.

[0101] The plurality of second electrodes CE2 can be configured of a transparent conductive material, but exemplary embodiments of the present disclosure are not limited thereto. The plurality of second electrodes CE2 is configured of a transparent conductive material so that light emitted from the micro-LED (ED) can travel toward the top of the second electrode CE2. For example, the second electrode CE2 can be configured of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), but exemplary embodiments of the present disclosure are not limited thereto.

[0102] The plurality of contact electrodes CCE can be disposed on the substrate 110. For example, the plurality of contact electrodes CCE can be disposed to be spaced apart from the plurality of banks BNK and the plurality of signal lines TL. Each of the plurality of second electrodes CE2 can overlap at least one contact electrode CCE. For example, one second electrode CE2 can overlap the plurality of contact electrodes CCE.

[0103] For example, the plurality of contact electrodes CCE can be electrically connected to the plurality of second electrodes CE2. The plurality of contact electrodes CCE is disposed between the substrate 110 and the plurality of second electrodes CE2 to transmit a cathode voltage from the pixel driving circuit PD to the second electrode CE2.

[0104] For example, when using micro-LEDs (EDs), a plurality of micro-LEDs EDs are formed on a wafer and are transferred onto the substrate 110 of the display device 1000 to manufacture the display device 1000. However, various defects can occur during a process of transferring a plurality of micro-LEDs (EDs) having a micro size from the wafer to the substrate 110. For example, in some sub-pixels, a non-transfer defect in which a micro-LED is not transferred can occur, and in another sub-pixel, a defect in which a micro-LED (ED) is transferred at a wrong position can occur due to an alignment error. Also, even if the transfer process is normally performed, the transferred micro-LEDs (EDs) can be defective. Accordingly, considering defects for the transfer process of the plurality of micro-LEDs (EDs), a plurality of micro-LEDs of the same type can be transferred in one sub-pixel. Also, an illumination test is performed for the plurality of micro-LEDs (EDs), and only one micro-LED (ED) finally determined to be normal can be used.

[0105] For example, the 1-1 micro-LED 130a and the 1-2 micro-LED 130b are transferred together to one pixel PX, and defects thereof can be tested. If both the 1-1 micro-LED 130a and the 1-2 micro-LED 130b are determined to be normal, only the 1-1 micro-LED 130a is used, but the 1-2 micro-LED 130b is not used. As another example, if only the 1-2 micro-LED 130b among the 1-1 micro-LED 130a and the 1-2 micro-LED 130b is determined to be normal, the 1-1 micro-LED 130a is not used, but only the 1-2 micro-LED 130b can be used. Accordingly, even if a plurality of micro-LEDs (EDs) of the same type are transferred to one pixel PX, only one micro-LED (ED) can be finally used.

[0106] Accordingly, either one of a pair of micro-LEDs (EDs) can be a main (or primary) micro-LED (ED), and the other micro-LED (ED) can be a redundant micro-LED (ED). The redundant micro-LED (ED) can be an additional micro-LED (ED) that is transferred to prepare for a defect of the main micro-LED (ED). When the main micro-LED (ED) is defective, the redundant micro-LED (ED) can be used instead. Accordingly, the main micro-LED (ED) and the redundant micro-LED (ED) are transferred together to one pixel PX, so that degradation of display quality due to defects of the main micro-LED (ED) and the redundant micro-LED (ED) can be minimized.

[0107] For example, the 1-1st micro-LED 130a, the 2-1st micro-LED 140a, and the 3-1st micro-LED 150a transferred to a pixel PX are used as a main micro-LED (ED), and the 1-2nd micro-LED 130b, the 2-2nd micro-LED 140b, and the 3-2nd micro-LED 150b can be used as a redundant micro-LED (ED).

[0108] Figure 8 is a cross-sectional view of a display device according to an exemplary embodiment of the present disclosure. For example, Figure 8 is a cross-sectional view taken along Figure 3 VIII-VIII' of FIG. 1A, which is a cross-sectional view of the active area AA, the first non-active area NA1, the bending area BA, and the second non-active area NA2. For example, Figure 9 is an enlarged cross-sectional view of the first sub-pixel SP1.

[0109] Referring to Figure 8 , the first buffer layer 111a and the second buffer layer 111b can be disposed in the remaining area of the substrate 110 except for the bending area BA.

[0110] The first buffer layer 111a and the second buffer layer 111b can be disposed in the active area AA, the first non-active area NA1, and the second non-active area NA2. The first buffer layer 111a and the second buffer layer 111b can reduce penetration of moisture or impurities through the substrate 110. The first buffer layer 111a and the second buffer layer 111b can be formed of an inorganic insulating material. For example, the first buffer layer 111a and the second buffer layer 111b can be configured by a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but exemplary embodiments of the present disclosure are not limited thereto.

[0111] For example, the first buffer layer 111a and the second buffer layer 111b on the bending area BA can be partially removed. The top surface of the substrate 110 located in the bending area BA can be exposed from the first buffer layer 111a and the second buffer layer 111b. The first buffer layer 111a and the second buffer layer 111b formed of an inorganic insulating material are removed from the bending area BA to minimize cracks of the first buffer layer 111a and the second buffer layer 111b that can be generated during bending.

[0112] A plurality of alignment marks MK can be disposed between the first buffer layer 111a and the second buffer layer 111b. The plurality of alignment marks MK can be configured to identify the position of the pixel driving circuit PD during the manufacturing process of the display device 1000. For example, the plurality of alignment marks MK can be configured to align the position of the pixel driving circuit PD transferred onto the adhesive layer 112. As another example, the plurality of alignment marks MK can be omitted.

[0113] The adhesive layer 112 can be disposed on the second buffer layer 111b. The adhesive layer 112 can be disposed in the active area AA, the first non-active area NA1, the bending area BA, and the second non-active area NA2. As another example, at least a portion of the adhesive layer 112 can be removed in the non-active area NA including the bending area BA. For example, the adhesive layer 112 can be formed of any one of an adhesive polymer, an epoxy resin, a UV-cured resin, a polyimide-based, an acrylate-based, a polyurethane-based, and a polydimethylsiloxane (PDMS), but exemplary embodiments of the present disclosure are not limited thereto.

[0114] The pixel driving circuit PD can be disposed on the adhesive layer 112 in the active area AA. When the pixel driving circuit PD is implemented as a driving driver, the driving driver can be mounted on the adhesive layer 112 through a transfer process, but exemplary embodiments of the present disclosure are not limited thereto.

[0115] The protective layer 113 can be disposed on the adhesive layer 112 and the pixel driving circuit PD. The protective layer 113 can be disposed to surround the pixel driving circuit PD, but exemplary embodiments of the present disclosure are not limited thereto. For example, the protective layer 113 can be disposed to cover at least a portion of a side surface of the pixel driving circuit PD. As another example, the protective layer 113 can be disposed to cover at least a portion of a top surface of the pixel driving circuit PD.

[0116] The protective layer 113 can include one or more organic insulating layers. For example, the protective layer 113 can include a first protective layer 113a disposed on the adhesive layer 112 and a second protective layer 113b disposed on the first protective layer 113a. For example, the first protective layer 113a and the second protective layer 113b can be disposed to surround a side surface of the pixel driving circuit PD. For example, the second protective layer 113b can be disposed to cover at least a portion of a top surface of the pixel driving circuit PD. For example, at least one of the first protective layer 113a and the second protective layer 113b of the protective layer 113 disposed in the bending area BA can be omitted. For example, the first protective layer 113a is entirely disposed in the active area AA and the non-active area NA, and the second protective layer 113b can be partially disposed in the active area AA, the first non-active area NA1, and the second non-active area NA2. For example, a portion of the second protective layer 113b in the bending area BA can be removed. However, the protective layer 113 can be formed of a single layer, but exemplary embodiments of the present disclosure are not limited thereto.

[0117] Each of the first protective layer 113a and the second protective layer 113b of the protective layer can be configured of an organic insulating material, but example embodiments of the present disclosure are not limited thereto. For example, the first protective layer 113a and the second protective layer 113b can be configured of a photoresist, a polyimide (PI), or a photoacryl material, but example embodiments of the present disclosure are not limited thereto. For example, the first protective layer 113a and the second protective layer 113b can be an overcoat layer or an insulating layer, but example embodiments of the present disclosure are not limited thereto.

[0118] According to the present disclosure, in the active area AA, a plurality of first connection lines 121 can be disposed on the second protective layer 113b. The plurality of first connection lines 121 can be a wiring electrically connecting the pixel driving circuit PD to other components. For example, the pixel driving circuit PD can be electrically connected to the plurality of signal lines TL and the plurality of contact electrodes CCE through the plurality of first connection lines 121. For example, the plurality of first connection lines 121 can include a 1-1 connection line 121a, a 1-2 connection line 121b, a 1-3 connection line 121c, and a 1-4 connection line 121d, but example embodiments of the present disclosure are not limited thereto.

[0119] For example, a plurality of 1-1 connection lines 121a can be disposed on the second protective layer 113b. The plurality of 1-1 connection lines 121a can be electrically connected to the pixel driving circuit PD. The plurality of 1-1 connection lines 121a can transmit a voltage output from the pixel driving circuit PD to the first electrode CE1 or the second electrode CE2.

[0120] For example, an additional protective layer can also be disposed on the second protective layer 113b. For example, a third protective layer 114 can also be disposed on the second protective layer 113b. The third protective layer 114 can be completely disposed in the active area AA and the non-active area NA. In the bending area BA, the third protective layer 114 can cover the side surface of the second protective layer 113b and the top surface of the first protective layer 113a. The third protective layer 114 can be configured of an organic insulating material. For example, the third protective layer 114 can be configured of a photoresist, a polyimide (PI), or a photoacryl material, but example embodiments of the present disclosure are not limited thereto. For example, the first protective layer 113a, the second protective layer 113b, and the third protective layer 114 can be configured of the same material, but example embodiments of the present disclosure are not limited thereto.

[0121] A plurality of first-2 connection lines 121b can be disposed on the third protective layer 114. The plurality of first-2 connection lines 121b can be indirectly or directly connected to the pixel driving circuit PD. For example, a portion of the first-2 connection lines 121b can be directly connected to the pixel driving circuit PD through a contact hole of the third protective layer 114. Another portion of the first-2 connection lines 121b can be electrically connected to the first-1 connection lines 121a through a contact hole of the third protective layer 114. However, exemplary embodiments of the present disclosure are not limited thereto. A voltage output from the pixel driving circuit PD can be transmitted to the first electrode CE1 or the second electrode CE2 through a connection line other than the plurality of first-2 connection lines 121b.

[0122] A first insulating layer 115a can be disposed on the plurality of first-2 connection lines 121b. The first insulating layer 115a can be completely disposed in the active area AA and the non-active area NA, but exemplary embodiments of the present disclosure are not limited thereto. The first insulating layer 115a can be configured of an organic insulating material, but exemplary embodiments of the present disclosure are not limited thereto. For example, the first insulating layer 115a can be configured of a photoresist, a polyimide (PI), or a photoacryl material, but exemplary embodiments of the present disclosure are not limited thereto.

[0123] A plurality of first-3 connection lines 121c can be disposed on the first insulating layer 115a. The plurality of first-3 connection lines 121c can be electrically connected to the plurality of first-2 connection lines 121b. For example, the first-3 connection lines 121c can be electrically connected to the first-2 connection lines 121b through a contact hole of the first insulating layer 115a.

[0124] A second insulating layer 115b can be disposed on the plurality of first-3 connection lines 121c. The second insulating layer 115b can be disposed in a remaining area except for the bending area BA, but exemplary embodiments of the present disclosure are not limited thereto. The second insulating layer 115b can be disposed in the active area AA, the first non-active area NA1, and the second non-active area NA2, but exemplary embodiments of the present disclosure are not limited thereto. For example, a portion of the second insulating layer 115b disposed in the bending area BA can be removed. The second insulating layer 115b can be configured of an organic insulating material, but exemplary embodiments of the present disclosure are not limited thereto. For example, the second insulating layer 115b is configured of a photoresist, a polyimide (PI), or a photoacryl material, but exemplary embodiments of the present disclosure are not limited thereto.

[0125] A plurality of first 1-4 connection lines 121d can be disposed on the second insulating layer 115b. The plurality of first 1-4 connection lines 121d can be electrically connected to the plurality of first 1-3 connection lines 121c. For example, the first 1-4 connection lines 121d can be electrically connected to the first 1-3 connection lines 121c through contact holes of the second insulating layer 115b.

[0126] According to the present disclosure, in the non-active area NA, a plurality of second connection lines 122 can be disposed on the second protective layer 113b. The plurality of second connection lines 122 can be wiring lines that transmit signals transmitted from the flexible circuit board (or flexible film) 400 and the printed circuit board 500 (see Figure 1 ) to the pad unit PAD to the pixel driving circuit PD of the active area AA. For example, the plurality of second connection lines 122 are electrically connected to the plurality of pad electrodes PE to be applied with signals from the flexible circuit board (or flexible film) 400 and the printed circuit board 500.

[0127] For example, the plurality of second connection lines 122 extend from the pad unit PAD toward the active area AA to transmit signals to the wiring lines of the active area AA. In this case, the plurality of second connection lines 122 can function as link lines LL. The plurality of second connection lines 122 can include a second 2-1 connection line 122a, a second 2-2 connection line 122b, a second 2-3 connection line 122c, and a second 2-4 connection line 122d.

[0128] The plurality of second 2-1 connection lines 122a can be disposed on the second protective layer 113b. The plurality of second 2-1 connection lines 122a can extend from the second non-active area NA2 to the bending area BA and the first non-active area NA1. The plurality of second 2-1 connection lines 122a can transmit signals transmitted from the flexible circuit board (or flexible film) 400 and the printed circuit board 500 to the pad unit PAD to the pixel driving circuit PD of the active area AA. For example, the second 2-1 connection line 122a extends from the second non-active area NA2 to the first non-active area NA1 and can be electrically connected to any one of the first 1-1 connection line 121a, the first 1-2 connection line 121b, the first 1-3 connection line 121c, and the first 1-4 connection line 121d of the plurality of first connection lines 121. For example, the second 2-1 connection line 122a can be directly connected to the first 1-1 connection line 121a disposed on the same layer, or can be connected to the first 1-2 connection line 121b disposed on a different layer through a contact hole of the third protective layer 114, but is not limited thereto.

[0129] A plurality of second-2 connection lines 122b can be disposed on the third protective layer 114. The plurality of second-2 connection lines 122b can be disposed in the second non-active area NA2. The second-2 connection lines 122b can be electrically connected to the second-1 connection lines 122a through contact holes of the third protective layer 114. Accordingly, signals from the flexible circuit board (or flexible film) 400 and the printed circuit board 500 can be transmitted to the second-1 connection lines 122a through the second-2 connection lines 122b.

[0130] A second-3 connection line 122c can be disposed on the first insulating layer 115a. The second-3 connection line 122c can be disposed in the second non-active area NA2. The second-3 connection line 122c can be electrically connected to the second-2 connection lines 122b through a contact hole of the first insulating layer 115a. Accordingly, signals from the flexible circuit board (or flexible film) 400 and the printed circuit board 500 can be transmitted to the second-1 connection lines 122a through the second-3 connection line 122c and the second-2 connection lines 122b.

[0131] A second-4 connection line 122d can be disposed on the second insulating layer 115b. The second-4 connection line 122d can be disposed in the second non-active area NA2. The second-4 connection line 122d can be electrically connected to the second-3 connection line 122c through a contact hole of the second insulating layer 115b. Accordingly, signals from the flexible circuit board (or flexible film) 400 and the printed circuit board 500 can be transmitted to the second-1 connection lines 122a through the second-4 connection line 122d, the second-3 connection line 122c, and the second-2 connection lines 122b.

[0132] The plurality of first connection lines 121 and the plurality of second connection lines 122 can be formed of a conductive material having excellent ductility or any one of various conductive materials used for the active area AA. For example, the second connection lines 122 disposed partially in the bending area BA can be configured of a conductive material having excellent ductility, such as gold (Au), silver (Ag), or aluminum (Al), but exemplary embodiments of the present disclosure are not limited thereto. As another example, the plurality of first connection lines 121 and the plurality of second connection lines 122 can be configured of molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and an alloy of silver (Ag) and magnesium (Mg), or an alloy thereof, but exemplary embodiments of the present disclosure are not limited thereto.

[0133] The third insulating layer 115c can be disposed on the plurality of first connection lines 121 and the plurality of second connection lines 122. The third insulating layer 115c can be disposed in the remaining area except for the bending area BA, but exemplary embodiments of the present disclosure are not limited thereto. The third insulating layer 115c can be disposed in the active area AA, the first non-active area NA1, and the second non-active area NA2. A portion of the third insulating layer 115c disposed in the bending area BA can be removed. The third insulating layer 115c can be configured of an organic insulating material, but exemplary embodiments of the present disclosure are not limited thereto. For example, the third insulating layer 115c can be configured of a photoresist, a polyimide (PI), or a photoacryl material, but exemplary embodiments of the present disclosure are not limited thereto.

[0134] A plurality of banks BNK can be disposed on the third insulating layer 115c in the active area AA. The plurality of banks BNK can be disposed to overlap each of the plurality of sub-pixels. One or more micro-LEDs of the same type can be disposed above each of the plurality of banks BNK.

[0135] A plurality of signal lines TL can be disposed on the third insulating layer 115c in the active area AA. The plurality of signal lines TL can be disposed in an area between the plurality of banks BNK. For example, the plurality of signal lines TL can be disposed adjacent to any one of the plurality of banks BNK.

[0136] A plurality of contact electrodes CCE can be disposed on the third insulating layer 115c in the active area AA. The plurality of contact electrodes CCE can supply a cathode voltage from the pixel driving circuit PD to the second electrode CE2.

[0137] The first electrode CE1 can be disposed on the bank BNK. For example, the first electrode CE1 can be disposed to extend from the adjacent signal line TL toward the top of the bank BNK. The first electrode CE1 can be disposed on the top surface of the bank BNK and the side surface of the bank BNK. For example, the first electrode CE1 can be disposed to extend from the signal line TL on the top surface of the third insulating layer 115c to the side surface of the bank BNK and the top surface of the bank BNK.

[0138] Referring to Figure 9 The first electrode CE1 can be configured of a plurality of conductive layers. For example, the first electrode CE1 can include a first conductive layer CE1a, a second conductive layer CE1b, a third conductive layer CE1c, and a fourth conductive layer CE1d, but exemplary embodiments of the present disclosure are not limited thereto.

[0139] The first conductive layer CE1a can be disposed on the bank BNK. The second conductive layer CE1b can be disposed on the first conductive layer CE1a. The third conductive layer CE1c can be disposed on the second conductive layer CE1b. The fourth conductive layer CE1d can be disposed on the third conductive layer CE1c. For example, the first conductive layer CE1a, the second conductive layer CE1b, the third conductive layer CE1c, and the fourth conductive layer CE1d can be configured of titanium (Ti), molybdenum (Mo), aluminum (Al), or titanium (Ti) and indium tin oxide (ITO), but exemplary embodiments of the present disclosure are not limited thereto.

[0140] According to the present disclosure, some of the plurality of conductive layers configuring the first electrode CE1 having a good reflection efficiency can be configured as an alignment mark for alignment of the micro LED (ED) and / or the reflection plate. For example, the second conductive layer CE1b among the plurality of conductive layers of the first electrode CE1 can include a reflective material. For example, the second conductive layer CE1b can include aluminum (Al), but exemplary embodiments of the present disclosure are not limited thereto. Accordingly, the second conductive layer CE1b can be configured as a reflection plate. Further, the second conductive layer CE1b has a high reflection efficiency so as to be easily recognized during a manufacturing process, so that a position of the micro LED (ED) or a transfer position can be aligned based on the second conductive layer CE1b.

[0141] For example, in order to configure the second conductive layer CE1b as a reflection plate, the third conductive layer CE1c and the fourth conductive layer CE1d covering the second conductive layer CE1b can be partially removed or etched. For example, a portion of the third conductive layer CE1c and the fourth conductive layer CE1d disposed on the bank BNK is removed or etched to expose a top surface of the second conductive layer CE1b. For example, a central portion in which a solder pattern SPD is disposed and an edge portion (or a boundary portion) of the third conductive layer CE1c and the fourth conductive layer CE1d are left, and a remaining portion other than these portions can be removed. For example, an edge portion (or a boundary portion) of each of the third conductive layer CE1c formed of titanium (Ti) and the fourth conductive layer CE1d formed of indium tin oxide (ITO) can not be etched. Accordingly, corrosion of another conductive layer of the first electrode CE1 caused by a tetramethylammonium hydroxide (TMAH) solution used in a mask process for the first electrode CE1 can be suppressed.

[0142] According to the present disclosure, the first conductive layer CE1a and the third conductive layer CE1c can include titanium (Ti) or molybdenum (Mo). The second conductive layer CE1b can include aluminum (Al). The fourth conductive layer CE1d can include a transparent conductive oxide layer such as indium tin oxide (ITO) or indium zinc oxide (IZO) attached to the solder pattern SPD and having corrosion resistance and acid resistance. However, exemplary embodiments of the present disclosure are not limited thereto.

[0143] The first conductive layer CE1a, the second conductive layer CE1b, the third conductive layer CE1c, and the fourth conductive layer CE1d are sequentially deposited, and then a photolithography process and an etching process are performed to be patterned. However, exemplary embodiments of the present disclosure are not limited thereto.

[0144] According to the present disclosure, the signal line TL, the contact electrode CCE, and the pad electrode PE disposed on the same layer as the first electrode CE1 can be configured by a plurality of layers of a conductive material, but exemplary embodiments of the present disclosure are not limited thereto. For example, the signal line TL, the contact electrode CCE, and the pad electrode PE can be formed by a plurality of layers of indium tin oxide (ITO) / titanium (Ti) / aluminum (Al) / titanium (Ti), but exemplary embodiments of the present disclosure are not limited thereto.

[0145] According to the present disclosure, in each of the plurality of sub-pixels, a soldering pattern SDP can be disposed on the first electrode CE1. The soldering pattern SDP can join the micro-LED (ED) to the first electrode CE1. The first electrode CE1 and the micro-LED (ED) can be electrically connected by using eutectic bonding of the soldering pattern SDP, but exemplary embodiments of the present disclosure are not limited thereto. For example, when the soldering pattern SDP is configured by indium (In) and the anode electrode 134 of the micro-LED (ED) is configured by gold (Au), heat and pressure are applied to join the soldering pattern SDP and the anode electrode 134 during a transfer process of the micro-LED (ED). The micro-LED (ED) can be joined to the soldering pattern SDP and the first electrode CE1 using eutectic bonding without a separate adhesive material. For example, the soldering pattern SDP can be configured by indium (In), tin (Sn), or an alloy thereof, but exemplary embodiments of the present disclosure are not limited thereto. For example, the soldering pattern SDP can be a joining pad or an adhesive pad, but exemplary embodiments of the present disclosure are not limited thereto.

[0146] According to the disclosure, a passivation layer 116 can be disposed on the plurality of signal lines TL, the plurality of first electrodes CE1, the plurality of contact electrodes CCE, and the third insulating layer 115c. For example, the passivation layer 116 can be disposed in the active area AA, the first non-active area NA1, and the second non-active area NA2. A portion of the passivation layer 116 disposed in the bending area BA can be removed. A portion of the passivation layer 116 covering the plurality of pad electrodes PE in the second non-active area NA2 can be removed. The passivation layer 116 is disposed to cover the remaining area except for the bending area BA, the plurality of pad electrodes PE, and the solder pattern SDP to reduce penetration of moisture or impurities into the micro-LED (ED). For example, the passivation layer 116 can be configured by a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but exemplary embodiments of the disclosure are not limited thereto. For example, the passivation layer 116 can be a protective layer or an insulating layer, but exemplary embodiments of the disclosure are not limited thereto. For example, the passivation layer 116 can include a hole through which the solder pattern SDP is exposed.

[0147] In each of the plurality of sub-pixels, a micro-LED (ED) can be disposed on the solder pattern SDP. A first micro-LED 130 can be disposed in a first sub-pixel SP1. A second micro-LED 140 can be disposed in a second sub-pixel SP2. A third micro-LED 150 can be disposed in a third sub-pixel SP3.

[0148] The micro-LED (ED) can be formed on a silicon wafer using metal organic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), or a sputtering method. However, exemplary embodiments of the disclosure are not limited thereto.

[0149] Referring to Figure 9 , the first micro-LED 130 can include an anode electrode 134, a first semiconductor layer 131, an active layer 132, a second semiconductor layer 133, a cathode electrode 135, and an encapsulation film 136, but exemplary embodiments of the disclosure are not limited thereto. For example, the encapsulation film 136 can not be included in the first micro-LED 130.

[0150] The first semiconductor layer 131 can be disposed on the solder pattern SDP. The second semiconductor layer 133 can be disposed on the first semiconductor layer 131.

[0151] For example, one of the first semiconductor layer 131 and the second semiconductor layer 133 can be implemented by a compound semiconductor such as a Group III-V or a Group II-VI, and can be doped with an impurity (or a dopant). For example, one of the first semiconductor layer 131 and the second semiconductor layer 133 is an n-type impurity-doped semiconductor layer, and the other is a p-type impurity-doped semiconductor, although example embodiments of the present disclosure are not limited thereto. For example, one or more of the first semiconductor layer 131 and the second semiconductor layer 133 can be a layer in which an n-type or p-type impurity is doped on a material such as gallium nitride (GaN), gallium phosphide (GaP), gallium arsenide phosphide (GaAsP), aluminum gallium indium phosphide (AlGaInP), indium aluminum phosphide (InAlP), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), aluminum indium gallium nitride (AlInGaN), aluminum gallium arsenide (AlGaAs), or gallium arsenide (GaAs). However, example embodiments of the present disclosure are not limited thereto. For example, the n-type impurity can be silicon (Si), germanium (Ge), selenium (Se), carbon (C), tellurium (Te), or tin (Sn), although example embodiments of the present disclosure are not limited thereto. For example, the p-type impurity can be magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), or beryllium (Be), although example embodiments of the present disclosure are not limited thereto.

[0152] For example, each of the first semiconductor layer 131 and the second semiconductor layer 133 can be a nitride semiconductor including an n-type impurity or a nitride semiconductor including a p-type impurity, although example embodiments of the present disclosure are not limited thereto. For example, the first semiconductor layer 131 can be a nitride semiconductor including a p-type impurity, and the second semiconductor layer 133 can be a nitride semiconductor including an n-type impurity, although example embodiments of the present disclosure are not limited thereto.

[0153] The active layer 132 can be disposed between the first semiconductor layer 131 and the second semiconductor layer 133. The active layer 132 is supplied with holes and electrons from the first semiconductor layer 131 and the second semiconductor layer 133 to emit light. For example, the active layer 132 can be configured by one of a single-well structure, a multi-well structure, a signal quantum well structure, a multi-quantum well (MQW) structure, a quantum dot structure, and a quantum wire structure, although example embodiments of the present disclosure are not limited thereto. For example, the active layer 132 can be configured by indium gallium nitride (InGaN) or gallium nitride (GaN), although example embodiments of the present disclosure are not limited thereto.

[0154] As another example, the active layer 132 has a multi-quantum well (MQW) structure having a well layer and a barrier layer having a band gap higher than that of the well layer. For example, in the active layer 132, InGaN is configured as the well layer, and an AlGaN layer is configured as the barrier layer, but exemplary embodiments of the present disclosure are not limited thereto.

[0155] The anode electrode 134 can be disposed between the first semiconductor layer 131 and the solder pattern SDP. For example, the anode electrode 134 can electrically connect the first semiconductor layer 131 and the first electrode CE1. The anode voltage output from the pixel driving circuit PD can be applied to the first semiconductor layer 131 through the signal line TL, the first electrode CE1, and the anode electrode 134. For example, the anode electrode 134 can be configured of a conductive material that can form a eutectic bond with the solder pattern SDP, but exemplary embodiments of the present disclosure are not limited thereto. For example, the anode electrode 134 can be configured of gold (Au), tin (Sn), tungsten (W), silicon (Si), silver (Ag), titanium (Ti), iridium (Ir), chromium (Cr), indium (In), zinc (Zn), lead (Pb), nickel (Ni), platinum (Pt), and copper (Cu), or an alloy thereof, but exemplary embodiments of the present disclosure are not limited thereto.

[0156] The cathode electrode 135 can be disposed on the second semiconductor layer 133. For example, the cathode electrode 135 can electrically connect the second semiconductor layer 133 and the second electrode CE2. The cathode voltage output from the pixel driving circuit PD can be applied to the second semiconductor layer 133 through the contact electrode CCE, the second electrode CE2, and the cathode electrode 135. The cathode electrode 135 can be configured of a transparent conductive material to allow light emitted from the micro-LED (ED) to be guided to the top of the micro-LED (ED), but exemplary embodiments of the present disclosure are not limited thereto. For example, the cathode electrode 135 can be configured of a material such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), but exemplary embodiments of the present disclosure are not limited thereto.

[0157] The encapsulation film 136 can be disposed around at least a portion of the first semiconductor layer 131, the active layer 132, the second semiconductor layer 133, the anode electrode 134, and the cathode electrode 135. For example, the encapsulation film 136 can enclose at least a portion of the first semiconductor layer 131, the active layer 132, the second semiconductor layer 133, the anode electrode 134, and the cathode electrode 135.

[0158] For example, the encapsulation film 136 can protect the first semiconductor layer 131, the active layer 132, and the second semiconductor layer 133. For example, the encapsulation film 136 can be disposed on the side surface of the first semiconductor layer 131, the side surface of the active layer 132, and the side surface of the second semiconductor layer 133.

[0159] For example, the encapsulation film 136 can be disposed on at least a portion of the anode electrode 134 and the cathode electrode 135, for example, on an edge portion (or a boundary portion or one side) of the anode electrode 134 and an edge portion (or a boundary portion or one side) of the cathode electrode 135. At least a portion of the anode electrode 134 is exposed from the encapsulation film 136 so that the anode electrode 134 and the solder pattern SDP can be connected. For example, at least a portion of the cathode electrode 135 is exposed from the encapsulation film 136 so that the cathode electrode 135 and the second electrode CE2 can be connected. For example, the encapsulation film 136 can be formed of an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), but exemplary embodiments of the present disclosure are not limited thereto.

[0160] As another example, the encapsulation film 136 can have a structure in which a reflective material is dispersed in a resin layer, but exemplary embodiments of the present disclosure are not limited thereto. For example, the encapsulation film 136 can be manufactured with a reflector having various structures, but exemplary embodiments of the present disclosure are not limited thereto. Light emitted from the active layer 132 is reflected upward by the encapsulation film 136 so that light extraction efficiency can be improved. For example, the encapsulation film 136 can be a reflective layer, but exemplary embodiments of the present disclosure are not limited thereto.

[0161] According to the present disclosure, it is described that the micro LED (ED) has a longitudinal structure, but exemplary embodiments of the present disclosure are not limited thereto. For example, the micro LED (ED) can have a lateral structure or a flip chip structure.

[0162] Reference has been made to Figure 9 The first micro LED 130 is described, and the second micro LED 140 and the third micro LED 150 can have substantially the same structure as the first micro LED 130. For example, the second micro LED 140 and the third micro LED 150 can be substantially the same as the first semiconductor layer 131, the active layer 132, the second semiconductor layer 133, the anode electrode 134, the cathode electrode 135, and the encapsulation film 136 of the first micro LED 130.

[0163] According to the disclosure, in the active area AA, a first optical layer 117a surrounding the plurality of micro-LEDs (ED) can be disposed. For example, the first optical layer 117a can be disposed to cover the plurality of micro-LEDs (ED) and the bank BNK in the area of the plurality of sub-pixels. For example, the first optical layer 117a can cover the bank BNK, a portion of the passivation layer 116, and between the plurality of micro-LEDs (ED). The first optical layer 117a can be disposed or cover between the plurality of micro-LEDs (ED) included in one pixel PX and between the plurality of banks BNK. For example, the first optical layer 117a extends in the first direction and can be spaced apart from each other in the second direction. For example, the first optical layer 117a can be disposed to surround the side portions of the micro-LEDs (ED) and the bank BNK between the passivation layer 116 and the second electrode CE2, but exemplary embodiments of the disclosure are not limited thereto. For example, the first optical layer 117a can be a diffusion layer or a sidewall diffusion layer, but exemplary embodiments of the disclosure are not limited thereto.

[0164] The first optical layer 117a can include an organic insulating material in which micro-particles are dispersed, but exemplary embodiments of the disclosure are not limited thereto. For example, the first optical layer 117a can be configured by silicone in which micro-metal particles such as titanium dioxide (TiO2) particles are dispersed, but exemplary embodiments of the disclosure are not limited thereto. Light from the plurality of micro-LEDs (ED) is scattered by the micro-particles dispersed in the first optical layer 117a to be emitted to the outside of the display device 1000. Accordingly, the first optical layer 117a can improve the extraction efficiency of light emitted from the plurality of micro-LEDs (ED).

[0165] For example, the first optical layer 117a can be disposed in each of the plurality of pixels PX, or disposed in some of the pixels PX disposed together in the same row, but exemplary embodiments of the disclosure are not limited thereto. For example, the first optical layer 117a is disposed in each of the plurality of pixels PX, or the plurality of pixels PX can share one first optical layer 117a. As another example, each of the plurality of sub-pixels includes the first optical layer 117a, respectively, but exemplary embodiments of the disclosure are not limited thereto.

[0166] According to the disclosure, in the active area AA, the second optical layer 117b can be disposed on the passivation layer 116. For example, the second optical layer 117b can be disposed to surround the first optical layer 117a. For example, the second optical layer 117b can be in contact with the side surface of the first optical layer 117a. For example, the second optical layer 117b can be disposed in an area between the plurality of pixels PX. However, the exemplary embodiments of the disclosure are not limited thereto. For example, the second optical layer 117b can be a diffusion layer, a diffusion window, or a window diffusion layer, but the exemplary embodiments of the disclosure are not limited thereto.

[0167] The second optical layer 117b can be configured of an organic insulating material, but the exemplary embodiments of the disclosure are not limited thereto. The second optical layer 117b can be configured of the same material as the first optical layer 117a, but the exemplary embodiments of the disclosure are not limited thereto. For example, the first optical layer 117a can include micro-particles, but the second optical layer 117b does not include micro-particles. For example, the second optical layer 117b is configured of silicone, but the exemplary embodiments of the disclosure are not limited thereto.

[0168] For example, the thickness of the first optical layer 117a can be less than the thickness of the second optical layer 117b, but the exemplary embodiments of the disclosure are not limited thereto. Accordingly, in a plan view, an area in which the first optical layer 117a is disposed can include a recessed portion recessed inward from the upper surface of the second optical layer 117b.

[0169] According to the disclosure, the second electrode CE2 can be disposed on the first optical layer 117a and the second optical layer 117b. For example, the second electrode CE2 can be electrically connected to the plurality of contact electrodes CCE through a contact hole of the second optical layer 117b. For example, the second electrode CE2 can be disposed on the plurality of micro-LEDs (EDs). For example, the second electrode CE2 can include a transparent conductive oxide, such as indium tin oxide (ITO) or indium zinc oxide (IZO), but the exemplary embodiments of the disclosure are not limited thereto. For example, the second electrode CE2 can be disposed to be in contact with the cathode electrode 135. For example, the second electrode CE2 can overlap the first optical layer 117a. For example, the second electrode can cover a plane outside the first optical layer 117a.

[0170] The second electrode CE2 can continuously extend in the first direction of the substrate 110. Accordingly, the second electrode can be commonly connected to the plurality of pixels PX disposed in the first direction of the substrate 110. For example, the second electrode CE2 can be commonly connected to the plurality of pixels PX.

[0171] According to the disclosure, the second electrode CE2 can continuously extend over the first optical layer 117a, the second optical layer 117b, and the micro-LEDs (ED). The area in which the first optical layer 117a is disposed can include a recessed portion recessed inward from an upper surface of the second optical layer 117b. Accordingly, a first portion of the second electrode CE2 disposed on the first optical layer 117a is disposed along the recessed portion, such that the first portion can be disposed lower than a second portion of the second electrode CE2 disposed on the second optical layer 117b.

[0172] The third optical layer 117c can be disposed on the second electrode CE2. The third optical layer 117c can be disposed to overlap the plurality of micro-LEDs (ED) and the first optical layer 117a. The third optical layer 117c is disposed above the second electrode CE2 and the plurality of micro-LEDs (ED), such that unevenness that can be generated in a portion of the plurality of micro-LEDs (ED) can be improved. For example, when the plurality of micro-LEDs (ED) are transferred onto the substrate 110 of the display device 1000, due to process deviation, an area in which intervals between the plurality of micro-LEDs (ED) are not uniform can be caused. When the intervals between the plurality of micro-LEDs (ED) are not uniform, the emission area of each of the plurality of micro-LEDs (ED) is not uniformly disposed, and thus the unevenness can be visible to a user. Accordingly, the third optical layer 117c configured to uniformly diffuse light is configured above the plurality of micro-LEDs (ED), such that light emitted from some of the micro-LEDs (ED) that is visible as unevenness can be reduced. Accordingly, light emitted from the plurality of micro-LEDs (ED) is uniformly diffused by the third optical layer 117c to be extracted to the outside of the display device 1000, such that the brightness uniformity of the display device 1000 can be improved.

[0173] The third optical layer 117c can be configured of an organic insulating material in which micro-particles are dispersed, but exemplary embodiments of the disclosure are not limited thereto. For example, the third optical layer 117c can be configured of silicone in which micro-metal particles such as titanium dioxide (TiO2) particles are dispersed, but exemplary embodiments of the disclosure are not limited thereto. For example, the third optical layer 117c is configured of the same material as the first optical layer 117a, but exemplary embodiments of the disclosure are not limited thereto. For example, the third optical layer 117c can be a diffusion layer or an upward diffusion layer, but exemplary embodiments of the disclosure are not limited thereto.

[0174] According to the disclosure, light from the plurality of micro-LEDs (EDs) is scattered by the micro-particles in the third optical layer 117c to be emitted to the outside of the display device 1000. The third optical layer 117c uniformly mixes light emitted from the plurality of micro-LEDs (EDs) to further improve the brightness uniformity of the display device 1000. In addition, the light extraction efficiency of the display device 1000 can be improved by light scattered from the plurality of micro-particles, so that the display device 1000 can be driven with low power.

[0175] In the active area AA, a black matrix BM can be disposed on the second electrode CE2, the first optical layer 117a, the second optical layer 117b, and the third optical layer 117c. For example, the contact hole of the second optical layer 117b can be filled with the black matrix BM. The black matrix BM is configured to cover the active area AA to reduce color mixing and external light reflection of light of the plurality of sub-pixels. For example, the black matrix BM can be disposed in the contact hole through which the second electrode CE2 and the contact electrode CCE are connected, so that light leakage between the plurality of adjacent sub-pixels can be suppressed.

[0176] For example, the black matrix BM can be configured of an opaque material, but exemplary embodiments of the disclosure are not limited thereto. For example, the black matrix BM can be configured of an organic insulating material to which a black pigment or a black dye is added, but exemplary embodiments of the disclosure are not limited thereto.

[0177] The black matrix BM includes a plurality of transmission holes. The plurality of transmission holes are openings overlapping the micro-LEDs (EDs) of the plurality of sub-pixels. Light emitted from the plurality of micro-LEDs (EDs) can be extracted to the outside of the display panel 100 through the plurality of transmission holes. The plurality of transmission holes can be disposed to overlap some of the plurality of sub-pixels included in one pixel PX. For example, the plurality of transmission holes can be formed to overlap one of a pair of first sub-pixels, one of a pair of second sub-pixels, and one of a pair of third sub-pixels. At this time, the remaining plurality of sub-pixels in which the plurality of transmission holes are not formed can be sub-pixels including defective main micro-LEDs or sub-pixels including redundant micro-LEDs, but exemplary embodiments of the disclosure are not limited thereto.

[0178] The plurality of transmission holes can be larger than the plurality of micro-LEDs (EDs). For example, in a plan view, the plurality of transmission holes are formed to be wider than the plurality of micro-LEDs (EDs) to secure a margin for process deviation.

[0179] A planar shape of the plurality of transmission holes can correspond to a planar shape of the plurality of micro-LEDs (EDs). For example, when the planar shape of the plurality of micro-LEDs (EDs) is a rectangle, the planar shape of the plurality of transmission holes can be a rectangle. However, the planar shape of the plurality of transmission holes and the planar shape of the plurality of micro-LEDs (EDs) can be different from each other, but are not limited thereto.

[0180] In the active area AA, the cap layer 118 can be disposed on the black matrix BM. The cap layer 118 can protect the configuration under the cap layer 118. For example, the cap layer 118 can be configured of an organic insulating material, but exemplary embodiments of the present disclosure are not limited thereto. For example, the cap layer 118 can be configured of a photoresist, a polyimide (PI), or a photoacryl material, but exemplary embodiments of the present disclosure are not limited thereto. For example, the cap layer 118 can be an overcoat layer or an insulating layer, but exemplary embodiments of the present disclosure are not limited thereto.

[0181] The polarizing layer 293 can be disposed on the cap layer 118 by means of the first adhesive layer 291. The cover member 200 can be disposed on the polarizing layer 293 by means of the second adhesive layer 295. For example, the first adhesive layer 291 and the second adhesive layer 295 can include an optical clear adhesive (OCA), an optical clear resin (OCR), or a pressure sensitive adhesive (PSA), but exemplary embodiments of the present disclosure are not limited thereto.

[0182] According to the present disclosure, a plurality of pad electrodes PE can be disposed on the third insulating layer 115c in the second non-active area NA2. For example, at least a portion of the plurality of pad electrodes PE can be exposed from the passivation layer 116. For example, the plurality of pad electrodes PE can be electrically connected to the 2-4 connection line 122d through a contact hole of the third insulating layer 115c.

[0183] An adhesive layer ACF can be disposed on the plurality of pad electrodes PE. The adhesive layer ACF can be an adhesive layer in which conductive balls are dispersed in an insulating material, but exemplary embodiments of the present disclosure are not limited thereto. When heat or pressure is applied to the adhesive layer ACF, the conductive balls are electrically connected to have conductive properties in a portion to which heat or pressure is applied. The adhesive layer ACF is disposed between the plurality of pad electrodes PE and a flexible circuit board (or a flexible film) 400, which can be attached or bonded to the plurality of pad electrodes PE. For example, the adhesive layer ACF can be an anisotropic conductive film, but exemplary embodiments of the present disclosure are not limited thereto.

[0184] The flexible circuit board (or the flexible film) 400 can be disposed on the adhesive layer ACF. The flexible circuit board (or the flexible film) 400 can be electrically connected to the plurality of pad electrodes PE through the adhesive layer ACF. Accordingly, signals output from the flexible circuit board (or the flexible film) 400 and the printed circuit board 500 can be transmitted to the pixel driving circuit PD of the active area AA through the plurality of pad electrodes PE, the 2-4 connection line 122d, the 2-3 connection line 122c, the 2-2 connection line 122b, and the 2-1 connection line 122a.

[0185] Figure 10 is an enlarged view of a display device according to an exemplary embodiment of the present disclosure. Figure 11 and Figure 12 is a diagram illustrating a placement structure of a plurality of power lines according to an exemplary embodiment of the present disclosure.

[0186] Referring to Figure 10 , a plurality of link lines LL and a plurality of pad electrodes PE can be disposed in the non-active area NA. The plurality of link lines LL can include a plurality of power lines to which various power signals are applied from one or more flexible circuit boards (or flexible films) 400 and a printed circuit board 500 through the plurality of pad electrodes PE to transmit the various power signals to the pixel driving circuit PD. The pixel driving circuit PD can generate an anode voltage and a cathode voltage based on the power signals from the plurality of power lines.

[0187] For example, the plurality of power lines extend from the second non-active area NA2 to the bending area BA and the first non-active area NA1, and transmit signals to the pixel driving circuit PD of the active area AA. For example, the plurality of power lines include a negative power line VNEGL, an analog power line AVDDL, a first digital power line DVSSL, and a second digital power line DVDDL. The negative power line VNEGL transmits a negative power signal VNEG to the pixel driving circuit PD, and the analog power line AVDDL transmits an analog power signal AVDD to the pixel driving circuit PD. The first digital power line DVSSL transmits a first digital power signal DVSS to the pixel driving circuit PD, and the second digital power line DVDDL transmits a second digital power signal DVDD to the pixel driving circuit PD. However, exemplary embodiments of the present disclosure are not limited thereto.

[0188] For example, the plurality of pad electrodes PE can be disposed in the second non-active area NA2 which is a pad area. For example, the plurality of pad electrodes PE include a pad electrode PE for transmitting a negative power signal VNEG to a negative power line VNEGL, a pad electrode PE for transmitting an analog power signal AVDD to an analog power line AVDDL, a pad electrode PE for transmitting a first digital power signal DVSS to a first digital power line DVSSL, and a pad electrode PE for transmitting a second digital power signal DVDD to a second digital power line DVDDL.

[0189] In the non-active area NA, the plurality of power lines can be disposed adjacent to each other. For example, the plurality of power lines in the plurality of link lines LL can be disposed adjacent to each other, and the remaining link lines LL can be disposed between the plurality of power lines. For example, the negative power line VNEGL, the analog power line AVDDL, the first digital power line DVSSL, and the second digital power line DVDDL can be disposed adjacent to each other.

[0190] Meanwhile, between a plurality of power lines disposed adjacent to each other, an electric field can be formed due to voltage differences of a plurality of power signals. For example, the negative power signal VNEG, the analog power signal AVDD, the first digital power signal DVSS, and the second digital power signal DVDD have different voltages, and an electric field can be formed between the plurality of power lines due to the voltage differences thereof. If two power lines having a large voltage difference among the plurality of power lines are disposed adjacent to each other, a strong electric field is formed between the two power lines, thereby causing corrosion of a configuration in the vicinity of the plurality of power lines.

[0191] Accordingly, in the display device 1000 according to the exemplary embodiment of the disclosure, the first digital power line DVSSL to which the first digital power signal DVSS, which is a ground signal, is applied is disposed between other power lines to weaken an electric field between the plurality of power lines. Referring to Figure 11 and Figure 12 , the first digital power line DVSSL is disposed between the negative power line VNEGL and the analog power line AVDDL, and the first digital power line DVSSL can be disposed between the analog power line AVDDL and the second digital power line DVDDL. The first digital power signal DVSS among the plurality of power signals is a ground signal having a voltage of 0 V, and a voltage difference with other power signals can be relatively small. Accordingly, the first digital power line DVSSL is disposed between the remaining power lines other than the first digital power line DVSSL, so that an electric field between the plurality of power lines can be weakened.

[0192] For example, if it is assumed that the negative power signal VNEG is -n V and the analog power signal AVDD is +m V and the negative power line VNEGL and the analog power line AVDDL are disposed adjacent to each other, a voltage difference between the negative power signal VNEG and the analog power signal AVDD is greater than a voltage difference between the first digital power signal DVSS and the negative power signal VNEG. Accordingly, a strong electric field can be formed. At this time, if the first digital power line DVSSL is disposed between the negative power line VNEGL and the analog power line AVDDL in which a relatively strong electric field is formed, electric fields formed between the negative power line VNEGL and the first digital power line DVSSL and between the first digital power line DVSSL and the analog power line AVDDL can be weakened. Further, corrosion due to a strong electric field can be minimized. Accordingly, the first digital power line DVSSL to which the first digital power line DVSS, which is a ground signal, is applied is disposed between the plurality of power lines to reduce an electric field between the plurality of power lines.

[0193] Referring to Figure 11 and Figure 12The widths of the plurality of first digital power lines DVSSL can be varied in consideration of the area of the non-active area NA. In the bending area BA in which the plurality of link lines LL are bent, the structure of the plurality of link lines LL can be simplified to reduce the resistance of the plurality of link lines LL and minimize damage to wiring. For example, the plurality of link lines LL can be formed as a single line on a single layer, instead of a structure in which a plurality of wiring connections are provided on different layers, or the plurality of link lines LL can be formed so as not to intersect each other. Specifically, when the plurality of link lines LL are provided to be parallel at a predetermined interval so as not to intersect each other, the interval between the plurality of link lines LL and the line width of the plurality of link lines LL can be adjusted in consideration of the area of the bending area BA.

[0194] Referring to Figure 11 The plurality of link lines LL including the plurality of power lines can be provided to be spaced apart from each other at the same interval (e.g., an interval corresponding to the first length a). It is difficult to reduce the interval between the plurality of link lines LL to a predetermined level or less in consideration of an electric field or migration between wirings, and the plurality of link lines LL can be provided to be spaced apart from each other at an interval corresponding to at least the first length a.

[0195] The plurality of link lines LL including the plurality of power lines are also formed to have the same line width. For example, all of the negative power lines VNEGL, the analog power lines AVDDL, the first digital power lines DVSSL, and the second digital power lines DVDDL have a line width corresponding to the second length b.

[0196] Referring to Figure 12 If it is necessary to reduce the placement area of the plurality of link lines LL including the plurality of power lines due to the area limitation of the non-active area NA including the bending area BA, the line width of the first digital power lines DVSSL is reduced to reduce the overall placement area of the plurality of link lines LL. Also, when the first digital power lines DVSSL are additionally provided between some power lines in a case where there is no available space in the bending area BA, the line width of the existing first digital power lines DVSSL is reduced and the first digital power lines DVSSL can be additionally provided.

[0197] For example, the first digital power lines DVSSL are ground lines to which a first digital signal DVSS that is a 0V ground signal is applied. Accordingly, the limitation of the line width and the number of the first digital power lines DVSSL is not great compared to the analog power lines AVDDL, the negative power lines VNEGL, and the second digital power lines DVDDL, and the degree of freedom of design can be high. Thus, the line width of the first digital power lines DVSSL is reduced from the second length b to a third length c to form a plurality of first digital power lines DVSSL between the plurality of power lines.

[0198] Meanwhile, if the first digital power line DVSSL is set to reduce the line width and is divided into a plurality of lines in a case where it is difficult to secure available space in the bending area BA, the third length c can be adjusted such that the sum of a value obtained by multiplying the number of the first digital power lines DVSSL by the third length c and a value obtained by multiplying the number of the first digital power lines DVSSL by the first length a is equal to or less than the second length b, which is the line width of the existing first digital power line DVSSL. For example, if one first digital power line DVSSL having the line width of the second length b is divided into two first digital power lines DVSSL, the third length c can be adjusted such that two first digital power lines DVSSL having the line width of the third length c are disposed in the space allocated to the existing first digital power line DVSSL, i.e., in the space having the width of the second length b. At this time, the interval between the plurality of link lines LL needs to maintain the first length a. Accordingly, as expressed in Equation 1 below, the third length c can be adjusted such that the sum of twice the third length c, which is the space occupied by the two first digital power lines DVSSL, and the first length a, which is the interval between the two first digital power lines DVSSL, is equal to or less than the second length b. As another example, when one first digital power line DVSSL is set to be divided into three first digital power lines DVSSL, the third length c can be adjusted such that the second length b is equal to or greater than the sum of a value obtained by multiplying the first length a by 2 and a value obtained by multiplying the third length c by 3.

[0199] [Equation 1]

[0200] Second length (b) ≥ First length (a) * (n-1) + Third length (c) * n

[0201] (n is the number of divided first digital power lines)

[0202] Accordingly, in the display device 1000 according to the exemplary embodiment of the present disclosure, the first digital power line DVSSL is disposed between the plurality of power lines to weaken the electric field between the plurality of power lines and protect the configuration near the plurality of power lines. At this time, the line width of the first digital power line DVSSL can be adjusted based on the area of the bending area BA in which the plurality of link lines LL including the plurality of power lines are disposed. If the available space for forming the wiring is insufficient in the bending area BA, the line width of the first digital power line DVSSL is reduced to additionally form the first digital power line DVSSL.

[0203] Figures 13 to 16 FIG. 1 is a diagram illustrating a device to which a display device according to an exemplary embodiment of the present disclosure is applied.

[0204] Referring to Figures 13 to 16The display device 1000 according to example embodiments of the present disclosure can be included in various devices or electronic devices. For example, referring to Figures 13 to 16 Various electronic devices can include a wearable device 1100, a mobile device 1200, a notebook 1300, and a monitor or TV 1400, but example embodiments of the present disclosure are not limited thereto.

[0205] The wearable device 1100, the mobile device 1200, the notebook 1300, and the monitor or TV 1400 can include a housing unit 1005, 1010, 1015, and 1020, and a display panel 100 and a display device 1000 according to example embodiments of the present disclosure described in Figures 1 to 9

[0206] For example, the display device 1000 according to example embodiments of the present disclosure can be applied to a mobile device, a video phone, a smart watch, a watch phone, a wearable device, a foldable device, a rollable device, a bendable device, a flexible device, a curved device, a sliding device, a variable device, an electronic pen, an electronic book, a portable multimedia player (PMP), a personal digital assistant (PDA), an MP3 player, a mobile medical device, a desktop PC, a laptop PC, a netbook computer, a workstation, navigation, a display device for a vehicle, a theater display device, a television, a wallpaper device, a sign device, a game device, a notebook, a monitor, a camera device, a camcorder, and a consumer electronics device.

[0207] Example embodiments of the present disclosure can also be described as follows:

[0208] According to an aspect of the present disclosure, a display device includes a substrate including an active area in which a plurality of pixels are defined and a non-active area extending from the active area, one or more pixel driving circuits disposed in the active area, a plurality of micro-LEDs disposed in the plurality of pixels and electrically connected to the pixel driving circuits, a plurality of power lines disposed in the non-active area and electrically connected to the pixel driving circuits, and a ground line disposed between the plurality of power lines and to which a plurality of ground signals are applied, and different power signals are applied to the plurality of power lines.

[0209] The display device can further include a plurality of first electrodes disposed in the plurality of pixels and electrically connected to the plurality of micro-LEDs, and a plurality of signal lines disposed in the active area and electrically connected to the plurality of first electrodes and the pixel driving circuits, the plurality of first electrodes and the plurality of signal lines can be configured to transmit an anode voltage output from the pixel driving circuits to the plurality of micro-LEDs.

[0210] ​The display device can further include a plurality of contact electrodes electrically connected to the pixel driving circuit; and one or more second electrodes disposed in the plurality of pixels and electrically connected to the plurality of contact electrodes, the one or more second electrodes and the plurality of contact electrodes can be configured to transmit the cathode voltage output from the pixel driving circuit to the plurality of micro-LEDs.

[0211] The plurality of power lines can include a negative power line configured to transmit a negative power signal to the pixel driving circuit, an analog power line configured to transmit an analog power signal to the pixel driving circuit, a first digital power line configured to transmit a first digital power signal to the pixel driving circuit, and a second digital power line configured to transmit a second digital power signal to the pixel driving circuit, and the ground line can be the first digital power line.

[0212] The first digital power line can be disposed adjacent to the negative power line, the analog power line, and the second digital power line.

[0213] The first digital power line can be disposed between the negative power line and the analog power line and between the analog power line and the second digital power line.

[0214] A voltage difference between the negative power signal and the first digital power signal can be less than a voltage difference between the negative power signal and the analog power signal.

[0215] A spacing between the plurality of power lines and the ground line can be constant.

[0216] A line width of each of the plurality of power lines can be equal to a line width of the ground line.

[0217] A line width of each of the plurality of power lines can be greater than a line width of the ground line.

[0218] The non-active area can include a first non-active area extending from the active area, a curved area extending from the first non-active area, and a second non-active area extending from the curved area, and a width of the curved area can be less than a width of the second non-active area, and in the curved area, the plurality of power lines and the ground line can be disposed in parallel.

[0219] The non-active area can include a pad area in which a plurality of pad electrodes are disposed, and some of the plurality of pad electrodes can be configured to apply different power signals to the plurality of power lines.

[0220] The non-active area can include a pad area in which a plurality of pad electrodes are disposed, and some of the plurality of pad electrodes can be configured to transmit a negative power signal, an analog power signal, and a digital power signal to the plurality of power lines, and other pad electrodes can be configured to transmit a ground signal to a ground line.

[0221] Each of the plurality of micro-LEDs can include an anode electrode, a first semiconductor layer disposed on the anode electrode, an active layer on the first semiconductor layer, a second semiconductor layer on the active layer, and a cathode electrode on the second semiconductor layer.

[0222] The display device can further include a plurality of first electrodes electrically connected to the plurality of micro-LEDs and the pixel driving circuit, and a solder pattern disposed between the plurality of micro-LEDs and the plurality of first electrodes, and the plurality of first electrodes and the anode electrodes of the plurality of micro-LEDs can be electrically connected by using a eutectic bonding of the solder pattern.

[0223] Although the exemplary embodiments of the disclosure have been described in detail with reference to the accompanying drawings, the disclosure is not limited thereto and can be implemented in many different forms without departing from the technical idea of the disclosure. Therefore, the exemplary embodiments of the disclosure are provided only for illustrative purposes, not intended to limit the technical idea of the disclosure. The scope of the technical idea of the disclosure is not limited thereto. Therefore, it should be understood that the above-described exemplary embodiments are illustrative in all aspects and do not limit the disclosure. All technical ideas within the scope of equivalents of the disclosure should be interpreted as falling within the scope of the disclosure.

Claims

1. A display device, comprising: A substrate, the substrate including an active region and an active region extending from the active region, wherein a plurality of pixels are defined in the active region; One or more pixel driving circuits are configured in the active region; Multiple micro-LEDs are disposed in the multiple pixels and electrically connected to the pixel driving circuit; Multiple power lines are arranged in the non-active area and electrically connected to the pixel driving circuit; as well as A grounding wire is disposed between the plurality of power lines and is subjected to multiple grounding signals. Different power signals are applied to the multiple power lines.

2. The display device according to claim 1, further comprising: A plurality of first electrodes are disposed in the plurality of pixels and electrically connected to the plurality of micro-LEDs; as well as Multiple signal lines are disposed in the active region and electrically connected to the multiple first electrodes and the pixel driving circuit. The plurality of first electrodes and the plurality of signal lines are configured to transmit the anode voltage output from the pixel driving circuit to the plurality of microLEDs.

3. The display device according to claim 1, further comprising: Multiple contact electrodes electrically connected to the pixel driving circuit; as well as One or more second electrodes, said one or more second electrodes being disposed in said plurality of pixels and electrically connected to said plurality of contact electrodes; The one or more second electrodes and the plurality of contact electrodes are configured to transmit the cathode voltage output from the pixel driving circuit to the plurality of microLEDs.

4. The display device according to claim 1, wherein, The multiple power lines include: A negative electric field line, configured to transmit a negative electric field signal to the pixel driving circuit; Simulated power lines, configured to transmit simulated power signals to the pixel driving circuit; A first digital power line, configured to transmit a first digital power signal to the pixel driving circuit; and A second digital power line, configured to transmit a second digital power signal to the pixel driving circuit, and The grounding wire is the first digital power line.

5. The display device according to claim 4, wherein, The first digital power line is configured to be adjacent to the negative power line, the analog power line, and the second digital power line.

6. The display device according to claim 4, wherein, The first digital power line is disposed between the negative power line and the analog power line, and between the analog power line and the second digital power line.

7. The display device according to claim 4, wherein, The voltage difference between the negative power signal and the first digital power signal is less than the voltage difference between the negative power signal and the analog power signal.

8. The display device according to claim 4, wherein, The first digital power line is configured to have a reduced line width and is divided into multiple lines.

9. The display device according to claim 1, wherein, The spacing between the multiple power lines and the grounding wire is constant.

10. The display device according to claim 1, wherein, The width of each of the plurality of power lines is equal to the width of the grounding wire.

11. The display device according to claim 1, wherein, The width of each of the plurality of power lines is greater than the width of the grounding wire.

12. The display device according to claim 1, wherein, The non-active region includes: A first non-active region extending from the active region; The curved region extending from the first non-active region; and The second non-active region extends from the curved region, and The width of the curved region is smaller than the width of the second non-active region, and in the curved region, the plurality of power lines and the grounding wire are arranged in parallel.

13. The display device according to claim 1, wherein, The non-active region includes a pad region, in which multiple pad electrodes are disposed, and some of the multiple pad electrodes are configured to apply different power signals to the multiple power lines.

14. The display device according to claim 1, wherein, The non-active region includes a pad region with multiple pad electrodes. Some of the multiple pad electrodes are configured to transmit negative power signals, analog power signals, and digital power signals to the multiple power lines, while other pad electrodes are configured to transmit ground signals to the ground line.

15. The display device according to claim 1, wherein, Each of the plurality of micro-LEDs includes: Anode electrode; A first semiconductor layer disposed on the anode electrode; An active layer on the first semiconductor layer; A second semiconductor layer on the active layer; and Cathode electrode on the second semiconductor layer.

16. The display device according to claim 15, further comprising: Multiple first electrodes electrically connected to the plurality of micro LEDs and the pixel driving circuit; as well as The welding pattern is disposed between the plurality of micro-LEDs and the plurality of first electrodes. The plurality of first electrodes and the anode electrodes of the plurality of microLEDs are electrically connected by using eutectic bonding of the welding pattern.

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