Low-power processing method, device, processor, medium and program product
By receiving low-power control instructions and modifying the configuration register, the enable bit value is used to control the target module to enter low-power mode, which solves the problem of high CPU design complexity and achieves the effects of low power consumption and efficient heat dissipation.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 上海芯联芯智能科技有限公司
- Filing Date
- 2025-12-23
- Publication Date
- 2026-05-19
AI Technical Summary
The low-power design of existing CPUs is complex, affecting packaging, cooling and reliability, and power consumption and heat generation issues have not been effectively resolved.
By receiving low-power control instructions, the enable bit value of the target module in the configuration register is modified to control the target module to enter low-power mode. The configuration is determined by the frequency of instructions, which reduces the design complexity.
This approach achieves reduced CPU power consumption and heat generation while maintaining performance, simplifies the design process, and improves system reliability and heat dissipation efficiency.
Smart Images
Figure CN121387054B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer technology, and in particular to a low-power processing method, apparatus, processor, medium, and program product. Background Technology
[0002] With the development of artificial neural network research and its widespread application in the field of artificial intelligence, artificial neural networks have shown unique advantages compared to traditional artificial intelligence algorithms. This has led to continuous advancements in processor development and performance. However, the power consumption and local power density of modern processors are also constantly increasing, which negatively impacts packaging, cooling, and reliability. Furthermore, rising temperatures can cause exponential increases in failure rates, slower speeds, and increased leakage current.
[0003] Therefore, low-power CPU design has emerged. Low-power CPU design is a systematic project that spans architecture, circuitry, manufacturing process, and software. Its core objective is to minimize power consumption (electrical energy consumed per unit time) and heat generation while ensuring that performance meets requirements. It is widely used in scenarios where battery life and heat dissipation are sensitive, such as mobile devices (phones, tablets), laptops, and Internet of Things (IoT) devices.
[0004] However, the current low-power designs for CPUs are quite complex. Summary of the Invention
[0005] Therefore, it is necessary to provide a low-power processing method, device, processor, medium, and program product that can reduce design complexity in response to the above-mentioned technical problems.
[0006] In a first aspect, this application provides a low-power processing method, the method comprising:
[0007] Receive input low-power control instructions, which are input when the instruction usage frequency of the target module in the processor meets preset conditions;
[0008] Based on the low-power control instruction, the value of the enable bit corresponding to the target module in the configuration register is modified to the target value;
[0009] When the enable bit corresponding to the target module in the configuration register is set to the target value, the target module is controlled to enter a low-power mode.
[0010] In one embodiment, after controlling the target module to enter a low-power mode, the process includes:
[0011] If data input is detected in the target module that has entered low-power mode, the corresponding clock of the target module is enabled.
[0012] If it is determined that the target module entering low-power mode has no input or output data, and the internal state machine of the target module entering low-power mode is in the IDLE state, the clock corresponding to the target module entering low-power mode is turned off.
[0013] In one embodiment, the target module includes at least one of a data caching module, a memory management module, a shadow register module, a floating-point operation module, a user-defined coprocessor module, a tracing module, and a debugging module.
[0014] In one embodiment, the data caching related modules include a data caching controller module, a data caching module, and a bus interface module;
[0015] The step of enabling the corresponding clock of the target module when data input is detected in the target module that has entered low-power mode includes:
[0016] When the target module is a data cache-related module, and data input is detected in the target module that has entered low-power mode, the clocks of the data cache controller module, the data cache module, and the bus interface module are enabled.
[0017] In one embodiment, the target module is at least one set of independent shadow registers; the step of controlling the corresponding clock enable of the target module when data input is detected in the target module entering low-power mode includes:
[0018] In the event of an interrupt or anomaly, the clock corresponding to the at least one set of independent shadow registers is enabled, and the at least one set of independent shadow registers is used for hardware-level context switching.
[0019] In one embodiment, the configuration register further includes a frequency setting bit for the tracking module; the method further includes:
[0020] Upon detecting a debug signal, enable the clocks corresponding to the debug module and the tracking module.
[0021] Based on the frequency setting bit of the tracking module in the configuration register, the clock frequency of the clock corresponding to the tracking module is controlled;
[0022] If the debug module is detected to have exited debug mode, the clock enable corresponding to the debug module and the tracing module is turned off.
[0023] In one embodiment, the method further includes:
[0024] When the target instruction reaches the memory access stage of the pipeline, the key status signals of the processor are acquired;
[0025] When all the key status signals indicate that the processor can enter low-power mode, the low-power signal corresponding to the low-power mode flag is sent to the processor's external power management system through the system interface. The low-power signal is used to instruct the external power management system to reduce the clock frequency, shut down some clock domains, enter sleep mode, or power off.
[0026] In one embodiment, the critical status signal includes at least one of an abnormal interrupt signal, an error signal, and a debug signal;
[0027] The method further includes:
[0028] When the processor is in low-power mode and sends an interrupt, an abnormal interrupt signal is output to each of the processor's external power management systems; the abnormal interrupt signal is used to instruct each of the external power management systems to increase the clock frequency.
[0029] When the processor is in a low-power mode and an error is sent, an error signal is output to each of the processor's external power management systems; the error signal is used to instruct each of the external power management systems to increase the clock frequency.
[0030] When a debug signal is received while the processor is in low-power mode, the debug signal is output to each of the processor's external power management systems.
[0031] Secondly, this application also provides a low-power processing device, the device comprising:
[0032] A receiving module is used to receive input low-power control instructions, which are input when the instruction usage frequency of the target module in the processor meets preset conditions.
[0033] The modification module is used to modify the value of the enable bit corresponding to the target module in the configuration register to the target value based on the low-power control instruction.
[0034] A low-power control module is used to control the target module to enter a low-power mode when the value of the enable bit corresponding to the target module in the configuration register is a target value.
[0035] Thirdly, this application also provides a processor, including processor modules, wherein the processor is used to implement the method in any of the above embodiments to control a target module in the processor to enter a low-power mode.
[0036] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the methods in any of the above embodiments.
[0037] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the method in any of the above embodiments.
[0038] The aforementioned low-power processing method, apparatus, processor, medium, and program product receive an input low-power control instruction. This low-power control instruction is input when the instruction usage frequency of the target module in the processor meets a preset condition. Based on the low-power control instruction, the value of the enable bit corresponding to the target module in the configuration register is modified to a target value. When the value of the enable bit corresponding to the target module in the configuration register is the target value, the target module is controlled to enter a low-power mode. Thus, determining whether to modify the value of the enable bit corresponding to the target module in the configuration register to the target value and enter a low-power mode based on the instruction usage frequency only requires configuration based on frequency, reducing design complexity. Attached Figure Description
[0039] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0040] Figure 1 This is a schematic diagram of the processor structure in one embodiment;
[0041] Figure 2 This is a flowchart illustrating a low-power processing method in one embodiment;
[0042] Figure 3 This is a schematic diagram illustrating the configuration of registers in one embodiment;
[0043] Figure 4 This is a schematic diagram of the gated clock control logic in one embodiment;
[0044] Figure 5 This is a schematic diagram of the overall control of each target module in one embodiment;
[0045] Figure 6 This is a block diagram of a low-power processing device in one embodiment. Detailed Implementation
[0046] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0047] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.
[0048] The low-power processing method provided in this application embodiment can be applied to, for example... Figure 1 The processor shown can be a CPU and includes various modules, such as an instruction decoder, an execution unit, a general-purpose register module (GPR), a multiplication and division module (MDU), a system control conprocessor, a memory management unit (MMU), an instruction cache module (I-cache), a data cache module (D-cache), an instruction cache control module 603 (I-cache), a data cache control module 603 (D-cache), a bus interface module (BIU), a virtualization support module (located in the memory management module), a floating-point unit (FPU), a user-defined coprocessor module (UDI), an anti-tamper security module (anti-TAMPER security), a power management module (Power Manager), a debug / profiling module, and a flow trace module, etc.
[0049] Among them, the data cache related modules (data cache controller module, data cache module, and bus interface module), memory management module, shadow register module, floating-point operation module, user-defined coprocessor module, tracing module, and debugging module are not always used frequently. The frequency of instruction usage can be used to determine whether to configure the module to enter low-power mode. When the instruction usage frequency is low, the enable bit of the target module in the configuration register is modified to the target value. When the enable bit of the target module in the configuration register is the target value, the target module is controlled to enter low-power mode.
[0050] This approach determines whether to modify the enable bit of the target module in the configuration register to the target value based on the frequency of instruction usage, thus entering a low-power mode. Configuration is only required based on frequency, reducing design complexity.
[0051] In one exemplary embodiment, such as Figure 2 As shown, a low-power processing method is provided, which can be applied to... Figure 1 Taking the processor in the image as an example, the explanation includes the following steps S202 to S206. Wherein:
[0052] S202: Receive an input low-power control instruction, which is input when the instruction usage frequency of the target module in the processor meets a preset condition.
[0053] The modules in the processor are not used frequently. Users can determine whether the frequency of instruction usage of the target module in the processor is low based on the business scenario. This preset condition can be determined by the user based on the business scenario and is not a fixed value. If the frequency of instruction usage of the target module in the processor meets the preset condition, a low-power control instruction is input. This low-power operation instruction is used to instruct the corresponding module to enter the low-power mode.
[0054] S204: Based on low-power control instructions, modify the value of the enable bit corresponding to the target module in the configuration register to the target value.
[0055] The target module includes at least one of the following: data caching module, memory management module, shadow register module, floating-point operation module, user-defined coprocessor module, tracing module, and debugging module.
[0056] When there are few user storage instructions and few load and store operations, the enable bit of the data caching module in the configuration register can be modified to the target value.
[0057] The memory management module includes root mode (host) and guest mode, specifically comprising the Root Mode Protection Unit (RPU), the Client Address Translation Buffer (GTLB), and the Root Address Translation Buffer (RTLB). When the TLB is not needed, it can be disabled, thereby setting the enable bit corresponding to the TLB in the memory management module's configuration register to the target value.
[0058] In traditional processor designs, when an interrupt or exception occurs (such as a system call or hardware interrupt), the CPU needs to switch from user mode to kernel mode. To save context, the processor must: save the values of all general-purpose registers (GPRs) to memory (the stack); execute the interrupt service routine (ISR); and restore the previously saved GPR values from memory after interrupt handling. This "save-restore" process requires numerous memory read / write operations and is time-consuming, especially for high-frequency, high-priority interrupts, which can severely impact system performance. To address this issue, this application introduces multiple independent copies of shadow register modules. When interrupts and exceptions occur, or when exceptions are nested, multiple sets of shadow register modules are available, enabling hardware-level context switching optimization, reducing operations, and lowering power consumption. When shadow register modules are not needed, their clocks can be turned off, allowing modification of the corresponding enable bit in the configuration register to the target value.
[0059] When there are few user arithmetic instructions, the floating-point arithmetic module can modify the value of the enable bit corresponding to the floating-point arithmetic module in the configuration register to the target value.
[0060] User-defined coprocessor modules are user-defined. When there are few user-defined instructions, the enable bit corresponding to the user-defined coprocessor module in the configuration register can be modified to the target value.
[0061] If the user does not enable debug mode, the debug module will enable the gated clock. If the user does not enable debug mode, the tracing module will modify the enable bit corresponding to the debug module in the configuration register to the target value.
[0062] Therefore, when the frequency of instruction usage for the corresponding module is less than the threshold, the value of the enable bit corresponding to that module in the configuration register is modified to the target value.
[0063] Specifically, for ease of understanding, combined with Figure 3 As shown, Figure 3 This is a schematic diagram of a configuration register in one embodiment, used to determine whether a module enters a low-power mode. Fields of the configuration register include enable bits for each target module. In some alternative embodiments, the fields of the configuration register also include the gated clock frequency of the tracking module.
[0064] The following explanation uses the target module, which includes data caching modules, memory management modules, shadow register modules, floating-point operation modules, user-defined coprocessor modules, tracing modules, and debugging modules, as an example.
[0065] The reserved bits can be used for expansion.
[0066] Lsu_cen (load store unit clock enable) is used to control the low-power mode of the LSU unit.
[0067] Tlb_cen (tlb unit clock enble) is used to control the low-power mode of the TLB to be enabled.
[0068] Sreg_cen (shadow register clock enable) is used to control the low-power mode of the shadow register module.
[0069] Fpu_cen (Floating-point Unit clock enable) is used to control the low-power mode of the floating-point unit.
[0070] UDI_cen (CorExtend User-Defined Instruction clock enable) is used to control the low-power mode of the user-defined instruction clock module.
[0071] Debug_cen (debug module clock enable) is used to control the low-power mode of the debug module.
[0072] Clk_ratio (trace mode clock ratio) is used to control the gated clock frequency of the tracing module. When Clk_ratio=0, the tracing module uses the system clock. When Clk_ratio=1, the tracing module reduces its frequency to 1 / 2 of the system clock. When Clk_ratio=2, the tracing module reduces its frequency to 1 / 4 of the system clock. Other values can also be set in other embodiments, and no specific limitation is made here.
[0073] S206: When the value of the enable bit corresponding to the target module in the configuration register is the target value, control the target module to enter the low-power mode.
[0074] The configuration register is used to control the corresponding target module to enter low-power mode. For example, if the enable bit of the target module in the configuration register is set to the target value, the target module enters low-power mode. Modules in low-power mode do not need to have their clock turned on when not in operation; the clock is only turned on when the module is in operation.
[0075] The aforementioned low-power processing method receives an input low-power control instruction, which is input when the instruction usage frequency of the target module in the processor meets a preset condition. Based on the low-power control instruction, the value of the enable bit corresponding to the target module in the configuration register is modified to a target value. When the value of the enable bit corresponding to the target module in the configuration register is the target value, the target module is controlled to enter a low-power mode. In this way, determining whether to modify the value of the enable bit corresponding to the target module in the configuration register to the target value and enter the low-power mode based on the instruction usage frequency only requires configuration based on frequency, reducing design complexity.
[0076] In some optional embodiments, after controlling the target module to enter the low-power mode, the method further includes: enabling the corresponding clock of the target module when data input is detected in the target module entering the low-power mode; and turning off the corresponding clock of the target module entering the low-power mode when it is determined that there is no input data or output data in the target module entering the low-power mode and the internal state machine of the target module entering the low-power mode is in the IDLE state.
[0077] Combination Figure 4 As shown, the default values of the enable bits corresponding to each target module in the configuration register are used to disable the input data detection module, state machine state detection module, and output data detection module. That is, when not in low-power mode, the clock of the target module is normal and requires no intervention. When the enable bit of the target module in the configuration register has a target value, that is, when the target module enters low-power mode, the input data detection module, state machine state detection module, and output data detection module of that target module are enabled to detect whether the target module needs to work, and thus, when the target module is working, the corresponding clock is turned on.
[0078] The control logic for the gated clock in each module is as follows: when there is data input to the target module, the gated clock is enabled, such as... Figure 4 If the input data detection module detects that there is input data in the module, the gate clock will have an enable signal, thus turning on the clock of the module and enabling the module to work normally.
[0079] Furthermore, when the target module enters a low-power mode, the input data detection module, state machine state detection module, and output data detection module of the target module all operate normally. These modules are used to detect the input data, output data, and internal state machine state of the target module. Based on the state of these three components, the system determines whether to disable the gating clock. For example, if the target module has no input or output data and its internal state machine is in the IDLE state, the gating clock of the module is disabled. The IDLE state includes idle state, waiting state, or sleep state.
[0080] For ease of understanding, combined with Figure 5 As shown, Figure 5 This is a schematic diagram of the overall control of each target module in one embodiment.
[0081] In some optional embodiments, the data cache related module includes a data cache controller module, a data cache module, and a bus interface module; when a data input is detected in the target module that has entered the low-power mode, the gated clock of the target module is enabled, including: when the target module is a data cache related module and a data input is detected in the target module that has entered the low-power mode, the gated clock of the data cache controller module, the data cache module, and the bus interface module is enabled.
[0082] Users can configure whether to enable the low-power mode of a module based on the frequency of use of various types of instructions. When low-power mode is enabled, if the user has few storage-related instructions and few load and store-related operations, the low-power mode of the data cache module (LSU) can be enabled. In low-power mode, the enable signal of the relevant gate clock is off by default, and the corresponding input data detection module, state machine state detection module, and output data detection module all operate normally. When the input data detection module detects data access, the clock enable of the data cache controller module (Dcache controller), the data cache RAM module (Dcache RAM), and the write buffer of the bus interface module (BIU) will go high. When there is no input or output data related to the data cache module (LSU), and the state machine of the data cache module (LSU) is in the Idle state, the clock enable of the data cache controller module (Dcache controller), the data cache RAM module (Dcache RAM), and the write buffer of the bus interface module (BIU) will go low, thus these modules will not work, meaning they only operate when needed, reducing energy consumption.
[0083] If the user has relatively few floating-point operation instructions, a low-power mode for the floating-point unit (FPU) can be configured. In low-power mode, the clock enable is initially off. When the FPU receives data input, i.e., when the corresponding input data detection module detects the input data, the FPU's gated clock is pulled high. Then, based on the presence or absence of input and output data and the FPU's internal state, the system dynamically determines whether to disable the gated clock, thus preventing the FPU from working. In other words, the FPU only operates when needed, reducing energy consumption.
[0084] The instructions of the user-defined coprocessor module are user-defined. When the data corresponding to the user-defined instruction exists, that is, when the corresponding data detection module detects the user-defined instruction, the gated clock of the user-defined coprocessor module is enabled. Then, based on the input data, output data and internal state of the user-defined coprocessor module, it is determined whether to disable the gated clock. Thus, the user-defined coprocessor module no longer works, that is, it only works when needed, reducing energy consumption.
[0085] In this application, one EntryLo corresponds to two EntryLo entries in the TLB: EntryLo0 and EntryLo1. One TLB entry can describe a larger storage space. A larger page means fewer page boundaries, thereby reducing the probability of TLB Miss due to cross-page access, reducing the number of TLB accesses, and thus reducing TLB power consumption. Furthermore, by modifying the enable bit of the configuration register to the target value, the module enters a low-power mode. When the TLB is not needed, i.e., when the input data detection module and output data detection module corresponding to the TLB have not detected any data, and the state machine state detection module confirms that the state is IDLE, the TLB gate clock enable can be turned off to shut down the TLB clock.
[0086] In some optional embodiments, the target module is at least one set of independent shadow registers; when data input is detected in the target module entering low-power mode, the gating clock of the target module is enabled, including: when an interrupt or exception is detected, the gating clock of at least one set of independent shadow registers is enabled, and the at least one set of independent shadow registers is used for hardware-level context switching.
[0087] In this application, the "save-restore" process during interruptions or exceptions (such as system calls or hardware interrupts) requires numerous memory read / write operations, resulting in significant time consumption. This is particularly problematic for high-frequency, high-priority interrupts, which can severely impact system performance. This embodiment addresses this issue by introducing multiple independent copies of shadow register modules. When interruptions or exceptions occur, or when exceptions are nested, multiple sets of shadow register modules are available, enabling hardware-level context switching optimization and reducing operations. When shadow register modules are not needed, their clocks can be disabled, allowing for the configuration of corresponding gated clocks.
[0088] Specifically, the enable bit corresponding to the shadow register module in the configuration register can be modified to the target value, that is, the shadow register module enters the low power mode. When the input data detection module detects an interrupt or abnormality, the gate clock corresponding to the shadow register module is enabled, so that the shadow register module works normally. When neither the input data detection module nor the output data detection module corresponding to the shadow register module detects data, and the state machine state detection module confirms that the state is IDLE, the gate clock enable of the shadow register module can be turned off to turn off the clock of the shadow register module.
[0089] In some optional embodiments, the configuration register further includes a frequency setting bit for the tracking module; the method further includes: configuring the gating clock enable of the debugging module and the tracking module when a debugging signal is detected; controlling the clock frequency of the tracking module based on the frequency setting bit of the tracking module in the configuration register; and disabling the gating clock enable of the debugging module and the tracking module when the debugging module is detected to have exited the debugging mode.
[0090] In this application, when the debug module and trace module are in low-power mode, the corresponding debug mode detection module starts working. When the debug mode detection module detects that the processor has switched to debug mode, it will enable the gated clock of the debug module and trace module. That is, the debug mode detection module outputs a signal to enable the gated clock of the debug module and trace module, so that the debug module and trace module can work normally. When the trace module is enabled, the user can set the clock frequency of the trace module as needed, and can reduce the frequency of the trace module to 1 / 2 or 1 / 4 of the system clock. When the debug mode detection module detects that the processor has exited debug mode, it outputs a signal to disable the gated clock of the debug module and trace module to reduce power consumption.
[0091] The above embodiments are optimizations for low power consumption within the processor during operation. This application also optimizes power management at the SoC application layer. Specifically, in some optional embodiments, the method further includes: acquiring key status signals of the processor when the target instruction reaches the memory access stage of the pipeline; and, when all key status signals indicate that the processor can enter a low-power mode, sending the low-power signal corresponding to the low-power mode flag bit of the configuration register to each external power management system of the processor through the system interface. The low-power signal is used to instruct each external power management system to reduce the clock frequency, shut down some clock domains, enter a sleep state, or power off.
[0092] The Low Power Mode Flag (RP) enables a standard software mechanism to put the system into low power mode. It works in conjunction with the MIPS WAIT instruction. When the WAIT instruction reaches the M stage (memory access stage) of the pipeline, it pauses the internal clock and freezes the pipeline based on the bus status. The state of the RP flag can be transmitted externally via the SI_RP signal in the system interface. When the RP bit in the configuration register is set to 1, SI_RP = 1. Combined with critical system status signals, this enables low-power information communication between the processor and the external power management system.
[0093] Specifically, when the target instruction reaches the memory access stage of the pipeline, the processor's key status signals are obtained. If all key status signals indicate that the processor can enter low-power mode, the low-power mode flag is sent to each external power management system through the system interface, thereby causing each external power management system to reduce the clock frequency, shut down some clock domains, enter sleep mode, or power off.
[0094] The SI_RP signal acts as a power-saving request signal, telling the external power management system (such as a PMU) that the CPU needs to conserve power. The process involves the software setting the value of RP and simultaneously executing a wait instruction, causing the CPU to enter an idle state. The external system can then use this to: reduce the system's main clock frequency, disable some clock domains, enter deep sleep, or power off.
[0095] In some alternative embodiments, the critical status signals include at least one of the exception interrupt signal SI_EXL, the error signal SI_ERL, and the debug signal EJ_DebugM.
[0096] The method further includes: when an interrupt is sent while the processor is in a low-power mode, outputting an abnormal interrupt signal to each of the processor's external power management systems; the abnormal interrupt signal is used to instruct each of the external power management systems to increase the clock frequency; when an error is sent while the processor is in a low-power mode, outputting an error signal to each of the processor's external power management systems; the error signal is used to instruct each of the external power management systems to increase the clock frequency; and when a debug signal is received while the processor is in a low-power mode, outputting a debug signal to each of the processor's external power management systems.
[0097] When an interrupt occurs while the device is in low-power mode, the exception interrupt signal SI_EXL will go high; when an error occurs, the error signal SI_ERL will go high; and when entering debug mode, the debug signal EJ_DebugM will be output. When the external power management system detects SI_EXL=1 or SI_ERL=1, it can increase the clock frequency to quickly respond to interrupts or handle errors. After processing, the frequency can be decreased again. When the external power management system detects the debug signal EJ_DebugM=1, it will increase the clock frequency to facilitate debugging.
[0098] In the above embodiments, communication between the processor and the external power management system can be achieved through configured key status signals, enabling rapid response in the event of interruptions, errors, or debugging.
[0099] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.
[0100] Based on the same inventive concept, this application also provides a low-power processing apparatus for implementing the low-power processing method described above. The solution provided by this apparatus is similar to the implementation scheme described in the above method; therefore, the specific limitations in one or more low-power processing apparatus embodiments provided below can be found in the limitations of the low-power processing method described above, and will not be repeated here.
[0101] In one exemplary embodiment, such as Figure 6 As shown, a low-power processing device is provided, including: a receiving module 601, a modification module 602, and a low-power control module 603, wherein:
[0102] The receiving module 601 is used to receive input low-power control instructions, which are input when the instruction usage frequency of the target module in the processor meets preset conditions.
[0103] Modify module 602 to modify the value of the enable bit corresponding to the target module in the configuration register to the target value based on low-power control instructions;
[0104] The low-power control module 603 is used to control the target module to enter a low-power mode when the value of the enable bit corresponding to the target module in the configuration register is the target value.
[0105] In one optional embodiment, the device further includes: a door clock control module, configured to enable the corresponding clock of the target module when data input is detected in the target module entering the low-power mode; and to disable the corresponding clock of the target module entering the low-power mode when it is determined that there is no input data or output data in the target module entering the low-power mode and the internal state machine of the target module entering the low-power mode is in the IDLE state.
[0106] In one optional embodiment, the target module includes at least one of a data caching module, a memory management module, a shadow register module, a floating-point arithmetic module, a user-defined coprocessor module, a tracing module, and a debugging module.
[0107] In one optional embodiment, the data caching related modules include a data caching controller module, a data caching module, and a bus interface module;
[0108] The aforementioned door clock control module is specifically used to control the clock enable of the data cache controller module, the data cache module, and the bus interface module when the target module is a data cache related module and data input is detected in the target module that has entered low power mode.
[0109] In one optional embodiment, the target module is at least one set of independent shadow registers; the aforementioned gate clock control module is specifically used to control the clock enable corresponding to at least one set of independent shadow registers when an interrupt or abnormality is detected, and at least one set of independent shadow registers is used for hardware-level context switching.
[0110] In one optional embodiment, the configuration register further includes a frequency setting bit for the tracking module; the aforementioned gate clock control module is specifically used to configure the clock enable corresponding to the debugging module and the tracking module when a debugging signal is detected; control the clock frequency of the clock corresponding to the tracking module based on the frequency setting bit of the tracking module in the configuration register; and disable the clock enable corresponding to the debugging module and the tracking module when the debugging module is detected to have exited the debugging mode.
[0111] In one optional embodiment, the above-mentioned device further includes: a first output module, configured to acquire key status signals of the processor when the target instruction reaches the memory access stage of the pipeline; and when all key status signals indicate that the processor can enter a low-power mode, send the low-power signal corresponding to the low-power mode flag bit to the processor's external power management system through the system interface, wherein the low-power signal is used to instruct the external power management system to reduce the clock frequency, shut down some clock domains, enter a sleep state, or power off.
[0112] In one optional embodiment, the critical status signal includes at least one of an abnormal interrupt signal, an error signal, and a debug signal; the device further includes: a second output module, configured to output an abnormal interrupt signal to each of the processor's external power management systems when the processor is in a low-power mode and an interrupt is sent; the abnormal interrupt signal is used to instruct each of the external power management systems to increase the clock frequency; to output an error signal to each of the processor's external power management systems when the processor is in a low-power mode and an error is sent; the error signal is used to instruct each of the external power management systems to increase the clock frequency; and to output a debug signal to each of the processor's external power management systems when a debug signal is received while the processor is in a low-power mode.
[0113] Each module in the aforementioned low-power processing device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the operations corresponding to each module.
[0114] Those skilled in the art will understand that Figure 1 The processor structure shown in the figure is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.
[0115] In one embodiment, a processor is also provided, including modules, the processor being configured to implement the method in any of the above embodiments to control a target module in the processor to enter a low-power mode.
[0116] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.
[0117] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.
[0118] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.
[0119] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.
[0120] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.
Claims
1. A low-power processing method, characterized in that, The method includes: Receive input low-power control instructions, which are input when the instruction usage frequency of the target module in the processor meets preset conditions; Based on the low-power control instruction, the value of the enable bit corresponding to the target module in the configuration register is modified to the target value; When the value of the enable bit corresponding to the target module in the configuration register is the target value, the target module is controlled to enter a low-power mode. The target module includes at least one of the following: a data caching module, a memory management module, a shadow register module, a floating-point operation module, a user-defined coprocessor module, a tracing module, and a debugging module. The configuration register further includes a frequency setting bit for the tracking module; the method further includes: Upon detecting a debug signal, enable the clocks corresponding to the debug module and the tracking module. Based on the frequency setting bit of the tracking module in the configuration register, the clock frequency of the clock corresponding to the tracking module is controlled; If the debugging module is detected to have exited the debugging mode, the clock enable corresponding to the debugging module and the tracing module shall be turned off. The method further includes: When the target instruction reaches the memory access stage of the pipeline, the key status signals of the processor are acquired; When all the key status signals indicate that the processor can enter low power mode, the low power signal corresponding to the low power mode flag is sent to the processor's external power management system through the system interface. The low power signal is used to instruct the external power management system to reduce the clock frequency, turn off some clock domains, enter sleep mode, or power off mode. The critical status signals include at least one of abnormal interruption signals, error signals, and debug signals; The method further includes: When the processor is in low-power mode and sends an interrupt, an abnormal interrupt signal is output to each of the processor's external power management systems; the abnormal interrupt signal is used to instruct each of the external power management systems to increase the clock frequency. When the processor is in a low-power mode and an error is sent, an error signal is output to each of the processor's external power management systems; the error signal is used to instruct each of the external power management systems to increase the clock frequency. When a debug signal is received while the processor is in low-power mode, the debug signal is output to each of the processor's external power management systems.
2. The method according to claim 1, characterized in that, After the target module is controlled to enter a low-power mode, the following steps are included: If data input is detected in the target module that has entered low-power mode, the corresponding clock of the target module is enabled. If it is determined that the target module entering low-power mode has no input or output data, and the internal state machine of the target module entering low-power mode is in the IDLE state, the clock corresponding to the target module entering low-power mode is turned off.
3. The method according to claim 1, characterized in that, The data caching related modules include a data caching controller module, a data caching module, and a bus interface module; The step of enabling the corresponding clock of the target module when data input is detected in the target module that has entered low-power mode includes: When the target module is a data cache-related module, and data input is detected in the target module that has entered low-power mode, the clocks of the data cache controller module, the data cache module, and the bus interface module are enabled.
4. The method according to claim 1, characterized in that, The target module is at least one independent shadow register; the step of controlling the corresponding clock enable of the target module when data input is detected in the target module entering low-power mode includes: In the event of an interrupt or anomaly, the clock corresponding to the at least one set of independent shadow registers is enabled, and the at least one set of independent shadow registers is used for hardware-level context switching.
5. A low-power processing apparatus applied to the low-power processing method of claim 1, characterized in that, The device includes: A receiving module is used to receive input low-power control instructions, which are input when the instruction usage frequency of the target module in the processor meets preset conditions. The modification module is used to modify the value of the enable bit corresponding to the target module in the configuration register to the target value based on the low-power control instruction. A low-power control module is used to control the target module to enter a low-power mode when the value of the enable bit corresponding to the target module in the configuration register is a target value.
6. The apparatus according to claim 5, characterized in that, The device further includes: The door clock control module is used to enable the corresponding clock of the target module when it detects that there is data input in the target module that has entered the low-power mode; and to turn off the corresponding clock of the target module that has entered the low-power mode when it is determined that there is no input data or output data in the target module that has entered the low-power mode, and the internal state machine of the target module that has entered the low-power mode is in the IDLE state.
7. The apparatus according to claim 6, characterized in that, The data caching related modules include a data caching controller module, a data caching module, and a bus interface module; The door clock control module is specifically used to control the clock enable of the data cache controller module, the data cache module, and the bus interface module when the target module is a data cache related module and data input is detected in the target module that has entered low power mode.
8. A processor, comprising processor modules, characterized in that, The processor is used to implement the method of any one of claims 1 to 4 to control the target module in the processor to enter a low-power mode.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 4.
10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 4.