A dynamic scheduling system and method for prediction models based on heterogeneous computing platforms

Abstract

This invention relates to the field of heterogeneous computing technology, specifically to a dynamic scheduling system and method for prediction models based on a heterogeneous computing platform. The prediction model runs on an edge host, abstracting computationally intensive operators in the model into candidate offload tasks. A time cost model is constructed, incorporating host execution time, FPGA execution time, and transmission overhead, and dynamically updated based on execution statistics. The scheduling module compares the estimated completion time of the local machine with that of the offload path based on the time cost model, selecting whether to execute the prediction task on the host or the FPGA. A page-locked DMA buffer is set in the system memory, allowing the FPGA to directly read and write historical data. Tasks are scheduled on the FPGA according to priority and deadline, and the time cost model is corrected in a closed-loop manner using traditional calculations. Compared with existing technologies, this invention can dynamically adapt to changes in lighting conditions and system load, reducing the average inference latency and high quantile tail latency of tasks, and improving the performance and stability of edge-side photovoltaic power prediction.

Description

Technical Field

[0001] This invention relates to the fields of photovoltaic power prediction and heterogeneous computing technology, and in particular to a dynamic scheduling system and method for photovoltaic prediction xLSTM models based on edge hosts and FPGAs. Background Technology

[0002] Large-scale photovoltaic power plants and distributed photovoltaic scenarios generally require prediction of photovoltaic output power for the next few minutes to tens of minutes to support smooth power control, energy storage scheduling, and safe grid operation. To improve prediction accuracy, more and more systems are using deep learning models based on Long Short-Term Memory (LSTM) networks and their extended structures (such as xLSTM) to model multi-source time series data such as historical power, irradiance, and temperature.

[0003] In practical engineering, photovoltaic forecasting is often deployed on edge devices near substations, control centers, or inverters. Due to power consumption and size constraints, edge devices typically use embedded GPU boards as the main processing platform. Meanwhile, to further improve inference performance, coprocessors such as FPGAs are being introduced to accelerate some computations. However, xLSTM models have complex structures and large parameter counts. If all are executed sequentially on the Jetson edge computing host, problems such as high inference latency and unstable tail latency can easily occur. Simply offloading certain layers to the FPGA can lead to low resource utilization when the load changes or link bandwidth fluctuates, and may even cause the offloading process to slow down the process.

[0004] In existing heterogeneous computing solutions, the common practice is to use static partitioning or simple threshold strategies to allocate tasks, which lacks fine-grained scheduling for workloads with strong periodic and real-time requirements, such as photovoltaic forecasting. In data interaction between the host and FPGA, intermediate buffers and multiple copies are still widely used, resulting in large PCIe transmission overhead. On the FPGA side, task scheduling often only considers fixed priorities, making it difficult to dynamically sort multiple photovoltaic forecasting requests by combining the forecast period's deadline and queue status.

[0005] Therefore, there is an urgent need for a heterogeneous dynamic scheduling system and method that can simultaneously balance inference accuracy and real-time performance for photovoltaic prediction scenarios. Summary of the Invention

[0006] The purpose of this invention is to address the current difficulty in balancing inference accuracy and real-time performance on heterogeneous computing platforms, and to provide a dynamic scheduling system and method for prediction models based on heterogeneous computing platforms.

[0007] The objective of this invention can be achieved through the following technical solutions:

[0008] As a first aspect of the present invention, a predictive model dynamic scheduling system based on a heterogeneous computing platform is provided, including an edge host and an FPGA coprocessor connected via a PCIe bus.

[0009] The edge host runs a prediction model and is configured with: a task feature extraction module, which abstracts computationally intensive operators in the prediction model into candidate offload prediction tasks; a runtime cost modeling module, which maintains a runtime time cost model including host execution time, FPGA execution time, and transmission overhead; a scheduling decision module, which compares the estimated completion time of candidate offload prediction tasks on the local path and the offload execution path based on the runtime time cost model, and dynamically selects the edge host or FPGA coprocessor for execution; a task descriptor construction and distribution module, which generates prediction task descriptors for prediction tasks selected for the offload execution path; a DMA buffer and page-locked memory management module, which pre-allocates input and output buffers on the edge host through the CUDA page-locked memory mechanism; and a closed-loop statistical feedback module, which updates the runtime time cost model parameters online based on the actual execution time and transmission time of the prediction tasks.

[0010] The FPGA coprocessor is configured with: a task receiving and parsing module, which receives and parses the prediction task descriptor; a task queue and scheduling module, which schedules tasks to be executed according to priority and time margin before the deadline; a DMA access module, which reads input data from the page-locked memory of the edge host according to the buffer address in the task descriptor and writes the prediction result back to the corresponding output buffer; and an execution statistics module, which records the task execution statistics of the FPGA coprocessor and returns them to the edge host through the PCIe bus.

[0011] The edge host and the FPGA coprocessor exchange prediction task descriptors, DMA buffer addresses, execution results, and statistics via the PCIe bus.

[0012] As a preferred technical solution, the runtime cost modeling module obtains initial estimates of the host local execution time, FPGA execution time, and PCIe transmission time through a preheating task;

[0013] For edge hosts and FPGA coprocessors, their execution time estimates are multiplied by the ratio of the task size to the preset baseline computing size to obtain the corresponding predicted execution time.

[0014] For PCIe transfer time, the estimated PCIe transfer time is multiplied by the ratio of the output / input data size to the baseline data size to obtain the corresponding data output / input transfer time.

[0015] During dynamic scheduling, based on the observed actual execution time and transmission time, the cost modeling module updates the estimated parameters of host local execution time, FPGA execution time and PCIe transmission time in the runtime time cost model using an exponentially weighted moving average method, and adaptively adjusts the weight coefficients during the update according to the task queue length or resource utilization of the edge host and FPGA coprocessor.

[0016] As a preferred technical solution, when the scheduled task arrives, the scheduling decision module adds the edge host execution time predicted by the runtime time cost model to the estimated host-side queue waiting time to obtain the predicted completion time of the local execution path.

[0017] The predicted completion time of the unloading execution path is obtained by adding the estimated values ​​of FPGA execution time, data output transmission time, data input transmission time, and FPGA-side queue waiting time predicted by the runtime time cost model.

[0018] If the predicted completion time of the unloading execution path plus the preset safety margin is less than the predicted completion time of the local execution path, and the task queue length of the FPGA coprocessor does not exceed the preset threshold, the predicted task is classified as an unloading task; otherwise, the predicted task is classified as a local execution task.

[0019] As a preferred technical solution, the DMA buffer and page-locked memory management module pre-allocates input and output buffers on the edge host through the CUDA page-locked memory mechanism; it stores data including historical time series and prediction results in the page-locked memory buffer and provides the physical address or I / O virtual address of the buffer to the task descriptor construction and distribution module, so that the DMA access module of the FPGA coprocessor can directly access the buffer.

[0020] As a preferred technical solution, the task descriptor construction and distribution module encapsulates the input buffer address and length, output buffer address and length, task size, prediction period, prediction period deadline, and task priority fields of the prediction task into a task descriptor, and distributes it to the FPGA coprocessor through the PCIe bus.

[0021] As a preferred technical solution, when the task descriptor construction and distribution module detects that there are multiple prediction tasks with a scale lower than a preset threshold and belonging to the same prediction period, it merges the multiple prediction tasks into a batch processing task and distributes it to the FPGA coprocessor in the form of a single task descriptor.

[0022] As a preferred technical solution, the task queue and scheduling module inserts the parsed prediction task into the task queue; uses the weighted sum of task priority and the reciprocal of the task deadline margin as the calculation scheduling weight; and selects prediction tasks from the task queue according to the scheduling weight and assigns them to multiple parallel computing cores inside the FPGA coprocessor for execution.

[0023] As a preferred technical solution, the execution statistics module is used to collect the actual execution time, DMA transfer time and queue waiting time of each prediction task on the FPGA coprocessor, and transmit them back to the edge host through the PCIe bus. The closed-loop statistics feedback module then centrally summarizes and provides them to the runtime cost modeling module.

[0024] As a preferred technical solution, the internal hardware resources of the edge host include a multi-core CPU, a GPU acceleration unit, and system memory;

[0025] The multi-core CPU is used to run the task feature extraction module, runtime cost modeling module, scheduling decision module, DMA buffer and page locking memory management module, task descriptor construction and distribution module, closed-loop statistical feedback module, and control logic for deep learning model prediction and inference.

[0026] The GPU acceleration unit is used to execute the xLSTM model operators that have not been unloaded;

[0027] The page-locked buffers in the system memory are accessed by both the GPU and the FPGA coprocessor connected via PCIe.

[0028] As a second aspect of the present invention, a dynamic scheduling method for photovoltaic prediction models based on a heterogeneous computing platform is provided. The method employs the dynamic scheduling system described above, and the steps include:

[0029] Historical time series data are collected on edge hosts to construct the input tensor of the prediction model. During the inference process of the prediction model, computationally intensive operators are abstracted into prediction tasks for candidate unloading, and task features including task size, input and output data size, prediction period, task priority and deadline are obtained.

[0030] On the edge host, based on the actual execution time and transmission time of the completed prediction tasks, establish and maintain a runtime time cost model that includes host execution overhead, FPGA execution overhead and PCIe transmission overhead;

[0031] When the predicted task reaches the scheduling point, the runtime time cost model is invoked to predict the completion time of the task on the local execution path of the edge host and on the offload execution path of the FPGA, respectively.

[0032] Based on the completion time prediction results, the preset safety margin, and the FPGA coprocessor task queue length, the predicted tasks are divided as follows: when the sum of the predicted completion time of the unloading execution path and the preset safety margin is less than the predicted completion time of the local execution path, and the task queue length does not exceed the preset threshold, the predicted task is divided into an unloading task; otherwise, it is divided into a local execution task. Multiple small-scale tasks that meet the preset conditions are then batch-processed and merged.

[0033] For prediction tasks that are classified as offloading tasks, input and output buffers are allocated in the page-locked memory of the edge host, the corresponding historical data is written into the input buffer, a task descriptor containing buffer address information and task characteristics is generated, and then sent to the FPGA coprocessor via the PCIe bus.

[0034] The task descriptor is received and parsed on the FPGA coprocessor side, the corresponding prediction task is inserted into the task queue, and the scheduling weight is calculated based on the task priority and deadline margin. The task is then assigned to the parallel computing core for execution according to the scheduling weight. Input data is read from the page-locked memory of the edge host according to the buffer address, and the prediction result is written back to the corresponding output buffer.

[0035] After the prediction task is completed, execution statistics including actual execution time, DMA transfer time and queue waiting time are recorded on the FPGA coprocessor side. The execution statistics are fed back to the edge host through the PCIe bus and provided to the runtime cost modeling module along with the actual execution time of the task executed locally on the host, so as to update the runtime time cost model parameters online.

[0036] Compared with the prior art, the present invention has the following beneficial effects:

[0037] This invention tightly couples the time cost model, DMA zero-copy, and FPGA scheduling through closed-loop statistical feedback: the actual execution time and PCIe transmission time of the photovoltaic prediction task on the host and FPGA are fed back to the host by the execution statistics module to update the runtime time cost model; the updated time cost model directly affects whether each deep learning model computation unit is unloaded, whether it is batched and merged, and how the DMA buffer is configured in subsequent prediction cycles; the task partitioning and batch processing method between the host and FPGA changes the data distribution of the next round of statistical feedback, thus forming an adaptive closed loop of "task execution → statistical feedback → time cost model update → scheduling strategy adjustment → task execution". In typical photovoltaic scenarios, this closed-loop mechanism can automatically adjust the offloading ratio and task aggregation granularity when the load increases suddenly or the link bandwidth decreases, stabilizing the average latency and tail latency performance. While ensuring that the accuracy of the photovoltaic prediction xLSTM model remains unchanged, it can dynamically adapt to changes in illumination conditions and system load, improve the overall utilization rate of the edge host and FPGA coprocessor, and enhance the overall performance and stability of the edge-side photovoltaic power prediction system. Attached Figure Description

[0038] Figure 1 A schematic diagram of the structure of a dynamic scheduling system for photovoltaic prediction models based on a heterogeneous computing platform provided in an embodiment of the present invention;

[0039] Figure 2 A flowchart illustrating the dynamic scheduling method for photovoltaic prediction models provided in an embodiment of the present invention;

[0040] Figure 3 This is a schematic diagram of the photovoltaic prediction task queue and scheduling on the FPGA side in an embodiment of the present invention;

[0041] Figure 4 This is a schematic diagram comparing the CPU utilization over time between the static scheduling scheme and the dynamic scheduling scheme of this invention in an embodiment of the invention. Detailed Implementation

[0042] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. These embodiments are based on the technical solution of the present invention and provide detailed implementation methods and specific operating procedures. However, the scope of protection of the present invention is not limited to the following embodiments.

[0043] Example 1

[0044] The dynamic scheduling system for the photovoltaic prediction model in this embodiment is deployed on a heterogeneous computing platform. It consists of an edge host and an FPGA coprocessor connected via PCIe. The edge host runs a deep learning model for photovoltaic power prediction, abstracting computationally intensive operators into candidate offload tasks for photovoltaic prediction. A runtime time cost model is constructed, including host execution time, FPGA execution time, and transmission overhead, and updated online using execution statistics. The scheduling module compares the estimated completion time of the local machine with the offload path based on the runtime time cost model, dynamically selecting whether to execute on the host or the FPGA. A page-locked DMA buffer is set in the system memory, allowing the FPGA to directly read and write historical photovoltaic data. The FPGA schedules tasks according to priority and deadline and returns them to the traditional calculation, achieving closed-loop correction of the runtime time cost model.

[0045] Specifically, such as Figure 1 As shown, the edge host uses Jetson Orin NX to run a deep learning model for photovoltaic power prediction. The edge host internally includes hardware resources such as a multi-core CPU, a GPU acceleration unit, and system memory. The multi-core CPU is used to run the photovoltaic task feature extraction module, runtime cost modeling module, scheduling decision module, DMA buffer and page-locked memory management module, task descriptor construction and distribution module, closed-loop statistical feedback module, and control logic for xLSTM photovoltaic prediction inference. The GPU acceleration unit is used to execute the xLSTM model operators that are not unloaded. The page-locked buffer in the system memory is accessed by both the GPU and the FPGA coprocessor connected via PCIe. The FPGA coprocessor uses a VD100, which implements logic for task reception and parsing, task queuing and scheduling, DMA access, and execution statistics.

[0046] In this embodiment, the Jetson Orin NX edge host side includes:

[0047] The photovoltaic task feature extraction module is used to abstract several matrix multiplications and gating unit operations in each prediction cycle into several candidate unloading tasks during the xLSTM model inference process, and record information such as the time step index, input feature dimension, batch size, and task scale (e.g., the number of floating-point operations) corresponding to the task.

[0048] The runtime cost modeling module is used to maintain a runtime time cost model that includes parameters such as host execution time, FPGA execution time, and PCIe transmission latency, based on the execution statistics of historical prediction tasks.

[0049] The scheduling decision module is used to compare the estimated completion time of each candidate offloaded task when executed locally on the edge host versus when offloaded to the FPGA, based on the runtime time cost model, and taking into account the FPGA queue length and the predicted cycle deadline, to determine the execution location of the task and whether it should participate in batch processing.

[0050] The DMA buffer and page-locked memory management module is used to allocate a set of DMA-accessible buffers on the Jetson Orin NX edge host via the CUDA page-locked memory interface. These buffers are used to store time-series data such as historical power, irradiance, and temperature of photovoltaics, as well as prediction results.

[0051] The task descriptor construction and distribution module is used to encapsulate information such as the input and output buffer addresses, task size, prediction period, and task priority of the photovoltaic prediction task into task descriptors, and distribute them to the FPGA coprocessor via the PCIe bus.

[0052] The closed-loop statistical feedback module is used to receive execution statistics from the FPGA coprocessor and provide them to the runtime cost modeling module to update the runtime time cost model parameters.

[0053] In this embodiment, the FPGA coprocessor VD100 side includes:

[0054] The task receiving and parsing module is used to receive and parse task descriptors from the edge host Jetson Orin NX to obtain information such as the input and output buffer addresses, task size, prediction period deadline, and priority of each photovoltaic prediction task.

[0055] The task queue and scheduling module is used to insert the parsed photovoltaic prediction tasks into the task queue, calculate the scheduling weight based on the task priority and the time margin before the prediction period deadline, and allocate task execution among multiple parallel computing cores.

[0056] The DMA access module drives the DMA engine inside the FPGA coprocessor. It reads input data directly from the page-locked memory of the Jetson Orin NX edge host based on the edge host input / output buffer address carried in the task descriptor, and writes the prediction result back to the corresponding output buffer after the task is completed.

[0057] The execution statistics module records the start time, end time, and DMA transfer time of the photovoltaic prediction task on the FPGA coprocessor side, and returns them to the edge host Jetson Orin NX via PCIe for closed-loop updating of the runtime time cost model.

[0058] Through the above structure, the edge host Jetson Orin NX and the FPGA coprocessor are connected via the PCIe bus, forming a closed-loop system around the photovoltaic prediction xLSTM model, which includes task abstraction and feature extraction, runtime cost modeling, dynamic scheduling decision-making, DMA zero-copy transfer, FPGA execution, statistical feedback, and time cost model update.

[0059] Example 2

[0060] As another embodiment of the present invention, this embodiment describes the working process of the present invention in photovoltaic prediction scenarios from the perspective of method flow. For example... Figure 2 As shown, a dynamic scheduling method for photovoltaic prediction models based on a heterogeneous computing platform includes the following steps:

[0061] S1: Photovoltaic forecasting task construction and feature extraction. In each forecasting period, the edge host Jetson Orin NX collects data from the photovoltaic power plant. Hourly historical power, irradiance, and temperature time-series data are used to construct the input tensor of the xLSTM model. The xLSTM forward inference process is analyzed, and computationally intensive operations such as matrix multiplication and linear transformation of gated units are divided into several candidate unloading photovoltaic prediction tasks. For each candidate unloading task, the task feature extraction module records the task scale. (e.g., the corresponding number of floating-point operations (FLOPs)) and the size of the input data. Output data size The end time of the forecast period t deadline And task priorities.

[0062] S2: Runtime Time Cost Model Initialization and Maintenance. During the system deployment phase, the edge host Jetson OrinNX obtains initial estimates of the host local execution time, FPGA execution time, and PCIe transfer time through a small number of warm-up tasks, denoted as follows: , and The runtime cost modeling module maintains runtime time cost model parameters in the following manner:

[0063] Predict host execution time:

[0064]

[0065] Predicting FPGA execution time:

[0066]

[0067] Predicted transmission time:

[0068]

[0069] in, For the task size, For data size, and These are the preset baseline calculation scale and baseline data scale, respectively. As the system runs, the closed-loop statistical feedback module continuously sends the actual measured execution time and transmission time back to the runtime cost modeling module, using an exponentially weighted moving average method to... , and Perform online updates:

[0070]

[0071] in, The actual execution time and transmission time observed in this study. This is the updated time estimate. This is the original time estimate. The weighting coefficient is between 0 and 1, and can be adaptively adjusted according to the task queue length or system load.

[0072] S3: Candidate Task Completion Time Prediction. When a candidate offloading task reaches the scheduling point within a prediction period, the scheduling decision module calls the current runtime time cost model to predict the completion time of the candidate offloading task, both when executed locally on the edge host and when offloaded to the FPGA coprocessor. The completion time can be expressed as:

[0073]

[0074]

[0075] in, For host execution time, This is an estimate of the host-side queue waiting time. , These represent the transmission time for data output and input, respectively. For FPGA execution time, This is an estimate of the queue waiting time on the FPGA coprocessor side, which can be obtained based on the current number of queued tasks and historical statistics.

[0076] S4: Photovoltaic forecasting task allocation and offloading decision; the scheduling decision module will use the results from step S3. and Compare and introduce a preset safety margin. To compensate for runtime time cost model errors. In a preferred implementation, when: And FPGA queue length If the photovoltaic prediction task is not executed, it is classified as an offload task; otherwise, it is classified as a local execution task. For multiple offload tasks that are small in scale, belong to the same prediction period, and have the same input feature dimensions, the scheduling decision module can also merge them into a batch processing task, which can be completed in subsequent steps through a single DMA transfer and a single batch calculation to reduce PCIe transaction overhead.

[0077] S5: DMA Buffer Management and Task Descriptor Distribution. On the Jetson Orin NX edge host, for the photovoltaic prediction task classified as an offload task in S4, the DMA buffer and page-locked memory management module allocates input and output buffers in a pre-allocated page-locked memory pool and copies the corresponding historical power, irradiance, and temperature time-series data to the input buffer. The task descriptor construction and distribution module generates a task descriptor, which includes the input buffer address and length, the output buffer address and length, the task size K, and the prediction period deadline. Task priority The fields are sent to the FPGA coprocessor via the PCIe bus.

[0078] S6: FPGA-side task scheduling and execution, such as Figure 3 As shown, on the FPGA coprocessor VD100 side, the task receiving and parsing module receives and parses the task descriptor, inserting the corresponding photovoltaic prediction task into the task queue. The task queue and scheduling module then schedules tasks according to their priority. and the time margin before the deadline ( Calculate scheduling weights ,take:

[0079]

[0080] in, , These are the weighting coefficients. As a task priority, To prevent tiny constants with a denominator of zero, To predict the end time of the period, The current time is displayed. The task queue and scheduling module selects tasks to be executed from high to low scheduling weights and assigns them to idle parallel computing cores. The DMA access module reads input features from the Jetson Orin NX page-locked memory on the edge host according to the buffer address in the task descriptor, drives the hardware core to execute the corresponding xLSTM operation, and writes the prediction result back to the output buffer.

[0081] S7: Performs closed-loop updates of statistical feedback and runtime time cost model. After the FPGA coprocessor completes a photovoltaic prediction task, the statistical module records the actual execution time of the task on the FPGA. DMA read / write time And the waiting time in the task queue The aforementioned statistical information is then returned to the Jetson Orin NX edge host via PCIe. After receiving the statistical information on the Jetson side, the closed-loop statistical feedback module submits it, along with the actual execution time of the task executed locally on the host, to the runtime cost modeling module. The runtime cost modeling module then uses these observations to... , and The parameters are updated, and the updated runtime time cost model is used in steps S3 and S4 of the next prediction cycle to make new completion time predictions and unloading decisions, thus forming a closed loop of task execution—statistical feedback—time cost model update—scheduling strategy adjustment—task execution.

[0082] To verify the performance improvement effect of this invention in photovoltaic prediction scenarios, different scheduling strategies were compared and evaluated on a real-world dataset from a photovoltaic power plant. In the test, both schemes used the same xLSTM model structure, input time window, and prediction time span, and were deployed on the same heterogeneous computing platform of Jetson Orin NX and FPGA VD100.

[0083] The comparison schemes include:

[0084] 1) Static scheduling scheme: During the deployment phase, a number of xLSTM layers or operators are pre-selected and fixedly offloaded to the FPGA for execution, while the remaining operations are always executed locally on Jetson Orin NX. During operation, the offloading division is not adjusted with changes in task load and link status.

[0085] 2) The solution of this invention: The photovoltaic prediction model dynamic scheduling system proposed in this invention adaptively adjusts the unloading ratio and task batch processing method in each prediction cycle between Jetson OrinNX and FPGA VD100 based on the runtime time cost model and execution statistics.

[0086] Under the same hardware environment and data load, the inference performance and system resource consumption of the two schemes were statistically analyzed. The results show that, compared with the static scheduling scheme, the scheme of the present invention can significantly reduce the average inference latency and high quantile tail latency of photovoltaic prediction tasks while maintaining prediction accuracy, and increase the number of prediction samples that can be completed per unit time.

[0087] In addition, CPU utilization during operation was sampled and analyzed. Figure 4 A comparative diagram is provided showing the CPU utilization over a continuous runtime between the static scheduling scheme and the scheme proposed in this invention. The static scheduling scheme is shown at the top, and the dynamic scheduling scheme proposed in this invention is shown at the bottom. It can be seen that under the dynamic scheduling scheme of this invention, the peak CPU utilization and its fluctuation range are both lower than those of the static scheduling scheme. This indicates that task partitioning driven by the runtime time cost model, batch processing, and DMA access based on page-locked memory help reduce data transfer and scheduling overhead on the host side, thereby improving system stability and resource utilization efficiency.

[0088] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0089] The preferred embodiments of the present invention have been described in detail above. It should be understood that those skilled in the art can make numerous modifications and variations based on the concept of the present invention without creative effort. Therefore, all technical solutions that can be obtained by those skilled in the art based on the concept of the present invention through logical analysis, reasoning, or limited experimentation on the basis of existing technology should be within the scope of protection defined by the claims.

Claims

1. A dynamic scheduling system for prediction models based on a heterogeneous computing platform, characterized in that, This includes the edge host and the FPGA coprocessor connected via the PCIe bus; The edge host runs a prediction model and is configured with: a task feature extraction module, which abstracts computationally intensive operators in the prediction model into candidate offload prediction tasks; a runtime cost modeling module, which maintains a runtime time cost model including host execution time, FPGA execution time, and transmission overhead; a scheduling decision module, which, based on the runtime time cost model, compares the estimated completion time of candidate offload prediction tasks on the local path with the offload execution path, and dynamically selects whether to execute them on the edge host or the FPGA coprocessor; a task descriptor construction and distribution module, which generates prediction task descriptors for selecting prediction tasks on the offload execution path; a DMA buffer and page-locked memory management module, which pre-allocates input and output buffers on the edge host through the CUDA page-locked memory mechanism; and a closed-loop statistical feedback module, which updates the runtime time cost model parameters online based on the actual execution time and transmission time of the prediction tasks. The FPGA coprocessor is configured with: a task receiving and parsing module, which receives and parses the prediction task descriptor; a task queue and scheduling module, which schedules tasks to be executed according to priority and deadline margin; a DMA access module, which reads input data from the page-locked memory of the edge host according to the buffer address in the task descriptor and writes the prediction result back to the corresponding output buffer; and an execution statistics module, which records the task execution statistics of the FPGA coprocessor and returns them to the edge host through the PCIe bus. The edge host and the FPGA coprocessor exchange prediction task descriptors, DMA buffer addresses, execution results, and statistical information via the PCIe bus. The runtime cost modeling module obtains initial estimates of host execution time, FPGA execution time, and PCIe transmission time through a preheating task. For edge hosts and FPGA coprocessors, the estimated execution time is multiplied by the ratio of the task size to the preset baseline computing size to obtain the corresponding predicted execution time. For PCIe transmission time, the estimated PCIe transmission time is multiplied by the ratio of the output / input data size to the baseline data size to obtain the corresponding data output / input transmission time. When performing dynamic scheduling, based on the observed actual execution time and transmission time, the cost modeling module updates the estimated parameters of host execution time, FPGA execution time and PCIe transmission time in the runtime time cost model using an exponentially weighted moving average method, and adaptively adjusts the updated weight coefficients according to the task queue length or resource utilization of the edge host and FPGA coprocessor. The task queue and scheduling module inserts the parsed predicted tasks into the task queue; the scheduling weight is the weighted sum of the task priority and the reciprocal of the task deadline margin. Predictive tasks are selected from the task queue according to scheduling weights and assigned to multiple parallel computing cores within the FPGA coprocessor for execution.

2. The predictive model dynamic scheduling system based on a heterogeneous computing platform according to claim 1, characterized in that, The scheduling decision module predicts when a task will arrive. The predicted execution time of the edge host is added to the estimated queue waiting time on the host side to obtain the predicted completion time of the local execution path; The predicted completion time of the unloading execution path is obtained by adding the estimated values ​​of FPGA execution time, data output transmission time, data input transmission time, and FPGA-side queue waiting time predicted by the runtime time cost model. When the sum of the predicted completion time of the unloading execution path and the preset safety margin is less than the predicted completion time of the local execution path, and the task queue length of the FPGA coprocessor does not exceed the preset threshold, the predicted task is classified as an unloading task; otherwise, the predicted task is classified as a local execution task.

3. The predictive model dynamic scheduling system based on a heterogeneous computing platform according to claim 1, characterized in that, The DMA buffer and page-locked memory management module pre-allocates input and output buffers on the edge host through the CUDA page-locked memory mechanism; it stores data including historical time series and prediction results in the page-locked memory buffer and provides the physical address or I / O virtual address of the buffer to the task descriptor construction and distribution module, and the DMA access module of the FPGA coprocessor can directly access the buffer.

4. The predictive model dynamic scheduling system based on a heterogeneous computing platform according to claim 1, characterized in that, The task descriptor construction and distribution module encapsulates the input buffer address and length, output buffer address and length, task size, prediction period, prediction period deadline, and task priority fields of the prediction task into a task descriptor, and distributes it to the FPGA coprocessor via the PCIe bus.

5. The predictive model dynamic scheduling system based on a heterogeneous computing platform according to claim 4, characterized in that, When the task descriptor construction and distribution module detects that there are multiple prediction tasks with a scale lower than a preset threshold and belonging to the same prediction period, it merges the multiple prediction tasks into a batch processing task and distributes it to the FPGA coprocessor in the form of a single task descriptor.

6. The predictive model dynamic scheduling system based on a heterogeneous computing platform according to claim 1, characterized in that, The execution statistics module is used to collect the actual execution time, DMA transfer time and queue waiting time of each prediction task on the FPGA coprocessor, and transmit them back to the edge host via the PCIe bus. The closed-loop statistics feedback module then aggregates these data and provides them to the runtime cost modeling module.

7. The predictive model dynamic scheduling system based on a heterogeneous computing platform according to claim 1, characterized in that, The internal hardware resources of the edge host include a multi-core CPU, a GPU acceleration unit, and system memory; The multi-core CPU is used to run the task feature extraction module, runtime cost modeling module, scheduling decision module, DMA buffer and page locking memory management module, task descriptor construction and distribution module, closed-loop statistical feedback module, and control logic for deep learning model prediction and inference. The GPU acceleration unit is used to execute deep learning model operators that have not been unloaded; The page-locked buffers in the system memory are accessed by both the GPU and the FPGA coprocessor connected via PCIe.

8. A dynamic scheduling method for prediction models based on a heterogeneous computing platform, characterized in that, The method employs the dynamic scheduling system as described in any one of claims 1-7, and includes the following steps: Historical time series data are collected on edge hosts to construct the input tensor of the prediction model. During the inference process of the prediction model, computationally intensive operators are abstracted into prediction tasks for candidate unloading, and task features including task size, input and output data size, prediction period, task priority and deadline are obtained. On the edge host, based on the actual execution time and transmission time of the completed prediction tasks, establish and maintain a runtime time cost model that includes host execution overhead, FPGA execution overhead and PCIe transmission overhead; When the predicted task reaches the scheduling point, the runtime time cost model is invoked to predict the completion time of the task on the local execution path of the edge host and on the offload execution path of the FPGA, respectively. Based on the completion time prediction results, the preset safety margin, and the FPGA coprocessor task queue length, the predicted tasks are divided as follows: when the sum of the predicted completion time of the unloading execution path and the preset safety margin is less than the predicted completion time of the local execution path, and the task queue length does not exceed the preset threshold, the predicted task is divided into an unloading task; otherwise, it is divided into a local execution task. Multiple small-scale tasks that meet the preset conditions are then batch-processed and merged. For prediction tasks that are classified as offloading tasks, input and output buffers are allocated in the page-locked memory of the edge host, the corresponding historical data is written into the input buffer, a task descriptor containing buffer address information and task characteristics is generated, and then sent to the FPGA coprocessor via the PCIe bus. The task descriptor is received and parsed on the FPGA coprocessor side, the corresponding prediction task is inserted into the task queue, and the scheduling weight is calculated based on the task priority and deadline margin. The task is then assigned to the parallel computing core for execution according to the scheduling weight. Input data is read from the page-locked memory of the edge host according to the buffer address, and the prediction result is written back to the corresponding output buffer. After the prediction task is completed, execution statistics including actual execution time, DMA transfer time and queue waiting time are recorded on the FPGA coprocessor side. The execution statistics are fed back to the edge host through the PCIe bus and provided to the runtime cost modeling module along with the actual execution time of the task executed locally on the edge host. The runtime cost model parameters are then updated online.

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