Data management and consistency synchronization method and system for flexible direct control protection device

Abstract

The invention discloses a data management and consistency synchronization method and system for a flexible direct-current control protection device, and relates to the technical field of flexible direct-current transmission, and the method comprises the steps: generating a memory allocation table of a global resource pool through the static analysis of a compiler, pre-dividing a fixed memory space according to the resource type, forbidding the dynamic memory operation, and storing the memory allocation table; dividing privileged areas through the memory protection unit; dynamically adjusting a transmission dead zone through a differential transmission mechanism and an adaptive transmission arbitration mechanism based on the pre-allocated global resource pool and the characteristics of data in the pool, and synchronizing the data in the global resource pool to a corresponding memory area of a target core from a source core; based on synchronized cross-domain data, multi-core data atomic update is ensured through clock synchronization and dual-mode consistency control. According to the method, dynamic balance of memory access efficiency, data integrity and task real-time performance is realized in a microsecond-level control period through technologies of static memory allocation, hardware isolation, multi-mode consistency control and the like.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of flexible direct current power transmission, in particular to a data management and consistency synchronization method and system for a flexible direct current control and protection device. BACKGROUND

[0002] In a flexible direct current power transmission system, a control and protection device (hereinafter referred to as "flexible direct current control and protection device") needs to complete massive data processing and decision-making within a microsecond control cycle. The memory management efficiency and data consistency directly affect the stability of the system. The traditional memory management scheme has the following technical bottlenecks:

[0003] First, the real-time performance of a single CPU core is insufficient: Traditional dynamic memory allocation (such as malloc) can cause uncertain delay jitter, which may cause protection action timeout and affect system stability. In addition, the lack of hardware-level memory isolation mechanism also makes the system vulnerable to abnormal tasks.

[0004] Second, the efficiency of multi-core cooperation is low: cross-CPU core data interaction relies on polling or non-deterministic bus protocols, which cannot meet the microsecond-level synchronization requirements of high-frequency control parameters, and the lack of differentiated transmission strategies leads to waste of bandwidth resources.

[0005] Third, data consistency risk: synchronization errors of distributed sampling nodes may cause protection misjudgment, and traditional cross-domain data pool mechanisms cannot ensure the atomicity of data updates in a multi-core environment, especially in interrupt tasks, which are prone to logical conflicts. SUMMARY

[0006] Therefore, it is necessary to provide a data management and consistency synchronization method and system for a flexible direct current control and protection device to solve the above technical problems.

[0007] In a first aspect, the present application provides a data management and consistency synchronization method for a flexible direct current control and protection device, comprising:

[0008] S1, in the compilation and linking stage, a memory allocation table of a global resource pool is generated by static analysis of a compiler, a fixed memory space is pre-divided according to resource types, dynamic memory operations are prohibited, and a memory protection unit is used to divide a privileged area to realize hardware-level isolation and error detection;

[0009] S2, based on the pre-allocated global resource pool and the data characteristics in the pool, the transmission dead zone is dynamically adjusted through a differentiated transmission mechanism and an adaptive transmission arbitration mechanism, the data in the global resource pool is synchronized from the source core to the corresponding memory area of the target core, and cross-domain data update is realized;

[0010] S3, based on synchronization across domain data, through clock synchronization and double mode consistency control to ensure multi-core data atomicity update, and combined with temporary buffer writing, CRC check and mutex mechanism to avoid logical conflict, realize the atomicity and timing consistency of data update in distributed environment.

[0011] Further, the memory allocation table of the global resource pool is generated by the compiler static analysis, the fixed memory space is pre-divided according to the resource type, the dynamic memory operation is prohibited, and the privilege area is divided by the memory protection unit, including:

[0012] S11, based on resource type, the variables are classified, the partition attribute is added to the variables through the compiler pseudo instruction, the resource list containing variable information is generated through the static scanning in the compilation period, the memory segment is fixed to the physical address space according to the description file by the linker, and the ring buffer is pre-allocated to store the real-time sampling value;

[0013] S12, different types of independent address spaces are divided by the memory management unit, the hardware parity check function is enabled, and the software buffer overflow detection is combined, the critical buffer sentinel value is defined, and the overflow access is captured through periodic inspection;

[0014] S13, the data stored in the isolation is processed in a lightweight manner, the protection constant value is mapped to the read-only area, the hot data is cached and optimized, and when the protection constant value is modified, the new data is written to the temporary buffer first, and then the main storage area is updated atomically after the verification.

[0015] Further, based on resource type, the variables are classified, the partition attribute is added to the variables through the compiler pseudo instruction, the resource list containing variable information is generated through the static scanning in the compilation period, the memory segment is fixed to the physical address space according to the description file by the linker, and the ring buffer is pre-allocated to store the real-time sampling value, including:

[0016] S111, the variables are divided into different types and partition attributes, the memory allocation table of the global resource pool is generated by the compiler static analysis, and the fixed memory space is pre-divided for the real-time task;

[0017] S112, the fixed size ring queue and buffer are pre-allocated for storing real-time data to avoid dynamic allocation overhead;

[0018] S113, the dynamic memory function is prohibited in the real-time task through the compiler forced check, to ensure the determinacy of the target priority task execution.

[0019] Further, the variables are divided into different types and partition attributes, the memory allocation table of the global resource pool is generated by the compiler static analysis, and the fixed memory space is pre-divided for the real-time task, including:

[0020] S1111, according to the resource type of the data and the service attribute, setting the variable to different types;

[0021] S1112, using the pseudo-instruction or keyword provided by the compiler, adding specific partition attributes to the variable for marking the variable allocation to the corresponding memory segment;

[0022] S1113, in the compilation process, the compiler performs lexical and syntax analysis on the source code, identifies the global variable and static variable with specific partition attributes, and extracts the variable information of each variable to form an initial resource list; the variable information includes name, data type, occupied space size and predefined target memory segment information;

[0023] S1114, in the linking stage, the linker places the different memory segments of the extracted variable information to the specified area of the physical address space according to the configuration of the linking description file.

[0024] Further, based on the pre-allocated global resource pool and the data characteristics in the pool, the transmission dead zone is dynamically adjusted through the differentiated transmission mechanism and the adaptive transmission arbitration mechanism to synchronize the data in the global resource pool from the source core to the corresponding memory area of the target core, including:

[0025] S21, based on the real-time requirement of the data in the global resource pool, performing differentiated transmission, using the active notification mode to trigger the real-time data synchronization of the control parameter, using the polling lookup mode to periodically access the non-real-time data, and using the shared pipeline technology to perform streaming transmission on the fault recording file;

[0026] S22, setting the transmission protocol of the inter-core data, dividing the system running state by real-time analysis of key performance indicators, establishing a prediction model of core control variables; dynamically adjusting the transmission dead zone according to the steady state, transient state and fault state, and making transmission arbitration decisions based on the prediction verification mechanism.

[0027] Further, by real-time analysis of key performance indicators to divide the system running state, a prediction model of core control variables is established; the transmission dead zone is dynamically adjusted according to the steady state, transient state and fault state, and transmission arbitration decisions are made based on the prediction verification mechanism, including:

[0028] S221, deploying a lightweight state monitor in the main control core, dividing into multiple running states by real-time analysis of key performance indicators; the running states include steady state, transient state and fault state;

[0029] S222, for the core control variable, a prediction model is established at the data sending end, and according to the latest preset number of historical samples, the predicted value and confidence interval of the next control period data are continuously monitored;

[0030] S223, construct an adaptive arbitration device, set different widths of transmission dead zones according to the current running state;

[0031] S224, a transmission arbitration logic based on prediction and verification, establishes data transmission decision rules, triggers data transmission when the absolute value of the difference between the current value and the last transmission value is greater than the dynamic transmission dead zone; if the data change does not exceed the dynamic transmission dead zone, but the absolute value of the difference between the current value and the predicted value exceeds the confidence interval of the prediction model, then force trigger data transmission.

[0032] Further, based on the synchronization of cross-domain data, through clock synchronization and double-mode consistency control to ensure multi-core data atomicity update, combined with temporary buffer writing, CRC check and mutual exclusion mechanism to avoid logical conflict, including:

[0033] S31, through clock synchronization, time alignment is performed on cross-domain data, and periodic synchronization, event triggered synchronization and state verification are combined to maintain the consistency of data timestamp and logical association;

[0034] S32, through double-mode consistency control, mark the variable and system rule constraint, realize the switching and forced execution of fast mode and consistency mode; fast mode allows variable to directly access memory, and consistency mode realizes serialization of variable read-write operation by using mutual exclusion;

[0035] S33, based on fast mode and consistency mode, implement access rule verification, force fast mode variables to be used for interrupt processing tasks and prohibit access to consistency mode variables, prohibit the same core from performing read-write operation on unified variables, and ensure access rule execution through compiler static check.

[0036] Further, the periodic synchronization, event triggered synchronization and state verification are combined to maintain the consistency of data timestamp and logical association, including:

[0037] S311, the timer triggers the baseline synchronization task at a fixed period, which is used to broadcast regular heartbeat information, and the regular heartbeat information includes core state word, synchronization counter and timestamp;

[0038] S312, when a target priority event occurs, immediately trigger the target priority task processing mechanism to preferentially execute the task synchronization and data update of the target priority event;

[0039] S313, after each event triggered synchronization is completed, the receiving core recalculates the CRC of the received data and compares it with the received CRC, checks whether the version number meets the expected increment, and if the verification fails, rejects this update and reports synchronization exception.

[0040] In a second aspect, the present application also provides a system for data management and consistency synchronization of a flexible direct control and protection device, comprising:

[0041] A single-core global resource pool management module is configured to generate a memory allocation table of the global resource pool through static analysis of a compiler in a compilation and linking stage, pre-divide fixed memory space according to resource types, prohibit dynamic memory operation, and divide a privileged area through a memory protection unit to realize hardware-level isolation and error detection.

[0042] A multi-core cross-domain data pool management module is configured to dynamically adjust a transmission dead zone through a differentiated transmission mechanism and an adaptive transmission arbitration mechanism based on a pre-allocated global resource pool and data characteristics in the pool, synchronize data in the global resource pool from a source core to a corresponding memory area of a target core, and realize cross-domain data updating.

[0043] A multi-mode data consistency guarantee module is configured to ensure multi-core data atomic updating through high-precision clock synchronization and double-mode consistency control based on synchronized cross-domain data, and avoid logical conflicts through temporary buffer writing, CRC checking and mutual exclusion mechanism to realize atomicity and timing consistency of data updating in a distributed environment.

[0044] The present application has the following technical advantages: 1. Deterministic memory allocation: through static memory pool and resource mapping technology, fixed memory space is pre-divided for real-time tasks, dynamic allocation delay jitter is eliminated, and microsecond-level control cycle requirements are met; 2. Multi-core collaborative optimization: hierarchical transmission strategy and low-latency bus protocol are adopted for different types of data to realize microsecond-level synchronization of high-frequency parameters and efficient transmission of large files; 3. Multi-mode consistency control: combined with hardware synchronization and software buffering, the "temporary buffer writing + atomic updating after passing the check" mechanism ensures atomic updating of distributed sampling data when modifying protection constants and other key operations, even in abnormal scenarios such as power failure, and avoids logical conflict risks. BRIEF DESCRIPTION OF DRAWINGS

[0045] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and serve to explain the principles of the application, and do not limit the application in any way. In the drawings:

[0046] Figure 1 is a flowchart of a method for data management and consistency synchronization of a flexible direct control and protection device according to an embodiment of the present application;

[0047] Figure 2is a principle block diagram of a system for data management and consistency synchronization of a flexible straight control and protection device according to an embodiment of the present application;

[0048] Figure 3 is a system architecture schematic diagram of a system for data management and consistency synchronization of a flexible straight control and protection device according to an embodiment of the present application;

[0049] Figure 4 is an interface schematic diagram (English) according to an embodiment of the present application;

[0050] Figure 5 is an interface schematic diagram (Chinese) according to an embodiment of the present application.

[0051] Corresponding reference signs: 1, single-core global resource pool management module; 2, multi-core cross-domain data pool management module; 3, multi-mode data consistency guarantee module. DETAILED DESCRIPTION

[0052] In order to make the purpose, technical scheme and advantages of the present application more clear, the present application is further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0053] Please refer to Figure 1 , a method for data management and consistency synchronization of a flexible straight control and protection device is provided, comprising:

[0054] S1, single-CPU core global resource pool management technology: in the compilation and linking stage, a memory allocation table of the global resource pool is generated by static analysis of the compiler, the fixed memory space is pre-divided according to the resource type, the dynamic memory operation is prohibited, and the privileged area is divided by the memory protection unit to realize the hardware-level isolation and error detection.

[0055] In the description of the present application, the memory allocation table of the global resource pool is generated by static analysis of the compiler, the fixed memory space is pre-divided according to the resource type, the dynamic memory operation is prohibited, and the privileged area is divided by the memory protection unit, comprising:

[0056] S11, classify variables based on resource type, add partition attributes to variables through compiler pseudo instructions, generate resource list containing variable information through static scanning during compilation, and link the memory segment to the physical address space according to the description file, and pre-allocate a ring buffer to store real-time sampling values.

[0057] In the description of the present application, the memory allocation table of the global resource pool is generated by static analysis of the compiler, the fixed memory space is pre-divided according to the resource type, the dynamic memory operation is prohibited, and the privileged area is divided by the memory protection unit, comprising:

[0058] S111, dividing variables into different types and partition attributes, generating a memory allocation table of a global resource pool through static analysis of a compiler, and pre-dividing fixed memory space for real-time tasks.

[0059] Specifically, step S111 designs a resource mapping technology, generates a memory allocation table of a global resource pool through static analysis of a compiler according to resource types such as fixed values, telemetering values and remote signals, and pre-divides fixed memory space for real-time tasks. For example, a dedicated memory area is reserved for protection logic with a control cycle of 50 μs to ensure that data access is not blocked. The specific implementation steps are as follows:

[0060] 1. Resource classification and attribute definition: In the coding stage, the developer defines variables as different types according to the business attributes of the data, such as protection fixed values, telemetering values, remote signals, etc.

[0061] 2. Use the pseudo instruction (such as #pragma DATA_SECTION) or keyword (such as __attribute__((section("name"))) provided by the compiler to attach specific partition attributes to these variables, indicating which memory segment they should be allocated to.

[0062] 3. Static scanning and information extraction during compilation, in the compilation process, the compiler performs lexical and syntax analysis on the source code, identifies global variables and static variables with specific partition attributes. The compiler will extract the name, data type, occupied space size and pre-defined target memory segment of each variable, forming an initial resource list.

[0063] 4. Address allocation and mapping table generation during linking. In the linking stage, the linker will accurately place the different memory segments extracted in the previous step into the specified area of the physical memory address space according to the configuration of the linking description file.

[0064] The principle of step S111 is to complete the address allocation and solidification of variables during the compilation and linking stage, avoiding the uncertainty caused by allocation during running.

[0065] In the description of the present application, dividing variables into different types and partition attributes, generating a memory allocation table of a global resource pool through static analysis of a compiler, and pre-dividing fixed memory space for real-time tasks includes:

[0066] S1111, according to the resource type and business attribute of the data, the variable is set to different types.

[0067] S1112, use the pseudo instruction or keyword provided by the compiler to attach specific partition attributes to the variable, which is used to mark the variable to be allocated to the corresponding memory segment.

[0068] S1113、In the compilation process, the compiler performs lexical and syntax analysis on the source code, identifies global variables and static variables with specific partition attributes, and extracts variable information of each variable to form an initial resource list. The variable information includes name, data type, occupied space size, and predefined target memory segment information.

[0069] S1114、In the linking stage, the linker places different memory segments of the extracted variable information to the specified area of the physical address space according to the configuration of the linking description file.

[0070] S112、Pre-allocate a fixed-size ring queue and buffer to store real-time data to avoid dynamic allocation overhead.

[0071] Specifically, step S112 designs a static memory pool technology to store real-time data such as alternating voltage / current sample values by pre-allocating a fixed-size ring queue and buffer, avoiding dynamic allocation overhead. For example, a static array is used to implement data overwrite update in each control period.

[0072] S113、Through compiler forced checking, prohibit the use of dynamic memory functions in real-time tasks to ensure the determinacy of target priority task execution.

[0073] Specifically, step S113 is used to implement blocking operation prohibition, that is, through compiler forced checking, prohibit the use of malloc and other dynamic memory functions in real-time tasks to ensure the determinacy of high-priority task execution. The specific implementation steps are as follows:

[0074] 1、Configure compiler options: In the project build environment, configure specific flags (such as the --noheap option) for the compiler, which instructs the linker not to create a heap memory area (Heap).

[0075] 2、Function call static check: In the compilation phase, the compiler scans the source code to build a function call relationship graph. It checks whether there is a call to the standard dynamic memory allocation function library (such as malloc, free, realloc, calloc).

[0076] 3、Force interrupt compilation: Once any call to the above prohibited function is detected in the code, the compiler will immediately generate a fatal error (Fatal Error) instead of a warning and terminate the compilation process.

[0077] The principle of step S113 is to convert this runtime uncertainty problem into a deterministic problem that can be discovered and solved at compile time through the compiler's forced checking, thereby ensuring the stability and predictability of high-priority real-time task execution.

[0078] S12, by memory management unit, different types of independent address space is divided, enabling hardware parity check function, and combined with software buffer overflow detection, define the key buffer sentinel value, through the periodic inspection to capture the access.

[0079] Specifically, step S12 is used to realize the global resource pool memory space isolation and protection, including the following aspects:

[0080] 1, TOS memory management unit (MMU): division control logic, communication module, such as independent address space, to prevent abnormal task access.

[0081] 2, hardware level error detection: integrated parity, combined with software buffer overflow detection, real-time capture memory overflow and wild pointer problem. The specific implementation steps are as follows:

[0082] a) hardware enable: in the system startup phase, through the boot program configuration memory controller, enable the memory parity function;

[0083] b) automatic check: in the system running process, memory controller hardware for each memory write operation, automatically calculate parity, to determine whether there is a hardware error;

[0084] c) interrupt response: if the parity error occurs, automatically report error, to avoid serious problems;

[0085] d) software buffer definition: in the coding process, the key data buffer to be protected is defined in a specific memory segment;

[0086] e) boundary detection: using a special memory check library (such as `osal_memcheck` library), set sentinel value outside the buffer boundary, special marking;

[0087] f) timing inspection: in the key node of program execution, set up low priority background task, periodically patrol sentinel value whether to change;

[0088] g) exception capture: if the sentinel value is found to be modified in the inspection process, trigger buffer overflow error.

[0089] Step S12 technical principle is through the real-time monitoring of hardware circuit, with the logic "fence" set by software, detect hardware and software errors.

[0090] S13, the data stored in the isolation is lightweight processing, the protection constant value is mapped to the read-only area, the hot data is cached and optimized, and when the protection constant value is modified, the new data is written to the temporary buffer first. After verification, it is updated to the main storage area atomically.

[0091] Specifically, step S13 is used to realize memory efficiency optimization and transaction guarantee, including the following aspects:

[0092] 1. Lightweight data structure: use bit segments to represent switch states, and map read-only data such as protection constants to Flash / ROM, which is loaded into the memory read-only area at runtime.

[0093] 2. Cache optimization: cache hot data such as PI parameters and fault thresholds in the current control period to reduce main memory access delay.

[0094] 3. Atomicity of transactional operations: when modifying protection constants, use the "temporary buffer writing + verification passing atomic update" mechanism to ensure the integrity of the constants in the power-off scenario; fault recording uses a circular buffer + index marker to ensure continuous data storage. The specific implementation steps are as follows:

[0095] a) Temporary buffer writing: when modifying protection constants and other resources, the system does not directly overwrite the memory area in use. It first writes the new constant data into a dedicated, pre-allocated temporary buffer. This buffer is independent of the main constant storage area.

[0096] b) Integrity verification: after writing data to the temporary buffer, the system immediately performs integrity verification on the data, such as CRC checksum, to ensure that the data has not been corrupted or damaged during writing.

[0097] c) Atomic update: only after verification passes, the system will perform an atomic update operation. Atomic update refers to an indivisible operation that either completes entirely or does not execute at all. In this mechanism, the system uses an atomic instruction to copy or map the valid data block in the temporary buffer to the main constant storage area in one operation without interruption.

[0098] The technical principle of step S13 is based on phased submission, first verifying data, then performing atomic operations, to ensure data integrity and reliability.

[0099] S2, multi-CPU core cross-domain data pool management technology: based on pre-allocated global resource pool and data characteristics in the pool, use differential transmission mechanism and adaptive transmission arbitration mechanism to dynamically adjust the transmission dead zone, synchronize data from the source core to the corresponding memory area of the target core in the global resource pool, and realize cross-domain data update.

[0100] In the description of the present application, based on the pre-allocated global resource pool and the data characteristics in the pool, the data in the global resource pool is synchronized from the source core to the corresponding memory area of the target core through the differential transmission mechanism and the adaptive transmission arbitration mechanism to dynamically adjust the transmission dead zone, including:

[0101] S21, performing differentiated transmission based on the real-time requirement of the in-pool data in the global resource pool, triggering instant data synchronization of control parameters in an active notification mode, periodically accessing non-real-time data in a polling lookup mode, and performing stream transmission of fault recording files in a shared pipeline technology.

[0102] Specifically, the differentiated transmission mechanism is embodied in the following aspects:

[0103] 1. Active notification mode: for high-frequency control parameters such as current instructions, instant data synchronization is triggered through hardware interrupts or inter-core signals to ensure microsecond-level response.

[0104] 2. Polling lookup mode: for non-real-time data such as device self-test results, a periodic polling mechanism is used to reduce communication overhead.

[0105] 3. Shared pipeline technology: for large-volume fault recording files, stream transmission is used to avoid memory fragmentation.

[0106] S22, setting the transmission protocol of inter-core data, dividing the system operating state by real-time analysis of key performance indicators, establishing a prediction model of core control variables, dynamically adjusting the transmission dead zone according to steady state, transient state and fault state, and making transmission arbitration decisions based on the prediction verification mechanism.

[0107] Specifically, step S22 is used to realize data compression and filtering, i.e. compressing non-real-time data and enabling the “change transmission” (OSoC) mechanism for real-time control data, triggering transmission only when data changes to reduce invalid traffic. At the same time, the traditional “change transmission” (OSoC) mechanism is improved by introducing an adaptive transmission arbitration mechanism to solve the problem of missing small but critical change information due to improper threshold setting in steady state.

[0108] In the description of the present application, the system operating state is divided by real-time analysis of key performance indicators, and a prediction model of core control variables is established. Dynamic adjustment of the transmission dead zone according to steady state, transient state and fault state, and transmission arbitration decisions based on the prediction verification mechanism include:

[0109] S221, deploying a lightweight state monitor in the main control core, dividing into multiple operating states by real-time analysis of key performance indicators. The operating states include steady state, transient state and fault state.

[0110] Specifically, real-time division of system operating state: a lightweight system state monitor is deployed in the main control CPU core. The monitor divides the system into at least three states by real-time analysis of key performance indicators (KPIs) such as DC voltage ripple coefficient, AC current change rate (di / dt), and protection logic trigger flag:

[0111] 1. Steady state: all indicators are within normal range with small fluctuations;

[0112] 2. Transient state: expected system disturbance such as load step, command change, etc. is monitored;

[0113] 3. Fault state: severe fault characteristics such as overcurrent, overvoltage, etc. are monitored, or protection logic has been activated.

[0114] S222, for core control variables, a prediction model is established at the data sending end, and the predicted value and confidence interval of the next control period data are continuously monitored according to the latest preset number of historical samples.

[0115] Specifically, step S222 is used to implement the establishment of a prediction model for key data. For core control variables that require high-frequency synchronization, a simple prediction model such as linear extrapolation or first-order Kalman filter is established at the data sending end. The model continuously predicts the possible value and confidence interval of the next control period data based on the latest N historical samples.

[0116] S223, an adaptive adjustment arbitrator is constructed, and different widths of transmission dead zones are set according to the current running state.

[0117] Specifically, adaptive adjustment of dynamic transmission dead zone: the traditional OSoC mechanism uses a fixed dead zone (i.e. data changes more than what is sent), while the dead zone of this mechanism is dynamic:

[0118] 1. In steady state, the arbitrator adopts a wider dead zone, effectively filtering out meaningless data fluctuations caused by measurement noise, and minimizing transmission.

[0119] 2. In transient state, the arbitrator automatically narrows the dead zone, improving the sensitivity of data transmission to accurately capture the system dynamic process.

[0120] 3. In fault state, the arbitrator sets the dead zone to zero and forces full-scale, highest-priority transmission to ensure that any small change is acquired by all cores without delay, providing the most complete data support for fault diagnosis and protection decisions.

[0121] S224, transmission arbitration logic based on prediction and verification, establish data transmission decision rules, if the absolute value of the difference between the current value and the last transmission value is greater than the dynamic transmission dead zone, then trigger data transmission. If the data change does not exceed the dynamic transmission dead zone, but the absolute value of the difference between the current value and the predicted value exceeds the confidence interval of the prediction model, then force data transmission.

[0122] Specifically, the transmission arbitration logic based on "prediction-verification". The final decision of data transmission is made by an arbitration logic module, and its judgment process is as follows:

[0123] 1. Rule A (regular change): Trigger transmission when "|current value - last transmission value| > dynamic deadband". This is a catch for significant change.

[0124] 2. Rule B (unexpected change): Also trigger transmission when data change does not exceed dynamic deadband, but "|current value - predicted value|" exceeds the confidence interval of the prediction model.

[0125] The technical principle of step S22 is to change "passive transmission" to "intelligent arbitration". Instead of relying solely on whether the data itself changes, it comprehensively considers the current macro running state of the system, the micro significance of data change, and the short-term trend of the future, so as to dynamically determine which data needs to be transmitted at what time and with what priority. This makes the data transmission strategy actively adapt to the working condition change of the system, maximizes the saving of precious inter-core communication bandwidth on the premise of ensuring that key information is not lost.

[0126] S3, based on the synchronization of cross-domain data, through clock synchronization and double-mode consistency control to ensure atomic update of multi-core data, and combined with temporary buffer writing, CRC check and mutex mechanism to avoid logical conflict, realize the atomicity and timing consistency of data update in distributed environment.

[0127] In the description of the application, based on the synchronization of cross-domain data, through clock synchronization and double-mode consistency control to ensure atomic update of multi-core data, and combined with temporary buffer writing, CRC check and mutex mechanism to avoid logical conflict includes:

[0128] S31, through clock synchronization, the cross-domain data is time-aligned, and periodic synchronization, event-triggered synchronization and state checking are combined to maintain the consistency of data timestamp and logical association.

[0129] Specifically, high-precision clock synchronization: through IEEE 1588, IRIG-B protocol to realize nanosecond-level time alignment of distributed nodes such as converter valve submodules and transformers.

[0130] Synchronization mechanism combination: periodic synchronization (update key registers every 1ms), event-triggered synchronization (force synchronization when value is modified) and state checking (CRC check, version number comparison) are combined to ensure the consistency of data timestamp and logical association. The three mechanisms are complementary through a cooperative workflow.

[0131] In the description of the application, periodic synchronization, event-triggered synchronization and state checking are combined to maintain the consistency of data timestamp and logical association includes:

[0132] S311, trigger a baseline synchronization task with a fixed period to broadcast regular heartbeat information including core status word, synchronization counter and timestamp.

[0133] Specifically, baseline maintenance (periodic synchronization): a high-precision timer in the system triggers a baseline synchronization task at a fixed period (e.g., 1 ms). The task is responsible for broadcasting regular heartbeat information such as core status word, synchronization counter or timestamp.

[0134] S312, when a target priority event (in the present invention, the target priority event is set as a high-priority task) occurs, immediately trigger the target priority task processing mechanism to execute the task synchronization and data update of the target priority event.

[0135] Specifically, high-priority task processing (time-triggered synchronization): when a high-priority event such as protection setting value modification or critical control mode switching occurs, this mechanism will be triggered immediately. The mechanism will: 1, preempt or suspend low-priority regular tasks; 2, apply a mutex lock to the target data set (such as the setting value table) to prevent other tasks from accessing; 3, perform data update and synchronize the associated version number and CRC check code; 4, broadcast a "data update" event notification to all related cores through the most efficient way such as inter-core interrupt; 5, receive core response interrupt, immediately load new data from the specified address (such as cross-domain data pool) in shared memory, and release the lock.

[0136] S313, after each event-triggered synchronization is completed, the receiving core recalculates the CRC of the received data and compares it with the received CRC, synchronously checks whether the version number is as expected, and if the check fails, rejects the update and reports a synchronization exception.

[0137] Specifically, integrity audit (state verification), this mechanism serves as the "last line of defense" for the previous two synchronizations. After each event-triggered synchronization is completed, the receiving core will immediately recalculate the CRC of the received data and compare it with the received CRC, and check whether the version number is as expected. If the check fails, reject the update and report a synchronization exception.

[0138] S32, mark variables and system rule constraints through dual-mode consistency control to achieve fast mode and consistency mode switching and enforcement. Fast mode allows variables to directly access memory, and consistency mode serializes variable read and write operations using mutex locks.

[0139] Specifically, dual-mode consistency control achieves flexible switching and enforcement of "fast mode" and "consistency mode" by marking variables and system rule constraints.

[0140] 1. Fast Mode: enabled by default, skip consistency check to maximize access efficiency. When a CPU core writes the "Fast" attribute variable, the modification value can be immediately perceived by the write operation of other cores, but the read operation does not guarantee strong consistency, which is suitable for parameter broadcast scenarios.

[0141] 2. Consistency Mode: activated by canceling the "Fast" label through the editor, triggering the buffer system to serialize the read and write operations. Ensure that the multi-variable values written by the same source core task are read by the target core from the same complete operation period, avoiding voltage / current sampling timing misalignment.

[0142] Developers manually activate "Consistency Mode" by canceling the "Fast" label for specific variables in the code. This operation marks the variable as requiring atomic operation, and the system will perform special processing on it at compile and run time.

[0143] S33, based on the access rule check of fast mode and consistency mode, the interrupt processing task is forced to use fast mode variable and is prohibited to access consistency mode variable, the same core is prohibited to execute read and write operations on the unified variable, and the compiler static check is used to ensure the execution of the access rule.

[0144] Specifically, the access rule and system check designed in step S33 include the following aspects:

[0145] 1. Interrupt task limitation: interrupt processing tasks are only allowed in "Fast" mode to avoid consistency buffer delay risks and ensure microsecond-level response.

[0146] 2. CPU core isolation principle: simultaneous read and write operations on the same variable by the same core are strictly prohibited, and read access is only allowed on a core different from the write-in end to avoid race conditions from the hardware architecture layer.

[0147] 3. Static check in the construction phase: the above rules are enforced through the compiler, and the compilation is terminated when violated, forming a "design-implementation-verification" closed loop.

[0148] In a second aspect, the present application also provides a system for data management and consistency synchronization of a flexible and rigid control and protection device, which comprises:

[0149] A single-core global resource pool management module 1 is used to generate a memory allocation table of the global resource pool through static analysis by the compiler in the compilation and linking stage, pre-divide fixed memory space according to resource types, prohibit dynamic memory operations, and divide privileged areas through a memory protection unit to realize hardware-level isolation and error detection.

[0150] Multi-core cross-domain data pool management module 2, for synchronizing data in the global resource pool from the source core to the corresponding memory area of the target core based on the pre-allocated global resource pool and the data characteristics in the pool, through the differential transmission mechanism and the adaptive transmission arbitration mechanism to dynamically adjust the transmission dead zone, realizing the cross-domain data update;

[0151] Multi-mode data consistency guarantee module 3, for ensuring multi-core data atomic update based on synchronized cross-domain data through high-precision clock synchronization and dual-mode consistency control, and combining temporary buffer writing, CRC checking and mutual exclusion mechanism to avoid logical conflicts, realizing atomicity and timing consistency of data update in a distributed environment.

[0152] The application will be further described below in conjunction with specific embodiments.

[0153] I. The specific implementation of the single CPU core global resource pool management is as follows.

[0154] Taking a multi-core CPU hardware as an example (8-core CPU architecture, main frequency 1.25 GHz, on-chip shared DDR3 memory 2 GB), the single core configuration is as follows:

[0155] 1. Memory allocation of the global resource pool;

[0156] The static memory pool of the global resource pool is pre-allocated by using the MEM module of the CPU core, and 512 KB fixed memory area is allocated for the protection logic task (with the highest priority), which includes:

[0157] (1) 256 KB ring buffer (created by RingBuf_create) for storing sampling values (updated by EDMA every 50 μs).

[0158] (2) 128 KB bit segment compression space (using the packed struct of the hardware architecture) for storing 64 remote signaling states (1 64-bit variable carrying 64 states).

[0159] (3) 128 KB read-only area mapping the protection fixed value in the external FLASH (loaded by the BIOS_FLASHMap function).

[0160] (4) The compiler adds the --noheap option to prohibit dynamic memory allocation, and the call of malloc in the real-time task triggers a compilation error.

[0161] 2. Isolation and protection of the memory space in the global resource pool;

[0162] Three privilege areas are divided by the memory protection unit (MPU) of the CPU core:

[0163] (1) Control logic area (0x80000000-0x80400000, privileged mode read-only): store protection algorithm code;

[0164] (2) Data buffer area (0x80400000-0x80800000, user mode read-write): store sample values and intermediate calculation results;

[0165] (3) Communication register area (0x80800000-0x80800100, privileged mode read-write): connect inter-core communication interface.

[0166] (4) Hardware layer enables ECC check (single-bit error correction) of DDR3, and software layer detects buffer overflow in real time through osal_memcheck library, for example:

[0167] #pragma DATA_SECTION(buffer, ".protected_buffer")

[0168] Uint32 buffer

[1024] __attribute__((mpu_region("data_buffer")));

[0169] 3. Memory efficiency optimization and transaction guarantee;

[0170] The protection constant uses Q31 fixed-point number format (such as current threshold 1000A represented as 0x447A1480, i.e. 1000*2^31), saving 50% memory of 32-bit floating point number;

[0171] Fault recording uses the EDMA3 controller of the CPU core to realize zero-copy storage:

[0172] / / Configure EDMA channel to loop and carry data

[0173] Edma3_ChannelHandle hChannel = Edma3_createChannel(0, 0); Edma3_setTransferParams(hChannel, srcAddr, dstAddr, bytesPerTransfer, numTransfers); Edma3_startChannel(hChannel).

[0174] II. Specific implementation of cross-CPU core cross-domain data pool management, the specific process is as follows.

[0175] The 8 cores of a certain multi-core CPU hardware communicate through shared DDR3 memory and inter-core interrupt (IPC) mechanism, such as Figures 4-5The interface diagram of the system is shown, and the specific strategy is as follows:

[0176] 1. Differentiated transmission mechanism;

[0177] (1) Active notification mode: current command (update frequency 20 kHz) triggers transmission through IPC interrupt (IPC_INT0-IPC_INT7), and the target core moves data from the cross-domain data pool (address 0x90000000) through EDMA, with a delay of ≤500 ns;

[0178] (2) Polling lookup mode: device self-test results (update frequency 10 Hz) are stored in the cross-domain data pool flag (0x9000FFFC), and the core polls every 1 ms through the CACHE_readThrough instruction;

[0179] (3) Shared pipe technology: fault recording file (single file ≤2MB) is transmitted through the Scatter-Gather mode of EDMA3, and the VPIF interface of the CPU core is connected to external storage, with a transmission rate of 1.2GB / s.

[0180] (4) Efficient transmission protocol;

[0181] Inter-core communication uses a custom 32-bit data frame, as shown in Table 1.

[0182] Table 1: Transmission format

[0183] (4) External sampling data is received through the McASP interface of the CPU core, using IEEE 1588 synchronous clock, with a sampling value transmission delay of ≤2μs.

[0184] III. The specific implementation process of multi-mode data consistency guarantee is as follows.

[0185] 1. Multi-source data synchronization;

[0186] (1) The clock manager (CM) of the CPU core is configured in IEEE 1588 slave mode, and nanosecond-level clock synchronization is achieved through the PHY chip, with a core timer error of ≤10 ns;

[0187] (2) Cross-domain data pool modification triggers inter-core synchronization: the master core sends a synchronization message (message ID=0xFFFF) through IPC, and the slave core suspends the pipeline after receiving it, waits for the master core to complete the "temporary buffer writing + 32-bit CRC verification" process (about 200 ns), and then refreshes the cache through CACHE_wbInvAll() and atomically updates the fixed value.

[0188] 2. Dual-mode consistency control;

[0189] (1) Fast mode: Inter-core protection start signal (variable trip_signal) is stored in the L2 cache addressable area (0x02000000), the host core writes directly to the memory, and the slave core ensures memory visibility through the __dsb() instruction, and the single access delay is ≤20 ns;

[0190] (2) Consistency mode: Power instruction set (voltage, current, phase) is stored in the shared DDR3 coherent domain (Coherent Domain), and the host core updates through the following steps:

[0191] Ipc_claimMutex (IPC_LOCK_ID); / / Get inter-core mutex * (volatile Uint32 *) 0x90000000 = new_voltage; * (volatile Uint32 *) 0x90000004 = new_current; Ipc_releaseMutex (IPC_LOCK_ID); / / Release the lock / / The slave core triggers a consistency update through MULTICORE_TRIGGER.

[0192] 3. Access rule verification;

[0193] The Fast mode is forced to be used in the interrupt service program (ISR), and the interrupt controller (INTC) of the CPU core prohibits Consistency variable access, for example:

[0194] #pragma INTERRUPT (fault_isr, INT0) void fault_isr ()

[0195] {

[0196] volatile Uint32 fast_var @0x02000000; / / Fast mode variable

[0197] / / Prohibit operation on Consistency variables, compiler checks through symbol table

[0198] }

[0199] In summary, by means of the technical scheme of the present application, through static memory allocation, hardware isolation, multi-mode consistency control and other technologies, the dynamic balance of memory access efficiency, data integrity and task real-time performance is achieved under a microsecond-level control cycle, and the following technical advantages are possessed: 1. Deterministic memory allocation: through static memory pool and resource mapping technology, a fixed memory space is pre-divided for real-time tasks, dynamic allocation delay jitter is eliminated, and microsecond-level control cycle requirements are met; 2. Multi-core collaborative optimization: a hierarchical transmission strategy and a low-delay bus protocol are adopted for different types of data, microsecond-level synchronization of high-frequency parameters and efficient transmission of large files are achieved; 3. Multi-mode consistency control: combined with hardware synchronization and software buffering, the “temporary buffer writing + atomic update after verification” mechanism ensures that when modifying the protection constant value and other key operations, even in the case of power failure and other abnormal scenarios, the atomic update of distributed sampling data can be ensured, and the risk of logical conflict is avoided.

[0200] It should be understood that although each step in the flowchart of the accompanying drawings is displayed in sequence according to the direction of the arrow, these steps are not necessarily executed in sequence according to the direction of the arrow. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and they can be executed in other sequences. Moreover, at least part of the steps in the flowchart of the accompanying drawings can include multiple sub-steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence is not necessarily sequential, but can be alternately executed with at least part of other steps or other steps, sub-steps or stages.

Claims

1. A method for data management and consistency synchronization in a flexible DC control and protection device, characterized in that, include: S1. During the compilation and linking stage, the compiler generates a memory allocation table for the global resource pool through static analysis, pre-divides fixed memory space according to resource type, prohibits dynamic memory operations, and divides privileged areas through memory protection units to achieve hardware-level isolation and error detection. S2. Based on the pre-allocated global resource pool and the characteristics of the data within the pool, the transmission dead zone is dynamically adjusted through a differentiated transmission mechanism and an adaptive transmission arbitration mechanism to synchronize the data in the global resource pool from the source core to the corresponding memory area of ​​the target core, thereby achieving cross-domain data updates. S3, based on synchronous cross-domain data, ensures atomic updates of multi-core data through clock synchronization and dual-mode consistency control, and avoids logical conflicts by combining temporary buffer writing, CRC check and mutex lock mechanism, thus achieving atomicity and timing consistency of data updates in a distributed environment.

2. The method for data management and consistency synchronization of a flexible DC control and protection device according to claim 1, characterized in that, The process of generating a global resource pool memory allocation table through compiler static analysis, pre-allocating fixed memory space according to resource type, prohibiting dynamic memory operations, and dividing privileged regions through memory protection units includes: S11. Classify variables based on resource type, add partition attributes to variables through compiler pseudo-instructions, generate a resource list containing variable information through static scanning during compilation, and linker solidifies memory segments into physical address space according to description file, and pre-allocate ring buffer to store real-time sampled values. S12. Divide different types of independent address spaces through the memory management unit, enable hardware parity checking function, and combine with software buffer out-of-bounds detection to define key buffer sentinel values ​​and capture out-of-bounds access through periodic inspection. S13. Perform lightweight processing on isolated storage data, map protection settings to read-only areas, optimize caching for hot data, and write new data to a temporary buffer before modifying protection settings. After verification, atomically update the main storage area.

3. The method for data management and consistency synchronization of a flexible DC control and protection device according to claim 2, characterized in that, The process involves classifying variables based on resource type, attaching partition attributes to variables via compiler pseudo-instructions, generating a resource list containing variable information through static scanning during compilation, and the linker embedding memory segments into the physical address space based on the description file. A pre-allocated circular buffer stores real-time sampled values, including: S111. Divide variables into different types and partition attributes, generate a memory allocation table for the global resource pool through static analysis by the compiler, and pre-allocate fixed memory space for real-time tasks. S112. Pre-allocate a fixed-size circular queue and buffer to store real-time data to avoid the overhead of dynamic allocation; S113. By enforcing compiler checks, the use of dynamic memory functions in real-time tasks is prohibited to ensure the deterministic execution of target priority tasks.

4. The method for data management and consistency synchronization of a flexible DC control and protection device according to claim 3, characterized in that, The process of classifying variables into different types and partition attributes, generating a memory allocation table for a global resource pool through static analysis by the compiler, and pre-allocating fixed memory space for real-time tasks includes: S1111. Based on the resource type and business attributes of the data, set the variables to different types; S1112. Use pseudo-instructions or keywords provided by the compiler to attach specific partition attributes to variables, which are used to mark the variables to be allocated to the corresponding memory segments. S1113. During the compilation process, the compiler performs lexical and syntactic analysis on the source code, identifies global and static variables with specific partition attributes, and extracts the variable information for each variable to form an initial resource list; the variable information includes name, data type, occupied space size, and predefined target memory segment information; S1114. During the linking phase, the linker places different memory segments of the extracted variable information into designated areas of the physical address space according to the configuration of the linker description file.

5. The method for data management and consistency synchronization of a flexible DC control and protection device according to claim 1, characterized in that, The method of synchronizing data in the global resource pool from the source core to the corresponding memory region of the target core based on the pre-allocated global resource pool and the characteristics of the data within the pool, through a differentiated transmission mechanism and an adaptive transmission arbitration mechanism to dynamically adjust the transmission dead zone, includes: S21. Based on the real-time requirements of the data in the global resource pool, differentiated transmission is performed. The active notification mode is used to trigger the instantaneous data synchronization of control parameters. The polling search mode is used to periodically access non-real-time data. The shared pipe technology is used to stream the fault recording file. S22. Set the data transmission protocol between cores, divide the system operating state by analyzing key performance indicators in real time, and establish a predictive model for core control variables; dynamically adjust the transmission dead zone according to steady state, transient state and fault state, and make transmission arbitration decisions based on the prediction verification mechanism.

6. A method for data management and consistency synchronization of a flexible DC control and protection device according to claim 5, characterized in that, The system analyzes key performance indicators in real time to classify system operating states and establishes a predictive model for core control variables.

7. A method for data management and consistency synchronization of a flexible DC control and protection device according to claim 6, characterized in that, The transmission dead zone is dynamically adjusted based on steady-state, transient, and fault states, and transmission arbitration decisions are made based on a predictive verification mechanism, including: S221. Deploy a lightweight state monitor in the main control core to analyze key performance indicators in real time and divide them into multiple operating states; the operating states include steady state, transient state and fault state; S222. For core control variables, establish a prediction model at the data sending end, and continuously monitor the predicted value and confidence interval of the data in the next control cycle based on the most recently preset number of historical samples. S223. Construct an adaptive arbiter and set different transmission dead zones according to the current operating state; S224. Based on the transmission arbitration logic of prediction and verification, establish data transmission decision rules. If the absolute value of the difference between the current value and the previous transmission value is greater than the dynamic transmission dead zone, then data transmission is triggered. If the data change does not exceed the dynamic transmission dead zone, but the absolute value of the difference between the current value and the predicted value exceeds the confidence interval of the prediction model, then data transmission is forcibly triggered.

8. A method for data management and consistency synchronization of a flexible DC control and protection device according to claim 1, characterized in that, The synchronous cross-domain data ensures atomic updates of multi-core data through clock synchronization and dual-mode consistency control, and avoids logical conflicts by combining temporary buffer writing, CRC check, and mutex lock mechanisms, including: S31. Time alignment of cross-domain data is achieved through clock synchronization, and periodic synchronization, event-triggered synchronization, and status verification are combined to maintain the consistency between data timestamps and logical associations. S32. By marking variables and constraining them with system rules through dual-mode consistency control, the switching and enforcement of fast mode and consistency mode are realized; the fast mode allows variables to directly access memory, and the consistency mode uses mutex locks to serialize the read and write operations of variables. S33. Implement access rule verification based on fast mode and consistent mode, force interrupt handling tasks to use fast mode variables and prohibit access to consistent mode variables, prohibit read and write operations on the same core's unified variable, and ensure access rule execution through compiler static checks.

9. A method for data management and consistency synchronization of a flexible DC control and protection device according to claim 8, characterized in that, The method of combining periodic synchronization, event-triggered synchronization, and status verification to maintain the consistency between data timestamps and logical associations includes: S311. Trigger the baseline synchronization task with a timer at a fixed period to broadcast regular heartbeat information, the regular heartbeat information including core status word, synchronization counter and timestamp; S312. When a target priority event occurs, the target priority task processing mechanism is immediately triggered to prioritize the execution of task synchronization and data update for the target priority event. S313. After each event-triggered synchronization is completed, the receiver checks the received data, recalculates the CRC, and compares it with the received CRC. It also checks whether the version number increases as expected. If the check fails, the update is rejected and a synchronization error is reported.

10. A system for data management and consistency synchronization of a flexible DC control and protection device, used to implement the method for data management and consistency synchronization of a flexible DC control and protection device as described in any one of claims 1-9, characterized in that, The system includes: The single-core global resource pool management module is used to generate a memory allocation table for the global resource pool through static analysis by the compiler during the compilation and linking stage. It pre-divides fixed memory space according to resource type, prohibits dynamic memory operations, and divides privileged areas through memory protection units to achieve hardware-level isolation and error detection. The multi-core cross-domain data pool management module is used to dynamically adjust the transmission dead zone based on the pre-allocated global resource pool and the characteristics of the data in the pool, through a differentiated transmission mechanism and an adaptive transmission arbitration mechanism, to synchronize the data in the global resource pool from the source core to the corresponding memory area of ​​the target core, thereby realizing cross-domain data updates. The multi-mode data consistency guarantee module is used for cross-domain data based on synchronization. It ensures atomic updates of multi-core data through high-precision clock synchronization and dual-mode consistency control, and avoids logical conflicts by combining temporary buffer writing, CRC check and mutex lock mechanism, so as to achieve atomicity and timing consistency of data updates in a distributed environment.

Images