Partition refresh circuit, refresh control method thereof, display panel and display device

Abstract

The application discloses a partition refreshing circuit and a refreshing control method thereof, a display panel and a display device, and relates to the technical field of display. The circuit comprises a plurality of cascaded gate driving modules. The gate driving module comprises a gate scanning unit and a refreshing selection unit. The gate scanning unit is driven by an upper-stage scanning signal to transmit a direct-current potential signal of a direct-current voltage end to the refreshing selection unit, triggers the refreshing selection unit to access a data memory signal provided by a data signal end, determines a refreshing start signal acting on a refreshing start end according to the data memory signal, triggers the gate scanning unit to output a dynamic refreshing signal from a starting pixel row row by row, performs a partition refreshing operation on all pixel rows of a dynamic refreshing partition, and terminates the partition refreshing operation according to a reset signal of a reset end when the gate scanning unit scans to a final pixel row of the dynamic refreshing partition, so that independent refreshing rate control of different areas of a screen is realized to reduce the display power consumption of the screen.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a partitioned refresh circuit and its refresh control method, a display panel, and a display device. Background Technology

[0002] With the continuous development of display technology, users have increasingly higher requirements for the power consumption and display effect of mobile device screens. In the current partitioned refresh circuit design, the display screen of mobile devices can only operate at a globally fixed refresh rate (such as 60Hz or 120Hz). Even when displaying static images (such as reading text or viewing pictures), the display screen continues to refresh at a high refresh rate, resulting in a large amount of power being wasted on meaningless pixel refreshes. The increased power consumption brought about by the upgrading of processors in mobile devices requires lower power consumption of the display screen to balance the distribution of power.

[0003] Currently, adaptive refresh technology is commonly used in the industry as the mainstream screen power consumption optimization solution. However, although the current adaptive refresh technology can dynamically select a fixed refresh rate according to the display scenario, it can only achieve a single refresh rate change across the entire screen. When the display screen of a mobile device simultaneously displays dynamic and static images, the adaptive refresh technology must still operate at a high refresh rate and cannot independently adjust the refresh rate for different areas, thus limiting further reductions in screen power consumption and restricting its application scenarios.

[0004] Therefore, while maintaining visual smoothness, how to achieve independent refresh rate control for different areas of the screen to reduce screen display power consumption is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] The main objective of this application is to provide a partitioned refresh circuit and its refresh control method, a display panel, and a display device, which aims to maintain visual smoothness while achieving independent refresh rate control for different areas of the screen to reduce display power consumption.

[0006] To achieve the above objectives, this application provides a partition refresh circuit, the partition refresh circuit comprising:

[0007] A gate scanning unit, wherein the input terminal of the gate scanning unit is configured to receive the scanning signal provided by the output terminal of the previous stage, the voltage input terminal of the gate scanning unit is electrically connected to a DC voltage terminal, and the gate scanning unit is configured to determine the starting pixel row of the dynamic refresh partition. When the scanning pixel row of the previous stage scanning signal is the pixel row preceding the starting pixel row, the DC potential signal of the DC voltage terminal is received under the drive of the previous stage scanning signal.

[0008] A refresh selection unit is electrically connected to a data signal terminal, a reset terminal, the voltage output terminal of the gate scan unit, and the refresh start terminal of the gate scan unit. The refresh selection unit is configured to receive a data memory signal provided by the data signal terminal under the drive of the DC potential signal, and determine the refresh start signal acting on the refresh start terminal based on the data memory signal. This triggers the gate scan unit to output dynamic refresh signals line by line starting from the starting pixel line, so as to perform partition refresh operation on all pixel lines of the dynamic refresh partition. The partition refresh operation is terminated based on the reset signal of the reset terminal when the gate scan unit scans to the final pixel line of the dynamic refresh partition.

[0009] In one embodiment, the gate driving module includes a first clock terminal and a second clock terminal, wherein the first clock terminal is used to provide a first clock signal, and the second clock terminal is used to provide a second clock signal that is inversely phase to the first clock signal;

[0010] The clock input terminal of the refresh selection unit is electrically connected to the target clock terminal, and the clock potential terminal of the gate scan unit is electrically connected to the inverted clock terminal of the target clock terminal. The target clock terminal is either the first clock terminal or the second clock terminal.

[0011] In multiple cascaded gate drive modules, the target clock signal provided by the target clock terminal in adjacent gate drive modules is inverted.

[0012] In one embodiment, the refresh selection unit includes a refresh control subunit and a refresh reset subunit. The refresh control subunit is electrically connected to the data signal terminal, the local voltage output terminal, the refresh start terminal, and the refresh reset subunit, respectively. The refresh control subunit includes:

[0013] First potential node;

[0014] The first switching transistor has its gate electrically connected to the voltage output terminal of this stage, its first path terminal electrically connected to the data signal terminal, and its second path terminal electrically connected to the first potential node.

[0015] The second switching transistor has its gate electrically connected to the first potential node, its first path terminal electrically connected to the data signal terminal, and its second path terminal electrically connected to the voltage output terminal of this stage.

[0016] The third switch has its gate electrically connected to the second path terminal of the second switch, its first path terminal electrically connected to the target clock terminal, and its second path terminal electrically connected to the refresh start terminal of the gate scan unit.

[0017] The first capacitor is connected between the first potential node and the second path terminal of the second switch.

[0018] In one embodiment, the refresh start terminal of the gate scan unit is a second potential node, and the refresh reset subunit includes a fourth switch and a fifth switch.

[0019] The gate of the fourth switch is electrically connected to the reset terminal, the first path terminal of the fourth switch is electrically connected to the target clock terminal, the second path terminal of the fourth switch is electrically connected to the gate of the fifth switch, the first path terminal of the fifth switch is electrically connected to the low potential terminal, and the second path terminal of the fifth switch is electrically connected to the second potential node.

[0020] In one embodiment, when there are two dynamically refreshed partitions, the gate drive module further includes a sixth switch and a termination signal terminal;

[0021] The gate of the sixth switch is electrically connected to the termination signal terminal, the first path terminal of the sixth switch is electrically connected to the voltage input terminal of this stage, and the second path terminal of the sixth switch is electrically connected to the low potential terminal.

[0022] Furthermore, to achieve the above objectives, this application also provides a refresh control method, which is applied to the partition refresh circuit described in any of the above claims. The partition refresh circuit includes a refresh selection unit and a plurality of cascaded gate scanning units, and the gate scanning unit further includes a refresh start terminal. The refresh control method includes:

[0023] When the gate scanning unit receives the previous level scanning signal output by the previous level gate driving module, the starting pixel row of the dynamic refresh partition is determined.

[0024] When the scanning pixel line of the previous level scanning signal is the pixel line preceding the starting pixel line, the DC potential signal of the gate scanning unit is enabled to be connected to the DC voltage terminal under the drive of the previous level scanning signal.

[0025] Driven by the DC potential signal, the refresh selection unit is enabled to access the data memory signal provided by the data signal terminal, and the refresh start signal acting on the refresh start terminal is determined according to the data memory signal, triggering the gate scan unit to output the dynamic refresh signal line by line from the starting pixel row to refresh the dynamic refresh partition line by line.

[0026] The refresh operation of the gate scanning unit is terminated when the gate scanning unit scans to the final pixel row of the dynamic refresh partition, based on the reset signal at the reset terminal.

[0027] In one embodiment, after the step of refreshing the dynamically refreshed partition line by line, the refresh control method includes:

[0028] When the number of the dynamic refresh partitions is one, the step of terminating the partition refresh operation of the gate scan unit according to the reset signal of the reset terminal is executed until the gate scan unit scans to the final pixel row of the dynamic refresh partition.

[0029] When there are two dynamic refresh partitions, the dynamic refresh partition that is refreshed first among the two dynamic refresh partitions is determined as the first partition, and the dynamic refresh partition other than the first partition among the two dynamic refresh partitions is determined as the second partition. If the gate scan unit scans to the final pixel row of the first partition, the gate scan unit is triggered to terminate the partition refresh operation according to the partition termination signal at the termination signal terminal, and then the gate scan unit is reset according to the reset signal.

[0030] After being enabled and reset, the gate scanning unit scans each pixel row after the first partition line by line according to a preset static refresh signal until it scans the starting pixel row in the second partition. Then, based on the fact that the scan drive signal output from the previous pixel row of the starting pixel row is a valid signal, the gate scanning unit is triggered to dynamically refresh the second partition.

[0031] In addition, to achieve the above objectives, this application also provides a display panel, which includes a display area and a non-display area. The display area is provided with a plurality of parallel rows of pixels, and the non-display area is arranged around the periphery of the display area. The non-display area is provided with the aforementioned partition refresh circuit.

[0032] When the number of dynamically refreshed partitions is one or two, the multiple cascaded gate scanning units in the partition refresh circuit are electrically connected one-to-one with the multiple pixel rows in the display area.

[0033] In one embodiment, when the number of the dynamic refresh partitions exceeds two, the partition refresh circuits are respectively disposed on a first side and a second side of the display area, with the second side being the opposite side of the first side;

[0034] The display area is provided with an odd row set and an even row set. The odd row set includes all pixel rows with odd numbers, and the even row set includes all pixel rows with even numbers.

[0035] Each level of the gate scanning unit in the partition refresh circuit on the first side is electrically connected to each pixel row in the odd row set;

[0036] Each level of the gate scanning unit in the partition refresh circuit located on the second side is electrically connected to each pixel row in the even-numbered row set.

[0037] Furthermore, to achieve the above objectives, this application also provides a display device, which includes the display panel described above; or,

[0038] The display device further includes a memory, a processor, and a refresh control program stored in the memory and executable on the processor, wherein the processor, when executing the refresh control program, implements the steps of the refresh control method described above.

[0039] The partitioned refresh circuit described in this application includes multiple cascaded gate drive modules. Each gate drive module integrates a gate scan unit and a refresh selection unit, enabling independent refresh rate control for different areas of the screen while maintaining visual smoothness, thereby reducing overall power consumption. Specifically, the gate scan unit receives the previous level scan signal from the previous level scan output terminal through its own input terminal. This allows it to accurately identify the starting pixel row of the dynamic refresh partition based on the previous level scan signal. Specifically, when the scanned pixel row of the previous level scan signal is the pixel row preceding the starting pixel row, the gate scan unit uses its own voltage input terminal, electrically connected to the DC voltage terminal, to receive a DC potential signal from the DC voltage terminal under the drive of the previous level scan signal. This DC potential signal is then transmitted to the refresh selection unit via the gate scan unit's own voltage output terminal, providing a precise potential trigger condition for the refresh selection unit's startup during the refresh preparation phase. Subsequently, through the electrical connection between the refresh selection unit and the data signal terminal, the refresh selection unit receives the data record from the data signal terminal under the trigger of the DC potential signal. The system remembers the data memory signal and determines the refresh start signal applied to the refresh start terminal of the gate scan unit. This allows the gate scan unit to automatically trigger the output of dynamic refresh signals line by line, starting from the identified initial pixel row, to perform partitioned refresh operations on all pixel rows within the dynamic refresh partition. Finally, when the gate scan unit reaches the final pixel row of the dynamic refresh partition, the refresh selection unit automatically resets and terminates the partitioned refresh operation based on the reset signal provided by the reset terminal. This strictly limits the refresh range to the specified dynamic refresh partition, achieving independently controllable refresh rates for the dynamic refresh partition. While maintaining the smoothness of dynamic images within the dynamic refresh partition, it avoids meaningless pixel refreshes in static image areas running at high refresh rates, thereby effectively reducing screen display power consumption. Attached Figure Description

[0040] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0041] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a schematic diagram of the partition refresh circuit involved in the embodiments of this application;

[0043] Figure 2 This is a schematic diagram of the cascaded structure of the gate driving module involved in the embodiments of this application;

[0044] Figure 3 This is a schematic diagram of the partition refresh circuit involved in the embodiment of this application;

[0045] Figure 4 This is a timing waveform diagram of a single-partition refresh scenario involved in the embodiments of this application;

[0046] Figure 5 This is another schematic diagram of the partition refresh circuit involved in the embodiment of this application;

[0047] Figure 6 This is a circuit diagram showing the selection and preparation phase when performing a partition refresh operation in a single-partition refresh scenario.

[0048] Figure 7 This is a circuit diagram showing the selection refresh phase when performing a partition refresh operation in a single-partition refresh scenario.

[0049] Figure 8 This is a circuit diagram of the termination refresh period during the selected refresh phase in a single-partition refresh scenario.

[0050] Figure 9 This is a circuit diagram of the signal reset period during the select refresh phase in a single-partition refresh scenario.

[0051] Figure 10 This is a circuit diagram showing the selection and preparation phase when the first partition performs a partition refresh operation in a dual-partition refresh scenario.

[0052] Figure 11 This is a timing waveform diagram of a dual-partition refresh scenario involved in the embodiments of this application;

[0053] Figure 12 This is a circuit diagram showing the first partition in the selection refresh phase during a partition refresh operation.

[0054] Figure 13 This is a circuit diagram showing the period when the first partition is in the selected refresh phase and the refresh is terminated during the partition refresh operation.

[0055] Figure 14 This is a circuit diagram showing the signal reset period during the selection refresh phase when the first partition is performing a partition refresh operation;

[0056] Figure 15 This is a schematic diagram of the structure of the display device involved in the embodiments of this application.

[0057] Explanation of icon numbers:

[0058] 10. Gate drive module; 11. Gate scan unit; 12. Refresh selection unit; VDS, DC potential signal; Vdata, data memory signal; ctrl, reset signal; CLKn, first clock signal; CLKn+1, second clock signal; end, partition termination signal; Pn, first potential node; Qn, second potential node; VGL, low potential terminal; M1, first switch; M2, second switch; M3, third switch; M4, fourth switch; M5, fifth switch; C1, first capacitor; 1001. Processor; 1002. Communication bus; 1003. User interface; 1004. Network interface; 1005. Memory.

[0059] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0060] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0061] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0062] Furthermore, if the embodiments of this application involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0063] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0064] With the continuous development of display technology, users have increasingly higher requirements for the power consumption and display effect of mobile device screens. In the current partitioned refresh circuit design, the display screen of mobile devices can only operate at a globally fixed refresh rate (such as 60Hz or 120Hz). Even when displaying static images (such as reading text or viewing pictures), the display screen continues to refresh at a high refresh rate, resulting in a large amount of power being wasted on meaningless pixel refreshes. The increased power consumption brought about by the upgrading of processors in mobile devices requires lower power consumption of the display screen to balance the distribution of power.

[0065] Currently, adaptive refresh technology is commonly used in the industry as the mainstream screen power consumption optimization solution. However, although the current adaptive refresh technology can dynamically select a fixed refresh rate according to the display scenario, it can only achieve a single refresh rate change across the entire screen. When the display screen of a mobile device simultaneously displays dynamic and static images, the adaptive refresh technology must still operate at a high refresh rate and cannot independently adjust the refresh rate for different areas, thus limiting further reductions in screen power consumption and restricting its application scenarios.

[0066] Therefore, while maintaining visual smoothness, how to achieve independent refresh rate control for different areas of the screen to reduce screen display power consumption is a technical problem that urgently needs to be solved.

[0067] To address the aforementioned technical deficiencies, this application provides a partitioned refresh circuit and its refresh control method, a display panel, and a display device.

[0068] This application provides a partition refresh circuit, referring to... Figure 1 As shown, Figure 1 This is a structural block diagram of the first embodiment of the partition refresh circuit of this application. The partition refresh circuit includes multiple cascaded gate driving modules 10, and each gate driving module 10 includes:

[0069] Gate scanning unit 11, wherein the input terminal of the gate scanning unit 11 is configured to receive the scanning signal provided by the output terminal of the previous stage scanning unit, the voltage input terminal of the gate scanning unit 11 is electrically connected to the DC voltage terminal, and the gate scanning unit 11 is configured to determine the starting pixel row of the dynamic refresh partition. When the scanning pixel row of the previous stage scanning signal is the pixel row preceding the starting pixel row, the DC potential signal VDS of the DC voltage terminal is received under the drive of the previous stage scanning signal.

[0070] In this embodiment, the input terminal of the gate scanning unit 11 in each gate driving module 10 is electrically connected to the scanning output terminal of the previous stage gate driving module 10. When the gate scanning unit 11 receives the scanning signal provided by the previous stage scanning output terminal, the starting pixel row of the dynamic refresh partition can be accurately identified based on the scanning signal. Specifically, since the previous stage scanning signal carries a pixel row number identifier, the pixel row mapped by the pixel row number identifier can be used as the scanning pixel row. When this scanning pixel row is the pixel row preceding the starting pixel row in the dynamic refresh partition, the gate scanning unit 11, driven by the previous stage scanning signal, introduces the DC potential signal VDS from the voltage input terminal and outputs it to the voltage output terminal. Thus, the DC potential signal VDS can be transmitted to the refresh selection unit 12 through the voltage output terminal, providing an accurate and reliable trigger signal for the subsequent refresh selection unit 12 to mark the starting pixel row.

[0071] It should be noted that dynamic refresh partitions can be understood as display areas within the display screen that are configured to perform refresh operations at a first refresh rate (i.e., partition refresh operations); where the first refresh rate is usually higher than the refresh rate of other static display areas within the display screen, in order to adapt to the display requirements of dynamic or high-speed changing images (such as video playback images or game images).

[0072] The starting pixel row can be understood as the first pixel row that triggers the start of dynamic refresh partition operation. The starting pixel row can be accurately determined by the detection of the previous level scan signal by the gate scan unit 11.

[0073] In a specific embodiment, multiple gate driving modules 10 (i.e. Figure 2 The gate driving modules 10_(n-1), 10_n, and 10_(n+1) shown are cascaded to form the core driving architecture of the partitioned refresh circuit. Each gate driving module 10 corresponds to a pixel row in the display panel and provides a scan driving signal to the corresponding pixel row through its own scan output terminal. For example, the input terminal of the gate driving module 10_n is electrically connected to the scan output terminal of the previous stage gate driving module 10_(n-1) to receive the scan driving signal Gn-1 output from the previous stage gate driving module 10_(n-1). At the same time, the scan output terminal of the gate driving module 10_n is electrically connected to the scan input terminal (i.e., the next stage input terminal) of the next stage gate driving module 10_(n+1) to transmit the scan driving signal Gn generated at this stage to the next stage gate driving module 10_(n+1). Similarly, all gate drive modules 10 are cascaded in the above connection method to form a chain drive structure that can trigger row by row and transmit scan drive signals sequentially.

[0074] It should be noted that, Figure 2 The scan drive signal Gn-1 shown is provided to pixel row n-1 by the gate drive module 10n-1, which integrates gate scan unit 11_n-1 and refresh selection unit 12_n-1. At the same time, the scan drive signal Gn-1 also serves as the previous scan signal of the gate drive module 10_n, which is used to trigger the gate drive module 10_n to generate its corresponding scan drive signal Gn. Figure 2 The scan drive signal Gn shown is a drive signal provided to pixel row n by the gate drive module 10n, which integrates gate scan unit 11_n and refresh selection unit 12_n. At the same time, the scan drive signal Gn also serves as the previous level scan signal of the gate drive module 10_(n+1), which is used to trigger the gate drive module 10_(n+1) to generate its corresponding scan drive signal Gn+1. Figure 2 The scan drive signal Gn+1 shown is provided to pixel row n+1 by the gate drive module 10n+1, which integrates gate scan unit 11_n+1 and refresh selection unit 12_n+1. At the same time, the scan drive signal Gn+1 also serves as the previous scan signal of the gate drive module 10_(n+2), which is used to trigger the subsequent gate drive module 10 to generate the corresponding scan drive signal, thereby maintaining the continuous operation of the chain drive structure.

[0075] Furthermore, it should be noted that the gate drive module 10 can integrate transistor-capacitor combination circuits such as 5T1C, 6T1C, or 9T2C. Figure 3 The gate driving module 10 of 9T2C (i.e., thin film transistors T1~T9 and capacitors C2~C1) shown is only one feasible implementation of this application, and this application does not limit it.

[0076] A refresh selection unit 12 is electrically connected to a data signal terminal, a reset terminal, the voltage output terminal of the gate scan unit 11, and the refresh start terminal of the gate scan unit 11. The refresh selection unit 12 is configured to receive a data memory signal Vdata provided by the data signal terminal under the drive of the DC potential signal VDS, and determine the refresh start signal acting on the refresh start terminal based on the data memory signal Vdata, triggering the gate scan unit 11 to output dynamic refresh signals line by line starting from the starting pixel line, so as to perform partition refresh operation on all pixel lines of the dynamic refresh partition, until the gate scan unit 11 scans to the final pixel line of the dynamic refresh partition, and terminates the partition refresh operation based on the reset signal ctrl of the reset terminal.

[0077] In this embodiment, through the electrical connection between the refresh selection unit 12 and the voltage output terminal of the gate scan unit 11, the refresh selection unit 12 receives the data memory signal Vdata from the data signal terminal under the drive of the DC potential signal VDS. Next, based on the data memory signal Vdata, the refresh start signal acting on the refresh start terminal of the gate scan unit 11 is determined. Thus, the gate scan unit 11 can be automatically triggered to output dynamic refresh signals line by line starting from the starting pixel line in the dynamic refresh partition. The partition refresh operation is performed sequentially on all pixel lines in the dynamic refresh partition until the gate scan unit 11 scans to the final pixel line of the dynamic refresh partition. At this point, the refresh selection unit 12 automatically resets and terminates the partition refresh operation based on the reset signal ctrl provided by the reset terminal. This strictly limits the refresh range to the specified dynamic refresh partition, realizing an independently controllable refresh rate for the dynamic refresh partition. While maintaining the smoothness of the dynamic image in the dynamic refresh partition, it avoids meaningless pixel refreshes in the static image area when running at a high refresh rate, thereby effectively reducing the power consumption of the screen display.

[0078] It should be noted that refresh selection unit 12 is... Figure 3 The first capacitor C1 and the first to fifth switching transistors M1 and M5 are shown. The input terminal of the gate scanning unit 11 can be the gate of the thin film transistor T1, and the voltage output terminal of the gate scanning unit 11 can be the first path terminal of the thin film transistor T9. The first path terminal refers to one end of the output scanning drive signal Gn. The refresh start terminal of the gate scanning unit 11 is the second potential node Qn.

[0079] The data memory signal Vdata is in a high-level state when performing a partition refresh operation on the dynamically refreshed partition.

[0080] The dynamic refresh signal refers to the scan drive signal output by the gate drive module 10, which is electrically connected to each pixel row in the dynamic refresh partition. When the starting pixel row of the dynamic refresh partition is the nth pixel row and the final pixel row of the dynamic refresh partition is the (n+3)th pixel row, the dynamic refresh signal specifically includes a scan signal sequence composed of scan drive signals Gn, Gn+1, Gn+2, and Gn+3 output by gate drive modules 10_n, 10_n+1, 10_n+2, and 10_n+3. This scan signal sequence has strict timing continuity in the partition refresh mode. The scan drive signal Gn serves as the trigger signal for the starting pixel row within the dynamic refresh partition. Figure 2 The cascaded gate drive module 10 shown sequentially transmits and triggers the outputs of scan drive signals Gn+1, Gn+2, and Gn+3, forming a... Figure 4 The waveform shown is a continuous local refresh waveform from the nth pixel row to the (n+3)th pixel row.

[0081] In a specific embodiment, when the refresh start terminal of the gate scan unit 11 in the gate drive module 10_n receives a valid refresh start signal, the gate scan unit 11 outputs a scan drive signal Gn under the drive of the refresh start signal. This scan drive signal Gn not only drives the nth pixel row, but also serves as a cascade trigger signal to the gate drive module 10_n+1, causing the gate drive module 10_n+1 to also output a scan drive signal Gn+1. This process continues sequentially until the gate drive module 10_n+3 outputs a scan drive signal Gn+3, forming a complete four-row dynamic refresh sequence, ensuring that all pixel rows within the dynamic refresh partition can complete the targeted refresh operation in sequence.

[0082] Furthermore, in some other feasible embodiments, the gate driving module 10 includes a first clock terminal and a second clock terminal. The first clock terminal is used to provide a first clock signal CLKn, and the second clock terminal is used to provide a second clock signal CLKn+1 that is inverted from the first clock signal CLKn. The clock access terminal of the refresh selection unit 12 is electrically connected to the target clock terminal, and the clock potential terminal of the gate scanning unit 11 is electrically connected to the clock terminal that is inverted from the target clock terminal. The target clock terminal is either the first clock terminal or the second clock terminal. In the multiple cascaded gate driving modules 10, the target clock signals provided by the target clock terminals in adjacent gate driving modules 10 are inverted.

[0083] In this embodiment, refer to Figure 4 The first clock signal CLKn provided by the first clock terminal and the second clock signal CLKn+1 provided by the second clock terminal are interleaved clock signal pairs with the same frequency but opposite phases, that is, the first clock signal CLKn and the second clock signal CLKn+1 are out of phase. Specifically, if the target clock terminal electrically connected to the clock access terminal of the refresh selection unit 12 is the second clock terminal, then the clock potential terminal of the gate scan unit 11 is electrically connected to the clock terminal that is out of phase with the target clock terminal as the first clock terminal, and the target clock signal provided by the target clock terminal in the adjacent gate drive module 10 is set to be out of phase, forming an interleaved clock control architecture. Next, based on this interleaved clock control architecture, the gate drive modules 10 of adjacent rows are alternately activated under the drive of mutually out of phase clock signals, thereby realizing the row-by-row transmission and precise control of the scan drive signal. This configuration not only effectively avoids the overlap and crosstalk of adjacent row drive signals, but also ensures the stable transmission of cascaded signals in the partition refresh process, providing key timing guarantees for the accurate delineation of dynamic refresh partitions and the reliable execution of independent refresh operations.

[0084] In a specific embodiment, taking the gate driving module 10_n and the gate driving module 10_n+1 electrically connected to the nth pixel row as examples, the refresh selection unit 12 in the gate driving module 10_n is connected to the second clock signal CLKn+1, and the gate scanning unit 11 in the gate driving module 10_n is connected to the first clock signal CLKn; while the refresh selection unit 12 in the gate driving module 10_n+1 is connected to the first clock signal CLKn, and the gate scanning unit 11 in the gate driving module 10_n+1 is connected to the second clock signal CLKn+1; next, when the first clock signal CLKn is... Figure 3 When the high-level state is shown, the gate scanning unit 11 in the gate driving module 10_n is activated and outputs the scan driving signal Gn when the thin film transistor T9 is turned on, realizing the pixel refresh of the nth pixel row; at the same time, the second clock signal CLKn+1 is in a low-level state, so that the gate scanning unit 11 in the gate driving module 10_n+1 is in an inactive state, thereby ensuring the alternating operation of the gate driving modules 10 of adjacent stages, not only avoiding the overlap and interference of adjacent row scan signals, but also ensuring the stable transmission of cascaded scan signals, providing a precise timing basis for the implementation of the partition refresh function.

[0085] Furthermore, in some feasible embodiments, reference is made to Figure 3 The refresh selection unit 12 includes a refresh control subunit and a refresh reset subunit. The refresh control subunit is electrically connected to the data signal terminal, the current stage voltage output terminal, the refresh start terminal, and the refresh reset subunit, respectively. The refresh control subunit includes: a first potential node Pn; a first switching transistor M1, the gate of which is electrically connected to the current stage voltage output terminal, the first path terminal of which is electrically connected to the data signal terminal, and the second path terminal of which is electrically connected to the first potential node Pn; and a second switching transistor M2, the gate of which is electrically connected to the data signal terminal. The first potential node Pn is electrically connected; the first path terminal of the second switch M2 is electrically connected to the data signal terminal; the second path terminal of the second switch M2 is electrically connected to the voltage output terminal of this stage; the third switch M3 has its gate electrically connected to the second path terminal of the second switch M2; the first path terminal of the third switch M3 is electrically connected to the target clock terminal; the second path terminal of the third switch M3 is electrically connected to the refresh start terminal of the gate scan unit 11; and the first capacitor C1 is connected between the first potential node Pn and the second path terminal of the second switch M2.

[0086] In this embodiment, refer to Figure 3If the starting pixel row of the dynamically refreshed partition is the nth pixel row, and if the scan drive signal Gn-1 connected to the thin-film transistor T1 in the gate drive module 10_n is... Figure 4 When the high-level state is shown, it marks the selection preparation stage for the partition refresh operation of the gate drive module 10_n. At this time, the thin-film transistor T1 switches from the cutoff state to the on state under the drive of the scan drive signal Gn-1. Then, the DC potential signal VDS of the DC voltage terminal is introduced to the gate of the first switch transistor M1 through the on-state thin-film transistor T1, so that the first switch transistor M1 switches from the cutoff state to the on state under the drive of the DC potential signal VDS. Then, the data memory signal Vdata provided by the data signal terminal is written to the first potential node Pn through the on-state first switch transistor M1, so that the potential of the first potential node Pn is pulled high. The first capacitor C1, which is electrically connected to the first potential node Pn, stores and holds the data memory signal Vdata, thereby completing the accurate identification and potential marking of the starting pixel row.

[0087] Next, since the high potential of the first potential node Pn acts on the gate of the second switch M2, the second switch M2 switches from the cutoff state to the on state under the high potential drive of the first potential node Pn. Thus, the high potential data memory signal Vdata can be transmitted to the gate of the third switch M3 through the on-state second switch M2. The third switch M3 switches from the cutoff state to the on state under the drive of the data memory signal Vdata. Thus, the target clock signal of the target clock terminal can be used as the refresh start signal to act on the refresh start terminal (i.e., the second potential) of the gate drive unit through the third switch M3. This causes the gate scan unit 11 in the gate drive module 10_n to perform the selective refresh stage of the partition refresh operation, triggering the gate scan unit 11 to output the dynamic refresh signal line by line starting from the nth row, thereby realizing the line-by-line refresh operation of the dynamic refresh partition.

[0088] It should be noted that the initiation of the refresh phase depends on the coordinated action of the potential state stored in the first potential node Pn and the data memory signal Vdata provided by the data signal terminal. Only when the first potential node Pn maintains a high potential and the data signal terminal outputs a high-potential data memory signal Vdata can the second switch M2 and the third switch M3 be turned on successively, so as to determine the target clock signal provided by the target clock terminal, which is in a high-level state, as a valid refresh start signal.

[0089] The first switch M1 to the fifth switch M5 in the refresh selection unit 12 can be electrical components with switching characteristics, such as thin-film transistors, MOSFETs, and triodes.

[0090] Furthermore, in some other feasible embodiments, reference is made to... Figure 3 The refresh start terminal of the gate scanning unit 11 is the second potential node. The refresh reset subunit includes a fourth switch M4 and a fifth switch M5. The gate of the fourth switch M4 is electrically connected to the reset terminal. The first path terminal of the fourth switch M4 is electrically connected to the target clock terminal. The second path terminal of the fourth switch M4 is electrically connected to the gate of the fifth switch M5. The first path terminal of the fifth switch M5 is electrically connected to the low potential terminal VGL. The second path terminal of the fifth switch M5 is electrically connected to the second potential node Qn.

[0091] In this embodiment, refer to Figure 3 If the dynamically refreshed partition is the (n+3)th pixel row, in Figure 4 After the scan drive signal Gn+3 in the high-level state completes the pixel refresh of the (n+3)th pixel row, the second potential node Qn+3 in the gate drive module 10_n+3 is pulled high. At this time, the reset terminal outputs... Figure 4The reset signal ctrl, which is in a high-level state, turns on the fourth switch M4, thereby transmitting the target clock signal to the gate of the fifth switch M5 through the turned-on fourth switch M4. This, in turn, turns on the fifth switch M5 to connect the second potential node Qn+3 to the low-potential terminal VGL, causing the potential of the second potential node Qn+3 to be rapidly pulled down to the low-potential terminal VGL. This causes the scan drive signal Gn+3 to quickly switch from a high-level state to a low-level state, meaning that the scan drive signal Gn+3 is no longer output, marking the end of the selection refresh phase. Next, to prevent the high-level target clock signal from causing the second potential node Qn+2 in the gate scan unit 11_n+2 to remain abnormally high, and thus mistakenly triggering the gate scan unit 11_n+3 to output a high-level scan drive signal Gn... +3, therefore, the reset signal ctrl is kept at a high level. When the target clock signal in the gate drive module 10_n+2, which is electrically connected to the (n+2)th pixel row, is at a high level, the reset signal ctrl controls the fourth switch M4 to turn on, converting the high-level target clock signal into an effective drive for the gate of the fifth switch M5. Then, through the turned-on fifth switch M5, the second potential node Qn+2 is connected to the low potential terminal VGL, forcibly pulling the potential of the second potential node Qn+2 down to the potential reset level of the low potential terminal VGL. This completely eliminates the hidden danger of residual potential in the second potential node Qn+2, effectively preventing the problem of false triggering of the scan drive signal Gn+3 due to incomplete reset of the potential of the second potential node Qn+2, and ensuring the reliability and stability of the termination partition operation. Subsequently, the gate drive module 10 participating in this partition refresh operation enters the selection reset phase. Specifically, the gate drive module 10_n+3 and subsequent gate drive modules 10 output scan drive signals line by line at a low refresh rate to refresh their respective pixel rows. This ensures that the energy-saving display in the non-dynamic refresh area outputs low refresh rate scan drive signals to refresh their respective pixel rows line by line. This continues until the scan drive signal is transmitted to the starting pixel row of this partition operation again. Since the data signal terminal is in a low-level state in low refresh mode, the potential of the first potential node PnP is pulled low through the first switch transistor M1, thus clearing the starting pixel row mark and providing a clean initial state for the start of the next partition refresh operation.

[0092] Furthermore, in some feasible embodiments, when there are two dynamic refresh partitions, the gate drive module 10 further includes a sixth switch and a termination signal terminal; the gate of the sixth switch is electrically connected to the termination signal terminal, the first path terminal of the sixth switch is electrically connected to the voltage access terminal of this stage, and the second path terminal of the sixth switch is electrically connected to the low potential terminal VGL.

[0093] In this embodiment, refer to Figure 5When there are two dynamic refresh partitions, in order to prevent the uncontrolled partition refresh operation of a single dynamic refresh partition from continuing to another dynamic refresh partition in a dual-partition refresh scenario, thus causing the refresh boundary to become uncontrolled, the gate drive module 10 provided in this application can also be equipped with a sixth switch and a termination signal terminal. Figure 5 The circuit structure shown allows for the output of a valid partition termination signal end when the partition refresh operation of each dynamic refresh partition is completed in a dual-partition refresh scenario. This signal is then sent to the gate drive module 10 electrically connected to the final pixel row in each dynamic refresh partition. When the sixth switch in this gate drive module 10 switches from the off state to the on state under the drive of the partition termination signal end, the on-state sixth switch can pull the gate potential of the thin-film transistor T1 in this gate drive module 10 down to the low potential VGL. This forcibly blocks the transmission of the scan drive signal acting on the final pixel row to the gate drive module 10 electrically connected to the next pixel row, thereby eliminating signal crosstalk between each dynamic refresh partition and ensuring the independent operation of the partition refresh operation within each dynamic refresh partition.

[0094] It should be noted that the first path terminal of the sixth switch can be connected to the circuit. Figure 5 The scanning drive signal Gn-1 shown is electrically connected to its local voltage input terminal, and can also be connected to... Figure 5 The port connected to the scan drive signal Gn+1 is shown to be electrically connected.

[0095] Furthermore, based on the first embodiment of the partition refresh circuit of this application, a second embodiment of the refresh control method of this application is proposed.

[0096] The refresh control method of this application is applied to the partition refresh circuit of any of the above-mentioned applications. The refresh control method of this application is executed by the display device applied to the partition refresh circuit. The refresh control method of this application includes the following implementation steps S10 to S30.

[0097] Step S10: When the gate scanning unit 11 receives the previous level scanning signal output by the previous level gate driving module 10, the starting pixel row of the dynamic refresh partition is determined.

[0098] In this embodiment, refer to Figures 2 to 3When the gate scanning unit 11_n in the gate driving module 10_n receives the scan driving signal Gn-1 (i.e., the previous level scan signal) output by the previous level gate driving module 10_n-1, the gate scanning unit 11_n determines the starting pixel row of the dynamic refresh partition by identifying the pixel row number carried by the scan driving signal Gn-1. Specifically, when the scan pixel row of the scan driving signal Gn-1 is the pixel row preceding the starting pixel row, the gate scanning unit 11_n introduces the DC potential signal VDS from the DC voltage terminal under the drive of the scan driving signal Gn-1, and writes the data memory signal Vdata provided by the data signal terminal to the first potential node Pn for storage and retention through the conduction of the first switch M1. This completes the accurate identification and potential marking of the starting pixel row, laying the foundation for the start of subsequent partition refresh operations and ensuring that the partition refresh operation of the dynamic refresh partition can be accurately started from the starting pixel row.

[0099] Step S20: When the scanning pixel line of the previous level scanning signal is the pixel line preceding the starting pixel line, the DC potential signal VDS of the gate scanning unit 11 connected to the DC voltage terminal is enabled under the drive of the previous level scanning signal.

[0100] In this embodiment, we take a gate driving module 10_n, which integrates a gate scanning unit 11_n and a refresh selection unit 12_n, as an example, where the starting pixel row is the nth pixel row. Specifically, in Figure 5 During the accurate selection stage of the partition refresh operation, when the scan pixel row of the scan drive signal Gn-1 (i.e., the previous level scan signal) is the pixel row preceding the starting pixel row, the thin film transistor T1 in the gate scan unit 11_n switches from the off state to the on state, thereby introducing the DC potential signal VDS provided by the DC voltage terminal to the gate of the first switch transistor M1 in the refresh selection unit 12_n. This causes the first switch transistor M1 to switch from the off state to the on state under the drive of the DC potential signal VDS, thus establishing a path for the subsequent writing of the data memory signal Vdata through the on-state first switch transistor M1.

[0101] Step S30: Driven by the DC potential signal VDS, enable the refresh selection unit 12 to access the data memory signal Vdata provided by the data signal terminal, and determine the refresh start signal acting on the refresh start terminal according to the data memory signal Vdata, triggering the gate scan unit 11 to output dynamic refresh signals line by line from the starting pixel row, so as to refresh the dynamic refresh partition line by line.

[0102] In this embodiment, refer to Figure 6 The selected preparation stage for the partition refresh operation is shown. Figure 6The bold lines shown indicate the signal flow path during the selection preparation stage. In the refresh selection unit 12_n, the first switch M1 is turned on under the drive of the DC potential signal VDS, thus establishing a stable write path for the data memory signal Vdata provided by the data signal terminal. At this time, the data memory signal Vdata is written to the first potential node Pn through the turned-on first switch M1, and stored and maintained by the first capacitor C1 electrically connected to the first potential node Pn, effectively ensuring the stability and anti-interference capability of the marker start pixel row signal. Next, referring to... Figure 7 The selected refresh stage for the shown partition refresh operation. Figure 7 The bold lines shown indicate the signal flow path during the refresh selection phase. At this time, the high-potential data memory signal Vdata stored at the first potential node Pn acts on the gate of the second switch M2 in the refresh selection unit 12_n, causing the second switch M2 to switch from the off state to the on state. This allows the data memory signal Vdata, carrying the high-potential refresh command, to be transmitted from the data signal terminal to the gate of the third switch M3 through the on-state second switch M2. Simultaneously, the third switch M3, driven by the data memory signal Vdata, switches from the off state to the on state, forming a complete path from signal storage to signal transmission. Thus, the on-state third switch M3 can use the high-potential target clock signal provided by the target clock terminal as an effective refresh start signal to act on the refresh start terminal of the gate scan unit 11_n. This causes the gate scan unit 11_n to output a scan drive signal Gn to refresh its electrically connected nth pixel row at a high frequency. Simultaneously, the scan drive signal Gn output by the gate scan unit 11_n is provided as a cascade signal to the next-level gate drive module 10_n+1, ensuring that the partition refresh operation within the dynamic refresh partition is performed correctly. Figure 2 The module cascade structure shown enables continuous transmission and precise execution, achieving display power optimization while maintaining visual smoothness in dynamic areas.

[0103] Step S40: When the gate scanning unit 11 scans to the final pixel row of the dynamic refresh partition, the partition refresh operation of the gate scanning unit 11 is terminated according to the reset signal ctrl of the reset terminal.

[0104] In this embodiment, refer to Figure 8 The image shows the termination refresh period during the selected refresh phase. Figure 8The bold lines shown indicate the signal flow path during the refresh termination period. Taking the (n+3)th pixel row as the final pixel row of the dynamic refresh partition as an example, when the gate scanning unit 11_n+3 in the gate drive module 10_n+3 completes the high-frequency refresh of the (n+3)th pixel row, the reset terminal outputs a valid reset signal ctrl (i.e., a high-level reset signal ctrl) to turn on the fourth switch M4 in the refresh selection unit 12_n+3, establishing a critical path for the transmission of the reset signal ctrl. At this time, the target clock signal (i.e., the first clock signal CLKn) is transmitted to the gate of the fifth switch M5 through the turned-on fourth switch M4, driving the fifth switch M5 to switch from the off state to the on state. This establishes a complete partition refresh termination control path. Next, through the activated fifth switch M5, the second potential node Qn+3 in the gate scan unit 11_n+3 is connected to the low potential terminal VGL, causing the potential of the second potential node Qn+3 to be quickly pulled down to the low potential of the low potential terminal VGL. This achieves rapid zeroing of the potential of the second potential node Qn+3. Furthermore, through the low potential of the second potential node Qn+3, the scan drive signal Gn+3 is switched from a high level to a low level, so that the gate scan unit 11_n+3 no longer outputs a valid scan drive signal Gn+3. This ensures that the partition refresh operation is precisely terminated when the final pixel row is the (n+3)th pixel row.

[0105] Subsequently, referring to Figure 9 As shown, during the signal reset period of the refresh selection phase, to prevent the high-level target clock signal from causing the second potential node Qn+2 in the gate scan unit 11_n+2 to maintain an abnormally high potential state and mistakenly triggering the gate scan unit 11_n+3 to output a high-level scan drive signal Gn+3, the reset signal ctrl is continuously kept at a high level. When the target clock signal in the gate drive module 10_n+2, which is electrically connected to the (n+2)th pixel row, is also at a high level, the reset signal ctrl controls the fourth switch M4 to turn on, thus reducing the high-level target clock signal at this time. The standard clock signal (i.e., the second clock signal CLKn+1) is converted into an effective drive for the gate of the fifth switch M5. Then, the fifth switch M5, which is turned on, connects the second potential node Qn+2 to the low potential terminal VGL, forcibly pulling the potential of the second potential node Qn+2 down to the potential reset level of the low potential terminal VGL. This completely eliminates the hidden danger of residual potential at the second potential node Qn+2 and effectively prevents the problem of false triggering of the scan drive signal Gn+3 due to incomplete reset of the potential at the second potential node Qn+2. This ensures the reliability and stability of the termination partitioning operation.

[0106] In another embodiment, after the potential reset of the second potential node Qn+2 is completed, the selection reset stage is entered. Specifically, the gate drive module 10_n+3 and the subsequent gate drive module 10 output scan drive signals at a low refresh rate to refresh their respective pixel rows. This ensures that the energy-saving display in the non-dynamic refresh area outputs low refresh rate scan drive signals to refresh their respective pixel rows line by line. Until the scan drive signal is transmitted to the starting pixel row of this partition operation again, since the data signal terminal is in a low level state in low refresh mode, the potential of the first potential node PnP is pulled low through the first switch M1, completing the clearing of the starting pixel row mark, so as to provide a clean initial state for the start of the next partition refresh operation.

[0107] Furthermore, in some other feasible embodiments, after step S30 above: refreshing the dynamically refreshed partition line by line, the refresh control method includes:

[0108] Step A10: When the number of the dynamic refresh partitions is one, the step of terminating the partition refresh operation of the gate scan unit 11 according to the reset signal ctrl of the reset terminal is executed until the gate scan unit 11 scans to the final pixel row of the dynamic refresh partition.

[0109] In this embodiment, when there is only one dynamic refresh partition, i.e., the display panel is in a single-partition refresh scenario, the coordinated control of the refresh selection unit 12 and the gate scanning unit 11 enables precise marking of the initial pixel row, reliable initiation of the high refresh rate partition refresh operation, line-by-line refresh within a single dynamic refresh partition, termination of the partition refresh operation at the final pixel row, and partition refresh control of the reset circuit. This not only dynamically adapts to the display content to achieve a balance between local high-frequency refresh and global low power consumption, but also effectively eliminates signal residue and false triggering risks through the timing coordination of the reset signal ctrl and the target clock signal and the hierarchical reset mechanism. This ensures that only the dynamic refresh partition performs the high refresh rate partition refresh operation, achieving an independently controllable refresh rate for the dynamic refresh partition. While maintaining the smoothness of the dynamic image within the dynamic refresh partition, it avoids meaningless pixel refreshes in static image areas running at high refresh rates, thereby effectively reducing screen display power consumption.

[0110] Step A20: When there are two dynamic refresh partitions, the dynamic refresh partition that is refreshed first among the two dynamic refresh partitions is determined as the first partition, and the dynamic refresh partition other than the first partition among the two dynamic refresh partitions is determined as the second partition. If the gate scan unit 11 scans to the final pixel row of the first partition, the gate scan unit 11 is triggered to terminate the partition refresh operation according to the partition termination signal end at the termination signal terminal, and then the gate scan unit 11 is reset according to the reset signal ctrl.

[0111] In this embodiment, when there are two dynamically refreshed partitions, a sixth switch controlled by the partition termination signal end can be added at Gn-1 or Gn+1 in each gate drive module 10, and according to... Figure 11 The timing diagram shown illustrates the partition refresh operation in the dual-partition refresh scenario. For example, in the first partition, pixel row n (i.e., the nth pixel row) is selected as the refresh start point, and pixel row n+3 (i.e., the (n+3)th pixel row) is selected as the refresh end point.

[0112] exist Figure 10 The first partition is shown in the preparation phase when performing a partition refresh operation. Figure 10 The bold lines shown indicate the signal flow path during the selection preparation phase. When the scan drive signal Gn-1 is in... Figure 11 When the high level state is shown, Figure 10 The thin-film transistor T1 in the gate driving module 10_n is turned on, so that the DC potential signal VDS is transmitted to the gate of the first switch transistor M1 through the turned-on thin-film transistor T1, thereby triggering the first switch transistor M1 to switch from the cut-off state to the on state under the drive of the DC potential signal VDS. The data memory signal Vdata is connected through the turned-on first switch transistor M1 to pull up the potential of the first potential node Pn and maintain the high potential of the first potential node Pn through the first capacitor C1.

[0113] Subsequently, Figure 12 The first partition shown is selected during the refresh phase of the partition refresh operation. Figure 12 The target clock signal provided by the target clock terminal in the gate drive module 10_n is the second clock signal CLKn+1. When the second clock signal CLKn+1 is in Figure 11When the high-level state is shown, the high-potential first potential node Pn acts on the gate of the second switch M2, causing the second switch M2 to switch from the off state to the on state. This allows the data memory signal Vdata, carrying the high-potential refresh instruction, output from the data signal terminal, to be transmitted to the gate of the third switch M3 through the on-state second switch M2. At this time, the third switch M3, driven by the data memory signal Vdata, switches from the off state to the on state, forming a complete path from signal storage to signal transmission. Thus, the second clock signal CLKn+1 can be transmitted to the second node potential as an effective refresh start signal through the on-state third switch M3. By pulling up the second node potential, the scan drive signal Gn is output to refresh the nth pixel row electrically connected to it at a high frequency. Simultaneously, the scan drive signal Gn output from the gate scan unit 11_n is provided as a cascade signal to the next-stage gate drive module 10_n+1, ensuring that the partition refresh operation within the first partition is performed within the first partition. Figure 2 The module cascade structure shown enables continuous transmission and precise execution, achieving display power optimization while maintaining visual smoothness in dynamic areas.

[0114] Next, in Figure 13 The termination refresh period for the first partition's partition refresh operation, as shown, is during this period. Figure 13 In the gate drive module 10_n+3 shown, after the scan drive signal Gn+3 completes the high-frequency refresh of pixel row n+3 (i.e., the (n+3)th pixel row), the termination signal terminal provides a partition termination signal end representing a high potential to turn on the sixth switch. This, through the turned-on sixth switch, pulls the scan drive signal Gn+2 connected to the gate drive module 10_n+3 low to the low potential terminal VGL, thereby interrupting the effective output of the scan drive signal Gn+2. Figure 13 The thin-film transistor T1 shown cannot be turned on, that is, the thin-film transistor T1 is in the off state. At this time, the scan drive signal Gn+3 is always in a low level and is no longer effective, marking the end of the partition refresh operation of the first partition.

[0115] Subsequently, Figure 14 The signal reset period during which the first partition performs a partition refresh operation is shown, triggering the reset signal ctrl provided by the reset terminal. Figure 11As shown in the high-level state, the high-potential reset signal ctrl turns on the fourth switch M4 in the gate drive module 10_n+2, converting the high-potential second clock signal CLKn+1 into an effective drive for the gate of the fifth switch M5. This, in turn, connects the second potential node Qn+2 to the low potential terminal VGL through the turned-on fifth switch M5, forcibly pulling the potential of the second potential node Qn+2 down to the low potential terminal VGL's reset level. This completely eliminates the potential lingering risk of the second potential node Qn+2's potential, allowing the gate drive module 10_n+2 to be reset. This effectively prevents the scan drive signal Gn+3 from being falsely triggered due to incomplete reset of the second potential node Qn+2, ensuring the reliability and stability of the termination partitioning operation.

[0116] It should be noted that in the second partition, the starting point for refreshing is pixel row n+5 (i.e., the nth pixel row), and the ending point for refreshing is pixel row n+8 (i.e., the n+8th pixel row). That is, pixel row n+5 is the starting pixel row in the second partition, and pixel row n+8 is the final pixel row.

[0117] Step A30: After being enabled and reset, the gate scanning unit 11 scans each pixel row after the first partition line by line according to the preset static refresh signal until it scans the starting pixel row in the second partition. Then, the gate scanning unit 11 is triggered to dynamically refresh the second partition based on the scan drive signal output from the previous pixel row of the starting pixel row being a valid signal.

[0118] In this embodiment, by Figure 2 Enable the module cascade structure shown Figure 13The gate drive module 10_n+3 shown follows the reset action of the gate drive module 10_n+2, completing the reset of the gate drive module 10_n+3. This enables the subsequent gate drive modules 10 to output scan drive signals line by line at a low refresh rate to refresh their respective pixel rows until pixel row n+5 in the second partition is scanned. At this point, the scan drive signal Gn+4 connected to the gate drive module 10_n+5 electrically connected to pixel row n+5 becomes a valid signal, marking that the second partition has entered the selection preparation stage for performing the partition refresh operation. Since the target time in the gate drive module 10_n+5 is... The clock terminal is the first clock terminal. At this time, the data memory signal Vdata is pulled high when the first clock signal CLKn provided by the first clock terminal is at a high level. The thin film transistor T1 in the gate drive module 10_n+5 is turned on, so that the DC potential signal VDS is transmitted to the gate of the first switch transistor M1 through the turned thin film transistor T1, thereby triggering the first switch transistor M1 to switch from the cut-off state to the on state under the drive of the DC potential signal VDS. The data memory signal Vdata is connected through the turned first switch transistor M1 to pull up the potential of the first potential node Pn and the first potential node Pn is maintained at a high potential through the first capacitor C1.

[0119] Subsequently, during the selective refresh phase of the partition refresh operation in the second partition, in the gate drive module 10_n+5, the high-potential first potential node Pn triggers the second switch M2 to conduct, transmitting the pulled-up data memory signal Vdata to the gate of the third switch M3. At this time, the third switch M3, driven by the data memory signal Vdata, switches from the off state to the on state, forming a complete path from signal storage to signal transmission. Thus, the on-state third switch M3 can transmit the second clock signal CLKn+1 as an effective refresh start signal to the second node potential. The high-potential output of the second node, the scan drive signal Gn+5, refreshes the electrically connected pixel row n+5 at a high frequency. Simultaneously, the scan drive signal Gn+5 output from the gate scan unit 11_n+5 is provided as a cascade signal to the next-stage gate drive module 10_n+6, ensuring that the partition refresh operation within the second partition is performed correctly. Figure 2 The module cascade structure shown enables continuous transmission and precise execution, achieving display power optimization while maintaining visual smoothness in dynamic areas.

[0120] Next, during the termination refresh period when the second partition is performing a partition refresh operation, in the gate drive module 10_n+8, after the scan drive signal Gn+8 completes the high-frequency refresh of pixel row n+8 (i.e., the n+8th pixel row), the termination signal terminal provides a partition termination signal end that represents a high potential and turns on the sixth switch. This pulls the scan drive signal Gn+7 connected to the gate drive module 10_n+8 down to the low potential terminal VGL through the turned-on sixth switch, thereby interrupting the effective output of the scan drive signal Gn+7. This prevents the thin-film transistor T1 in the gate drive module 10_n+8 from being turned on, i.e., the thin-film transistor T1 is in the off state. At this time, the scan drive signal Gn+3 is always in a low level state and is no longer effective, marking the end of the partition refresh operation of the first partition.

[0121] Subsequently, during the signal reset period of the partition refresh operation in the second partition, the reset signal ctrl provided by the trigger reset terminal in the gate drive module 10_n+7 is in the state of... Figure 11 As shown in the high-level state, the high-potential reset signal ctrl turns on the fourth switch M4 in the gate drive module 10_n+7, converting the high-potential second clock signal CLKn+1 into an effective drive for the gate of the fifth switch M5. This, in turn, connects the second potential node Qn+7 to the low potential terminal VGL through the turned-on fifth switch M5, forcibly pulling the potential of the second potential node Qn+2 down to the low potential terminal VGL's reset level. This completely eliminates the potential lingering risk of the second potential node Qn+2's potential, allowing the gate drive module 10_n+7 to reset. This effectively prevents the scan drive signal Gn+8 from being falsely triggered due to incomplete reset of the second potential node Qn+2, ensuring the reliability and stability of the termination partitioning operation.

[0122] Finally, the gate drive module 10, which performs partition refresh operations on the first and second partitions, enters the selection reset phase. Specifically, the gate drive modules 10_n+3 and 10_n+8, and the subsequent gate drive modules 10, output scan drive signals at a low refresh rate to refresh their respective pixel rows. This ensures that the energy-saving display in the non-dynamic refresh area outputs low refresh rate scan drive signals to refresh their respective pixel rows line by line. When the scan drive signal scans to pixel row n+3 or n+5 again, since the data signal terminal is in a low-level state in low refresh mode, the first switch M1 in the gate drive module 10_n+3 or 10_n+8 pulls down the potential of the first potential node PnP, thus clearing the starting pixel row mark and providing a clean initial state for the start of the next partition refresh operation.

[0123] In summary, the partitioned refresh circuit of this application includes multiple cascaded gate drive modules 10. Each gate drive module 10 integrates a gate scan unit 11 and a refresh selection unit 12. This allows for independent refresh rate control of different areas of the screen while maintaining visual smoothness, thereby reducing overall power consumption. Specifically, the gate scan unit 11 receives the previous level scan signal from the previous level scan output terminal through its own input terminal. This allows it to accurately identify the starting pixel row of the dynamic refresh partition based on the previous level scan signal. Specifically, when the scanned pixel row of the previous level scan signal is the pixel row preceding the starting pixel row, the gate scan unit 11 uses its own voltage input terminal, electrically connected to the DC voltage terminal, to receive the DC potential signal VDS provided by the DC voltage terminal under the drive of the previous level scan signal. This DC potential signal VDS is then transmitted to the refresh selection unit 12 via the gate scan unit 11's own voltage output terminal, providing a precise potential trigger condition for the refresh selection unit 12 to start during the refresh preparation phase. Subsequently, through the electrical connection between the refresh selection unit 12 and the data signal terminal, the refresh selection unit 12 receives the data signal from the data signal terminal under the trigger of the DC potential signal VDS. The gate scanning unit 11 is triggered by a memory signal Vdata to determine the refresh start signal applied to its refresh start terminal. This allows the gate scanning unit 11 to automatically output dynamic refresh signals line by line, starting from the identified initial pixel row, to perform partitioned refresh operations on all pixel rows within the dynamic refresh partition. Finally, when the gate scanning unit 11 scans to the final pixel row of the dynamic refresh partition, the refresh selection unit 12 automatically resets and terminates the partitioned refresh operation based on the reset signal ctrl provided by the reset terminal. This strictly limits the refresh range to the specified dynamic refresh partition, achieving independently controllable refresh rates for the dynamic refresh partition. While maintaining the smoothness of dynamic images within the dynamic refresh partition, it avoids meaningless pixel refreshes in static image areas running at high refresh rates, thereby effectively reducing screen display power consumption.

[0124] In addition, this application also provides a display panel, which includes a display area and a non-display area. The display area is provided with multiple parallel rows of pixels. The non-display area is arranged around the periphery of the display area. The non-display area is provided with the aforementioned partition refresh circuit. When the number of dynamic refresh partitions is one or two, multiple cascaded gate scanning units in the partition refresh circuit are electrically connected to the multiple rows of pixels in the display area in a one-to-one correspondence.

[0125] Furthermore, in some feasible embodiments, when the number of dynamic refresh partitions exceeds two, the partition refresh circuits are respectively disposed on a first side and a second side of the display area, with the second side being the opposite side of the first side; the display area is provided with an odd-numbered row set and an even-numbered row set, the odd-numbered row set including all pixel rows with odd numbers, and the even-numbered row set including all pixel rows with even numbers; each stage of the gate scanning unit in the partition refresh circuit disposed on the first side is electrically connected to each pixel row in the odd-numbered row set; each stage of the gate scanning unit in the partition refresh circuit disposed on the second side is electrically connected to each pixel row in the even-numbered row set.

[0126] In this embodiment, when the number of dynamic refresh partitions exceeds two, the partition refresh circuit adopts a dual-sided layout structure, which is respectively set on the first side of the display area and the opposite second side. All pixel rows in the display area are divided into odd-numbered row sets and even-numbered row sets. Since the odd-numbered row sets contain all pixel rows with odd numbers and the even-numbered row sets contain all pixel rows with even numbers, the gate scanning units at each stage in the partition refresh circuit set on the first side establish a one-to-one electrical connection relationship with each pixel row in the odd-numbered row sets. Correspondingly, the gate scanning units at each stage in the partition refresh circuit set on the second side establish a one-to-one electrical connection relationship with each pixel row in the even-numbered row sets. When performing multi-partition (3 or more dynamic refresh partitions) refresh operation, the partition refresh circuits on both sides can work independently, effectively improving the flexibility of partition control and refresh efficiency.

[0127] Specifically, the partition refresh circuit set on the left side of the display area is specifically responsible for the refresh control of the odd-numbered rows 1, 3, 5... while the partition refresh circuit set on the right side of the display area is specifically responsible for the refresh control of the even-numbered rows 2, 4, 6... This architecture of separate driving for odd and even rows enables the system to process multiple independent refresh partitions at the same time, greatly enhancing the feasibility of partition refresh function in complex display scenarios.

[0128] In addition, this application also provides a display device. Please refer to... Figure 15 , Figure 15 This is a schematic diagram of the display device involved in the embodiments of this application. Specifically, the display device in the embodiments of this application may be a device that runs a local refresh control method.

[0129] The display device includes the display panel, memory, processor, and refresh control program stored in the memory and executable on the processor, wherein the processor executes the refresh control program to implement the steps of the refresh control method described above.

[0130] like Figure 15As shown, the display device in this embodiment may include: a display panel, a partition refresh circuit electrically connected to the display panel, and a processor 1001, such as a CPU, a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. The communication bus 1002 is used to enable communication between these components. The user interface 1003 may include a display screen and an input unit such as a keyboard; optionally, the user interface 1003 may also include a standard wired interface or a wireless interface. The network interface 1004 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface).

[0131] The memory 1005 is disposed on the main body of the display device. The memory 1005 stores a program that performs corresponding operations when executed by the processor 1001. The memory 1005 is also used to store parameters used by the display device. The memory 1005 can be a high-speed RAM or a stable, non-volatile memory, such as a disk drive. Optionally, the memory 1005 can also be a storage device independent of the aforementioned processor 1001.

[0132] Those skilled in the art will understand that Figure 15 The display device structure shown does not constitute a limitation on the display device and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0133] like Figure 15 As shown, the memory 1005, which serves as a storage medium, may include an operating system, a network communication module, a user interface module, and a refresh control program.

[0134] exist Figure 15 In the display device shown, the processor 1001 can be used to call the refresh control program stored in the memory 1005 and execute the steps of the refresh control method as described above.

[0135] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0136] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0137] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a display device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0138] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A partition refresh circuit, characterized in that, The partition refresh circuit includes multiple cascaded gate drive modules, each gate drive module comprising: A gate scanning unit, wherein the input terminal of the gate scanning unit is configured to receive the scanning signal provided by the output terminal of the previous stage, the voltage input terminal of the gate scanning unit is electrically connected to a DC voltage terminal, and the gate scanning unit is configured to determine the starting pixel row of the dynamic refresh partition. When the scanning pixel row of the previous stage scanning signal is the pixel row preceding the starting pixel row, the DC potential signal of the DC voltage terminal is received under the drive of the previous stage scanning signal. A refresh selection unit is electrically connected to a data signal terminal, a reset terminal, the voltage output terminal of the gate scan unit, and the refresh start terminal of the gate scan unit. The refresh selection unit is configured to receive a data memory signal provided by the data signal terminal under the drive of the DC potential signal, and determine the refresh start signal acting on the refresh start terminal based on the data memory signal. This triggers the gate scan unit to output dynamic refresh signals line by line starting from the starting pixel line, so as to perform partition refresh operation on all pixel lines of the dynamic refresh partition. The partition refresh operation is terminated based on the reset signal of the reset terminal when the gate scan unit scans to the final pixel line of the dynamic refresh partition.

2. The partition refresh circuit as described in claim 1, characterized in that, The gate driving module includes a first clock terminal and a second clock terminal. The first clock terminal is used to provide a first clock signal, and the second clock terminal is used to provide a second clock signal that is inversely phase to the first clock signal. The clock input terminal of the refresh selection unit is electrically connected to the target clock terminal, and the clock potential terminal of the gate scan unit is electrically connected to the inverted clock terminal of the target clock terminal. The target clock terminal is either the first clock terminal or the second clock terminal. In multiple cascaded gate drive modules, the target clock signal provided by the target clock terminal in adjacent gate drive modules is inverted.

3. The partition refresh circuit as described in claim 2, characterized in that, The refresh selection unit includes a refresh control subunit and a refresh reset subunit. The refresh control subunit is electrically connected to the data signal terminal, the local voltage output terminal, the refresh start terminal, and the refresh reset subunit, respectively. The refresh control subunit includes: First potential node; The first switching transistor has its gate electrically connected to the voltage output terminal of this stage, its first path terminal electrically connected to the data signal terminal, and its second path terminal electrically connected to the first potential node. The second switching transistor has its gate electrically connected to the first potential node, its first path terminal electrically connected to the data signal terminal, and its second path terminal electrically connected to the voltage output terminal of this stage. The third switch has its gate electrically connected to the second path terminal of the second switch, its first path terminal electrically connected to the target clock terminal, and its second path terminal electrically connected to the refresh start terminal of the gate scan unit. The first capacitor is connected between the first potential node and the second path terminal of the second switch.

4. The partition refresh circuit as described in claim 3, characterized in that, The refresh start terminal of the gate scan unit is the second potential node, and the refresh reset subunit includes a fourth switch and a fifth switch. The gate of the fourth switch is electrically connected to the reset terminal, the first path terminal of the fourth switch is electrically connected to the target clock terminal, the second path terminal of the fourth switch is electrically connected to the gate of the fifth switch, the first path terminal of the fifth switch is electrically connected to the low potential terminal, and the second path terminal of the fifth switch is electrically connected to the second potential node.

5. The partition refresh circuit as described in claim 1, characterized in that, When there are two dynamically refreshed partitions, the gate drive module further includes a sixth switch and a termination signal terminal; The gate of the sixth switch is electrically connected to the termination signal terminal, the first path terminal of the sixth switch is electrically connected to the voltage input terminal of this stage, and the second path terminal of the sixth switch is electrically connected to the low potential terminal.

6. A refresh control method for a partitioned refresh circuit, characterized in that, The refresh control method is applied to the partition refresh circuit according to any one of claims 1 to 5, the partition refresh circuit including a refresh selection unit and a plurality of cascaded gate scan units, the gate scan unit further including a refresh start terminal, and the refresh control method including: When the gate scanning unit receives the previous level scanning signal output by the previous level gate driving module, the starting pixel row of the dynamic refresh partition is determined. When the scanning pixel line of the previous level scanning signal is the pixel line preceding the starting pixel line, the DC potential signal of the gate scanning unit is enabled to be connected to the DC voltage terminal under the drive of the previous level scanning signal. Driven by the DC potential signal, the refresh selection unit is enabled to access the data memory signal provided by the data signal terminal, and the refresh start signal acting on the refresh start terminal is determined according to the data memory signal, triggering the gate scan unit to output the dynamic refresh signal line by line from the starting pixel row to refresh the dynamic refresh partition line by line. The refresh operation of the gate scanning unit is terminated when the gate scanning unit scans to the final pixel row of the dynamic refresh partition, based on the reset signal at the reset terminal.

7. The refresh control method as described in claim 6, characterized in that, After the step of refreshing the dynamically refreshed partition line by line, the refresh control method includes: When the number of the dynamic refresh partitions is one, the step of terminating the partition refresh operation of the gate scan unit according to the reset signal of the reset terminal is executed until the gate scan unit scans to the final pixel row of the dynamic refresh partition. When there are two dynamic refresh partitions, the dynamic refresh partition that is refreshed first among the two dynamic refresh partitions is determined as the first partition, and the dynamic refresh partition other than the first partition among the two dynamic refresh partitions is determined as the second partition. If the gate scan unit scans to the final pixel row of the first partition, the gate scan unit is triggered to terminate the partition refresh operation according to the partition termination signal at the termination signal terminal, and then the gate scan unit is reset according to the reset signal. After being enabled and reset, the gate scanning unit scans each pixel row after the first partition line by line according to a preset static refresh signal until it scans the starting pixel row in the second partition. Then, based on the fact that the scan drive signal output from the previous pixel row of the starting pixel row is a valid signal, the gate scanning unit is triggered to dynamically refresh the second partition.

8. A display panel, characterized in that, The display panel includes a display area and a non-display area. The display area is provided with multiple parallel rows of pixels. The non-display area is arranged around the periphery of the display area. The non-display area is provided with a partition refresh circuit as described in any one of claims 1 to 5. When the number of dynamically refreshed partitions is one or two, the multiple cascaded gate scanning units in the partition refresh circuit are electrically connected one-to-one with the multiple pixel rows in the display area.

9. The display panel as described in claim 8, characterized in that, When the number of the dynamic refresh partitions exceeds two, the partition refresh circuits are respectively located on the first side and the second side of the display area, with the second side being the opposite side of the first side; The display area is provided with an odd row set and an even row set. The odd row set includes all pixel rows with odd numbers, and the even row set includes all pixel rows with even numbers. Each level of the gate scanning unit in the partition refresh circuit on the first side is electrically connected to each pixel row in the odd row set; Each level of the gate scanning unit in the partition refresh circuit located on the second side is electrically connected to each pixel row in the even-numbered row set.

10. A display device, characterized in that, The display device includes the display panel according to any one of claims 8 to 9; or... The display device further includes a memory, a processor, and a refresh control program stored in the memory and executable on the processor, wherein the processor, when executing the refresh control program, implements the steps of the refresh control method as described in any one of claims 6 to 7.

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