A method for fast erasing of non-volatile memory based on channel hot electron induced hot hole injection and its application

Abstract

The application discloses a non-volatile memory fast erasing method based on channel hot electron induced hot hole injection and application thereof. In the non-volatile flash memory with split gate, a positive source voltage, a positive drain voltage and a negative storage gate voltage are applied under the opening of a selection gate MG and a storage node MS, so as to generate high-energy channel hot electrons in the channel. High-density hot holes are generated in the channel region through the collision ionization effect of the channel hot electrons. The hot holes are used to inject the charge trapping layer through the tunneling oxide layer, the neutralization of the storage electrons is completed, and the erasing operation is realized. The application generates high-density hot holes through the collision ionization effect of the hot electrons, and the hot holes are used to inject the charge trapping layer for fast erasing, so that the erasing efficiency is improved, the electric field stress is reduced, and the durability and retention performance of the equipment are improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor devices, and relates to a non-volatile memory fast erasing method based on channel hot electron induced hot hole (CHH) injection and application thereof. BACKGROUND

[0002] As an important component of semiconductor memory devices, non-volatile memories have been widely used in various electronic devices, including embedded systems, mobile terminals and data centers. The performance parameters, especially the erasing speed, reliability and long-term stability, directly affect the overall efficiency and service life of the storage system. Among many non-volatile memory structures, split-gate charge-trapping flash memory is of great concern due to its high programming efficiency and good charge retention characteristics.

[0003] In the erasing operation of split-gate flash memory, the band-gap band-to-band tunneling hot hole injection (BBHH) mechanism is traditionally used. This mechanism forms a strong electric field region by applying a negative bias to the storage gate and a high positive bias to the drain at the same time, inducing band-to-band tunneling effect, thereby generating hot holes near the drain junction. These hot holes then inject charge trapping layer through tunneling oxide layer and neutralize the storage electrons to achieve the erasing function. However, this method has the problem of slow erasing process due to the limited rate and spatial density of BBHH generated holes, resulting in typical erasing time usually in the order of milliseconds, which is difficult to meet the needs of high-speed storage systems. The strong electric field is concentrated near the drain junction, which easily causes local damage to the tunneling oxide layer, aggravates the generation of interface traps, and affects the durability and long-term reliability of the device. The hot holes generated by BBHH are relatively limited in spatial distribution and density, causing storage charge mismatch effect (TCME), which further inhibits the improvement of erasing efficiency. To improve the erasing efficiency, the operating voltage often needs to be increased, which in turn leads to increased power consumption and may cause reliability degradation. Obviously, it has the problems of slow erasing speed, large local electric field stress and difficult to maintain memory window. These problems seriously limit the further application of flash memory, especially in the storage demand of high speed, large capacity and high reliability.

[0004] Therefore, how to significantly improve the erasing speed and uniformity while maintaining low power consumption and electric field stress, and effectively suppress the TCME effect, has become a technical problem to be solved in the field of memory. SUMMARY

[0005] The application provides a non-volatile memory erasing method based on channel hot electron induced hot hole injection and application thereof, aiming at solving the problems in the existing BBHH erasing mechanism, especially the slow erasing speed, large electric field stress and low erasing efficiency caused by the storage charge mismatch effect (TCME). The method utilizes the collision ionization effect of hot electrons to generate high-density hot holes, and injects the hot holes into the charge trapping layer for rapid erasing, thereby significantly improving the erasing efficiency, reducing the electric field stress, and improving the durability and retention performance of the device.

[0006] In the first aspect, the application provides a non-volatile memory fast erasing method based on channel hot electron induced hot hole injection, comprising the following steps:

[0007] Step S1, in a non-volatile flash memory with split gates, a positive source voltage, a positive drain voltage and a negative storage gate voltage are applied under the condition that the select gate MG and the storage node MS are turned on, so as to generate high-energy channel hot electrons in the channel;

[0008] Step S2, high-density hot holes are generated in the channel region through the collision ionization effect of the channel hot electrons;

[0009] Step S3, the hot holes are injected into the charge trapping layer through the tunneling oxide layer, the neutralization of the storage electrons is completed, and the erasing operation is realized.

[0010] Preferably, the condition for turning on the select gate MG and the storage node MS is that the storage node voltage and the select gate voltage are both greater than 0V. More preferably, the storage node voltage V MS = 5V, and the select gate voltage V MG = 1V.

[0011] Preferably, the source voltage Vs = 0-0.2V, the drain voltage V D = 4.4 ~ 4.8V;

[0012] Preferably, the storage gate voltage V MD = -5.5 ~ -4.5 V, and more preferably -5 V;

[0013] Preferably, the erasing time TE ≤ 100 μs.

[0014] Preferably, the generation position of the hot holes is distributed in the deep depletion region of the channel, so that the spatial distribution range of the hot holes is greater than the local hole distribution area under the traditional band-to-band tunneling (BBHH) mechanism, thereby improving the hot hole injection efficiency.

[0015] Preferably, the generation rate of the hot holes through collision ionization is in the range of The above, and the peak concentration of holes in the channel reaches to achieve fast and uniform erasing.

[0016] Preferably, the hot hole injection process occurs in a region with a tunnel oxide thickness of 2.5-3.5 nm, ensuring that the hot hole can overcome the barrier and achieve efficient injection.

[0017] In a second aspect, the present application provides a non-volatile memory chip, whose erasing operation adopts the above method to realize charge neutralization by channel hot electron induced hot hole injection, and complete erasing.

[0018] The present application has at least the following beneficial effects:

[0019] The present application uses channel hot electron to excite hot holes, generates a large number of hot holes through the collision ionization effect of hot electrons, and then realizes the erasing operation. Compared with the traditional BBHH erasing mechanism, the CHH erasing mechanism has the following obvious characteristics:

[0020] (1) Hot holes excited by hot electrons: When a certain voltage is applied between the source and the drain, the electrons in the channel gain enough energy to collide and ionize, generating a large number of hot holes. The density and distribution range of hot holes in the channel far exceed that of hot holes generated by BBHH, forming a uniform distribution, which makes the erasing process more efficient.

[0021] (2) Hot hole injection efficiency: By applying a suitable negative storage gate voltage, hot holes can be injected into the charge trapping layer through the tunneling effect. Because the distribution of hot holes is more extensive, it can more effectively neutralize the stored electrons, thereby improving the erasing efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0023] Figure 1 is a non-volatile flash memory cell structure with split gate provided by the embodiment of the present application.

[0024] Figure 2 is a voltage bias configuration diagram for different methods of flash memory cell operation provided by the embodiment of the present application, wherein (a) CHE (channel hot electron programming), (b) BBHH (band gap band-to-band tunneling hot hole erasing), (c) CHH (channel hot electron induced hot hole erasing of the present application). Figure 1

[0025] Figure 3 ​Figure is a TCAD simulation diagram of BBHH and CHH erase operation provided by the embodiment of the present application, wherein (a) is the trapped hole distribution after BBHH erase, (b) is the trapped hole distribution after CHH erase, (c) is the electrostatic potential diagram under the BBHH bias, (d) is the electrostatic potential diagram under the CHH bias, (e) is the change of hole density with the BBHH erase process, (f) is the change of hole density with the CHH erase process, (g) is the change of hole generation rate with the BBHH erase process, (h) is the change of hole generation rate with the CHH erase process, (i) is the electron current density in the CHH erase process, and (j) is a schematic diagram of the CHH erase principle in the device.

[0026] Figure 4 Figure is a diagram of the change of electrical performance with time under different erase operations provided by the embodiment of the present application, wherein (a) is BBHH, and (b) is CHH.

[0027] In the figure, 1 is a substrate, 2 is a source, 3 is a drain, 4 is a select gate, 5 is a storage node, 6 is a storage gate, 7 is a storage layer, 71 is a blocking oxide layer, 72 is a charge trapping layer, 73 is a tunneling oxide layer, and 8 is an isolation oxide layer. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme of the present application will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the present application.

[0029] The terms “comprising” and “having” and any variations thereof mentioned in the embodiments of the present application are intended to cover non-exclusive inclusion.

[0030] The common BBHH erase in the existing erase mechanism is to generate hot holes by band-to-band tunneling (BTBT) effect. A negative storage gate voltage (V MD ) and a larger source-drain voltage (V SD ) form a tunneling window to allow band-to-band tunneling to generate hot holes. The generated hot holes are mainly concentrated near the drain and are injected into the charge trapping layer through the tunneling oxide layer. Since the select gate V MG = 0 V, no additional electric field can be provided, the erase effect is limited, and the erase speed is slow. From the above defects, it can be seen that there are problems such as slow erase speed, large electric field stress, and low erase efficiency caused by storage charge mismatch effect (TCME) in the prior art.

[0031] Based on this, the embodiment of the present application provides a non-volatile memory fast erasing method based on channel hot electron induced hot hole injection (CHH), and the principle is as follows:

[0032] 1. Hot electron excitation and collision ionization

[0033] The erasing method of the present application relies on the collision ionization effect of channel hot electrons. When a proper voltage bias is applied in the channel, the strong electric field between the source and the drain will make the electrons in the channel gain enough energy. These hot electrons will transition to high-energy states and undergo collision ionization reactions with atoms in the channel, generating a large number of hot holes.

[0034] 2. Generation and injection of hot holes

[0035] The generated hot holes have high energy and can overcome the energy barrier of the tunneling oxide layer (Tunneling Oxide) through the tunneling effect, thereby being injected into the charge trapping layer (such as a silicon nitride layer). The injection of hot holes directly neutralizes the stored electrons, realizing the erasing operation.

[0036] 3. Advantages of CHH mechanism

[0037] Unlike the traditional BBHH erasing mechanism, the hot holes generated by the collision ionization of hot electrons in CHH have higher density and more extensive spatial distribution. This uniform distribution of hot holes can effectively overlap with stored electrons, improving the erasing efficiency and avoiding the storage charge mismatch effect (TCME) existing in the traditional BBHH mechanism.

[0038] Referring to the accompanying drawings, Figure 1 The non-volatile memory provided by the embodiment comprises:

[0039] a substrate 1;

[0040] a source electrode 2 (S) and a drain electrode 3 (D) are respectively embedded in the two sides of the substrate 1; wherein there is also a channel region between the source electrode 2 and the drain electrode 3;

[0041] a selection gate 4 (MG) is arranged above the substrate 1;

[0042] a storage node 5 (MS) and a storage gate 6 (MD) are both arranged above the substrate 1 and are respectively located on the two sides of the selection gate 4;

[0043] The storage node 5 (MS), the storage gate 6 (MD) and the substrate 1 are all provided with a storage layer 7 (ONO), and the storage layer 7 comprises a blocking oxide layer 71, a charge trapping layer 72 and a tunneling oxide layer 73 in turn from the storage node to the substrate 1.

[0044] Wherein, the source 2 is the entrance of current, and the drain 3 is the exit of current. By applying appropriate voltage bias between the source and the drain, the electrons in the channel will be accelerated and enter or exit the memory cell. These two electrodes play a role in controlling the direction and intensity of current flow during programming and erasing processes.

[0045] The storage node 5 (MS) and the storage gate 6 (MD) are two independent storage nodes that store the charge in the flash memory cell. Due to the split-gate design, each storage node can be programmed or erased independently, thereby increasing the storage density. The storage node 5 (MS), the storage gate 6 (MD), and the intermediate select gate 4 (MG) electrode are electrically isolated. They control the stored charge through voltage bias, thereby realizing the programming and erasing of data.

[0046] The select gate 4 (MG) is a key component in the split-gate structure, located between MS and MD. The role of the select gate 4 is to selectively control the programming and erasing of the storage node 5 (MS) and the storage gate 6 (MD), ensuring that they can operate independently without interfering with each other. In the erasing operation, the voltage bias of the select gate adjusts the flow of electrons in the channel, affecting the charge state of the storage node.

[0047] The channel region between the source and the drain is the main path of current flow. This region is controlled by applying the source-drain voltage (V SD ) and the storage gate voltage (V MD ). In the erasing operation, the bias of the source-drain voltage and the storage gate voltage will affect the movement of electrons in the channel and the generation of hot electrons. Through the application of high voltage, hot electrons in the channel are accelerated, and hot holes are generated in the channel region through the effect of collision ionization. These hot holes will then be injected into the charge trapping layer through the tunneling oxide layer, thereby realizing the erasing operation. In this design, the region where the deep depletion region of the channel region is formed is the key region for the generation of hot holes, ensuring the generation of high-density hot holes and efficient erasing.

[0048] The charge trapping layer 72 is composed of silicon nitride (Si3N4), which is the core area of charge storage. This layer is the N part of the ONO structure, which plays a role in capturing stored charges.

[0049] The tunneling oxide layer 73 (Tunneling Oxide) is located between the charge trapping layer and the channel region, allowing hot holes to be injected into the charge trapping layer through the tunneling effect, completing the erasing operation. The preferred thickness of the tunneling oxide layer is 2.5-3.5 nm.

[0050] The blocking oxide layer 71 (Blocking Oxide) is located above the charge trapping layer, which can effectively isolate the stored charge and prevent the diffusion of charge, ensuring long-term stable storage of the charge.

[0051] The top of the memory node 5 (MS) and the memory gate 6 (MD) is also provided with an isolation oxide layer 8 and a metal silicide layer, the isolation oxide layer 8 is close to the select gate 4, and there is an isolation medium between the two.

[0052] The above-mentioned non-volatile memory fast erasing method based on channel hot electron induced hot hole injection is specifically:

[0053] Step S1: operating bias condition and hot hole generation

[0054] S11. Voltage bias setting

[0055] The gate voltage setting must be greater than 0V, and the memory node voltage V MS =5V, the select gate voltage V MG = 1V to maintain the channel conduction. In order to excite hot electrons in the channel, a specific voltage bias needs to be applied. Specifically, the source voltage Vs=0-0.2V, the drain voltage V D =4.4 ~4.8V, the source-drain voltage (V SD ) between the source and the drain is set to 4.4 ~4.8V, preferably 4.6V, and the memory gate voltage (V MD ) is set to -5.5 ~ -4.5 V, and the preferred value in the embodiment is -5 V. Through this bias, hot electrons obtain sufficient kinetic energy in the channel and start collision ionization to generate hot holes.

[0056] S12. Spatial distribution of hot holes

[0057] Under the CHH mechanism, the generation of hot holes is not limited to a small area, but is widely distributed in the channel below the MS or MD. Compared with the local generation in the BBHH mechanism, the hot holes generated by the CHH mechanism have a higher spatial distribution density. The hot holes generated not only cover the entire channel region, but also can neutralize the stored electrons in a larger range, improving the erasing effect.

[0058] Step S2: Hot hole injection into charge trapping layer

[0059] By applying a negative memory gate voltage (V MD =-5.5 ~ -4.5 V, and the preferred value in the embodiment is -5 V), hot holes will tunnel through the tunneling oxide layer (Tunneling Oxide) by tunneling effect and be effectively injected into the charge trapping layer. The hot hole injection process in the embodiment occurs in the region where the tunneling oxide layer is 2.5-4.0 nm thick. This process ensures that hot holes can directly neutralize stored electrons to complete the erasing operation.

[0060] The above-mentioned CHH mechanism erasing method at least achieves the following effect improvement:

[0061] Improved erasure efficiency: Due to the high density and wide distribution of hot holes, they can neutralize more stored electrons in a short time during the erasure process, greatly improving erasure efficiency. Compared to the traditional BBHH mechanism, the CHH mechanism completes erasure in a shorter time and avoids the problem of local electric field stress concentration, thus preventing excessive damage to the device.

[0062] Reduced electric field stress: Due to the uniform distribution of thermal holes, excessively large electric field stress regions are not formed during the erasure process. This makes the CHH erasure process gentler than the traditional BBHH erasure, reducing damage to the device interface. Reduced electric field stress not only extends the device's lifespan but also improves long-term write / erase performance.

[0063] Suppression of the TCME effect: The charge mismatch effect (TCME) is a problem in conventional BBHH erasure, stemming from the spatial distribution difference between hot holes and stored electrons during erasure. In the CHH mechanism, the widespread distribution of hot holes effectively suppresses the TCME effect, ensuring the efficiency and reliability of the erasure operation.

[0064] Erasing speed and durability: Compared to the traditional BBHH mechanism, the method of this invention can complete the erasure within 0.1 milliseconds, which is about 100 times faster than BBHH. At the same time, the low electric field stress and effective electron neutralization during the erasure process enable the device to maintain a stable memory window (MW) after up to 100k erase-write cycles, and the retention performance can reach more than 10 years at 175°C.

[0065] See appendix Figure 2 From (a), it can be seen that the voltage condition applied by the CHE mechanism programming operation is the source voltage V. S = 0 V, drain voltage V D = 4.4 V, storage gate voltage V MD = 6.4 V, storage node voltage V MS = 5 V, select gate voltage V MG = 1 V, source voltage V S = 0.2 V. Its erase / write time is 10 μs. In CHE programming, a strong electric field is generated in the channel by combining the source / drain voltage and the storage gate voltage, accelerating hot electrons to a high-energy state. These hot electrons are injected into the charge trapping layer through tunneling, thereby completing the storage operation. Storage node voltage (V MS ) and storage gate voltage (V MD The same principle applies to ensure effective electron injection.

[0066] See appendix Figure 2 From (b), it can be seen that the voltage condition applied during the erase operation of the BBHH mechanism is the source voltage V.S = 0 V, drain voltage V D = 5.4 V, storage gate voltage V MD =-5.4 V, storage node voltage V MS = 0V, select gate voltage V MG =0V, source voltage V S = 1.8V. Its erase / write time is 10 ms. BBHH erase utilizes the bandgap band-to-band tunneling (BTBT) effect to generate hot holes. Negative storage gate voltage (V MD ) and a large source-drain voltage (V SD Together, they form a tunneling window, allowing bandgap band-to-band tunneling to generate hot holes. The generated hot holes are mainly concentrated near the drain and are injected into the charge trapping layer through the tunneling oxide layer. Due to the selection of gate V... MG = 0 V, cannot provide an additional electric field, the erasing effect is relatively limited, and the erasing speed is slow.

[0067] See appendix Figure 2 As can be seen from (c), the voltage condition applied during the erase operation of the CHH mechanism of this invention is the source voltage V. S = 0V, drain voltage V D =4.6V, storage gate voltage V MD =-5V, storage node voltage V MS = 5V, select gate voltage V MG =1V, source voltage V S = 0.2V. Its erase / write time is 100 μs. In the CHH erase mechanism, the source-drain voltage (V) is used to erase the source-drain voltage. SD ) and storage gate voltage (V MD The combination of electrons generates hot electrons in the channel, which ionize through collisions to create hot holes. These hot holes are then injected into the charge trapping layer via tunneling and neutralize the stored electrons. Unlike the BBHH erase mechanism, in CHH erase, both the selected gate (MG) and the storage node (MS) must be enabled (V). MS = 5 V, V MG = 1 V), to ensure effective generation and uniform injection of hot holes. Compared with BBHH, the CHH mechanism can significantly improve the erasure speed (about 0.1ms) and erasure effect.

[0068] The main difference between the three operations mentioned above is:

[0069] Voltage settings: In CHE and CHH, the memory gate voltage (VMD) is negative, but it is mainly used for programming in CHE and for the erase process in CHH. In BBHH, the memory gate voltage (VMD) is also negative, but VMS is 0V, and the gate MG is selected as 0V, which limits the area where hot holes are generated.

[0070] Hot hole generation: CHE is a programming process by accelerating hot electron injection into the storage layer. BBHH generates hot holes by band-to-band tunneling, and the hot holes are localized. CHH generates hot holes by collision ionization of channel hot electrons, and the hot holes are widely and uniformly distributed, with much higher erasing speed than BBHH.

[0071] Erase efficiency and speed: CHE is mainly used for programming and is not involved in erasing. BBHH has a slow erasing speed (10 ms) and low erasing efficiency, and has a large electric field stress. CHH has the fastest erasing speed (0.1 ms), and has more uniform and efficient erasing effect, and has a low electric field stress and small device damage.

[0072] It can be seen from the accompanying Figure 3 (a)- Figure 3 (j) that the generation rate of the CHH hot holes generated by collision ionization in the embodiment is above, and the peak concentration of holes in the channel reaches During the erasing operation, through the spatial overlap of channel hot electrons and hot holes, complete neutralization of electrons and holes is realized, thereby eliminating the storage charge mismatch effect (TCME), improving erasing uniformity and reliability. The electric field stress during erasing is reduced by more than 30%, thereby reducing the formation of Si / SiO2 interface traps, delaying device migration and interface degradation.

[0073] It can be seen from the accompanying Figure 4 (a)- Figure 4 (b) that the electrical performance changes with time under the erasing operation of BBHH and CHH. The CHH erasing mechanism can achieve about 100 times faster erasing speed than the BBHH mechanism, and the erasing voltage is reduced by 1-2V. After 100k programming / erasing cycles, the memory window attenuation of the device is less than 15%, and the device has a data retention capability of more than 10 years at 175°C.

[0074] The above describes the preferred embodiments of the present application. It should be noted that for those skilled in the art, without departing from the principles of the present application, a number of improvements and refinements can be made, and these improvements and refinements are also considered within the protection scope of the present application.

Claims

1. A method for fast erasure of a non-volatile memory based on channel hot electron-induced hot hole injection, wherein the non-volatile memory comprises: A substrate; The source and drain electrodes are respectively embedded in both sides of the substrate; There is also a channel region between the source and the drain; A selection gate is disposed above the substrate; The storage nodes and storage gates are both disposed above the substrate and are located on both sides of the selection gate, respectively. A storage layer is provided between the storage node, the storage gate and the substrate. The storage layer includes, in sequence from the storage node toward the substrate, a barrier oxide layer, a charge trapping layer and a tunneling oxide layer. The source is the current inlet, and the drain is the current outlet. By applying an appropriate voltage bias between the source and drain, electrons in the channel are accelerated and enter or leave the memory cell. The storage nodes, storage gates, and intermediate select gate electrodes are electrically isolated. They control the stored charge through voltage bias, thereby enabling data programming and erasure. During the erase operation, the voltage bias of the gate is selected to regulate the flow of electrons in the channel, which affects the charge state of the memory node. The channel region located between the source and drain is the main path for current flow; this region is controlled by applying source-drain voltage and storage gate voltage; during the erase operation, the bias of the source-drain voltage and storage gate voltage will affect the movement of electrons in the channel and the generation of hot electrons; by applying a high voltage, the hot electrons in the channel are accelerated and generate hot holes in the channel region through collisional ionization; these hot holes are then injected into the charge trapping layer through the tunneling oxide layer, thereby realizing the erase operation; The charge trapping layer serves as the core region for charge storage; The tunneling oxide layer is located between the charge trapping layer and the channel region, allowing thermal holes to be injected into the charge trapping layer through the tunneling effect to complete the erasure operation; The barrier oxide layer is located above the charge trapping layer, which isolates the stored charge, prevents the charge from spreading, and ensures that the charge is stored stably for a long time. An isolation oxide layer and a metal silicide layer are also disposed on the top of the storage node and the storage gate. The isolation oxide layer is close to the select gate, and there is an isolation medium between the two. The method is characterized by comprising: In non-volatile flash memory, the storage node voltage V is set. MS =5V, select gate voltage V MG = 1V, which enables both the Select Gate (MG) and the Storage Node (MSS) simultaneously; Then, a positive source voltage, a positive drain voltage, and a negative storage gate voltage are applied to the source, drain, and storage gate, respectively, to generate high-energy channel hot electrons throughout the channel; wherein the source voltage Vs = 0-0.2V, and the drain voltage V D = 4.4 ~ 4.8V; High-density hot holes are generated in the deep depletion region of the channel through collisional ionization of hot electrons; the rate at which these hot holes are generated through collisional ionization is... The above, and the peak hole concentration within the channel reaches ;; By utilizing the negative voltage on the storage gate, the hot holes are driven to tunnel through the oxide layer and inject into the charge trapping layer, thereby neutralizing the stored electrons and realizing the erasure operation.

2. The method according to claim 1, characterized in that, The storage gate voltage V MD = -5.5 ~ -4.5 V.

3. The method according to claim 1, characterized in that, Erasure time TE ≤ 100 μs.

4. The erasing method according to claim 1, characterized in that, The injection of thermal holes occurs in the region where the tunnel oxide layer thickness is 2.5–3.5 nm.

5. A non-volatile memory chip, characterized in that, The chip erasure operation employs the method described in any one of claims 1-4 to perform channel hot electron-induced hot hole injection to achieve charge neutralization and complete the erasure.

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