Segmented bidirectional SCR device for ESD protection of high-voltage integrated circuit

Abstract

The invention belongs to the field of design of an electrostatic discharge (ESD) protection device of a high-voltage integrated circuit (IC), and particularly provides a split type bidirectional silicon controlled rectifier (SCR) device which is used for ESD protection of the high-voltage integrated circuit and is adjustable in turn-on voltage and maintaining voltage aiming at a bidirectional silicon controlled rectifier (DDSCR), and the split type bidirectional SCR device can be used for ESD protection of a high-voltage input / output port (I / O for short) and a power domain. The device has the advantages of being adjustable in turn-on voltage and maintaining voltage and the like, and can be suitable for integrated circuit ESD protection in various high-voltage power supply domains.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of electrostatic discharge (ESD) protection device design of high voltage integrated circuits (IC), and particularly relates to a structure design of an ESD protection device, in particular to a dual-directional silicon controlled rectifier (DDSCR). BACKGROUND

[0002] Electrostatic discharge (ESD) refers to the process of charge transfer through a conductive path when the induced electric field strength exceeds the dielectric breakdown field strength of two objects with different potentials. With the development of semiconductor process technology to nanometer nodes, device size is continuously reduced, and gate oxide layer is thinned. The damage caused by ESD to integrated circuits (IC) has the characteristics of concealment, latency and randomness, and has become one of the main factors affecting chip reliability. Therefore, the development of ESD protection devices with adjustable trigger voltage and holding voltage and high robustness is crucial for full-chip electrostatic protection under advanced processes.

[0003] In ESD protection design, ESD protection devices need to meet specific design windows (ESD Design Window): the trigger voltage should be less than the gate breakdown voltage of the protected circuit, and the holding voltage should be greater than the power supply operating voltage of the protected circuit, to avoid latch-up. In particular, in high voltage integrated circuit applications, ESD protection devices must meet high operating voltage requirements while maintaining high robustness. However, maintaining high robustness while increasing holding voltage and trigger voltage has always been a technical difficulty in ESD protection design.

[0004] Silicon controlled rectifiers (SCR) are widely used in ESD protection due to their high current carrying capacity per unit area, low off-state leakage current, and high robustness. In addition, since ESD stress in practical applications may act on IC pins in the forward or reverse direction, dual-directional silicon controlled rectifiers (DDSCR) have emerged to meet the protection needs of bidirectional discharge paths.

[0005] The DDSCR (Diverterless Discharge Damping Controller) bidirectional ESD protection device features high robustness, simple structure, and high area utilization, making it well-suited for ESD protection in chips. The device structure is as follows: Figure 1 As shown, it includes: The device includes a P-type silicon substrate 110, on which a first N-type doped region 120 is formed; a second N-type doped region 121, a first P-type doped region 130, a third N-type doped region 122, a second P-type doped region 131, and a fourth N-type doped region 123 are formed on the first N-type doped region; the first P-type doped region 130 is completely surrounded by the first N-type doped region 120, the second N-type doped region 121, and the third N-type doped region 122; the second P-type doped region 131 is surrounded by the first N-type doped region 120, the third N-type doped region 122, and the fourth N-type doped region 123. The region 123 completely surrounds the first P-type doped region 130; a third P-type doped region 140 is formed on the first P-type doped region 130, and a fourth P-type doped region 141 is formed on the second P-type doped region 131; a fifth N-type doped region 150 is formed on the second N-type doped region 121, a sixth N-type doped region 151 is formed on the third N-type doped region 122, and a seventh N-type doped region 152 is formed on the fourth N-type doped region 123; a fifth P-type doped region 160 is formed on the third P-type doped region 140, and a sixth P-type doped region 161 is formed on the fourth P-type doped region 141. The fifth P-type doped region 160 is provided with a first P-type heavily doped region 180 and a first N-type heavily doped region 170, and the sixth P-type doped region 161 is provided with a second P-type heavily doped region 181 and a second N-type heavily doped region 171. The first P-type heavily doped region 180 and the first N-type heavily doped region 170 are connected to the T1 port; the second P-type heavily doped region 181 and the second N-type heavily doped region 171 are connected to the T2 port. Shallow trench isolation is provided between the first P-type heavily doped region 180 and the first N-type heavily doped region 170, between the first N-type heavily doped region 170 and the second N-type heavily doped region 171, and between the second N-type heavily doped region 171 and the second P-type heavily doped region 181.

[0006] The device consists of one parasitic PNP transistor, two parasitic NPN transistors, and two well resistors: The first parasitic PNP transistor Q p1 It includes a first heavily doped P-type region 180, a fifth doped P-type region 160, a third doped P-type region 140, a first doped P-type region 130, a sixth doped N-type region 151, a third doped N-type region 122, a second doped P-type region 131, a fourth doped P-type region 141, a sixth doped P-type region 161, and a second heavily doped P-type region 181; the first parasitic NPN transistor Q n1It includes a first N-type heavily doped region 170, a fifth P-type doped region 160, a third P-type doped region 140, a first P-type doped region 130, a sixth N-type doped region 151, and a third N-type doped region 122; the second parasitic NPN transistor Q n2 It includes a second N-type heavily doped region 171, a sixth P-type doped region 161, a fourth P-type doped region 141, a second P-type doped region 131, a sixth N-type doped region 151, and a third N-type doped region 122; the first well resistor R PW1 The sum of the well resistances of the fifth P-type doped region 160, the third P-type doped region 140, and the first P-type doped region 130; the second well resistance R PW2 , refers to the sum of the well resistances of the sixth P-type doped region 161, the fourth P-type doped region 141, and the second P-type doped region 131.

[0007] The working principle of the device is as follows: When an ESD event reaches the TI port of the device, such as Figure 1 As shown in (a), the ESD voltage is greater than that of the parasitic PNP transistor Q in the device. p1 BV CEO When (common-emitter-collector junction avalanche breakdown voltage of a bipolar transistor) is reached, Q p1 When turned on, current will flow through R. PW2 That is, the current flows sequentially from T1 to T2 through the first heavily doped P-type region 180, the fifth doped P-type region 160, the third doped P-type region 140, the first doped P-type region 130, the sixth doped N-type region 151, the third doped N-type region 122, the second doped P-type region 131, the fourth doped P-type region 141, the sixth doped P-type region 161, and the second heavily doped N-type region 171. As the current increases, the well resistance R... PW2 The voltage drop increases, causing Q to... n2 As the emitter junction voltage increases, Q n2 Start. Q n2 As collector current increases, Q p1 The emitter junction voltage increases, and the parasitic NPN transistor Q... n2 and parasitic PNP transistor Q p1 The coupling between them forms a positive feedback, at which point the SCR channel is opened.

[0008] When an ESD event reaches the T2 port of the device, such as Figure 1 As shown in (b), the ESD voltage is greater than that of the parasitic PNP transistor Q in the device. p1 BV CEO When (common-emitter-collector junction avalanche breakdown voltage of a bipolar transistor) is reached, Q p1 When turned on, current will flow through R. PW1, the current flows through the second P-type heavily doped region 181, the sixth P-type doped region 161, the fourth P-type doped region 141, the second P-type doped region 131, the sixth N-type doped region 151, the third N-type doped region 122, the first P-type doped region 130, the third P-type doped region 140, the fifth P-type doped region 160 and the first N-type heavily doped region 170 in turn from T2 to T1. PW1 As the current increases, the voltage drop of the well resistance R n2 increases, the emission junction voltage of Q n2 increases, and Q n2 turns on. The collector current of Q p1 increases, the emission junction voltage of Q n2 increases, and the coupling between the parasitic NPN transistor Q p1 and the parasitic PNP transistor Q CEO forms positive feedback, and thus the SCR channel turns on.

[0009] The conventional DDSCR can effectively control the trigger voltage by controlling the size of the parasitic PNP transistor BV CEO , but the main way of discharging the ESD current is still through the SCR channel. Although the SCR channel has strong ESD current discharge capability, due to the positive feedback effect between the two bipolar transistors, the holding voltage of the SCR channel is about 10V, which cannot meet the needs of the ESD protection design of some high-voltage integrated circuits, and the latch-up effect is easy to occur, which makes the device unable to turn off and affects the normal operation of the circuit, and in severe cases, the chip will be damaged.

[0010] Therefore, the present application proposes a DDSCR device capable of adjusting the trigger voltage and the holding voltage, which has a unique split heavily doped region design. Such a design can effectively improve the holding voltage of the device, and thus make it suitable for integrated circuit ESD protection in various high-voltage power domains. SUMMARY

[0011] The purpose of the present application is to propose a split bidirectional SCR device with adjustable trigger voltage and holding voltage for high-voltage integrated circuit ESD protection, which has the characteristics of adjustable high trigger voltage and holding voltage, and can be applied to high-voltage integrated circuit ESD protection in various power domains.

[0012] The technical scheme adopted by the present application is: A split DDSCR with adjustable opening voltage and holding voltage, comprising: The device includes a P-type silicon substrate on which a first N-type doped region is formed. A second N-type doped region, a first P-type doped region, a third N-type doped region, a second P-type doped region, and a fourth N-type doped region are formed on the first N-type doped region. The first P-type doped region is completely surrounded by the first, second, and third N-type doped regions. The second P-type doped region is completely surrounded by the first, third, and fourth N-type doped regions. A third P-type doped region is formed on the first P-type doped region, and a fourth P-type doped region is formed on the second P-type doped region. A fifth N-type doped region is formed on the second N-type doped region, a sixth N-type doped region is formed on the third N-type doped region, and a seventh N-type doped region is formed on the fourth N-type doped region. A fifth P-type doped region is formed on the third P-type doped region, and a sixth P-type doped region is formed on the fourth P-type doped region. The fifth P-type doped region is provided with n alternating first P-type heavily doped regions and first N-type heavily doped regions, and the sixth P-type doped region is provided with n alternating second P-type heavily doped regions and second N-type heavily doped regions, where n is an integer greater than 2; A first silicide barrier layer is formed on the n first P-type heavily doped regions, and a second silicide barrier layer is formed on the n second P-type heavily doped regions; The n alternating first P-type heavily doped regions and the first N-type heavily doped regions are connected to port T1; the n alternating second P-type heavily doped regions and the second N-type heavily doped regions are connected to port T2. Shallow trench isolation is provided between the n alternating first P-type heavily doped regions and the n alternating first P-type heavily doped regions and the n alternating first N-type heavily doped regions.

[0013] The device consists of one parasitic PNP transistor, two parasitic NPN transistors, two well resistors, and two diffusion resistors. The first parasitic PNP transistor includes a first heavily doped P-type region, a fifth P-type doped region, a third P-type doped region, a first P-type doped region, a sixth N-type doped region, a third N-type doped region, a second P-type doped region, a fourth P-type doped region, a sixth P-type doped region, and a second heavily doped P-type region. The first parasitic NPN transistor includes a first heavily doped N-type region, a fifth doped P-type region, a third doped P-type region, a first doped P-type region, a sixth doped N-type region, and a third doped N-type region; the second parasitic NPN transistor includes a second heavily doped N-type region, a sixth doped P-type region, a fourth doped P-type region, a second doped P-type region, a sixth doped N-type region, and a third doped N-type region. The first well resistance refers to the sum of the well resistances of the fifth P-type doped region, the third P-type doped region and the first P-type doped region; and the second well resistance refers to the sum of the well resistances of the sixth P-type doped region, the fourth P-type doped region and the second P-type doped region. The first diffusion resistance refers to a diffusion resistance formed on the surface of the first P-type heavily doped region due to the existence of the first silicide barrier layer; and the second diffusion resistance refers to a diffusion resistance formed on the surface of the second P-type heavily doped region due to the existence of the second silicide barrier layer.

[0014] The first diffusion resistance, the first well resistance, the first parasitic PNP transistor, the second well resistance and the second diffusion resistance jointly form a PNP1 channel; the first diffusion resistance, the first well resistance, the first parasitic PNP transistor and the second parasitic NPN transistor jointly form an SCR1 channel; the second diffusion resistance, the second well resistance, the first parasitic PNP transistor, the first well resistance and the first diffusion resistance jointly form a PNP2 channel; and the second diffusion resistance, the second well resistance, the first parasitic PNP transistor and the first parasitic NPN transistor jointly form an SCR2 channel.

[0015] The present application provides a split type bidirectional SCR device with adjustable trigger voltage and holding voltage for ESD protection of high voltage integrated circuits, which not only inherits the high robustness, simple structure and high area utilization rate of traditional DDSCR devices, but also has adjustable trigger voltage and holding voltage. Compared with traditional DDSCR devices, the device has weaker positive feedback effect and more controllable diffusion resistance. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 It is a structure diagram and an equivalent circuit diagram of a traditional DDSCR device.

[0017] Figure 2 It is a split DDSCR structure diagram and an equivalent circuit diagram of the device described in Example 1. DETAILED DESCRIPTION

[0018] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings and specific embodiments. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0019] It should be noted that all directionality indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present application are only used to explain the relative positional relationship, movement condition, etc. between components in a certain specific posture (as shown in the drawings), and if the specific posture changes, the directionality indications will also change accordingly.

[0020] In addition, the descriptions related to "first", "second" and the like in the present application are only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implying the number of the indicated technical features. Therefore, the features defined as "first" and "second" can be explicitly or implicitly included at least one of the features.

[0021] In addition, the technical solutions of various embodiments can be combined with each other, but it must be based on the fact that a person skilled in the art can realize it. When the combination of technical solutions appears contradictory or unachievable, it should be considered that the combination of technical solutions does not exist and is not within the protection scope required by the present application.

[0022] Embodiment 1 The present embodiment provides a high-voltage integrated circuit ESD protection trigger voltage and holding voltage adjustable split type bidirectional SCR device, the device structure and equivalent circuit diagram as shown in Figure 2 .

[0023] The device described in embodiment 1 includes a P-type silicon substrate 110, a first N-type doped region 120 is formed on the P-type silicon substrate; a second N-type doped region 121, a first P-type doped region 130, a third N-type doped region 122, a second P-type doped region 131 and a fourth N-type doped region 123 are formed on the first N-type doped region; the first P-type doped region 130 is completely surrounded by the first N-type doped region 120, the second N-type doped region 121 and the third N-type doped region 122; the second P-type doped region 131 is completely surrounded by the first N-type doped region 120, the third N-type doped region 122 and the fourth N-type doped region 123; a third P-type doped region 140 is formed on the first P-type doped region 130, and a fourth P-type doped region 141 is formed on the second P-type doped region 131; a fifth N-type doped region 150 is formed on the second N-type doped region 121, a sixth N-type doped region 151 is formed on the third N-type doped region 122, and a seventh N-type doped region 152 is formed on the fourth N-type doped region 123; a fifth P-type doped region 160 is formed on the third P-type doped region 140, and a sixth P-type doped region 161 is formed on the fourth P-type doped region 141; n number of first P-type heavily doped regions 180 and first N-type heavily doped regions 170 are arranged alternately on the fifth P-type doped region 160, and n number of second P-type heavily doped regions 181 and second N-type heavily doped regions 171 are arranged alternately on the sixth P-type doped region 161, n is an integer greater than 2; A first silicide barrier layer 190 is formed on the n number of first P-type heavily doped regions 180, and a second silicide barrier layer 191 is formed on the n number of second P-type heavily doped regions 181; The n alternately arranged first P-type heavily doped regions 180 and first N-type heavily doped regions 170 are connected with the T1 port; the n alternately arranged second P-type heavily doped regions 181 and second N-type heavily doped regions 171 are connected with the T2 port. The n alternately arranged first P-type heavily doped regions 180 and first N-type heavily doped regions 170 are connected with the n alternately arranged first P-type heavily doped regions 181 and first N-type heavily doped regions 171.

[0024] The device is composed of one parasitic PNP transistor, two parasitic NPN transistors, two well resistances, and two diffusion resistances. The first parasitic PNP transistor comprises the first P-type heavily doped region 180, the fifth P-type doped region 160, the third P-type doped region 140, the first P-type doped region 130, the sixth N-type doped region 151, the third N-type doped region 122, the second P-type doped region 131, the fourth P-type doped region 141, the sixth P-type doped region 161, and the second P-type heavily doped region 171. The first parasitic NPN transistor comprises the first N-type heavily doped region 170, the fifth P-type doped region 160, the third P-type doped region 140, the first P-type doped region 130, the sixth N-type doped region 151, and the third N-type doped region 122; the second parasitic NPN transistor comprises the second N-type heavily doped region 171, the sixth P-type doped region 161, the fourth P-type doped region 141, the second P-type doped region 131, the sixth N-type doped region 151, and the third N-type doped region 122. The first well resistance refers to the sum R of the fifth P-type doped region 160, the third P-type doped region 140, and the first P-type doped region 130. PW1 The second well resistance refers to the sum R of the sixth P-type doped region 161, the fourth P-type doped region 141, and the second P-type doped region 131. PW2 ; The first diffusion resistance refers to the diffusion resistance R due to the presence of the first silicide barrier layer 190 on the surface of the first P-type heavily doped region 180. diff1 The second diffusion resistance refers to the diffusion resistance R due to the presence of the second silicide barrier layer 191 on the surface of the second P-type heavily doped region 181. diff2 .

[0025] The first diffusion resistance, the first well resistance, the first parasitic PNP transistor, the second well resistance, and the second diffusion resistance jointly form a PNP1 channel; the first diffusion resistance, the first well resistance, the first parasitic PNP transistor, and the second parasitic NPN transistor jointly form an SCR1 channel; the second diffusion resistance, the second well resistance, the first parasitic PNP transistor, the first well resistance, and the first diffusion resistance jointly form a PNP2 channel; and the second diffusion resistance, the second well resistance, the first parasitic PNP transistor, and the first parasitic NPN transistor jointly form an SCR2 channel.

[0026] The working principle of the device described in Embodiment 1 can be divided into two kinds according to ESD positive voltage reaching different ports T1 and T2: When an ESD event reaches the T1 port of the device, as shown in Figure 2 , the ESD voltage is greater than the BV p1 (basically the avalanche breakdown voltage of the common emitter collector junction of a bipolar transistor) of the parasitic PNP transistor Q CEO in the device, Q p1 is turned on, and current will flow through R PW2 , that is, the current flows through the first P-type heavily doped region 180, the fifth P-type doped region 160, the third P-type doped region 140, the first P-type doped region 130, the sixth N-type doped region 151, the third N-type doped region 122, the second P-type doped region 131, the fourth P-type doped region 141, the sixth P-type doped region 161, and the second N-type heavily doped region 171 in sequence from T1 to T2. As the current increases, the voltage drop of the well resistance R PW2 increases, so that the emitter junction voltage of Q n2 increases, Q n2 is turned on. The collector current of Q n2 increases, the emitter junction voltage of Q p1 increases, and the positive feedback is formed between the parasitic NPN transistor Q n2 and the parasitic PNP transistor Q p1 , and thus the SCR1 channel is turned on.

[0027] When an ESD event reaches the T2 port of the device, as shown in Figure 2 (c), the ESD voltage is greater than the BV p1 (basically the avalanche breakdown voltage of the common emitter collector junction of a bipolar transistor) of the parasitic PNP transistor Q CEO in the device, Q p1 is turned on, and current will flow through R PW1That is, the current flows sequentially from T2 to T1 through the second heavily doped P-type region 181, the sixth heavily doped P-type region 161, the fourth heavily doped P-type region 141, the second heavily doped P-type region 131, the sixth heavily doped N-type region 151, the third heavily doped N-type region 122, the first heavily doped P-type region 130, the third heavily doped P-type region 140, the fifth heavily doped P-type region 160, and the first heavily doped N-type region 170. As the current increases, the well resistance R... PW1 The voltage drop increases, causing Q to... n2 As the emitter junction voltage increases, Q n2 Start. Q n2 As collector current increases, Q p1 The emitter junction voltage increases, and the parasitic NPN transistor Q... n2 and parasitic PNP transistor Q p1 The coupling between them forms a positive feedback, at which point the SCR2 channel is turned on.

[0028] Device Q described in Example 1 p1 Triggered when the applied voltage is greater than the transistor's BV. CEO When the transistor is turned on, it can be controlled by adjusting the transistor Q. p1 BV CEO The magnitude of the trigger voltage of the device is adjusted by the magnitude of the voltage.

[0029] BV CEO The size can be obtained by the following formula: {BV}_{CEO}\approx \frac {{BV}_{CBO}} {\sqrt[{S}] {β}} Among them BV CBO This is the collector junction avalanche breakdown voltage when the emitter is open. β S is the common-emitter DC short-circuit current amplification factor, and S is a constant.

[0030] Q can be adjusted by regulating the distance between the third P-type doped region 140 and the sixth N-type doped region 151, and the distance between the sixth N-type doped region 151 and the fourth P-type doped region 141. p1 BV CBO This allows for the adjustment of the trigger voltage. By adjusting in this way, the trigger voltage of the device described in Example 1 can be adapted to different ESD design windows.

[0031] The maintaining voltage of the device of embodiment 1 is proportional to the ratio of the current through the PNP channel and the current through the SCR channel. Because of the existence of the parasitic PNP and parasitic NPN in the SCR, when the SCR is turned on, positive feedback is formed between the parasitic PNP and the parasitic NPN, which makes the SCR have a smaller applied voltage to maintain the conduction state, and the maintaining voltage of the SCR path is relatively low; while the transistor is turned on, a larger applied voltage is needed to make the emitter junction positively biased and the collector junction negatively biased to maintain the conduction state, and the maintaining voltage of the transistor path is relatively high. Therefore, the regulation of the maintaining voltage size can be realized by changing the size of the resistances in the PNP and SCR current paths. The present application can simply change the size of the first diffusion resistance R diff1 and the second diffusion resistance R diff2 by regulating the area of the first silicide barrier layer 190 and the second silicide barrier layer 191, and then achieve the purpose of regulating the maintaining voltage size. By adjusting in this way, the maintaining voltage of the device of embodiment 1 can be applied to different ESD design windows.

[0032] At the same time, compared with the reference device DDSCR, the device has n pairs of P-type and N-type heavily doped regions arranged alternately, which reduces the emitter injection efficiency of the parasitic NPN transistor, reduces the β size of the parasitic NPN transistor, and the positive feedback is not easy to form, the SCR opening speed is slow, and the maintaining voltage is further improved, which better meets the needs of high-voltage integrated circuit ESD protection.

[0033] The above examples are only used to illustrate the technical solutions of the present application and not to limit it. Although the present application has been described with reference to the preferred examples, it should be understood by those skilled in the art that any feature disclosed in the specification can be replaced by other equivalent or similar purpose alternative features, and all features disclosed in the specification, or steps in all methods or processes, except for mutually exclusive features and / or steps, can be combined in any way without departing from the purpose and scope of the technical solutions of the present application, which should be covered in the scope of the claims of the present application.

Claims

1. A split DDSCR with adjustable opening voltage and maintaining voltage, characterized in that: the device comprises a P-type silicon substrate, a first N-type doped region is formed on the P-type silicon substrate, a second N-type doped region, a first P-type doped region, a third N-type doped region, a second P-type doped region and a fourth N-type doped region are formed on the first N-type doped region, the first P-type doped region is entirely surrounded by the first N-type doped region, the second N-type doped region and the third N-type doped region, the second P-type doped region is entirely surrounded by the first N-type doped region, the third N-type doped region and the fourth N-type doped region, a third P-type doped region is formed on the first P-type doped region, a fourth P-type doped region is formed on the second P-type doped region, a fifth N-type doped region is formed on the second N-type doped region, a sixth N-type doped region is formed on the third N-type doped region, a seventh N-type doped region is formed on the fourth N-type doped region, a fifth P-type doped region is formed on the third P-type doped region, and a sixth P-type doped region is formed on the fourth P-type doped region; n first P-type heavily doped regions and n first N-type heavily doped regions are alternately arranged on the fifth P-type doped region, n second P-type heavily doped regions and n second N-type heavily doped regions are alternately arranged on the sixth P-type doped region, and n is an integer greater than 2; a first silicide barrier layer is formed on the n first P-type heavily doped regions, and a second silicide barrier layer is formed on the n second P-type heavily doped regions; the n first P-type heavily doped regions and the n first N-type heavily doped regions are connected to a T1 port, and the n second P-type heavily doped regions and the n second N-type heavily doped regions are connected to a T2 port; a shallow trench isolation is arranged between the n first P-type heavily doped regions and the n first N-type heavily doped regions and between the n second P-type heavily doped regions and the n second N-type heavily doped regions. ​

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