Time-based memory allocation

Abstract

Examples described herein relate to allocating memory capacity for a duration based on receiving a request to allocate memory capacity for a duration. The request may include a configuration requesting allocation of memory capacity, and the configuration specifies a time layer and / or duration. The request may specify one or more of the following: a request identifier, a memory capacity to be allocated, or a request duration for reserving memory capacity.

Description

[0001] Priority Statement This application claims priority to U.S. Patent Application No. 18 / 375,477, filed September 30, 2023, entitled “Time-Based Memory Allocation,” the entire contents of which are incorporated herein by reference. Background Technology

[0002] Memory pools provide access to scalable capacity memory in Dynamic Random Access Memory (DRAM) devices. However, expanding memory capacity in memory pools faces numerous challenges, such as capacity scaling, rising costs for adding memory, and bandwidth scaling challenges. Compute Fast Link (CXL) supports access to various memory types (e.g., CXL Double Data Rate (DDR5) memory on riser cards, CXL DDR4 memory on riser cards, phase-change memory (PCM) on CXL, flash memory on CXL, etc.) and may address some of the challenges faced by memory pools. Cloud service providers (CSPs) can offer managed CXL connected memory pools as memory pools. Accordingly, CSPs can provide tenants and end users with a variety of options to use memory with different latency and bandwidth characteristics and different capacities at different price points.

[0003] There are instances where memory utilization can increase to several times the average usage. The most severe peaks can be periodic or deterministic, such as at the end of a quarter or during shopping seasons (e.g., the back-to-school season in August and September, Friday sales, holiday sales, etc.). Over-provisioning memory for peak usage can result in wasted capacity during average usage. Attached Figure Description

[0004] Figure 1 An example system is shown.

[0005] Figure 2 The example process is described.

[0006] Figure 3 The example process is described.

[0007] Figure 4 An example system is described. Detailed Implementation

[0008] Various examples provide a parameterized interface for requesting the start time and duration of memory capacity to be allocated. This interface can include an application programming interface (API), a configuration file, an executable binary, or other messages or commands. The duration can be specified in seconds, minutes, hours, or fractions or multiples thereof. For example, the requester can include a process, and the operating system (OS) can provide the interface. In some examples, the requester can include the OS, and a coordinator can provide the interface. The OS and / or coordinator can manage memory allocation, such as timed usage, time extensions, and de-allocation. The OS and / or coordinator can track the address ranges and expiration dates of memory borrowed from one or more memory pools. The OS and / or coordinator can perform malloc() or mmap() based on the parameters specified in the interface. The requester can borrow memory of different technologies (e.g., memory type or memory interface) from one or more memory pools with different per-memory costs (e.g., dollars ($) per gigabyte (GB)) for a specified duration. Furthermore, the process, OS, and coordinator can negotiate and manage memory allocations with time semantics from the memory pools.

[0009] Figure 1 An example system is depicted. Node 10 may include processor 100, circuitry 110, and / or circuitry 120, and at least in combination with... Figure 3 Other circuitry and software described. Processor 100, circuitry 110, and / or circuitry 120 may include one or more of the following: a central processing unit (CPU), a graphics processing unit (GPU), an XPU, etc.; one or more accelerators; one or more application-specific integrated circuits (ASICs); one or more field-programmable gate arrays (FPGAs); one or more graphics processing units (GPUs); one or more memory devices; one or more storage devices; one or more network interface devices; or other components.

[0010] In some examples, processor 100, circuit 110, and / or circuit 120 may execute process 102. Process 102 may be implemented as one or more of the following: application, microservice, virtual machine (VM), microVM, container, thread, or other virtualized execution environment.

[0011] For example, process 102 can perform packet processing based on one or more of the following: Data Plane Development Kit (DPDK), Storage Performance Development Kit (SPDK), OpenDataPlane, Network Functions Virtualization (NFV), Software-Defined Networking (SDN), Evolved Packet Core (EPC), or 5G network slicing. Some example implementations of NFV are described in the European Telecommunications Standards Institute (ETSI) specifications or the ETSI Open Source Management and Orchestration (OSM) group's Open Source NFV Management and Orchestration (MANO). Virtual Network Functions (VNFs) can include service chains or sequences of virtualized tasks performed on general-purpose configurable hardware (e.g., firewalls, Domain Name System (DNS), caches, or Network Address Translation (NAT)) and can run in process 102. VNFs can be chained together as service chains. In some examples, EPC is a core architecture specified by 3GPP, at least for LTE access. 5G network slicing can provide the reuse of virtualized and independent logical networks on the same physical network infrastructure. Some processes can perform video processing or media transcoding (e.g., changing the encoding of audio, images, or video files).

[0012] In some examples, processor 100, circuitry 110, and / or circuitry 120 may execute an operating system (OS) 112. OS 112 may receive configuration 116 from a system administrator or coordinator 122, indicating whether memory allocation is performed based on a time-based or non-time-based approach. Furthermore, OS 112 may receive a budget configuration 117, indicating time-based memory allocation for a process or tenant identifier. For example, for a tenant or process, budget configuration 117 may indicate the maximum memory capacity to be allocated, the available memory categories, the duration for which that capacity and category of memory is allowed to be allocated, etc. Budget configuration 117 may specify a budget for the cost per unit of time allocated to a particular tenant or process via a process identifier. For example, a system administrator may specify budget 117 based on a Service Level Agreement (SLA) or Service Level Objective (SLO) for tenant or process 102.

[0013] Based on the verification of configuration 116 and budget 117 (e.g., by verifying checksums or other integrity checks), OS112 can apply configuration 116 and budget 117.

[0014] Process 102 may issue request 106 to OS 112. As described herein, request 106 may include parameters for memory allocation, including a start time, duration, and the amount of memory to be allocated (e.g., in bytes or bits). In some examples, request 106 may include one or more of the following fields or parameters: request identifier, expected start time, duration, requested memory capacity, memory time tier (e.g., memory read or write speed, memory interface latency or bandwidth or type, connection latency or bandwidth), and processing identifier (e.g., process address space identifier (PASID)).

[0015] The memory time tier can be based on the memory interface type, and includes at least: DDR3 (Double Data Rate version 3, initially released by JEDEC (Joint Electron Device Engineering Committee) on June 16, 2007); DDR4 (DDR version 4, the initial specification released by JEDEC in September 2012); DDR4E (DDR version 4); LPDDR3 (Low Power DDR version 3, JESD209-3B, released by JEDEC in August 2013); LPDDR4 (LPDDR version 4, JESD209- 4. (JEDEC initially released in August 2014); WIO2 (Wide Input / Output Version 2, JESD229-2, JEDEC initially released in August 2014); HBM (High Bandwidth Memory, JESD325, JEDEC initially released in October 2013); LPDDR5 (currently under discussion by JEDEC); HBM2 (HBM Version 2); DDR Version 5; CXL; High-Speed ​​Peripheral Component Interconnect (PCIe); or other memory technologies or combinations thereof; and technologies derived from or extended based on such specifications.

[0016] The time tier of memory can be based on the type of memory technology (e.g., memory read or write speed), and includes at least: cache, static random access memory (SRAM), DRAM, flash memory, and phase-change memory that can be accessed as memory.

[0017] Based on the time-based memory allocation tracker 114, configuration 116, and budget 117, OS 112 can determine to accept, reject, or partially accept a request 106. Based on configuration 116, budget 117, and tracker 114, OS 112 can satisfy the request 106 from a free page list (e.g., DRAM or CXL-connected memory) or request time-leased memory from one or more memory pools 130-0 to 130-N via coordinator 122, where N is an integer. The time-based memory allocation tracker 114 can indicate the range of virtual or physical memory addresses to be allocated to a particular process or circuit (e.g., start and end physical or virtual memory addresses). In some cases, the time-based memory allocation tracker 114 can indicate the duration or time period for which a virtual memory address range should be allocated to a particular process or circuit. OS 112 can provide a response 108 to process 102 (e.g., accept, reject, or partially accept the request 106). In some examples, when the requested memory time tier is unavailable, response 108 may allocate a slower memory time tier that lasts longer than the requested one.

[0018] The example format for tracker 114 is as follows.

[0019]

[0020] Response 108 may include one or more of the following parameters or fields: approval, partial approval, rejection, and (for an approval request) a pointer to the starting address of the memory allocation location. When response 108 is a partial acceptance, response 108 may include a counter-offer for: available time tier, available memory capacity, available start time, and / or available duration.

[0021] The time-based memory allocation tracker 114 may include an address range time hash map. The OS 112 and / or coordinator 122 may use time parameters as input for memory allocation to implement the hash map in the tracker 114. The tracker 114 may store an address range and its corresponding time expiration based on the allocated memory address range, using the current time and the request duration in seconds. The OS 112 and / or coordinator 122 may use time parameters from approved memory release requests to update the time-based hash map accordingly.

[0022] Circuits (e.g., processor 100, circuit 110, and / or circuit 120) may enter a lower power state and execute a TPAUSE instruction, and OS 112 and / or coordinator 122 (or other software, firmware, or circuitry) may perform memory release as the time period specified in tracker 114 approaches. In some examples, OS 112 may send request 118 to coordinator 122 to allocate memory for a certain duration according to request 106.

[0023] In some examples, processor 100, circuit 110, and / or circuit 120 may execute coordinator 122. In some examples, OS 112 may provide data to coordinator 122 to perform the release of a memory region based on the expiration of a memory region's timer. For example, coordinator 122 may determine a range of memory addresses to be allocated in one or more pooled memories 130-0 to 130-N based on data in request 118. Coordinator 122 may update time-based memory allocation tracker 124 based on data in request 118. Although not shown, coordinator 122 may receive time-based memory allocation requests from one or more of the following: another process, another OS, and another coordinator. This other process, another OS, and another coordinator may be within or executed by node 10 or another node.

[0024] OS 112 can track time-based leases for pooled memory and notify coordinator 122 to extend the lease period based on potential budgets from budget 117 or other criteria. If address range time tracker 114 indicates that the allocation time for a memory range has ended, OS 112 can revert to a set of options registered by the application or system administrator, such as actively requesting an extension of the memory region's time, or instructing process 102 that all or part of the memory address region is no longer available for allocation. Process 102 can receive an indication from OS 112 or coordinator 122 that memory capacity has been actively requested for a specific start time and duration, potentially avoiding duplicate requests from process 102.

[0025] OS 112 can predict the start time, duration, and memory usage of process 102 based on machine learning (ML) and / or artificial intelligence (AI) reasoning. For example, based on time-based or system event-based usage trends of process 102 or other processes, OS 112 can proactively request the predicted memory allocation capacity from coordinator 122 at a specific start time and for a specified duration by issuing request 118 again. For example, time-based trends could be the end of a season, the end of a quarter, a holiday season, etc. For example, system events could include page fault events triggered by process 102.

[0026] In some examples, process 102 does not use previously allocated memory and may issue a release request 106 to free the corresponding address range for allocation to another process. For example, release request 106 may indicate one or more of the following: a request identifier, a starting address, the amount of memory to be reserved or released, or a delay until release time. In some examples, release request 106 follows the same format as allocation request 106 but indicates a duration of zero (0) or a shorter duration than previously requested to reduce memory lease. When a duration of zero is specified, OS 112 and / or coordinator 122 may release the memory region immediately. However, when a delay until release time is specified in seconds, OS 112 and / or coordinator 122 may release the memory region after the delay until release time has elapsed. Conversely, if the delay until release time is longer than the previously allocated or remaining time, OS 112 and / or coordinator 122 may extend the memory lease of the previous memory region until the delay until release time is satisfied. In response to a request to shorten or extend memory allocation, OS 112 may issue a response 108 indicating one or more of the following: a request identifier and a response (e.g., approval, partial approval, or rejection). Partial approval may follow the same format as partial approval of memory allocation request 106 described above.

[0027] Coordinator 122 can provide interfaces to one or more memory pools 130-0 to 130-N (where N is an integer) and can track memory region allocations and durations in tracker 124. When a requested time expires, coordinator 122 can communicate with the operating system, which can decide to extend the lease, release memory, or provide a memory shortage notification to process 102. The decision to extend the lease, release memory, or provide a memory shortage notification can be made based on configuration 116 and budget 117.

[0028] Node 10 can access one or more memory pools 130-0 to 130-N through one or more of the following: device interface, memory interface, network (e.g., Ethernet), or related information. Figure 3 Other interconnect technologies described in the system description. A memory pool may include one or more memory pools having dual in-line memory modules (DIMMs) or other memory. Memory may include one or more of the following: one or more registers, one or more cache devices (e.g., L1 cache, L2 cache, L3 cache, Last Level Cache (LLC)), volatile memory devices, non-volatile memory devices, or persistent memory devices. For example, memory may include static random access memory (SRAM) technology, or memory technologies conforming to high bandwidth memory (HBM), double data rate (DDR), etc.

[0029] One or more memory pools 130-0 to 130-N can be accessed as local devices or remote memory pools via device interfaces, switches, or networks. Memory pools can be shared by multiple servers or processors. One or more memory pools 130-0 to 130-N may include at least two levels of memory that can be used (also referred to herein as “2LM” or tiered memory), including a cached subset of system disk-level storage (e.g., in addition to runtime data). The main memory includes: a first level (also referred to herein as “near-end memory”), which includes lower latency and / or higher bandwidth memory, such as dynamic random access memory (DRAM) or other volatile memory; and a second level (also referred to herein as “far-end memory”), which includes (relative to near-end memory) volatile memory (e.g., DRAM) or non-volatile memory storage devices (e.g., flash memory or byte-addressable non-volatile memory (e.g., Intel Optane®)) with higher latency and / or lower bandwidth. The far-end memory may be presented as “main memory” to the host operating system (OS), while the near-end memory may include caches for the far-end memory that are transparent to the OS. Two-tier memory management can be performed through a combination of circuitry and modules executed by the host central processing unit (CPU). Near-end memory can be coupled to the host system CPU via high-bandwidth, low-latency connections to achieve low-latency data availability. Far-end memory can be coupled to the CPU via low-bandwidth, high-latency connections (compared to near-end memory), networks or structures, or similar high-bandwidth, low-latency connections. Far-end memory devices can exhibit higher latency or lower memory bandwidth than near-end memory. For example, tier 2 memory may include far-end memory devices, while tier 1 may include near-end memory.

[0030] One or more memory pools 130-0 to 130-N can be accessed as virtual devices via hardware-assisted input / output (I / O) virtualization, which defines how endpoint devices are partitioned across multiple processes for direct sharing. Examples of hardware-assisted I / O virtualization are based on virtualization standards such as Single Root I / O Virtualization (SR-IOV) or Scalable Input / Output (I / O) Virtualization (S-IOV).

[0031] Example operation of the system is as follows. At (1), process 102 may make a request to OS 112 for the allocation of a memory capacity for a certain duration and time tier. At (2), OS 112 may determine whether to accept, reject, or partially accept the request. At (3), the OS may provide a response in response 108. At (4), based on acceptance or partial acceptance of request 106 (e.g., less than the requested memory capacity, less than the requested time tier, and / or less than the requested duration), OS 112 may make a request to coordinator 122 to allocate the approved memory capacity for the approved duration. In some examples, partial acceptance may satisfy the SLA of process 102. At (5), coordinator 122 may allocate the approved memory capacity for the approved duration in one or more memory pools 130-0 to 130-N. At (6), coordinator 122 may indicate to OS 112 that the duration has expired. At (7), OS 112 can proactively request memory capacity allocation for process 102 based on past memory usage.

[0032] Figure 2 An example process is depicted. This process can be executed by a virtual machine, container, application, etc. At 202, the process can provide a request for allocating memory capacity for a duration, as well as the start time for the memory capacity allocation and the memory time tier. In some examples, the process can issue this request to the OS and / or coordinator. At 204, the process can receive a response to the request, indicating the allocated memory capacity, the allocated duration, the allocated start time for the memory capacity allocation, and the allocated memory time tier. Subsequently, the process can issue a request to increase or decrease one or more of the following: duration, memory capacity, and / or memory time tier.

[0033] Figure 3 An example process is depicted. This process can be executed by the OS and / or coordinator or other components. At 302, a decision can be made regarding accepting, partially accepting, or rejecting a received request for allocating memory capacity for a certain duration and time tier. For example, this decision can be based on a tracker indicating the allocated memory, the time tier of the allocated memory, the time the memory was allocated, and the SLA associated with the requester. For example, the request can be accepted if it can be satisfied. For example, the request can be partially accepted if a portion of it can be accepted. For example, the request can be rejected if, according to the tracker and the applicable SLA, no part of the request can be satisfied.

[0034] At 304, a response to the request can be sent to indicate the decision.

[0035] Figure 4 A system is described. In some examples, the circuitry of system 400 may allocate memory time layers for specific time periods, as described herein. System 400 includes a processor 410 that provides processing, operation management, and instruction execution for system 400. Processor 410 may include any type of microprocessor, central processing unit (CPU), graphics processing unit (GPU), XPU, processing core, or other processing hardware used to provide processing for system 400, or a combination of processors. XPU may include one or more of the following: CPU, graphics processing unit (GPU), general purpose GPU (GPGPU), and / or other processing units (e.g., accelerators or programmable or fixed-function FPGAs). Processor 410 controls the overall operation of system 400 and may be or may include one or more programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), etc., or combinations of such devices.

[0036] In one example, system 400 includes an interface 412 coupled to processor 410. This interface can represent a higher-speed or high-throughput interface for system components requiring higher bandwidth connections, such as memory subsystem 420, graphics interface component 440, or accelerator 442. Interface 412 represents interface circuitry and can be a standalone component or integrated onto the processor die. If present, graphics interface 440 interfaces with the graphics component to provide a visual display to the user of system 400. In one example, graphics interface 440 generates the display based on data stored in memory 430, or based on operations performed by processor 410, or both.

[0037] Accelerator 442 may be a programmable or fixed-function load balancing engine that can be accessed or used by processor 410. For example, one of the accelerators 442 may provide data compression (DC) capabilities, cryptographic services (e.g., public key encryption (PKE)), cryptography, hashing / authentication capabilities, decryption, or other capabilities or services. In some cases, accelerator 442 may be integrated into a CPU socket (e.g., a connector on a motherboard or circuit board that includes a CPU and provides an electrical interface to the CPU). For example, accelerator 442 may include a single-core or multi-core processor, a graphics processing unit, a logic execution unit, a single-level or multi-level cache, functional units that can be used to independently execute programs or threads, an application-specific integrated circuit (ASIC), a neural network processor (NNP), programmable control logic, and programmable processing elements such as a field-programmable gate array (FPGA). Accelerator 442 can provide multiple neural networks, CPUs, processor cores, general-purpose graphics processing units, or graphics processing units that can be used by artificial intelligence (AI) or machine learning (ML) models. For example, AI models can use or include any or a combination of the following: reinforcement learning schemes, Q-learning schemes, deep Q-learning, or asynchronous advantage actor-critic (A3C), ensemble neural networks, recursive ensemble neural networks, or other AI or ML models. Multiple neural networks, processor cores, or graphics processing units can be used by AI or ML models to perform learning and / or inference operations.

[0038] Memory subsystem 420 represents the main memory of system 400 and provides storage for code to be executed by processor 410 or data values ​​to be used during routine execution. Memory subsystem 420 may include one or more memory devices 430, such as read-only memory (ROM), flash memory, one or more types of random access memory (RAM) (e.g., DRAM), or other memory devices, or combinations thereof. Memory 430 stores and hosts operating system (OS) 432, etc., to provide a software platform for the execution of instructions in system 400. Furthermore, application 434 can be executed from memory 430 on the software platform of OS 432. Application 434 represents a program with its own operating logic to perform one or more functions. Process 436 represents an agent or routine that provides auxiliary functions to OS 432 or one or more applications 434, or combinations thereof. OS 432, application 434, and process 436 provide software logic to provide functionality to system 400. In one example, memory subsystem 420 includes memory controller 422, which is a memory controller for generating and issuing commands to memory 430. It should be understood that memory controller 422 may be a physical part of processor 410 or a physical part of interface 412. For example, memory controller 422 may be an integrated memory controller, integrated into the circuitry along with processor 410.

[0039] Application 434 and / or process 436 may alternatively or additionally refer to virtual machines (VMs), containers, microservices, processors, or other software. The various examples described herein can execute applications composed of microservices, where microservices operate in their own processes and communicate using protocols such as Application Programming Interfaces (APIs), Hypertext Transfer Protocol (HTTP) resource APIs, messaging services, remote procedure calls (RPCs), or Google RPC (gRPC). Microservices can communicate with each other using service meshes and can be executed in one or more data centers or edge networks. Microservices can be deployed independently using centralized management of these services. Management systems can be written in different programming languages ​​and use different data storage technologies. Microservices can be characterized by one or more of the following: multi-language programming (e.g., code written in multiple languages ​​to capture additional functionality and efficiency that a single language cannot provide), lightweight container or virtual machine deployment, and distributed, continuous microservice delivery.

[0040] In some examples, OS 432 can be Linux®, FreeBSD, Windows® server or personal computer, FreeBSD®, Android®, macOS®, iOS®, VMware vSphere, openSUSE, RHEL, CentOS, Debian, Ubuntu, or any other operating system. The OS and driver can run on processors sold or designed by companies such as Intel®, ARM®, AMD®, Qualcomm®, IBM®, NVIDIA®, Broadcom®, Texas Instruments®, etc.

[0041] In some examples, OS 432, system administrators, and / or coordinators can allocate the capacity of the time tier of memory for specific time periods, as described in this article.

[0042] Although not specifically illustrated, it will be understood that system 400 may include one or more buses or bus systems between devices, such as a memory bus, graphics bus, interface bus, or others. Buses or other signal lines may communicatively or electrically couple components together, or both. Buses may include physical communication lines, point-to-point connections, bridges, adapters, controllers, or other circuitry or combinations thereof. Buses may include one or more of, for example, a system bus, a Peripheral Component Interconnect (PCI) bus, a Hyper Transport or Industry Standard Architecture (ISA) bus, a Small Computer System Interface (SCSI) bus, a Universal Serial Bus (USB), or an Institute of Electrical and Electronics Engineers (IEEE) standard 1394 bus (Firewire).

[0043] In one example, system 400 includes interface 414, which can be coupled to interface 412. In one example, interface 414 represents interface circuitry, which may include individual components and integrated circuits. In one example, multiple user interface components or peripheral components, or both, are coupled to interface 414. Network interface 450 provides system 400 with the ability to communicate with remote devices (e.g., servers or other computing devices) over one or more networks. Network interface 450 may include an Ethernet adapter, wireless interconnect component, cellular interconnect component, USB (Universal Serial Bus), or other wired or wireless standard-based or proprietary interfaces. Network interface 450 can transmit data to devices in the same data center or rack, or to remote devices; this may include sending data stored in memory. Network interface 450 can receive data from remote devices; this may include storing the received data in memory. In some examples, packet processing device or network interface device 450 may refer to one or more of the following: network interface controller (NIC), remote direct memory access (RDMA) enabled NIC, SmartNIC, router, switch, forwarding element, infrastructure processing unit (IPU), or data processing unit (DPU).

[0044] In some examples, the management controller 444 may perform one or more of the following: retrieve server identification and asset information (e.g., health status, temperature sensors and fans, power output levels, platform power consumption and thresholds, input / output (I / O) infrastructure data (e.g., host network interface controller media access control (MAC) addresses) of the device to be managed (e.g., a light-out management, LOM) device); hard disk status or failure reporting; network-based service endpoint discovery; system topology discovery (e.g., racks, chassis, servers, nodes); restart or power cycle the server and its connected devices; change the startup order of devices; set power thresholds; alarm or event notification; event log access; access and configure management controller network settings; manage management controller user accounts; perform power distribution across different parts of the system; allocate power management for the host system and network interface device 450; configure the operating frequency or power of the core and network interface device 450; manage the memory of the host system and network interface device 450; control software updates for the host system and network interface device 450; or control firmware updates for the host system and network interface device 450.

[0045] In one example, system 400 includes one or more input / output (I / O) interfaces 460. I / O interfaces 460 may include one or more interface components through which users interact with system 400. Peripheral interfaces 470 may include any hardware interfaces not specifically mentioned above. Peripherals generally refer to devices that are dependently connected to system 400.

[0046] In one example, system 400 includes a storage subsystem 480 for storing data in a non-volatile manner. In one example, in certain system implementations, at least some components of storage device 480 may overlap with components of memory subsystem 420. Storage subsystem 480 includes one or more storage devices 484, which may be or may include any conventional medium for storing large amounts of data in a non-volatile manner, such as one or more magnetic, solid-state, or optical-based disks, or combinations thereof. Storage device 484 retains code or instructions and data 486 in a persistent state (e.g., the value is retained despite a power outage to system 400). Storage device 484 can be generally considered as "memory," although memory 430 is typically execution or operational memory to provide instructions to processor 410. Storage device 484 is non-volatile, while memory 430 may include volatile memory (e.g., the value or state of data is indeterminate if power to system 400 is interrupted). In one example, the storage subsystem 480 includes a controller 482 to interface with the storage device 484. In one example, the controller 482 is a physical part of the interface 414 or the processor 410, or may include circuitry or logic from both the processor 410 and the interface 414.

[0047] Volatile memory can include memory whose state is uncertain (and therefore the data stored therein is uncertain) in the event of a power outage to the device. Non-volatile memory (NVM) devices can include memory whose state is deterministic even in the event of a power outage to the device.

[0048] In some examples, System 400 can be implemented using an interconnected computing platform of processors, memory, storage devices, network interfaces, and other components. High-speed interconnects can be used, such as: Ethernet (IEEE 802.3), Remote Direct Memory Access (RDMA), InfiniBand, Internet Wide Area RDMA Protocol (iWARP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Quick UDP Internet Connection (QUIC), RDMA over Converged Ethernet (RoCE), Peripheral Component Interconnect Express (PCIe), Intel QuickPath Interconnect (QPI), Intel Ultra Path Interconnect (UPI), Intel On-Chip System Fabric (IOSF), Omni-Path, Compute Express Link (CXL), HyperTransport, High-Speed ​​Fabric, NVLink, Advanced Microcontroller Bus Architecture (AMBA) Interconnect, OpenCAPI, Gen-Z, and Infinity Fabric. Fabric (IF), Cache Coherent Interconnect for Accelerator (CCIX), 3GPP Long Term Evolution (LTE) (4G), 3GPP 5G, and variations thereof. Data can be copied or stored to virtualized storage nodes, or accessed using protocols such as Fabric-based NVMe (NVMe-oF) or NVMe (e.g., Non-Volatile Memory Fast (NVMe) devices can operate in accordance with Non-Volatile Memory Fast (NVMe) Specification Revision 1.3c (“NVMe Specification”) released on May 24, 2018, or its derivatives or variations).

[0049] Communication between devices can occur using a network that provides die-to-die communication; chip-to-chip communication; board-to-board communication; and / or package-to-package communication.

[0050] In one example, System 400 can be implemented using an interconnected computing platform of processors, memory, storage devices, network interfaces, and other components. High-speed interconnects, such as PCIe, Ethernet, or optical interconnects (or combinations thereof), can be used.

[0051] The examples in this article can be implemented in various types of computing and networking devices, such as switches, routers, rack and blade servers, as seen in data center and / or server farm environments. Servers used in data centers and server farms include array-based server configurations, such as rack-based servers or blade servers. These servers are interconnected in communication via various network configurations, such as dividing groups of servers into Local Area Networks (LANs), with appropriate switching and routing facilities between LANs to form private intranets. For example, cloud hosting facilities may typically employ large data centers with numerous servers. Blades comprise individual computing platforms configured to perform server-type functions, i.e., "server-on-card." Therefore, blades include components common to traditional servers, including a main printed circuit board (motherboard) that provides internal wiring (e.g., buses) for coupling appropriate integrated circuits (ICs) and other components mounted on the board.

[0052] Various examples can be implemented using hardware elements, software elements, or a combination of both. In some examples, hardware elements may include devices, components, processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, etc.), integrated circuits, ASICs, PLDs, DSPs, FPGAs, memory cells, logic gates, registers, semiconductor devices, chips, microchips, chipsets, etc. In some examples, software elements may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, APIs, instruction sets, computational code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. Determining whether an example utilizes hardware elements and / or software elements to implement what is expected according to a given implementation method can vary based on any number of factors, such as expected computational speed, power level, thermal tolerance, processing cycle budget, input data rate, output data rate, memory resources, data bus speed, and other design or performance constraints. A processor can be a hardware state machine, digital control logic, a central processing unit, or one or more combinations of any hardware, firmware, and / or software elements.

[0053] Some examples may be implemented or be implemented as an article of art or at least a computer-readable medium. The computer-readable medium may include a non-transitory storage medium for storing logic. In some examples, the non-transitory storage medium may include one or more types of computer-readable storage media capable of storing electronic data, including volatile or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writable or rewritable memory, and so on. In some examples, the logic may include various software elements, such as software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, APIs, instruction sets, computational code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof.

[0054] According to some examples, computer-readable media may include non-transitory storage media to store or maintain instructions that, when executed by a machine, computing device, or system, cause that machine, computing device, or system to perform methods and / or operations according to the described examples. Instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, etc. Instructions may be implemented according to a predetermined computer language, manner, or syntax to instruct a machine, computing device, or system to perform specific functions. Instructions may be implemented using any suitable high-level, low-level, object-oriented, visual, compiled, and / or interpreted programming language.

[0055] One or more aspects of at least one example can be implemented by representative instructions representing various logic within a processor, stored on at least one machine-readable medium, which, when read by a machine, computing device, or system, cause the machine, computing device, or system to manufacture logic to perform the techniques described herein. This representation, referred to as an "IP core," can be stored on a tangible machine-readable medium and provided to various customer or manufacturing facilities for loading into the manufacturing machine that actually manufactures the logic or processor.

[0056] The phrases “an example” or “one example” do not necessarily refer to the same example or embodiment. Any aspect described herein may be combined with any other aspect or similar aspect described herein, whether or not these aspects are described with reference to the same drawings or elements. The division, omission, or inclusion of block functions depicted in the drawings does not imply that hardware components, circuits, software, and / or elements used to implement these functions will necessarily be divided, omitted, or included in the embodiments.

[0057] Examples can be described using the terms “coupling” and “connection” and their derivatives. For instance, descriptions using the terms “connection” and / or “coupling” indicate that two or more elements are in direct physical or electrical contact. However, the term “coupling” can also refer to two or more elements that are not in direct contact but still cooperate or interact.

[0058] The terms “first,” “second,” and the like are not used herein to indicate any order, quantity, or importance, but rather to distinguish one element from another. The term “a” herein does not imply a limitation on quantity, but rather indicates the presence of at least one mentioned item. The term “assertion” as used herein when referring to a signal refers to a state in which the signal is valid, and this state can be achieved by applying any logic level (whether logic 0 or logic 1) to the signal (e.g., active low or active high). The terms “subsequently” or “afterward” can mean immediately following or following one or more other events. According to alternative embodiments, other sequences of operations may also be performed. Furthermore, depending on the specific application, additional operations may be added or removed. Any combination of variations can be used, and many variations, modifications, and alternative embodiments will be understood by those skilled in the art who benefit from this disclosure.

[0059] Unless otherwise specifically stated, disjunctive language such as the phrase "at least one of X, Y, or Z" is understood in context to generally state that an item, term, etc., can be X, Y, or Z, or any combination thereof (e.g., X, Y, and / or Z). Thus, such disjunctive language is generally not intended, nor should it imply, that some embodiments require the presence of at least one X, at least one Y, or at least one Z. Furthermore, unless otherwise specifically stated, connective language such as the phrase "at least one of X, Y, and Z" should also be understood to refer to X, Y, Z, or any combination thereof, including "X, Y, and / or Z".

[0060] Illustrative examples of the devices, systems, and methods disclosed herein are provided below. Embodiments of the devices, systems, and methods may include any one or more of the examples described below, as well as any combination thereof.

[0061] Example 1 may include one or more examples and may include at least one non-transitory computer-readable medium including instructions that, if executed, cause circuitry to: receive a request to allocate memory capacity for a duration based on: receiving a configuration requesting the allocation of the memory capacity, wherein the configuration specifies a time tier and / or the duration; and allocate the memory capacity for the duration.

[0062] Example 2 may include one or more examples, wherein the request is used to specify one or more of the following: a request identifier, the memory capacity to be allocated, or the request duration for reserving the memory capacity.

[0063] Example 3 may include one or more examples in which the time layer is associated with the speed of read and / or write operations and the connection latency for accessing the memory.

[0064] Example 4 may include one or more examples, including instructions that, if executed, cause the circuit to: provide a response based on receiving the request, wherein the response includes: allocation, partial allocation, or rejection.

[0065] Example 5 may include one or more examples, including instructions that, if executed, cause the circuit to: release the allocated memory capacity before the duration expires based on receiving a second request.

[0066] Example 6 may include one or more examples, including instructions that, if executed, cause the circuit to: allocate a second memory capacity for a second duration based on: receiving a request to allocate the second memory capacity in a second configuration, wherein the second configuration specifies a second time layer, wherein the second duration is based on the second time layer, and wherein the second configuration is automatically generated based on a prediction of the process's memory usage.

[0067] Example 7 may include one or more examples, wherein the memory is part of a memory pool, and wherein the memory pool includes one or more memory devices connected via a device interface, the memory pool including one or more memory devices connected via one or more of the following: a device interface, an Ethernet-based network, or a memory interface.

[0068] Example 8 may include one or more examples, wherein the instructions include one or more of the following: an operating system (OS), a coordinator, or a process.

[0069] Example 9 may include one or more examples, and may include a method comprising: a process issuing a request to allocate memory capacity for a duration, wherein the request includes a configuration requesting the allocation of the memory capacity, the configuration specifying a time tier, and the duration being based on the time tier; and receiving a response to the request.

[0070] Example 10 may include one or more examples in which the request is used to specify one or more of the following: a request identifier, the memory capacity to be allocated, or the request duration for reserving the memory capacity.

[0071] Example 11 may include one or more examples in which the time layer is associated with the speed of read and / or write operations and the connection latency for accessing the memory.

[0072] Example 12 may include one or more examples, wherein the response includes: allocation, partial allocation, or rejection.

[0073] Example 13 may include one or more examples, and includes: the process issuing a second request to request the release of a portion of the allocated memory capacity before the duration expires.

[0074] Example 14 may include one or more examples, and includes: the process receiving an indication of a second memory allocation for a second start time and a second duration, without relying on the process requesting the second memory allocation, wherein the second memory allocation is based on a prediction of the process's memory usage.

[0075] Example 15 may include one or more examples, an apparatus comprising: an interface; and circuitry for: receiving a request to allocate memory capacity for a duration based on: receiving a configuration requesting the allocation of the memory capacity, wherein the configuration specifies a time tier, wherein the duration is based on the time tier; and allocating the memory capacity for the duration.

[0076] Example 16 may include one or more examples in which the request is used to specify one or more of the following: a request identifier, the memory capacity to be allocated, or the request duration for reserving the memory capacity.

[0077] Example 17 may include one or more examples in which the time layer is associated with the speed of read and / or write operations and the connection latency for accessing the memory.

[0078] Example 18 may include one or more examples, wherein the circuitry is configured to allocate a second memory capacity for a second duration based on: receiving a second configuration requesting the allocation of the second memory capacity, and the second configuration specifying a second time layer, wherein the second duration is based on the second time layer, and wherein the second configuration is automatically generated based on a prediction of the memory usage of the process.

[0079] Example 19 may include one or more examples, wherein the memory is part of a memory pool, and wherein the memory pool includes one or more memory devices connected via a device interface, the memory pool including one or more memory devices connected via one or more of the following: a device interface, an Ethernet-based network, or a memory interface.

[0080] Example 20 may include one or more examples in which the request is associated with one or more of the following: a process, an operating system (OS), or a coordinator.

Claims

1. At least one non-transitory computer-readable medium, comprising instructions that, if executed, cause a circuit to: A request is received to allocate memory capacity for a duration based on: receiving a configuration requesting the allocation of the memory capacity, and the configuration specifying a time tier and / or the duration; and The memory capacity is allocated for the duration specified.

2. The computer-readable medium according to claim 1, wherein, The request is used to specify one or more of the following: a request identifier, the memory capacity to be allocated, or the duration of the request to reserve the memory capacity.

3. The computer-readable medium according to one or more of claims 1-2, wherein, The time layer is associated with the speed of read and / or write operations and the connection latency for accessing the memory.

4. The computer-readable medium according to one or more of claims 1-3, comprising instructions that, if executed, cause the circuit to: Based on receiving the request, a response is provided, wherein the response includes: Allocate, partially allocate, or refuse.

5. The computer-readable medium according to one or more of claims 1-4, comprising instructions that, if executed, cause the circuit to: Upon receiving the second request, the allocated memory capacity is released before the duration expires.

6. The computer-readable medium according to one or more of claims 1-5, comprising instructions that, if executed, cause the circuit to: The second memory capacity is allocated for a second duration based on the following: receiving a second configuration requesting the allocation of the second memory capacity, wherein the second configuration specifies a second time layer, wherein the second duration is based on the second time layer, and wherein the second configuration is automatically generated based on a prediction of the process's memory usage.

7. The computer-readable medium according to one or more of claims 1-6, wherein, The memory is part of a memory pool, and the memory pool includes one or more memory devices connected via a device interface, the memory pool including one or more memory devices connected via one or more of the following: a device interface, an Ethernet-based network, or a memory interface.

8. The computer-readable medium according to one or more of claims 1-7, wherein, The instructions include one or more of the following: operating system (OS), coordinator, or process.

9. A method comprising: A process issues a request to allocate memory capacity for a duration, wherein the request includes a configuration for requesting the allocation of the memory capacity, the configuration specifying a time tier, and the duration being based on the time tier; as well as Receive a response to the request.

10. The method according to claim 9, wherein, The request is used to specify one or more of the following: a request identifier, the memory capacity to be allocated, or the duration of the request to reserve the memory capacity.

11. The method according to one or more of claims 9-10, wherein, The time layer is associated with the speed of read and / or write operations and the connection latency for accessing the memory.

12. The method according to one or more of claims 9-11, wherein, The response includes an indicator indicating the following: allocation, partial allocation, or rejection.

13. The method according to one or more of claims 9-12, comprising: The process issues a second request to release a portion of the allocated memory capacity before the duration expires.

14. The method according to one or more of claims 9-13, comprising: The process receives an instruction for a second memory allocation for a second start time and a second duration, without relying on the process requesting the second memory allocation, wherein the second memory allocation is based on a prediction of the process's memory usage.

15. An apparatus comprising: interface; as well as Circuit, used for: A request is received to allocate memory capacity for a duration based on: receiving a configuration requesting the allocation of the memory capacity, and the configuration specifying a time tier, wherein the duration is based on the time tier; and The memory capacity is allocated for the duration specified.

16. The apparatus according to claim 15, wherein, The request is used to specify one or more of the following: a request identifier, the memory capacity to be allocated, or the duration of the request to reserve the memory capacity.

17. The apparatus according to one or more of claims 15-16, wherein, The time layer is associated with the speed of read and / or write operations and the connection latency for accessing the memory.

18. The apparatus according to one or more of claims 15-17, wherein, The circuit is used for: The second memory capacity is allocated for a second duration based on the following: receiving a second configuration requesting the allocation of the second memory capacity, wherein the second configuration specifies a second time layer, wherein the second duration is based on the second time layer, and wherein the second configuration is automatically generated based on a prediction of the process's memory usage.

19. The apparatus according to one or more of claims 15-18, wherein, The memory is part of a memory pool, and the memory pool includes one or more memory devices connected via a device interface, the memory pool including one or more memory devices connected via one or more of the following: a device interface, an Ethernet-based network, or a memory interface.

20. The apparatus according to one or more of claims 15-19, wherein, The request is associated with one or more of the following: a process, an operating system (OS), or a coordinator.

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